self-calling-chip.flx

gistfile1.txt

chip A
  connector io
  pin i : %< int  // we read from
  pin o : %> int  // we write to
{
  while true do
    // take the value provided and send it upstream
    x := read io.i;

    // prep internal chip logic
    var r0,w0 = mk_ioschannel_pair[int]();
    circuit
      wire w0 to A.o  // rig it up to be self referential
      wire r0 to A.i
    endcircuit

    // spawn thread to provide stack semantics
    spawn_fthread {

      // real chip logic starts ------
      if (x <= 4) do
        println$ "Passing upstream: " + (x + 1).str;
        w0 `write` (x+1);
      done
      x = read r0;
      // real chip logic ends ------

    };

    // send values back to caller
    println$ "Passing downstream: " + x.str;
    io.o `write` x;      // pass it downstream
  done
}

var ai,ao = mk_ioschannel_pair[int]();

circuit
  wire ao to A.o
  wire ai to A.i
endcircuit

spawn_fthread {
  ao `write` 1;
  while true do
    println$ "Final Result=" + ai.read.str;
  done
};
/*
chip FibTo (maxN : int)
  connector io
  pin i1 : %< int
  pin i2 : %< int
  pin o : %> int
{
  while true do
    // take the value provided and send it upstream
    x := read io.i1;
    y := read io.i2;

    // prep internal chip logic
    var r0,w0 = mk_ioschannel_pair[int]();
    var r1,w1 = mk_ioschannel_pair[int]();

    circuit
      wire w0 to Fib.o  // rig it up to be self referential
      wire r0 to FibTo(maxN).i1
      wire r1 to FibTo(maxN).i2
    endcircuit

    // spawn thread to provide stack semantics
    spawn_fthread {

      // real chip logic starts ------
      if (y <= 1000) do
        println$ "Passing upstream: " + (x + y).str;
        w0 `write` (x+y);
      done
      x = read r0;
      y = read r1;
      // real chip logic ends ------

    };

    // send values back to caller
    println$ "Passing downstream: " + x.str;
    io.o `write` y;      // pass it downstream
  done
}

module B
{
var ai,ao = mk_ioschannel_pair[int]();
var bi,bo = mk_ioschannel_pair[int]();

device Fib = FibTo(5);

circuit
  wire ao to Fib.o
  wire ai to Fib.i1
  wire bi to Fib.i2
endcircuit

spawn_fthread {
  ao `write` 1;
  bo `write` 1;
  while true do
    println$ "Final Result=" + ai.read.str;
  done
};

}
*/