Verilog Howto

blink-always-example.v

always @(posedge clk)
    cnt = cnt + 1;

blink-delay-all.v

output wire led;
input wire clk;
reg [25:0] cnt;
reg led_state;

always @(posedge clk) begin
    cnt = cnt + 1;
    if (cnt > 50000000) begin
        // incrementing led_state causes it to alternate between 1 and 0
        led_state = led_state + 1; 
        // reset counter so that we count back up to exactly one second
        cnt = 0;
    end
end

assign led = led_state;

blink-delay-mostly.v

output wire led; // declare a wire that we'll use for output
input wire clk;  // our 50 MHz clock actually needs to be wired in as well
reg [25:0] cnt;
reg led_state;   // our 1-bit register to store the state of our LED

always @(posedge clk) begin
    cnt = cnt + 1;
    if (cnt > 50000000)
        led_state = 0;
    else
        led_state = 1;
end

// connect one end of the led output wire to our led_state register
assign led = led_state;

blink-delay-partial.v

// Note: [25:0] means a 26-bit register whose bits are labeled from 0 to 25,
// and the most significant bit (#25) comes first (big endian)
reg [25:0] cnt;

always @(posedge clk) begin // "begin" is Verilog's equivalent of C's "{"
    cnt = cnt + 1;
    if (cnt > 50000000)
        // turn off the LED
    else
        // turn on the LED
end                         // "end" is Verilog's equivalent of C's "}"

blink-delay.c

void loop() {
    digitalWrite(LED_PIN, HIGH);   // turn LED on
    delay(1000);                   // wait for 1000 milliseconds
    digitalWrite(LED_PIN, LOW);    // turn LED off
    delay(1000);                   // wait for 1000 milliseconds
}

blink.c

void loop() {
  digitalWrite(LED_PIN, HIGH);   // turn LED on
  digitalWrite(LED_PIN, LOW);    // turn LED off
}

blink.v

always @(posedge clk)    // whenever `clk` changes from a 0 to a 1,
    cnt = cnt + 1;       // increment the register `cnt` by one
assign led_pin = cnt;    // independently, also connect the `led` wire to the `cnt` register