7seg Driver

7seg_driver.v

// ACTIVE-LOW
// 0: 1000000	1: 1111001	2: 0100100	3: 0110000
// 4: 0011001	5: 0010010	6: 0000010	7: 1111000
// 8: 0000000	9: 0010000	A: 0001000	B: 0000011
// C: 1000110	D: 0100001	E: 0000110	F: 0001110
 
module driver_7seg(
	input  [3:0] in,
	output [6:0] out
);
	assign	out[6] = (~in[3] & ~in[2] & ~in[1]) | (~in[3] & in[2] & in[1] & in[0]) | (in[3] & in[2] & ~in[1] & ~in[0]);
	assign	out[5] = (~in[3] & ~in[2] & in[1]) | (~in[3] & ~in[2] & in[0]) | (~in[3] & in[1] & in[0]) | (in[3] & in[2] & ~in[1] & in[0]);
	assign	out[4] = (~in[3] & in[2] & ~in[1]) | (~in[3] & in[0]) | (~in[2] & ~in[1] & in[0]);
	assign	out[3] = (~in[3] & ~in[2] & ~in[1] & in[0]) | (~in[3] & in[2] & ~in[1] & ~in[0]) | (in[3] & ~in[2] & in[1] & ~in[0]) | (in[2] & in[1] & in[0]);
	assign	out[2] = (~in[3] & ~in[2] & in[1] & ~in[0]) | (in[3] & in[2] & in[1]) | (in[3] & in[2] & ~in[0]);
	assign	out[1] = (~in[3] & in[2] & ~in[1] & in[0]) | (in[3] & in[2] & ~in[0]) | (in[3] & in[1] & in[0]) | (in[2] & in[1] & ~in[0]);
	assign	out[0] = (~in[3] & ~in[2] & ~in[1] & in[0]) | (~in[3] & in[2] & ~in[1] & ~in[0]) | (in[3] & ~in[2] & in[1] & in[0]) | (in[3] & in[2] & ~in[1] & in[0]);
endmodule
 
module driver_7seg(
	input      [3:0] in,
	output reg [6:0] out
);
	always @(*) begin
		case(in)
		4'h0 : out <= 7'b1000000;
		4'h1 : out <= 7'b1111001;
		4'h2 : out <= 7'b0100100;
		4'h3 : out <= 7'b0110000;
		4'h4 : out <= 7'b0011001;
		4'h5 : out <= 7'b0010010;
		4'h6 : out <= 7'b0000010;
		4'h7 : out <= 7'b1111000;
		4'h8 : out <= 7'b0000000;
		4'h9 : out <= 7'b0010000;
		4'hA : out <= 7'b0001000;
		4'hB : out <= 7'b0000011;
		4'hC : out <= 7'b1000110;
		4'hD : out <= 7'b0100001;
		4'hE : out <= 7'b0000110;
		4'hF : out <= 7'b0001110;
		endcase
	end
endmodule