top_vgatest_640x480.v

module top_vgatest_640x480
(
  input clk_25mhz,
  output clk_stm32,
  output [3:0] gpdi_dp,
  input [7:3] R_in,
  output [7:3] R_out,
  input [7:2] G_in, 
  output [7:2] G_out,
  input [7:3] B_in, 
  output [7:3] B_out,
  input lcd_clk_in,
  input lcd_HSYNC_in,
  input lcd_VSYNC_in,
  input lcd_DE_in,
  output lcd_clk_out,
  output lcd_HSYNC_out,
  output lcd_VSYNC_out,
  output lcd_DE_out,
  input spi2_in_clk,spi2_in_miso,spi2_in_mosi,spi2_in_csa,spi2_in_csb,spi2_in_irq,
  input spi4_in_clk,spi4_in_miso,spi4_in_mosi,spi4_in_csa,spi4_in_csb,spi4_in_irq,
  input spi5_in_clk,spi5_in_miso,spi5_in_mosi,spi5_in_csa,spi5_in_csb,spi5_in_irq
);
    parameter C_ddr = 1'b1; // 0:SDR 1:DDR

    assign lcd_clk_out = lcd_clk_in;
    assign lcd_HSYNC_out = lcd_HSYNC_in;
    assign lcd_VSYNC_out = lcd_VSYNC_in;
    assign R_out = R_in;
    assign G_out = G_in;
    assign B_out = B_in;

    // clock generator
    wire clk_250MHz, clk_125MHz, clk_25MHz, clk_locked;

   clk_25_25
   clk_25_25_instance(
     .clk_in(clk_25mhz),
     .clk_out(clk_stm32)
   );


    clk_25_250_125_25
    clock_instance
    (
      .clki(clk_stm32),
      .clko(clk_250MHz),
      .clks1(clk_125MHz),
      .clks2(clk_25MHz),
      .locked(clk_locked)
    );
    
    // shift clock choice SDR/DDR
    wire clk_pixel, clk_shift;
    assign clk_pixel = clk_25MHz;
    generate
      if(C_ddr == 1'b1)
        assign clk_shift = clk_125MHz;
      else
        assign clk_shift = clk_250MHz;
    endgenerate

    // VGA signal generator
    wire [7:0] vga_r, vga_g, vga_b;
    wire vga_hsync, vga_vsync, vga_blank;
    vga
    vga_instance
    (
      .clk_pixel(clk_pixel),
      .clk_pixel_ena(1'b1),
      .test_picture(1'b1), // enable test picture generation
      .vga_r(vga_r),
      .vga_g(vga_g),
      .vga_b(vga_b),
      .vga_hsync(vga_hsync),
      .vga_vsync(vga_vsync),
      .vga_blank(vga_blank)
    );

    // VGA to digital video converter
    wire [1:0] tmds[3:0];
    vga2dvid
    #(
      .C_ddr(C_ddr),
      .C_shift_clock_synchronizer(1'b1)
    )
    vga2dvid_instance
    (
      .clk_pixel(clk_pixel),
      .clk_shift(clk_shift),
      .in_red(vga_r),
      .in_green(vga_g),
      .in_blue(vga_b),
      .in_hsync(vga_hsync),
      .in_vsync(vga_vsync),
      .in_blank(vga_blank),
      .out_clock(tmds[3]),
      .out_red(tmds[2]),
      .out_green(tmds[1]),
      .out_blue(tmds[0])
    );

    // output TMDS SDR/DDR data to fake differential lanes
    fake_differential
    #(
      .C_ddr(C_ddr)
    )
    fake_differential_instance
    (
      .clk_shift(clk_shift),
      .in_clock(tmds[3]),
      .in_red(tmds[2]),
      .in_green(tmds[1]),
      .in_blue(tmds[0]),
      .out_p(gpdi_dp)
      //.out_n(gpdi_dn)
    );

endmodule