Created
September 2, 2022 10:35
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`default_nettype none | |
module top ( | |
input clk48, | |
output rgb_led0_r, | |
output rgb_led0_g, | |
output rgb_led0_b, | |
output gpio_0, | |
input gpio_a0, | |
inout scl, | |
inout sda | |
); | |
assign rgb_led0_g = ~gpio_a0; | |
// Create a 27 bit register | |
reg [26:0] counter = 0; | |
// Every positive edge increment register by 1 | |
always @(posedge clk48) begin | |
counter <= counter + 1; | |
end | |
assign gpio_0 = counter[20]; | |
endmodule |
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