i2s_mic.v

module top (
    input clk_25mhz,
    output [7:0] led,
    input [6:0] btn,
    input mic_data,
	  output ftdi_rxd,
    output mic_clk,
    output mic_select,
    output reg [3:0] audio_l,
    output reg [3:0] audio_r,
    output wifi_gpio0
);
    assign wifi_gpio0 = 1'b1;
    assign mic_select = 1'b1;

wire clk2MHz;  // Standard clock for microphone
wire clk4MHz;  // Ultrasonic clock for microphone

pll
pll_inst
(
  .clki(clk_25mhz),
  .clks1(clk4MHz),
  .clko(clk2MHz)
);

wire data_is_ready; //not used

reg [3:0] audio_data_out;
reg [3:0] audio_data_buff_out;

reg [31:0] cnt = 0;
wire we;
assign we = ~btn[1];
wire btnClk;

//assign audio_r = audio_data_buff_out;
//assign audio_l = audio_data_buff_out;
//assign audio_r = audio_data_out;
//assign audio_l = audio_data_out;
assign audio_l = btn[1] ? audio_data_buff_out:audio_data_out;
assign audio_r = btn[1] ? audio_data_buff_out:audio_data_out;
wire mic_clk_cpy = btn[1] ? mic_clk_slow:mic_clk;

wire mic_clk_slow;

wire [31:0] raddr = cnt-65535;
wire [31:0] waddr = cnt;
wire uart_data_ready;
assign uart_data_ready = ~data_is_ready;

databuff databuff_inst(
  .clk(mic_clk_cpy),
  .raddr(cnt),
  .waddr(cnt),
  .we(uart_data_ready),
  .datain(audio_data_out),
  .dataout(audio_data_buff_out)
);

i2s_mic
#(
  .size(32)
)
i2s_mic_inst(
  .standard_clk(clk2MHz),
  .ultrasonic_clk(clk4MHz),
  .mic_clk_out(mic_clk),
  .btn(btn),
  .data_in(mic_data),
  .data_ready(data_is_ready),
  .data_out(audio_data_out)
  );

assign led[0] = mic_clk_cpy;

/*
  always @ (posedge mic_clk)
  	begin

  		// on negative edge of audio_clk data is ready
      //if (we)
  		//  cnt <= cnt + 1;
      //else
      //  cnt <= 0;
  		// colect data from second microphone -- currently ignore
  	end
*/

wire [7:0] audio_uart_out;
assign audio_uart_out = { audio_data_buff_out[3:0]};

assign led[1] = uart_data_ready;

uart_tx uart_transmit(
      .clk(clk4MHz),
      .resetn(1'b1),
      .ser_tx(ftdi_rxd),
      .cfg_divider(4000000/115200),
      .data(audio_uart_out),
      .data_we(uart_data_ready)
    );

always @ (posedge cnt[0])
  begin
    mic_clk_slow <= ~mic_clk_slow;
  end

always @ (posedge data_is_ready)
  begin
    cnt <= cnt + 1;
  end
endmodule