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static const uint8_t SX1276_REG_VERSION = 0x42;
static const uint8_t SX1276_REG_TEMP = 0x3C;
static const uint8_t SX1276_REG_LOW_BAT = 0x3D;
static const uint8_t SX1276_REG_OP_MODE = 0x01;
static const uint8_t SX1276_REG_OSC = 0x24;
static const uint8_t RF_OPMODE_MASK = 0xF8;
static const uint8_t RF_OPMODE_SLEEP = 0x00;
static const uint8_t RF_OPMODE_STANDBY = 0x00;
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
sudo apt-get install git
mkidr FPGA
cd FPGA
sudo apt-get install cmake
sudo apt-get install build-essential clang bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3
sudo apt-get install qt5-default
sudo apt-get install python3-dev
sudo apt-get install libboost-all-dev
git clone --recursive https://github.com/SymbiFlow/prjtrellis
cd prjtrellis
Apio BETA install 12F test
sudo apt install python3-pip python3-setuptools gtkwave
git clone https://github.com/mmicko/apio
cd apio
git checkout develop
sudo pip3 install -e .
apio install -a
module top_OV7640
(
input clk_25mhz,
output [7:0] led,
// output [3:0] gpdi_dp, gpdi_dn,
input [6:0] btn,
input [7:0] cam_data,
input cam_PCLK,
input cam_HREF,
input cam_VSYNC,
Q: Ice40 is using SB_IO how to do this on ECP5
A: Ice40
A: https://github.com/lawrie/OV7670-Verilog/blob/master/src/camera_configure.v#L55
A: ECP5
A: https://github.com/daveshah1/ulx3s/blob/master/rtl/verilog/orpsoc_top.v#L456
Q: I need same signal on multiple places
A: Make a copy of that signal and pass copy where needed
module top (
input clk_25mhz,
output [7:0] led,
input [6:0] btn,
input mic_data,
output ftdi_rxd,
output mic_clk,
output mic_select,
output reg [3:0] audio_l,
output reg [3:0] audio_r,
module top (
input clk_25mhz,
output [7:0] led,
input [6:0] btn,
input mic_data,
output ftdi_rxd,
output mic_clk,
output mic_select,
output reg [3:0] audio_l,
output reg [3:0] audio_r,
module i2s_mic
#(
// Not used
parameter size = 16
)
(
input wire clk, // 1.66MHz
input wire data_in, // data from microphone
input wire rst,
input [3:0] led,
#!/usr/bin/env python3
import argparse
import os
from litex.soc.integration.builder import Builder
from soc_linux import SoCLinux
kB = 1024
module dvi_in_out
(
input clk_25mhz,
input [6:0] btn,
output [7:0] led,
output [3:0] gpdi_dp, gpdi_dn,
input [27:0] gp,
output wifi_gpio0
);