TDD on VHDL

counter.vhd

----------------------------------------------------------------------------------
-- Engineer: Gustavo Villalta
--
-- Design Name: Counter
-- Project Name: counter
-- Description: Simple Sequential Counter
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter IS
    PORT ( clock : IN  STD_LOGIC;
           reset : IN  STD_LOGIC;
           count : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0));
END counter;

ARCHITECTURE Behavioral OF counter IS
	SIGNAL temporary_counter: std_logic_vector(7 DOWNTO 0) := "00000000" ;
BEGIN

  PROCESS (clock, reset)
  BEGIN
		if (reset = '1') then
			temporary_counter <= "00000000";
		else
			if (clock'event and clock='1') then
				temporary_counter <= temporary_counter + 1;
			end if;
		end if;
  END PROCESS;
	count <= temporary_counter;
END Behavioral;

counter_tb.prj

vhdl work "counter.vhd"
vhdl work "counter_tb.vhd"

counter_tb.vhd

--------------------------------------------------------------------------------
-- Engineer: Gustavo Villalta
--
-- Design Name:   Counter Testbench
-- Project Name:  counter
-- Description: Counter Testbench
-- 
-- Dependencies: counter.vhd
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY counter_tb IS
END counter_tb;
 
ARCHITECTURE Behavior OF counter_tb IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT counter
    PORT(
         clock : IN  std_logic;
         reset : IN  std_logic;
         count : OUT  std_logic_vector(7 DOWNTO 0)
        );
    END COMPONENT;

   --Inputs
   SIGNAL clock : std_logic := '0';
   SIGNAL reset : std_logic := '0';

 	--Outputs
   SIGNAL count : std_logic_vector(7 DOWNTO 0);

   -- Clock period definitions
   CONSTANT clock_period : time := 10 ns;
   CONSTANT settling_time : time := 100 ps;
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: counter PORT MAP (
          clock => clock,
          reset => reset,
          count => count
        );

   -- Clock process definitions
   clock_process : PROCESS
   BEGIN
		clock <= '0';
		wait for clock_period/2;
		clock <= '1';
		wait for clock_period/2;
   END PROCESS;
 

   -- Counter process
   counter_process : PROCESS
   BEGIN
    -- hold reset state for 100 ns.
		reset <= '1';

		wait for settling_time;
    
    -- Testing the reset
		assert count = "00000000"
			report "Reset is not setting counter to 0x00"
			severity error;

		wait for 2*clock_period - settling_time;
		
		-- Let the counter run
		reset <= '0';
		wait for clock_period;
		
    -- Testing the counter
		assert count = "00000001"
			report "Clock is changing counter value"
			severity error;
			
		assert count = "00000001"
			report "Clock is not incrementing correctly"
			severity error;

		wait for clock_period;
		
		assert count = "00000010"
			report "Clock is not incrementing correctly"
			severity error;
			
		-- reset it again asynchronously
		reset <= '1';
		
		wait for settling_time;
		
		assert count = "00000000"
			report "Reset is not setting counter to 0x00 asynchronously"
			severity error;
		
		reset <= '0';	
		
		wait for 255*clock_period;

    -- Testing the edge case of max value
		assert count = "11111111"
			report "Counter isn't reaching it's max value"
			severity error;
		
		wait for clock_period;

    -- Testing the edge case when the counter exceed the max value
		assert count = "00000000"
			report "Counter isn't cyclic"
			severity error;
		
		wait;
   END PROCESS;
END;

isim.cmd

onerror {resume}
wave add /
run 2600 ns

Makefile

#Project file
PRJ=counter_tb.prj
#Compiled executable
EXE=counter_tb.exe
#TCL commands that will run in the simulator
CMD=isim.cmd
#Temporary Command file
CMDTMP=isim.tmp.cmd
#Waveform DataBase from simulation
WDB=isim.wdb
#Log file from simulation
LOG=isim.log
#Top-Level Entity
TOP=work.counter_tb
#Files created after compilation
RM_FILES= fuse.log fuse.xmsgs fuseRelaunch.cmd
RM_FOLDERS= isim/

#Default action, just compile the files
all: compile

#Compile with fuse
compile: counter.vhd counter_tb.vhd
	fuse -incremental -o $(EXE) -prj $(PRJ) $(TOP)

#Run the simulation and the command file
simulate: compile $(EXE) $(CMD)
	cat $(CMD) >> $(CMDTMP)
	echo "exit 0" >> $(CMDTMP)
	./$(EXE) -gui -tclbatch $(CMDTMP) -log $(LOG)
	rm -f $(CMDTMP)

#Open the simulation to check out the waveform
view: simulate $(WDB)
	isimgui -view $(WDB)

#For TDD
test: simulate $(LOG)
	grep "Error" $(LOG)

clear: $(EXE) 
	rm -f $(RM_FILES)
	rm -rf $(RM_FOLDERS)