Template of Makefile. It may be used for a simple c, c++ project.

Makefile

.SUFFIXES : .c .o

CC = gcc
CFLAGS = -g $(INC)
INC = # -i -I
LIBS = # -l -L
DEPS = # *.h
OBJS = # *.o
TARGET =

all: $(TARGET)

%.o: %.c $(DEPS)
        $(CC) -c -o $@ $< $(CFLAGS)

$(TARGET): $(OBJS)
        $(CC) -o $@ $^ $(CFLAGS) $(LIBS)

.PHONY: clean

clean:
        rm -rf $(OBJS) $(TARGET) core