Patch to gcc-4.8.4 for Lexra processors

0001-gcc-4.8.4-add-lexra-support.patch

--- gcc-4.8.4.orig/gcc/config/mips/mips.c
+++ gcc-4.8.4/gcc/config/mips/mips.c
@@ -7062,6 +7062,8 @@ mips_block_move_straight (rtx dest, rtx
   if (MEM_ALIGN (src) == BITS_PER_WORD / 2
       && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
     bits = BITS_PER_WORD / 2;
+  else if (TARGET_LEXRA || TARGET_RLX)
+    bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest));
   else
     bits = BITS_PER_WORD;
 
@@ -7427,6 +7429,8 @@ mips_expand_ext_as_unaligned_load (rtx d
     }
   else
     {
+      if (TARGET_LEXRA || TARGET_RLX)
+        return false;
       emit_insn (gen_mov_lwl (temp, src, left));
       emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
     }
@@ -7470,6 +7474,8 @@ mips_expand_ins_as_unaligned_store (rtx
     }
   else
     {
+      if (TARGET_LEXRA || TARGET_RLX)
+        return false;
       emit_insn (gen_mov_swl (dest, src, left));
       emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
     }
@@ -16469,6 +16475,10 @@ mips_option_override (void)
   if (mips_arch_info == 0)
     mips_set_architecture (mips_default_arch ());
 
+  /* flag_fix_bdsl only works for Taroko processors */
+  if (flag_fix_bdsl && !(TARGET_LEXRA || TARGET_RLX))
+    flag_fix_bdsl = false;
+
   if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
     error ("%<-march=%s%> is not compatible with the selected ABI",
 	   mips_arch_info->name);
--- gcc-4.8.4.orig/gcc/config/mips/mips-cpus.def
+++ gcc-4.8.4/gcc/config/mips/mips-cpus.def
@@ -147,3 +147,11 @@ MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65
 MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)
 MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY)
+
+/* Lexra processors */
+MIPS_CPU ("lx4180", PROCESSOR_LX4180, 1, 0)
+MIPS_CPU ("rlx4181", PROCESSOR_RLX4181, 1, 0)
+MIPS_CPU ("rlx4281", PROCESSOR_RLX4281, 1, 0)
+MIPS_CPU ("rlx5181", PROCESSOR_RLX5181, 1, 0)
+MIPS_CPU ("lx5280", PROCESSOR_LX5280, 1, 0)
+MIPS_CPU ("rlx5281", PROCESSOR_RLX5281, 1, 0)
--- gcc-4.8.4.orig/gcc/config/mips/mips.h
+++ gcc-4.8.4/gcc/config/mips/mips.h
@@ -222,6 +222,16 @@ struct mips_cpu_info {
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
 #define TARGET_XLP                  (mips_arch == PROCESSOR_XLP)
 
+#define TARGET_MIPS4180		    (mips_arch == PROCESSOR_LX4180)
+#define TARGET_MIPS4181		    (mips_arch == PROCESSOR_RLX4181)
+#define TARGET_MIPS4281		    (mips_arch == PROCESSOR_RLX4281)
+#define TARGET_MIPS5181		    (mips_arch == PROCESSOR_RLX5181)
+#define TARGET_MIPS5280		    (mips_arch == PROCESSOR_LX5280)
+#define TARGET_MIPS5281		    (mips_arch == PROCESSOR_RLX5281)
+#define TARGET_RLX		    (TARGET_MIPS4180 || TARGET_MIPS4181	\
+				     || TARGET_MIPS4281 || TARGET_MIPS5181 \
+				     || TARGET_MIPS5280 || TARGET_MIPS5281)
+
 /* Scheduling target defines.  */
 #define TUNE_20KC		    (mips_tune == PROCESSOR_20KC)
 #define TUNE_24K		    (mips_tune == PROCESSOR_24KC	\
@@ -234,7 +244,7 @@ struct mips_cpu_info {
 #define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E	\
 				     || mips_tune == PROCESSOR_LOONGSON_2F)
 #define TUNE_LOONGSON_3A            (mips_tune == PROCESSOR_LOONGSON_3A)
-#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
+#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000 || TUNE_RLX)
 #define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
 #define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
 #define TUNE_MIPS4120               (mips_tune == PROCESSOR_R4120)
@@ -250,6 +260,29 @@ struct mips_cpu_info {
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1		\
 				     || mips_tune == PROCESSOR_SB1A)
 
+#define TUNE_MIPS4180		    (mips_tune == PROCESSOR_LX4180)
+#define TUNE_MIPS4181		    (mips_tune == PROCESSOR_RLX4181)
+#define TUNE_MIPS4281		    (mips_tune == PROCESSOR_RLX4281)
+#define TUNE_MIPS5181		    (mips_tune == PROCESSOR_RLX5181)
+#define TUNE_MIPS5280		    (mips_tune == PROCESSOR_LX5280)
+#define TUNE_MIPS5281		    (mips_tune == PROCESSOR_RLX5281)
+#define TUNE_RLX		    (TUNE_MIPS4180 || TUNE_MIPS4181	\
+				     || TUNE_MIPS4281 || TUNE_MIPS4181	\
+				     || TUNE_MIPS5280 || TUNE_MIPS5281)
+
+/* Instruction-set for Lexra defines. */
+#define INSN_RLX0		    (TARGET_MIPS4180)
+#define INSN_RLX1		    (TARGET_MIPS5280)
+#define INSN_RLX2		    (TARGET_MIPS4181 || TARGET_MIPS5181)
+#define INSN_RLX3		    (TARGET_MIPS4281 || TARGET_MIPS5281)
+
+#define INSN_RLXA		    (INSN_RLX0 || INSN_RLX1 || INSN_RLX2 \
+				     || INSN_RLX3)
+#define INSN_RLXB		    (INSN_RLX1 || INSN_RLX2 || INSN_RLX3)
+
+#define INSN_RAD1		    (INSN_5181 || INSN_5280 || INSN_5281)
+#define INSN_RAD2		    (INSN_5281)
+
 /* Whether vector modes and intrinsics for ST Microelectronics
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
    floating-point registers provide 64-bit values.  */
@@ -548,6 +581,26 @@ struct mips_cpu_info {
 									\
       if (TARGET_CACHE_BUILTIN)						\
 	builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE");		\
+									\
+      if (TARGET_MIPS4180)						\
+	builtin_define ("__m4180");					\
+      else if (TARGET_MIPS4181)						\
+	builtin_define ("__m4181");					\
+      else if (TARGET_MIPS4281)						\
+	builtin_define ("__m4281");					\
+      else if (TARGET_MIPS5181)						\
+	builtin_define ("__m5181");					\
+      else if (TARGET_MIPS5280)						\
+	builtin_define ("__m5280");					\
+      else if (TARGET_MIPS5281)						\
+	builtin_define ("__m5281");					\
+									\
+      if (TARGET_LEXRA || TARGET_RLX)					\
+	builtin_define ("__mlexra");					\
+									\
+      if (flag_fix_bdsl)						\
+	builtin_define ("__FIX_BDSL__");				\
+									\
     }									\
   while (0)
 
@@ -716,6 +769,8 @@ struct mips_cpu_info {
   "%{mhard-float|msoft-float|mno-float|march=mips*:; \
      march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
      |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
+     |march=lx4180|march=rlx4181|march=rlx4281|march=rlx5181 \
+     |march=lx5280|march=rlx5281 \
      |march=octeon|march=xlr: -msoft-float;		  \
      march=*: -mhard-float}"
 
@@ -838,7 +893,8 @@ struct mips_cpu_info {
 
 /* ISA has the integer conditional move instructions introduced in mips4 and
    ST Loongson 2E/2F.  */
-#define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
+#define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF \
+                                 || (!TARGET_MIPS16 && INSN_RLXB))
 
 /* ISA has LDC1 and SDC1.  */
 #define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1 && !TARGET_MIPS16)
@@ -1052,7 +1108,8 @@ struct mips_cpu_info {
 		       && !TARGET_MIPS16)
 
 /* ISA includes sync.  */
-#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
+#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900 || INSN_RLX3)	\
+		      && !TARGET_MIPS16)
 #define GENERATE_SYNC			\
   (target_flags_explicit & MASK_LLSC	\
    ? TARGET_LLSC && !TARGET_MIPS16	\
@@ -1061,7 +1118,7 @@ struct mips_cpu_info {
 /* ISA includes ll and sc.  Note that this implies ISA_HAS_SYNC
    because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
    instructions.  */
-#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
+#define ISA_HAS_LL_SC ((mips_isa >= 2 || INSN_RLX3) && !TARGET_MIPS16)
 #define GENERATE_LL_SC			\
   (target_flags_explicit & MASK_LLSC	\
    ? TARGET_LLSC && !TARGET_MIPS16	\
@@ -1169,6 +1226,12 @@ struct mips_cpu_info {
 
 #undef CC1_SPEC
 #define CC1_SPEC "\
+%{mlx4180:-march=lx4180} \
+%{mrlx4181:-march=rlx4181} \
+%{mrlx4281:-march=rlx4281} \
+%{mrlx5181:-march=rlx5181} \
+%{mlx5280:-march=lx5280} \
+%{mrlx5281:-march=rlx5281} \
 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
 %(subtarget_cc1_spec)"
 
--- gcc-4.8.4.orig/gcc/config/mips/mips.md
+++ gcc-4.8.4/gcc/config/mips/mips.md
@@ -64,6 +64,12 @@
   sr71000
   xlr
   xlp
+  lx4180
+  rlx4181
+  rlx4281
+  rlx5181
+  lx5280
+  rlx5281
 ])
 
 (define_c_enum "unspec" [
@@ -684,9 +690,13 @@
 
 ;; Can the instruction be put into a delay slot?
 (define_attr "can_delay" "no,yes"
-  (if_then_else (and (eq_attr "type" "!branch,call,jump")
-		     (and (eq_attr "hazard" "none")
-			  (eq_attr "single_insn" "yes")))
+  (if_then_else (and (ior (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+			  (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
+		     (ior (eq_attr "type" "!load")
+			  (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
+		     (and (eq_attr "type" "!branch,call,jump")
+			  (and (eq_attr "hazard" "none")
+			       (eq_attr "single_insn" "yes"))))
 		(const_string "yes")
 		(const_string "no")))
 
@@ -3956,7 +3966,7 @@
 	(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
 		     (match_operand:QI 2 "memory_operand" "m")]
 		    UNSPEC_LOAD_LEFT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
   "<load>l\t%0,%2"
   [(set_attr "move_type" "load")
    (set_attr "mode" "<MODE>")])
@@ -3967,7 +3977,7 @@
 		     (match_operand:QI 2 "memory_operand" "m")
 		     (match_operand:GPR 3 "register_operand" "0")]
 		    UNSPEC_LOAD_RIGHT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
   "<load>r\t%0,%2"
   [(set_attr "move_type" "load")
    (set_attr "mode" "<MODE>")])
@@ -3977,7 +3987,7 @@
 	(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
 		     (match_operand:QI 2 "memory_operand" "m")]
 		    UNSPEC_STORE_LEFT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
   "<store>l\t%z1,%2"
   [(set_attr "move_type" "store")
    (set_attr "mode" "<MODE>")])
@@ -3988,7 +3998,7 @@
 		     (match_operand:QI 2 "memory_operand" "m")
 		     (match_dup 0)]
 		    UNSPEC_STORE_RIGHT))]
-  "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
+  "!TARGET_MIPS16 && !TARGET_LEXRA && !TARGET_RLX && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
   "<store>r\t%z1,%2"
   [(set_attr "move_type" "store")
    (set_attr "mode" "<MODE>")])
--- gcc-4.8.4.orig/gcc/config/mips/mips.opt
+++ gcc-4.8.4/gcc/config/mips/mips.opt
@@ -293,6 +293,14 @@ mpaired-single
 Target Report Mask(PAIRED_SINGLE_FLOAT)
 Use paired-single floating-point instructions
 
+mlexra
+Target Report Mask(LEXRA)
+Do not use lwl/lwr/swl/swr instructions absent in Lexra chips
+
+mno-bdsl
+Target Report Var(flag_fix_bdsl) Init(0)
+Forbid the use of load instructions in the branch delay slots for all cases
+
 mr10k-cache-barrier=
 Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
 -mr10k-cache-barrier=SETTING	Specify when r10k cache barriers should be inserted
--- gcc-4.8.4.orig/gcc/config/mips/mips-tables.opt
+++ gcc-4.8.4/gcc/config/mips/mips-tables.opt
@@ -624,3 +624,21 @@ Enum(mips_arch_opt_value) String(octeon2
 EnumValue
 Enum(mips_arch_opt_value) String(xlp) Value(85) Canonical
 
+EnumValue
+Enum(mips_arch_opt_value) String(lx4180) Value(86) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(rlx4181) Value(87) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(rlx4281) Value(88) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(rlx5181) Value(89) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(lx5280) Value(90) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(rlx5281) Value(91) Canonical
+