stdin

stdin

// SPDX-License-Identifier: GPL-2.0-or-later
#include <dt-bindings/clock/hi3535-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		/* enable-method = "hisilicon,hi3620-smp"; */
		/**/
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		/* cpu@1 { */
		/* 	device_type = "cpu"; */
		/* 	compatible = "arm,cortex-a9"; */
		/* 	reg = <1>; */
		/* 	next-level-cache = <&l2>; */
		/* }; */
	};

	/* timer { */
	/* 	compatible = "arm,armv7-timer"; */
	/* 	interrupt-parent = <&gic>; */
	/* 	interrupts = <GIC_PPI 13 0xf08>, */
	/* 		     <GIC_PPI 14 0xf08>, */
	/* 		     <GIC_PPI 11 0xf08>, */
	/* 		     <GIC_PPI 10 0xf08>; */
	/* 	clock-frequency = <24000000>; */
	/* }; */

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	xin24M: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
		clock-output-names = "xin24M";
	};

	clk_3m: clk_3m {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <3000000>;
	};

	gic: interrupt-controller@20301000 {
		compatible = "arm,cortex-a9-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <1>;
		reg = <0x20301000 0x1000>,
			  <0x20300100 0x0100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		nand: nand@10000000 {
			compatible = "hisilicon,504-nfc";
			reg = <0x10000000 0x10000>, <0x50000000 0x4000000>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			status = "disabled";
		};

		sfc: sfc@10010000 {
			compatible = "hisilicon,fmc-spi-nor";
			reg = <0x10010000 0x10000>, <0x58000000 0x4000000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			status = "disabled";
		};

		usb0: usb@10030000 {
			compatible = "generic-ohci";
			reg = <0x10030000 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			status = "disabled";
		};

		usb1: usb@10040000 {
			compatible = "generic-ehci";
			reg = <0x10040000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			status = "disabled";
		};

		dmac: dma@10060000 {
			compatible = "arm,pl080";
			reg = <0x10060000 0x1000>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			status = "disabled";
		};

		dual_timer0: timer@20000000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x20000000 0x1000>;
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&xin24M>;
			clock-names = "apb_pclk";
			/* clocks = <&sysctrl HI3535_TIMER0_CLK>, */
			/* 		<&sysctrl HI3535_TIMER0_CLK>, */
			/* 		<&crg HI3535_APB_CLK>; */
			/* clock-names = "timer0clk", "timer1clk", "apb_pclk"; */
			status = "disabled";
		};

		dual_timer1: timer@20010000 {
			compatible = "arm,sp804";
			reg = <0x20010000 0x1000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&sysctrl HI3535_TIMER0_CLK>,
					<&sysctrl HI3535_TIMER0_CLK>,
					<&crg HI3535_APB_CLK>;
			clock-names = "timer0clk", "timer1clk", "apb_pclk";
			status = "disabled";
		};

		crg: clock-reset-controller@20030000 {
			compatible = "hisilicon,hi3535-crg";
			#clock-cells = <1>;
			#reset-cells = <2>;
			reg = <0x20030000 0x10000>;
		};

		sysctrl: system-controller@20050000 {
			compatible = "hisilicon,hi3535-sysctrl", "hisilicon,sysctrl", "syscon";
			reg = <0x20050000 0x1000>;
			smp-offset = <0x134>;
			#clock-cells = <1>;
			#reset-cells = <2>;
			reboot-offset = <0x4>;
		//	ranges = <0 0x20050000 0x1000>;
			/* sysctrl: clock@0 { */
			/* 	compatible = "hisilicon,hi3535-sysctrl"; */
			/* 	reg = <0x0 0x4>; */
			/* 	#clock-cells = <1>; */
			/* }; */
		};

		uart0: serial@20080000 {
			compatible = "arm,pl011";
			reg = <0x20080000 0x1000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&crg HI3535_UART0_CLK>, <&crg HI3535_UART0_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@20090000 {
			compatible = "arm,pl011";
			reg = <0x20090000 0x1000>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&crg HI3535_UART1_CLK>, <&crg HI3535_UART1_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@200a0000 {
			compatible = "arm,pl011";
			reg = <0x200a0000 0x1000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&crg HI3535_UART2_CLK>, <&crg HI3535_UART2_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@200b0000 {
			compatible = "arm,pl011";
			reg = <0x200b0000 0x1000>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&crg HI3535_UART3_CLK>, <&crg HI3535_UART3_CLK>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		dual_timer2: timer@20130000 {
			compatible = "arm,sp804";
			reg = <0x20130000 0x1000>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&sysctrl HI3535_TIMER0_CLK>,
					<&sysctrl HI3535_TIMER0_CLK>,
					<&sysctrl HI3535_TIMER0_CLK>;
			clock-names = "timer0clk", "timer1clk", "apb_pclk";
			status = "disabled";
		};

		dual_timer3: timer@20140000 {
			compatible = "arm,sp804";
			reg = <0x20140000 0x1000>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			clocks = <&sysctrl HI3535_TIMER0_CLK>,
					<&sysctrl HI3535_TIMER0_CLK>,
					<&sysctrl HI3535_TIMER0_CLK>;
			clock-names = "timer0clk", "timer1clk", "apb_pclk";
			status = "disabled";
		};

		gpio0: gpio@20150000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20150000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio1: gpio@20160000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20160000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio2: gpio@20170000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20170000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio3: gpio@20180000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20180000 0x1000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio4: gpio@20190000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20190000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio5: gpio@201a0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201a0000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio6: gpio@201b0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201b0000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio7: gpio@201c0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201c0000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio8: gpio@201d0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201d0000 0x1000>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio9: gpio@201e0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201e0000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio10: gpio@201f0000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x201f0000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio11: gpio@20200000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20200000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio12: gpio@20210000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20210000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio13: gpio@20220000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20220000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		gpio14: gpio@20230000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x20130000 0x1000>;
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
			gpio-controller;
			#gpio-cells = <2>;
			/* clocks = <&sysctrl HIX5HD2_FIXED_100M>; */
			/* clock-names = "apb_pclk"; */
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

		scu@20300000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x20300000 0x100>;
		};

		/* global_timer: global-timer@20300200 { */
		/* 	compatible = "arm,cortex-a9-global-timer"; */
		/* 	reg = <0x20300200 0x20>; */
		/* 	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; */
		/* }; */
		/**/
		/* local_timer: local-timer@20300600 { */
		/* 	compatible = "arm,cortex-a9-twd-timer"; */
		/* 	reg = <0x20300600 0x20>; */
		/* 	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; */
		/* }; */

		l2: cache-controller@20700000 {
			compatible = "arm,pl310-cache";
			reg = <0x20700000 0x100000>;
			cache-level = <2>;
			cache-unified;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};
	};
};