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hanetzer/stdin

Created June 9, 2022 14:11
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stdin
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stdin
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2017-2022 Marty Plummer <[email protected]>
*/
#include <dt-bindings/clock/hi3521a-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1100000000>;
};
};
/* timer { */
/* compatible = "arm,armv7-timer"; */
/* interrupt-parent = <&gic>; */
/* interrupts = <GIC_PPI 13 0xf08>, */
/* <GIC_PPI 14 0xf08>, */
/* <GIC_PPI 11 0xf08>, */
/* <GIC_PPI 10 0xf08>; */
/* clock-frequency = <24000000>; */
/* }; */
pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@10301000 {
compatible = "arm,pl390";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
};
xtal24m: xtal24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
hi_sfc: spi@10000000 {
compatible = "hisilicon,hi3521a-spi-nor", "hisilicon,fmc-spi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
reg-names = "control", "memory";
clocks = <&crg HI3521A_FMC_CLK>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
/* usb0: usb@10030000 { */
/* compatible = "generic-ohci"; */
/* reg = <0x10030000 0x1000>; */
/* interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; */
/* clocks = <&crg > */
/* }; */
dmac: dma-controller@10060000 {
compatible = "arm,pl080", "arm,primecell";
arm,primecell-periphid = <0x00041080>;
reg = <0x10060000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_DMAC_CLK>;
clock-names = "apb_pclk";
lli-bus-interface-ahb1;
lli-bus-interface-ahb2;
mem-bus-interface-ahb1;
mem-bus-interface-ahb2;
memcpy-burst-size = <256>;
memcpy-bus-width = <32>;
#dma-cells = <2>;
status = "okay";
};
gmac0: ethernet@100a0000 {
compatible = "hisilicon,hisi-gmac-v1";
reg = <0x100a0000 0x1000>, <0x1204008c 0x4>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_GMAC_CLK>;
clock-names = "mac_core";
/* resets = <&crg 0x78 0>, <&crg 0x78 2>, <&crg 0x78 5>; */
/* reset-names = "mac_core", "mac_ifc", "phy"; */
/* hisilicon,phy-reset-delays-us = <10000 10000 30000>; */
status = "disabled";
};
sata_phy: phy@11010000 {
compatible = "hisilicon,hi3521a-sata-phy";
reg = <0x11010000 0x10000>;
//#address-cells = <1>;
//#size-cells = <0>;
#phy-cells = <0>;
status = "okay";
//sata-phy@0 {
//reg = <0>;
//};
//sata-phy@1 {
//reg = <1>;
//};
};
ahci: sata@11010000 {
compatible = "hisilicon,hisi-ahci", "generic-ahci";
//compatible = "generic-ahci";
reg = <0x11010000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_SATA_CLK>;
phys = <&sata_phy>;
phy-names = "sata-phy";
status = "okay";
//#address-cells = <1>;
//#size-cells = <0>;
//sata0: sata-port@0 {
//reg = <0>;
//phys = <&sata_phy 0>;
//};
//sata1: sata-port@1 {
//reg = <1>;
//phys = <&sata_phy 1>;
//};
};
dual_timer0: timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12000000 0x1000>;
clocks = <&sysctrl HI3521A_TIMER0_CLK>,
<&sysctrl HI3521A_TIMER1_CLK>,
<&crg HI3521A_SYSAXI_CLK>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "okay";
};
dual_timer1: timer@12010000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12010000 0x1000>;
clocks = <&sysctrl HI3521A_TIMER2_CLK>,
<&sysctrl HI3521A_TIMER3_CLK>,
<&crg HI3521A_SYSAXI_CLK>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer2: timer@12020000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12020000 0x1000>;
clocks = <&sysctrl HI3521A_TIMER4_CLK>,
<&sysctrl HI3521A_TIMER5_CLK>,
<&crg HI3521A_SYSAXI_CLK>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
dual_timer3: timer@12030000 {
compatible = "arm,sp804", "arm,primecell";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12030000 0x1000>;
clocks = <&sysctrl HI3521A_TIMER6_CLK>,
<&sysctrl HI3521A_TIMER7_CLK>,
<&crg HI3521A_SYSAXI_CLK>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
crg: clock-reset-controller@12040000 {
compatible = "hisilicon,hi3521a-crg";
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12040000 0x1000>;
};
sysctrl: system-controller@12050000 {
compatible = "hisilicon,hi3521a-sysctrl", "syscon";
reg = <0x12050000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
wdt0: watchdog@12070000 {
compatible = "arm,sp805", "arm,primecell";
arm,primecell-periphid = <0x00141805>;
reg = <0x12070000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_FIXED_3M>;
clock-names = "apb_pclk";
status = "okay";
};
uart0: serial@12080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12080000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_UART0_CLK>, <&crg HI3521A_UART0_CLK>;
clock-names = "uartclk", "apb_pclk";
dmas = <&dmac 0 1>, <&dmac 1 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@12090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12090000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_UART1_CLK>;
clock-names = "apb_pclk";
dmas = <&dmac 2 1>, <&dmac 3 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@120a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x120a0000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_UART2_CLK>;
clock-names = "apb_pclk";
dmas = <&dmac 4 1>, <&dmac 5 2>;
dma-names = "rx", "tx";
status = "disabled";
};
spi_bus0: spi@120d0000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x120d0000 0x1000>;
arm,primecell-periphid = <0x00041022>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HI3521A_SPI0_CLK>;
clock-names = "apb_pclk";
dmas = <&dmac 6 1>, <&dmac 7 2>;
dma-names = "rx", "tx";
num-cs = <2>;
status = "disabled";
};
pmx0: pinmux@120f0000 {
compatible = "pinctrl-single";
reg = <0x120f0000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
#gpio-range-cells = <3>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <
&range 58 4 0
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@120f0800 {
compatible = "pinconf-single";
reg = <0x120f0800 0x1d4>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
};
gpio0: gpio@12150000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12150000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio1: gpio@12160000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12160000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio2: gpio@12170000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12170000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio3: gpio@12180000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12180000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio4: gpio@12190000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12190000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio5: gpio@121a0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121a0000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio6: gpio@121b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121b0000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio7: gpio@121c0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121c0000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio8: gpio@121d0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121d0000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio9: gpio@121e0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121e0000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio10: gpio@121f0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x121f0000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio11: gpio@12200000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12200000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio12: gpio@12210000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12210000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
gpio13: gpio@12220000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x12220000 0x1000>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
};
};
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