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Created September 7, 2022 08:40
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stdin
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stdin
Namespace(file='u-boot-hi3516dv300_emmc.reg', svd='hi3516dv300.svd', offset=0, size=0)
reg value delay attrs
0x12010080 0x00000000 0x00000000 0x000000fd WRITE CRG:PERI_CRG32[31:0] (SoC clock selection register)
field sysapb_cksel[11:10] (SYSAPB clock select)
field syscfg_cksel[9:8] (SYSCFG clock select)
field sysaxi_cksel[8:6] (SYSAXI clock select)
field ddr_cksel[6:3] (DDR SDRAM clock select)
field a7_cksel[3:0] (A7 clock select)
0x120101e0 0x00000000 0x00000000 0x00550000 READ CRG:PERI_CRG120[10:0] (SoC frequency indicator register)
field fmc_sc_seled[15:12] (FMC clock switch completion indicator)
0x00000000 0x00000000 0x00000064 0x00000000 DELAY 100
0x12010010 0x12d55555 0x00000000 0x000000fd WRITE CRG:CRG_PLL4[31:0] (EPLL configuration register 0)
0x12010014 0x0000102d 0x00000000 0x000000fd WRITE CRG:CRG_PLL5[31:0] (EPLL configuration register 1)
0x00000000 0x00000000 0x00000064 0x00000000 DELAY 100
0x120101e8 0x0000000f 0x00000000 0x001d0000 READ CRG:PERI_CRG_PLL122[3:0] (PLL lock status register)
field epll_lock[4:3] (EPLL lock status)
field vpll_lock[3:2] (VPLL lock status)
field dpll_lock[2:1] (DPLL lock status)
field apll_lock[1:0] (APLL lock status)
0x12010080 0x0000059b 0x00000000 0x000000fd WRITE CRG:PERI_CRG32[31:0] (SoC clock selection register)
field sysapb_cksel[11:10] (SYSAPB clock select)
field syscfg_cksel[9:8] (SYSCFG clock select)
field sysaxi_cksel[8:6] (SYSAXI clock select)
field ddr_cksel[6:3] (DDR SDRAM clock select)
field a7_cksel[3:0] (A7 clock select)
0x120101e0 0x0000059b 0x00000000 0x00550000 READ CRG:PERI_CRG120[10:0] (SoC frequency indicator register)
field fmc_sc_seled[15:12] (FMC clock switch completion indicator)
0x00000000 0x00000000 0x00000064 0x00000000 DELAY 100
0x12020090 0x100017ff 0x00000000 0x000000fd WRITE SYSCTL:SC_DDR_HW_PHY0_RANK0[31:0] (DDR PHY0 hardware training item rank 0)
0x12020094 0x00000000 0x00000000 0x000000fd WRITE SYSCTL:SC_DDR_HW_PHY0_RANK1[31:0] (DDR PHY0 hardware training item rank 1)
0x120200a0 0xffffffff 0x00000000 0x000000fd WRITE SYSCTL:SC_DDR_TRAINING_CFG[31:0] (DDR hardware training item cfg)
0x120200a8 0xc5a5720f 0x00000000 0x000000fd WRITE SYSCTL:SC_DDRT_PATTERN[31:0] (DDRT reversed data)
0x1202009c 0x00000000 0x00000000 0x000000fd WRITE SYSCTL:SC_DDR_HW_PHY1_RANK1[31:0] (DDR PHY1 hardware training item rank 1)
0x111f002c 0x00000600 0x00000000 0x000000fd WRITE IOCTRL1:iocfg_reg62[31:0] (Pin SVB_PWM IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x120300b0 0x00480c75 0x00000000 0x000000fd WRITE MISC:MISC_CTRL44[31:0] (SVB control register)
field svb_pwm_duty[26:16] (Number of high level times in a PWM period of the SVB output. The actual number is the configured value plus 1.)
0x120300b4 0xc0400000 0x00000000 0x000000fd WRITE MISC:MISC_CTRL45[31:0] (T-Sensor control register)
field tsensor_en[32:31] (T-Sensor enable)
field tsensor_monitor_en[31:30] (Cyclic temperature monitoring enable of T-Sensor)
field tsensor_monitor_period[28:20] (Cycle monitoring period of the T-Sensor. The timing reference is 2ms)
field tsensor_uplimit[20:10] (Upper limit of the temperature)
field tsensor_lowlimit[10:0] (Lower limit of the temperature)
0x120300d0 0x60000211 0x001e8480 0x000000fd WRITE MISC:MISC_CTRL52[31:0] (HPM control register 0)
0x120200ac 0x00000010 0x00000000 0x0000c03d WRITE SYSCTL:SC_DDR_TRAINING_VERSION_FLAG[31:24] (DDR training version flag)
0x12061004 0x000000a5 0x00000000 0x000000fd WRITE DDRC_TZASC:SEC_BYPASS[31:0] (Security function enable)
0x12060020 0x000fff01 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_ACTION[31:0] (AXI operating mode register)
0x12060008 0x00013fff 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_CKG[31:0] (Module clock gating register)
0x1206000c 0xffffffff 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_CKG_RD[31:0] (Pulled from xlsx)
0x12060010 0xffffffff 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_CKG_WD[31:0] (Pulled from xlsx)
0x12064088 0x0000001d 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_BUF_BYP[31:0] (QoSBuf bypass control register)
0x1206803c 0x00000010 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_POWER_CTRL[31:0] (Pulled from xlsx)
0x12060100 0x00001680 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_REGION0_MAP[31:0] (Address region %s mapping register)
field rgn_en[13:12] (Current address region enable)
field rgn_size[11:8] (Size of the current address region)
0x12060104 0x70050014 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_REGION0_ATTRIB[31:0] (Address region %s attribute register)
0x12068040 0x00012401 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_WORKMODE[31:0] (DDRC operating mode register)
0x12068050 0x00c10226 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_DDRMODE[31:0] (DDR SDRAM operating mode register)
0x12068060 0x00000142 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_RNKVOLn[31:0] (DDRC-controlled DDR SDRAM capacity configuration register)
0x12068100 0x3339d710 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING0[31:0] (DDRC timing parameter register 0)
0x12068104 0x4140090d 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING1[31:0] (DDRC timing parameter register 1)
0x12068108 0x5401106c 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING2[31:0] (DDRC timing parameter register 2)
0x1206810c 0x57896724 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING3[31:0] (DDRC timing parameter register 3)
0x12068110 0x00800000 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING4[31:0] (DDRC timing parameter register 4)
0x12068114 0x00041308 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING5[31:0] (DDRC timing parameter register 5)
0x12068118 0x00000066 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING6[31:0] (DDRC timing parameter register 6)
0x12068120 0x04623007 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_TIMING8[31:0] (DDRC timing parameter register 8)
0x120680a0 0x00000001 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_ODT[31:0] (DDRC SDRAM ODT configuration register)
0x12068200 0x001f0000 0x00000000 0x000000fd WRITE DDRC_DMC:DDRC_CFG_DDRPHY[31:0] (DDRC SDRAM I/O configuration register)
0x12068600 0x00044800 0x00000000 0x000000fd WRITE DDRC_DMC:DMC0_EFFI[31:0] (TODO pulled from xlsx)
0x1206d01c 0x08c00000 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_ACPLL[31:0] (TODO pulled from xlsx)
0x1206d234 0x000008c0 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_DX0PLL[31:0] (TODO pulled from xlsx)
0x1206d334 0x000008c0 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_DX1PLL[31:0] (TODO pulled from xlsx)
0x1206d020 0x0000000a 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_PLLCTRL_AC[31:0] (TODO pulled from xlsx)
0x1206d210 0x0000000a 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_PLLCTRL_DX0[31:0] (TODO pulled from xlsx)
0x1206d310 0x0000000a 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_PLLCTRL_DX1[31:0] (TODO pulled from xlsx)
0x1206c01c 0x0c000080 0x00000000 0x000000fd WRITE DDRC_PHY:PACK_PLLTMR[31:0] (TODO pulled from xlsx)
0x1206c010 0x000a00c0 0x00000000 0x000000fd WRITE DDRC_PHY:PACK_PHYTMR0[31:0] (TODO pulled from xlsx)
0x1206c014 0xf0006400 0x00000000 0x000000fd WRITE DDRC_PHY:PACK_PHYTMR1[31:0] (TODO pulled from xlsx)
0x1206c030 0x34892221 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER0[31:0] (DDR PHY timing parameter register 0)
0x1206c034 0x168d1285 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER1[31:0] (DDR PHY timing parameter register 1)
0x1206c038 0x20082208 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER2[31:0] (DDR PHY timing parameter register 2)
0x1206c03c 0x5000052c 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER3[31:0] (DDR PHY timing parameter register 3)
0x1206c040 0x4034657c 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER4[31:0] (DDR PHY timing parameter register 4)
0x1206c0bc 0x00000009 0x00000000 0x000000fd WRITE DDRC_PHY:DRAMTIMER5[31:0] (DDR PHY timing parameter register 5)
0x1206c064 0x00401014 0x00000000 0x000000fd WRITE DDRC_PHY:MODEREG01[31:0] (SDRAM mode register 01)
0x1206c068 0x00000020 0x00000000 0x000000fd WRITE DDRC_PHY:MODEREG23[31:0] (SDRAM mode register 23)
0x1206c074 0x20000000 0x00000000 0x000000fd WRITE DDRC_PHY:RNK2RNK[31:0] (TODO pulled from xlsx)
0x1206c070 0x08100908 0x00000000 0x000000fd WRITE DDRC_PHY:MISC[31:0] (DDR PHY control register with miscellaneous functions)
0x1206c084 0x0010410a 0x00000000 0x000000fd WRITE DDRC_PHY:DMSEL[31:0] (TODO pulled from xlsx)
0x1206d208 0x0002d85c 0x00000000 0x000000fd WRITE DDRC_PHY:LDQSSEL[31:0] (TODO pulled from xlsx)
0x1206d308 0x0002fd40 0x00000000 0x000000fd WRITE DDRC_PHY:HDQSSEL[31:0] (TODO pulled from xlsx)
0x1206c0b0 0xa0011010 0x00000000 0x000000fd WRITE DDRC_PHY:PHYRSCTRL[31:0] (TODO pulled from xlsx)
0x1206c078 0x00003184 0x00000000 0x000000fd WRITE DDRC_PHY:PHYCTRL0[31:0] (TODO pulled from xlsx)
0x1206c208 0x00f80000 0x00000000 0x000000fd WRITE DDRC_PHY:DXCTRL(BYTE0)[31:0] (TODO pulled from xlsx)
0x1206c288 0x00f80000 0x00000000 0x000000fd WRITE DDRC_PHY:DXCTRL(BYTE1)[31:0] (TODO pulled from xlsx)
0x1206c308 0x00f80000 0x00000000 0x000000fd WRITE DDRC_PHY:DXCTRL(BYTE2)[31:0] (TODO pulled from xlsx)
0x1206c388 0x00f80000 0x00000000 0x000000fd WRITE DDRC_PHY:DXCTRL(BYTE3)[31:0] (TODO pulled from xlsx)
0x1206c02c 0x001c0022 0x00000000 0x000000fd WRITE DDRC_PHY:PACK_DRAMCFG[31:0] (TODO pulled from xlsx)
0x1206c080 0x00010400 0x00000000 0x000000fd WRITE DDRC_PHY:RECTRL0[31:0] (TODO pulled from xlsx)
0x1206c044 0x00000001 0x00000000 0x000000fd WRITE DDRC_PHY:ODTCR[31:0] (TODO pulled from xlsx)
0x1206c020 0x04100461 0x00000000 0x000000fd WRITE DDRC_PHY:DLYMEASCTRL[31:0] (TODO pulled from xlsx)
0x1206c048 0x60cb00c0 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL0[31:0] (TODO pulled from xlsx)
0x1206c0d0 0xf806fb06 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL1[31:0] (TODO pulled from xlsx)
0x1206c0dc 0xca620040 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL3[31:0] (TODO pulled from xlsx)
0x1206c114 0x28032102 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL4[31:0] (TODO pulled from xlsx)
0x1206c118 0x02040200 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL5[31:0] (TODO pulled from xlsx)
0x1206c11c 0x03000090 0x00000000 0x000000fd WRITE DDRC_PHY:TRAINCTRL7[31:0] (TODO pulled from xlsx)
0x1206c024 0x88008220 0x00000000 0x000000fd WRITE DDRC_PHY:IMPCTRL[31:0] (TODO pulled from xlsx)
0x1206c170 0x83000120 0x00000000 0x000000fd WRITE DDRC_PHY:IMP_CTRL1[31:0] (TODO pulled from xlsx)
0x1206c194 0xffff000c 0x00000000 0x000000fd WRITE DDRC_PHY:ACPHYRSVDC[31:0] (TODO pulled from xlsx)
0x1206c124 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:ZQCAL offset control[31:0] (TODO pulled from xlsx)
0x1206d018 0x23de0001 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL(AC)[31:0] (TODO pulled from xlsx)
0x1206d204 0x2403b005 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL(DX0)[31:0] (TODO pulled from xlsx)
0x1206d304 0x2403b005 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL(DX1)[31:0] (TODO pulled from xlsx)
0x1206d028 0x0003cf03 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL2[31:0] (TODO pulled from xlsx)
0x1206d024 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL1[31:0] (TODO pulled from xlsx)
0x1206d21c 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL2(DX0)[31:0] (TODO pulled from xlsx)
0x1206d31c 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL2(DX1)[31:0] (TODO pulled from xlsx)
0x1206c274 0x00000008 0x00000000 0x000000fd WRITE DDRC_PHY:HVREF_STATUS(0)[31:0] (TODO pulled from xlsx)
0x1206c2f4 0x00000008 0x00000000 0x000000fd WRITE DDRC_PHY:HVREF_STATUS(1)[31:0] (TODO pulled from xlsx)
0x1206c374 0x00000008 0x00000000 0x000000fd WRITE DDRC_PHY:HVREF_STATUS(2)[31:0] (TODO pulled from xlsx)
0x1206c3f4 0x00000008 0x00000000 0x000000fd WRITE DDRC_PHY:HVREF_STATUS(3)[31:0] (TODO pulled from xlsx)
0x1206d218 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL1(DX0)[31:0] (TODO pulled from xlsx)
0x1206d318 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL1(DX1)[31:0] (TODO pulled from xlsx)
0x1206d0c8 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL5(AC)[31:0] (TODO pulled from xlsx)
0x1206d248 0x00303656 0x00000000 0x000000fd WRITE DDRC_PHY:DX(0)MISCCTRL2[31:0] (TODO pulled from xlsx)
0x1206d2c8 0x00303656 0x00000000 0x000000fd WRITE DDRC_PHY:DX(1)MISCCTRL2[31:0] (TODO pulled from xlsx)
0x1206d348 0x00303656 0x00000000 0x000000fd WRITE DDRC_PHY:DX(2)MISCCTRL2[31:0] (TODO pulled from xlsx)
0x1206d3c8 0x00303656 0x00000000 0x000000fd WRITE DDRC_PHY:DX(3)MISCCTRL2[31:0] (TODO pulled from xlsx)
0x1206c1d4 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:ADDRPHBOUND[31:0] (TODO pulled from xlsx)
0x1206d260 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL4(DX0)[31:0] (TODO pulled from xlsx)
0x1206d360 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:IOCTL4(DX1)[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x55aa55aa 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000001 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x55aa55aa 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000002 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x33cc33cc 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000003 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x33cc33cc 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000004 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x66996699 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000005 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x66996699 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000006 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xc33cc33c 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000007 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xc33cc33c 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000008 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xff00ff00 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000009 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x00ff00ff 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000200 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x55aa55aa 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000201 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x33cc33cc 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000202 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x66996699 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000203 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xc33cc33c 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000204 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xff00ff00 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000205 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x00ff00ff 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000208 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0x55555555 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c0ec 0x00000209 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATINDEX[31:0] (TODO pulled from xlsx)
0x1206c06c 0xaaaaaaaa 0x00000000 0x000000fd WRITE DDRC_PHY:DETPATTERN[31:0] (TODO pulled from xlsx)
0x1206c00c 0x00182000 0x00000000 0x000000fd WRITE DDRC_PHY:PHYCLKGATED[31:0] (TODO pulled from xlsx)
0x1206c1fc 0xc0003048 0x00000000 0x000000fd WRITE DDRC_PHY:DFIMISCCTRL[31:0] (TODO pulled from xlsx)
0x1206c200 0x2501ff01 0x00000000 0x000000fd WRITE DDRC_PHY:DX0BISTCTRL[31:0] (TODO pulled from xlsx)
0x1206c280 0x2501ff01 0x00000000 0x000000fd WRITE DDRC_PHY:DX1BISTCTRL[31:0] (TODO pulled from xlsx)
0x1206c300 0x2501ff01 0x00000000 0x000000fd WRITE DDRC_PHY:DX2BISTCTRL[31:0] (TODO pulled from xlsx)
0x1206c380 0x2501ff01 0x00000000 0x000000fd WRITE DDRC_PHY:DX3BISTCTRL[31:0] (TODO pulled from xlsx)
0x1206c054 0x10008262 0x00000000 0x000000fd WRITE DDRC_PHY:BISTCTRL[31:0] (TODO pulled from xlsx)
0x1206c0c0 0xc0400f04 0x00000000 0x000000fd WRITE DDRC_PHY:DDRC_PHY_REG48[31:0] (TODO not referenced)
0x1206c0c4 0x8c302032 0x00000000 0x000000fd WRITE DDRC_PHY:DDRC_PHY_REG49[31:0] (TODO not referenced)
0x1206c0c8 0x0181001f 0x00000000 0x000000fd WRITE DDRC_PHY:DDRC_PHY_REG50[31:0] (TODO not referenced)
0x1206c1f0 0x0003aaa7 0x00000000 0x000000fd WRITE DDRC_PHY:DDRC_PHY_REG124[31:0] (TODO not referenced)
0x1206d070 0x00802080 0x00000000 0x000000fd WRITE DDRC_PHY:AC_CKPHASE[31:0] (TODO pulled from xlsx)
0x1206d050 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_CKBDL[31:0] (TODO pulled from xlsx)
0x1206d038 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ODTBDL[31:0] (TODO pulled from xlsx)
0x1206c128 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_CSBDL[31:0] (TODO pulled from xlsx)
0x1206d048 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_CKEBDL[31:0] (TODO pulled from xlsx)
0x1206d0ac 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_CASBDL[31:0] (TODO pulled from xlsx)
0x1206d0b0 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_RASBDL[31:0] (TODO pulled from xlsx)
0x1206d0b4 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_BA01BDL[31:0] (TODO pulled from xlsx)
0x1206d0b8 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_BA2BDL[31:0] (TODO pulled from xlsx)
0x1206c140 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD01[31:0] (TODO pulled from xlsx)
0x1206c144 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD23[31:0] (TODO pulled from xlsx)
0x1206c148 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD45[31:0] (TODO pulled from xlsx)
0x1206c14c 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD67[31:0] (TODO pulled from xlsx)
0x1206c150 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD89[31:0] (TODO pulled from xlsx)
0x1206d0bc 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD10BDL[31:0] (TODO pulled from xlsx)
0x1206d0c0 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD12BDL[31:0] (TODO pulled from xlsx)
0x1206d0c4 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:AC_ADD14BDL[31:0] (TODO pulled from xlsx)
0x1206c210 0x00020306 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL0[31:0] (TODO pulled from xlsx)
0x1206c214 0x00040000 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL1[31:0] (TODO pulled from xlsx)
0x1206c218 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL2[31:0] (TODO pulled from xlsx)
0x1206c290 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL0[31:0] (TODO pulled from xlsx)
0x1206c294 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL1[31:0] (TODO pulled from xlsx)
0x1206c298 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL2[31:0] (TODO pulled from xlsx)
0x1206c310 0x05000806 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL0[31:0] (TODO pulled from xlsx)
0x1206c314 0x06020801 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL1[31:0] (TODO pulled from xlsx)
0x1206c318 0x00000009 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL2[31:0] (TODO pulled from xlsx)
0x1206c390 0x06090a07 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL0[31:0] (TODO pulled from xlsx)
0x1206c394 0x08070708 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL1[31:0] (TODO pulled from xlsx)
0x1206c398 0x00000009 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQNBDL2[31:0] (TODO pulled from xlsx)
0x1206c234 0x00000b00 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQDLY[31:0] (TODO pulled from xlsx)
0x1206c2b4 0x00000b00 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQDLY[31:0] (TODO pulled from xlsx)
0x1206c334 0x00000b00 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQDLY[31:0] (TODO pulled from xlsx)
0x1206c3b4 0x00000b00 0x00000000 0x000000fd WRITE DDRC_PHY:DXNWDQDLY[31:0] (TODO pulled from xlsx)
0x1206c004 0x0000a000 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_PHYINITTRL[31:0] (TODO pulled from xlsx)
0x1206c004 0x00000000 0x00000000 0x000000fd WRITE DDRC_PHY:PHY0_PHYINITTRL[31:0] (TODO pulled from xlsx)
0x12060200 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP0[31:0] (Command priority mapping mode register %s)
0x12060210 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP1[31:0] (Command priority mapping mode register %s)
0x12060220 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP2[31:0] (Command priority mapping mode register %s)
0x12060230 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP3[31:0] (Command priority mapping mode register %s)
0x12060240 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP4[31:0] (Command priority mapping mode register %s)
0x12060250 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP5[31:0] (Command priority mapping mode register %s)
0x12060260 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP6[31:0] (Command priority mapping mode register %s)
0x12060270 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP7[31:0] (Command priority mapping mode register %s)
0x12060280 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP8[31:0] (Command priority mapping mode register %s)
0x12060290 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP9[31:0] (Command priority mapping mode register %s)
0x120602a0 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP10[31:0] (Command priority mapping mode register %s)
0x120602b0 0x00110000 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_MAP11[31:0] (Command priority mapping mode register %s)
0x12060204 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI0[31:0] (Write command priority mapping table register %s)
0x12060214 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI1[31:0] (Write command priority mapping table register %s)
0x12060224 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI2[31:0] (Write command priority mapping table register %s)
0x12060234 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI3[31:0] (Write command priority mapping table register %s)
0x12060244 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI4[31:0] (Write command priority mapping table register %s)
0x12060254 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI5[31:0] (Write command priority mapping table register %s)
0x12060264 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI6[31:0] (Write command priority mapping table register %s)
0x12060274 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI7[31:0] (Write command priority mapping table register %s)
0x12060284 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI8[31:0] (Write command priority mapping table register %s)
0x12060294 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI9[31:0] (Write command priority mapping table register %s)
0x120602a4 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI10[31:0] (Write command priority mapping table register %s)
0x120602b4 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_WRPRI11[31:0] (Write command priority mapping table register %s)
0x12060208 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI0[31:0] (Read command priority mapping table register %s)
0x12060218 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI1[31:0] (Read command priority mapping table register %s)
0x12060228 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI2[31:0] (Read command priority mapping table register %s)
0x12060238 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI3[31:0] (Read command priority mapping table register %s)
0x12060248 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI4[31:0] (Read command priority mapping table register %s)
0x12060258 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI5[31:0] (Read command priority mapping table register %s)
0x12060268 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI6[31:0] (Read command priority mapping table register %s)
0x12060278 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI7[31:0] (Read command priority mapping table register %s)
0x12060288 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI8[31:0] (Read command priority mapping table register %s)
0x12060298 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI9[31:0] (Read command priority mapping table register %s)
0x120602a8 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI10[31:0] (Read command priority mapping table register %s)
0x120602b8 0x01234567 0x00000000 0x000000fd WRITE DDRC_AXI:AXI_QOS_RDPRI11[31:0] (Read command priority mapping table register %s)
0x12064000 0x00000002 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_PUSH_CTRL[31:0] (TODO pulled from xlsx)
0x1206410c 0x0000000b 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_DMC0_LVL[31:0] (QoSBuf threshold register for commands that enter the DMC%s module)
0x12064110 0x0000000b 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_DMC1_LVL[31:0] (QoSBuf threshold register for commands that enter the DMC%s module)
0x12064088 0x00000001 0x00000000 0x0000000d WRITE DDRC_QOSBUF:QOSB_BUF_BYP[1:0] (QoSBuf bypass control register)
0x1206408c 0x90b20906 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_WBUF_CTRL[31:0] (TODO pulled from xlsx)
0x12064090 0x90b20906 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_WBUF_CTRL[31:0] (TODO pulled from xlsx)
0x12064068 0x00000051 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_BANK_CTRL[31:0] (TODO pulled from xlsx)
0x1206406c 0x00000051 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_BANK_CTRL[31:0] (TODO pulled from xlsx)
0x120640ec 0x00000011 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_ROWHIT_PRILVL[31:0] (TODO pulled from xlsx)
0x120640f0 0x00001111 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_ROWHIT_PRI[31:0] (TODO pulled from xlsx)
0x120640f4 0x00000033 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_ROWHIT_CTRL[31:0] (TODO pulled from xlsx)
0x120641f0 0x00000001 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_TIMEOUT_MODE[31:0] (QoSBuf timeout mode selection register)
0x120641f4 0x00000000 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_WBUF_PRI_CTRL[31:0] (TODO pulled from xlsx)
0x120641f8 0x00800002 0x00000000 0x000000fd WRITE DDRC_QOSBUF:QOSB_RHIT_CTRL[31:0] (TODO pulled from xlsx)
0x12030080 0x46576666 0x00000000 0x000000fd WRITE MISC:MISC_CTRL32[31:0] (MDDRC W QOS register 0)
0x12030084 0x30000071 0x00000000 0x000000fd WRITE MISC:MISC_CTRL33[31:0] (MDDRC W QOS register 1)
0x12030088 0x00444455 0x00000000 0x000000fd WRITE MISC:MISC_CTRL34[31:0] (MDDRC W QOS register 2)
0x1203008c 0x00000003 0x00000000 0x000000fd WRITE MISC:MISC_CTRL35[31:0] (MDDRC W QOS register 3)
0x12030090 0x56575677 0x00000000 0x000000fd WRITE MISC:MISC_CTRL36[31:0] (MDDRC R QOS register 0)
0x12030094 0x30000071 0x00000000 0x000000fd WRITE MISC:MISC_CTRL37[31:0] (MDDRC R QOS register 1)
0x12030098 0x00445455 0x00000000 0x000000fd WRITE MISC:MISC_CTRL38[31:0] (MDDRC R QOS register 2)
0x1203009c 0x00000003 0x00000000 0x000000fd WRITE MISC:MISC_CTRL39[31:0] (MDDRC R QOS register 3)
0x120db400 0x00000004 0x00000000 0x000000fd WRITE GPIO11:GPIO_DIR[31:0] (GPIO direction control register)
field gpio_data[8:0] (Indicates the GPIO input data when the GPIO is configured as input; indicates the GPIO output data when the GPIO is configured as output. Each bit can be controlled separately. The register is used together with GPIO_DIR.)
0x120db010 0x00000004 0x00000000 0x000000fd WRITE GPIO11:GPIO_DATA4[31:0] (GPIO data register %s)
field gpio_data[8:0] (Indicates the GPIO input data when the GPIO is configured as input; indicates the GPIO output data when the GPIO is configured as output. Each bit can be controlled separately. The register is used together with GPIO_DIR.)
0x12090000 0x000101e0 0x00000000 0x000000fd WRITE PMC:PWR_CTRL0[31:0] (PWR control register 0)
0x111f0010 0x00000531 0x00000000 0x000000fd WRITE IOCTRL1:iocfg_reg55[31:0] (Pin UART0_RXD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x111f0014 0x00000431 0x00000000 0x000000fd WRITE IOCTRL1:iocfg_reg56[31:0] (Pin UART0_TXD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x111f0008 0x00000531 0x00000000 0x000000fd WRITE IOCTRL1:iocfg_reg53[31:0] (Pin UART1_RXD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x111f000c 0x00000431 0x00000000 0x000000fd WRITE IOCTRL1:iocfg_reg54[31:0] (Pin UART1_RXD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x10ff003c 0x00000531 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg16[31:0] (Pin USB_OVERCUR IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x10ff0044 0x00000531 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg17[31:0] (Pin USB_PWREN IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x10ff0040 0x00000531 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg16[31:0] (Pin USB_VBUS IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f004c 0x00000561 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg84[31:0] (Pin RMII_CLK IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0050 0x00000471 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg85[31:0] (Pin RMII_RX_DV IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0058 0x00000431 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg87[31:0] (Pin RMII_RXD0 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0054 0x00000431 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg86[31:0] (Pin RMII_RXD1 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0044 0x00000471 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg82[31:0] (Pin RMII_TX_EN IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0048 0x00000471 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg83[31:0] (Pin RMII_TXD0 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0040 0x00000471 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg81[31:0] (Pin RMII_TXD1 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0060 0x00000461 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg89[31:0] (Pin EPHY_CLK IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f005c 0x000006f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg88[31:0] (Pin EPHY_RSTN IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f003c 0x00000411 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg80[31:0] (Pin MDCK IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x112f0038 0x00000431 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg79[31:0] (Pin MDIO IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x10ff0020 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg8[31:0] (Pin SDIO0_CARD_DETECT IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff001c 0x000006f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg7[31:0] (Pin SDIO0_CARD_POWER_EN IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
0x10ff0024 0x000006c1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg9[31:0] (Pin SDIO0_CCLK_OUT IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff0028 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg10[31:0] (Pin SDIO_CCMD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff002c 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg11[31:0] (Pin SDIO_CDATA0 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff0030 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg12[31:0] (Pin SDIO_CDATA1 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff0034 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg13[31:0] (Pin SDIO_CDATA2 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x10ff0038 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL0:iocfg_reg14[31:0] (Pin SDIO_CDATA3 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f0008 0x000006c1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg67[31:0] (Pin SDIO1_CCLK_OUT IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f000c 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg68[31:0] (Pin SDIO1_CCMD IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f0010 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg69[31:0] (Pin SDIO1_CDATA0 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f0014 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg70[31:0] (Pin SDIO1_CDATA1 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f0018 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg71[31:0] (Pin SDIO1_CDATA2 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f001c 0x000005f1 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg72[31:0] (Pin SDIO1_CDATA3 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-15 correspond to I/O drive capability IO16_level1-16, respectively.)
field mux[4:0] (Function Select)
0x112f00b0 0x00000131 0x00000000 0x000000fd WRITE IOCTRL2:iocfg_reg109[31:0] (Pin PWR_SEQ1 IO Config register)
field sl[11:10] (Level conversion rate control)
field pd_en[10:9] (Pull-down resistor enable, active high)
field pu_en[9:8] (Pull-up resistor enable, active high)
field ds[8:4] (Drive capability. Values 0-3 correspond to I/O drive capability IO2_level1-4, respectively.)
field mux[4:0] (Function Select)
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