test_fw.py

from myhdl import *
from functools import wraps
from argparse import *
from unittest import main 
import sys


_trace = False

def testmain():
    p = ArgumentParser(add_help=False)
    p.add_argument('--trace', action='store_true')

    options, args = p.parse_known_args()
    global _trace
    _trace = options.trace
    main(argv=sys.argv[:1] + args)

def trace(func):
    func.trace = True
    return func

def myhdltest(func):
    @wraps(func)
    def wrapper(self):
        @instance
        def stimulus():
            self.reset.next = False
            yield delay(3*getattr(self, 'clkfreq', 1))
            self.reset.next = True

            yield func(self)
            raise StopSimulation

        @always(delay(getattr(self, 'clkfreq', 1)))
        def clkGen():
            self.clk.next = not self.clk               


        tracedec = getattr(wrapper, 'trace', None)  # True or None
        tracesel = getattr(self, 'trace', None)  # True or None
        tracecmd = _trace  # True or False

        trace = (x for x in (tracedec, tracesel, tracecmd) if x is not None).next()
        # traceSignals.filename = "{}.{}".format(self.dut.__name__, func.func_name)
        
        g = traceSignals(self.dut, *self.args) if trace else self.dut(*self.args)
        
        Simulation(g, stimulus, clkGen).run()
    return wrapper

test_registerbank.py

from myhdl import *
from k0 import RegisterBank, ProcMode 
from k0 import trace, myhdltest, testmain 
from unittest import TestCase
from random import randint


class RB(TestCase):

    def setUp(self):
        self.clk = Signal(bool(False))
        self.reset = ResetSignal(0, 0, True)
        self.we = Signal(bool(False))
        self.rs, self.rd = [Signal(intbv(0)) for _ in range(2)]
        self.sout, self.din = [Signal(intbv(0)[32:]) for _ in range(2)]
        self.mode = Signal(ProcMode(ProcMode.User))

        self.args = (self.clk, self.reset, self.we, self.rs, self.rd, self.mode, self.din, self.sout)
        self.dut = RegisterBank

    @myhdltest
    def test_write_enable(self):
        """ Checks if the write_enable bit is respected """
        self.we.next = True
        yield self.clk.negedge

        self.rd.next = 0
        self.rs.next = 0
        self.din.next = 5
        yield self.clk.negedge

        self.assertEquals(5, self.sout)

        self.we.next = False
        yield self.clk.negedge

        self.din.next = 9
        yield self.clk.negedge

        self.assertEquals(5, self.sout)


    @myhdltest
    def test_write_read(self):
        """ Checks if basic write/read to registers work """
        self.we.next = True
        yield self.clk.negedge

        self.rd.next = 0
        self.rs.next = 0
        self.din.next = 0x8000
        yield self.clk.negedge
        self.assertEquals(0x8000, self.sout)

        self.din.next = 0xFFFFFFFF
        yield self.clk.negedge
        self.assertEquals(0xFFFFFFFF, self.sout)

        self.din.next = 0x0
        yield self.clk.negedge
        self.assertEquals(0, self.sout)

        self.din.next = 0xAAAAAAAA
        yield self.clk.negedge
        self.assertEquals(0xAAAAAAAA, self.sout)

        for i in xrange(300):
            val = randint(0, 2**31)
            self.din.next = val
            yield self.clk.negedge
            self.assertEquals(val, self.sout)

    @myhdltest
    def test_mode_change(self):
        """ Checks if mode changing works, so the register values are preserved """
        pass
        
    @myhdltest
    def test_channel_change(self):
        """ Testing if channel changings works and values are preserverd during change """
        pass
        
if __name__ == '__main__':
    testmain()