regbank.py

from myhdl import *

R0 = 0
R1 = 1
R2 = 2
R3 = 3
R4 = 4
R5 = 5
R6 = 6
R7 = 7
R8 = 8
R9 = 9
R10 = 10
R11 = 11
R12 = 12
R13 = 13
R14 = 14
PC = 15
CPSR = 16

R13_svc = 17
R14_svc = 18
SPSR_svc = 19

R13_abt = 20
R14_abt = 21
SPSR_abt = 22

R13_und = 23
R14_und = 24
SPSR_und = 25

R13_irq = 26
R14_irq = 27
SPSR_irq = 28

R8_fiq = 29
R9_fiq = 30
R10_fiq = 31
R11_fiq = 32
R12_fiq = 33
R13_fiq = 34
R14_fiq = 35
SPSR_fiq = 36

# normally these are in an extra file
procmode_User = 0b10000
procmode_FIQ = 0b10001
procmode_IRQ = 0b10010
procmode_Supervisor = 0b10011
procmode_Abort = 0b101111
procmode_Undefined = 0b11011
procmode_System = 0b11111

regbank = {
        procmode_User : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, PC, CPSR),
        procmode_Supervisor : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_svc, R14_svc, PC, CPSR, SPSR_svc),
        procmode_Abort : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_abt, R14_abt, PC, CPSR, SPSR_abt),
        procmode_Undefined : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_und, R14_und, PC, CPSR, SPSR_und),
        procmode_IRQ : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_irq, R14_irq, PC, CPSR, SPSR_irq),
        procmode_FIQ : (R0, R1, R2, R3, R4, R5, R6, R7, R8_fiq, R9_fiq, R10_fiq, R11_fiq, R12_fiq, R13_fiq, R14_fiq, PC, CPSR, SPSR_fiq)
        }


USER = (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, PC, CPSR)
SUPERVISOR = (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_svc, R14_svc, PC, CPSR, SPSR_svc)
ABORT = (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_abt, R14_abt, PC, CPSR, SPSR_abt)
UNDEFINED = (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_und, R14_und, PC, CPSR, SPSR_und)
IRQ = (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13_irq, R14_irq, PC, CPSR, SPSR_irq)
FIQ = (R0, R1, R2, R3, R4, R5, R6, R7, R8_fiq, R9_fiq, R10_fiq, R11_fiq, R12_fiq, R13_fiq, R14_fiq, PC, CPSR, SPSR_fiq)


def RegisterBank(clk, reset, we, rs, rd, mode, sout, din):
    regs = [Signal(intbv(0)[32:]) for _ in range(37)]


    def getRegisterbank():
        if mode == procmode_User:
            return USER
        elif mode == procmode_FIQ:
            return FIQ
        # ...
        else:
            return UNDEFINED

    @always_seq(clk.posedge, reset=reset)
    def write():
        if we:
            #regs[regbank[mode][rd]].next = din  # first version -> not supported: dict
            # regs[getRegisterbank()[rd]].next = din  # second version -> var MYHDL2_getRegisterbank has unexpected type: _ROM

            if mode == procmode_User:  # third version -> not supported: tuple
                regs[USER[rd]].next = din
            elif mode == procmode_FIQ:
                regs[FIQ[rd]].next = din
            # ...
            else:
                regs[UNDEFINED[rd]].next = din

#    @always_comb
#    def read():
#        sout.next = regs[regbank[mode][rs]]

    return write