An example VHDL file showing a clock being written, with an assignment inbetween.

output_assignment.vhd

-- File: /tmp/tmpsSOg4v/dut_convertible_top.vhd
-- Generated by MyHDL 0.9dev
-- Date: Fri Apr  3 10:04:52 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_09.all;

entity dut_convertible_top is
end entity dut_convertible_top;
-- Acts as a top-level MyHDL method, implementing a portable, 
-- convertible version of the SynchronousTest object wrapping the 
-- device under test.
-- 
-- The test vector that serves as the stimulus to all the inputs (except
-- the clock) is generated by calls to the :meth:`cosimulate` method.
-- :meth:`cosimulate` should be run for at least as many cycles as is
-- the simulation of :meth:`dut_convertible_top`. If
-- cosimulate is run for fewer cycles than :meth:`dut_convertible_top`, 
-- the result is undefined.

architecture MyHDL of dut_convertible_top is


constant lut_length: integer := 33;



signal reset: std_logic;
signal copied_signal: std_logic;
signal each_sub_signal: std_logic;
signal test_input0: signed (10 downto 0);
signal output: signed (10 downto 0);

begin




DUT_CONVERTIBLE_TOP_INSTANCES_0_LUT_DRIVER: process is
    variable lut_idx: unsigned(5 downto 0);
begin
    lut_idx := to_unsigned(0, 6);
    while True loop
        case to_integer(lut_idx) is
            when 0 => reset <= '1';
            when 1 => reset <= '1';
            when 2 => reset <= '1';
            when 3 => reset <= '0';
            when 4 => reset <= '0';
            when 5 => reset <= '0';
            when 6 => reset <= '0';
            when 7 => reset <= '0';
            when 8 => reset <= '0';
            when 9 => reset <= '0';
            when 10 => reset <= '0';
            when 11 => reset <= '0';
            when 12 => reset <= '0';
            when 13 => reset <= '0';
            when 14 => reset <= '0';
            when 15 => reset <= '0';
            when 16 => reset <= '0';
            when 17 => reset <= '0';
            when 18 => reset <= '0';
            when 19 => reset <= '0';
            when 20 => reset <= '0';
            when 21 => reset <= '0';
            when 22 => reset <= '0';
            when 23 => reset <= '0';
            when 24 => reset <= '0';
            when 25 => reset <= '0';
            when 26 => reset <= '0';
            when 27 => reset <= '0';
            when 28 => reset <= '0';
            when 29 => reset <= '0';
            when 30 => reset <= '0';
            when 31 => reset <= '0';
            when others => reset <= '0';
        end case;
        wait until rising_edge(each_sub_signal);
        if ((lut_idx + 1) >= lut_length) then
            lut_idx := to_unsigned(0, 6);
        else
            lut_idx := (lut_idx + 1);
        end if;
    end loop;
    wait;
end process DUT_CONVERTIBLE_TOP_INSTANCES_0_LUT_DRIVER;


DUT_CONVERTIBLE_TOP_INSTANCES_1_LUT_DRIVER: process is
    variable lut_idx: unsigned(5 downto 0);
begin
    lut_idx := to_unsigned(0, 6);
    while True loop
        case to_integer(lut_idx) is
            when 0 => test_input0 <= "00000000000";
            when 1 => test_input0 <= "00000000000";
            when 2 => test_input0 <= "00000000000";
            when 3 => test_input0 <= "00000000000";
            when 4 => test_input0 <= "00011111111";
            when 5 => test_input0 <= "11000110111";
            when 6 => test_input0 <= "00011000101";
            when 7 => test_input0 <= "10111001000";
            when 8 => test_input0 <= "10001111111";
            when 9 => test_input0 <= "10011111110";
            when 10 => test_input0 <= "01110010011";
            when 11 => test_input0 <= "11111000010";
            when 12 => test_input0 <= "00101000110";
            when 13 => test_input0 <= "10011110101";
            when 14 => test_input0 <= "11010100001";
            when 15 => test_input0 <= "11111001011";
            when 16 => test_input0 <= "10000011011";
            when 17 => test_input0 <= "00011001110";
            when 18 => test_input0 <= "01011100101";
            when 19 => test_input0 <= "11000111000";
            when 20 => test_input0 <= "01101111011";
            when 21 => test_input0 <= "10110000111";
            when 22 => test_input0 <= "10001001000";
            when 23 => test_input0 <= "10001101111";
            when 24 => test_input0 <= "11010100001";
            when 25 => test_input0 <= "11110011000";
            when 26 => test_input0 <= "00000101110";
            when 27 => test_input0 <= "11001000111";
            when 28 => test_input0 <= "01111010100";
            when 29 => test_input0 <= "00001110001";
            when 30 => test_input0 <= "01000111011";
            when 31 => test_input0 <= "00100001001";
            when others => test_input0 <= "11100100101";
        end case;
        wait until rising_edge(each_sub_signal);
        if ((lut_idx + 1) >= lut_length) then
            lut_idx := to_unsigned(0, 6);
        else
            lut_idx := (lut_idx + 1);
        end if;
    end loop;
    wait;
end process DUT_CONVERTIBLE_TOP_INSTANCES_1_LUT_DRIVER;



CLOCK_SOURCE_CLOCKGEN: process is
begin
each_sub_signal <= '0';
while True loop
    wait for 5 ns;
    each_sub_signal <= '1';
    wait for 5 ns;
    each_sub_signal <= '0';
end loop;
wait;
end process CLOCK_SOURCE_CLOCKGEN;



copied_signal <= each_sub_signal;



write_to_file: process (each_sub_signal) is
    use IEEE.std_logic_textio.all;

    file output_file : TEXT open WRITE_MODE is "/tmp/tmpsSOg4v/signal_outputs";
    variable output_line : LINE;
    variable first_line_to_print : boolean := true;
begin
    if rising_edge(each_sub_signal) then
        if first_line_to_print then
            write(output_line, string'("signed output"));
            write(output_line, string'(","));
            write(output_line, string'("bool test_input.clock"));
            write(output_line, string'(","));
            write(output_line, string'("unsigned each_sub_signal"));
            writeLine(output_file, output_line);
            first_line_to_print := false;
        end if;
        write(output_line, std_logic_vector(output));
        write(output_line, string'(","));
        write(output_line, std_logic(copied_signal));
        write(output_line, string'(","));
        write(output_line, std_logic(each_sub_signal));
        writeline(output_file, output_line);
    end if;
end process write_to_file;
    

DUT_CONVERTIBLE_TOP_INSTANCES_5_IDENTITY: process (each_sub_signal) is
begin
    if rising_edge(each_sub_signal) then
        if (reset = '1') then
            output <= to_signed(0, 11);
        else
            output <= test_input0;
        end if;
    end if;
end process DUT_CONVERTIBLE_TOP_INSTANCES_5_IDENTITY;

end architecture MyHDL;