Interface int conversion

interface_twiddler.py

from myhdl import *

def interface_twiddler(interface, clock, reset):

    @always_seq(clock.posedge, reset=reset)
    def twiddle():
        interface.a.next = interface.b + interface.c

    return twiddle

class Interface(object):
    def __init__(self):
        self.a = Signal(intbv(0, min=-1000, max=1000))
        self.b = Signal(intbv(0, min=-(2**10 - 1), max=2**10 - 1))
        self.c = 10

interface = Interface()
clock  = Signal(bool(0))
reset = ResetSignal(1, active=1, async=False)

toVHDL(interface_twiddler, interface, clock, reset)

interface_twiddler.vhd

-- File: interface_twiddler.vhd
-- Generated by MyHDL 0.9dev
-- Date: Mon Mar 16 11:01:55 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_09.all;

entity interface_twiddler is
    port (
        clock: in std_logic;
        reset: in std_logic;
        interface_a: out signed (10 downto 0);
        interface_b: in signed (10 downto 0)
    );
end entity interface_twiddler;


architecture MyHDL of interface_twiddler is


constant interface.c: integer := 10;




begin




INTERFACE_TWIDDLER_TWIDDLE: process (clock) is
begin
    if rising_edge(clock) then
        if (reset = '1') then
            interface_a <= to_signed(0, 11);
        else
            interface_a <= (interface_b + interface.c);
        end if;
    end if;
end process INTERFACE_TWIDDLER_TWIDDLE;

end architecture MyHDL;