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@hgomersall
Last active August 29, 2015 14:15
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A trivial case showing multiple created processes from an identical source.
from myhdl import *
def TrivialTest(sig_out, sig_in, reset, clock):
@always_seq(clock.posedge, reset=reset)
def _trivial_test():
sig_out.next = sig_in
return _trivial_test
def TestWrapper(sig_out, sig_out2, sig_in, reset, clock):
test_list = []
test_list.append(TrivialTest(sig_out, sig_in, reset, clock))
test_list.append(TrivialTest(sig_out2, sig_in, reset, clock))
return test_list
def FullTest(sig_out, sig_out2, sig_in, reset, clock):
test_wrapper = TestWrapper(sig_out, sig_out2, sig_in, reset, clock)
return test_wrapper
clock = Signal(bool(0))
sig_in = Signal(intbv(0)[5:])
sig_out = Signal(intbv(0)[5:])
sig_out2 = Signal(intbv(0)[5:])
reset = ResetSignal(0, active=1, async=True)
inc_inst = toVHDL(FullTest, sig_out, sig_out2, sig_in, reset, clock)
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