Created
January 19, 2017 13:05
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from myhdl import * | |
class Interface(): | |
def __init__(self): | |
self.data = Signal(False) | |
class HDLClass1(object): | |
@block | |
def model(self, clock, input_interface, output_interface): | |
internal_in = Interface() | |
internal_out = Interface() | |
@always_comb | |
def assignments(): | |
internal_in.data.next = input_interface.data | |
output_interface.data.next = internal_out.data | |
@always(clock.posedge) | |
def do_something(): | |
internal_out.data.next = internal_in.data.next | |
return do_something, assignments | |
class HDLClass2(HDLClass1): | |
pass | |
class Pipeline(object): | |
def __init__(self): | |
self.class1_inst = HDLClass1() | |
self.class2_inst = HDLClass2() | |
@block | |
def pipeline_hdl( | |
self, clock, input_interface, output_interface): | |
intermediate_interface = Interface() | |
class1_hdl_inst = self.class1_inst.model( | |
clock, input_interface, intermediate_interface) | |
class2_hdl_inst = self.class2_inst.model( | |
clock, intermediate_interface, output_interface) | |
return class1_hdl_inst, class2_hdl_inst | |
def build_it(): | |
pipeline = Pipeline() | |
clock = Signal(False) | |
reset = Signal(False) | |
input_interface = Interface() | |
output_interface = Interface() | |
inst = pipeline.pipeline_hdl(clock, input_interface, output_interface) | |
inst.convert() | |
if __name__ == '__main__': | |
build_it() |
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