problem_with_interface_name.py

from myhdl import *
import myhdl

class Interface(object):

    def __init__(self):
        self.bar = Signal(intbv(0)[4:])

@block
def block1(out_interface, foo):
    @always_comb
    def assign_output():
        out_interface.bar.next = foo.bar
    
    block1.vhdl_code = '''
    $foo_bar
    ${foo.bar}
    ${foo_bar}
    ${out_interface.bar}
    '''
    
    out_interface.bar.driven = True
    foo.bar.read = True

    return assign_output

@block
def block2(data_out, foo_bar):

    @always_comb
    def assign_output():
        data_out.next = foo_bar

    return assign_output

@block
def top(data_out, foo_bar, foo, out_interface):
    
    return block2(data_out, foo_bar), block1(out_interface, foo)

@block
def top2(out_interface, foo):
    return block1(out_interface, foo)

data_out = Signal(intbv(0)[8:])
foo_bar = Signal(intbv(10)[8:])
foo = Interface()
interface_out = Interface()

foo_inst = top(data_out, foo_bar, foo, interface_out)
#foo_inst = top2(interface_out, foo)

foo_inst.convert(hdl='VHDL')

An example of problems with naming of interface objects in vhdl_code blocks.

This myhdl branch will build the above, converting the foo.bar symbol to the correct one, avoiding the name conflict and referencing the correct object.

It is necessary to remove foo.bar from vhdl_code to get it to work with master, in which case the names in the resultant vhdl_file will be wrong.

(the vhdl is nonsense, its just an example of the name conflict problem)