block_test.py

from myhdl import *

class Interface(object):

    def __init__(self):
        self.foo = Signal(intbv(0)[20:])
        self.bar = Signal(intbv(0)[20:])

@block
def Foo(a, b, c, d, e, clock):

    if e == True:
        @always(clock.posedge)
        def instance():

            a.next = b
            c.next = d
            
        instances = [instance]
    else:
        @always(clock.posedge)
        def instance():
            c.next = d
            a.foo.next = b.foo
            a.bar.next = b.bar

        instances = [instance]
            
    return instances

clock = Signal(False)
a = Signal(intbv(0)[10:])
b = Signal(intbv(0)[10:])
#a = Interface()
#b = Interface()
c = Signal(intbv(0)[10:])
d = Signal(intbv(0)[10:])

foo = Foo(a, b, c, d, True, clock)

foo._inferInterface()

print foo.argnames
print foo.argdict
for each in foo.argnames:
    print(each, len(foo.argdict[each]))

#foo.convert(hdl='Verilog')
foo.convert(hdl='VHDL')
foo.convert(hdl='VHDL')