A modified functional version of code in http://permalink.gmane.org/gmane.comp.python.myhdl/4091

vga_fifo.py

from myhdl import *

CACHE_SIZE = 20
NUM_OF_ADDRESSES = 25

# entity creation:
def vga_fifo(
  # ports:
  clk,
  rst,
  # VGA: Avalon Memory Mapped Slave
  read_request_from_vga ,
  addr_req_by_vga,
  data_out_to_vga,

  # EXPORT
  vga_cache_miss,
  oldest_stored_addr,
  newest_stored_addr,

  # SDRAM: Avalon Memory Mapped Master
  read_req_to_sdram,
  valid_from_sdram,
  wait_req_from_sdram,
  addr_req_to_sdram ,
  data_in_from_sdram
):
    # Entity instantiation:
    # entity_name = entity_name(ports, in, order)
    
    most_recent_addr_req_to_sdram = Signal(intbv(0)[23:]) # modbv loops back to zero when incremented
    addr_array = Signal(intbv(0)[459:0])
    data_array = Signal(intbv(0)[319:0])
    cas_delay_counter = Signal(modbv(0)[2:])

    # procedural process:
    @always_seq(clk.posedge, reset=rst)
    def main_process():

        
        #############################
        #  addr_array & data_array  #
        #############################
        if valid_from_sdram:
            if most_recent_addr_req_to_sdram + 1 > 0:
                addr_array[436:0].next = addr_array[436:0]
                addr_array[:436].next = most_recent_addr_req_to_sdram - 1
            else:
                addr_array[436:0].next = addr_array[436:0]
                addr_array[:436].next = most_recent_addr_req_to_sdram - 1

            oldest_stored_addr.next = addr_array[459:437]
            newest_stored_addr.next = addr_array[22:0]
            data_array[303:0].next = data_array[303:0]
            data_array[:303].next = data_in_from_sdram

        #######################
        #  addr_req_to_sdram  #
        #######################
        if not wait_req_from_sdram:
            if addr_array[22:0] + 1 < NUM_OF_ADDRESSES:
                addr_req_to_sdram.next = addr_array[22:0] + 1
                most_recent_addr_req_to_sdram.next = addr_array[22:0] + 1
            else:
                addr_req_to_sdram.next = 0
                most_recent_addr_req_to_sdram.next = 0

        #######################
        #  read_req_to_sdram  #
        #######################
        if not wait_req_from_sdram and addr_req_by_vga != addr_array[459:437]:
            read_req_to_sdram.next = 1
        else:
            read_req_to_sdram.next = 0


        #####################
        #  data_out_to_vga  #
        #####################
        if read_request_from_vga:
            vga_cache_miss.next = 0
            if addr_array[459:437] == addr_req_by_vga: # oldest
                data_out_to_vga.next = data_array[319:304]
            elif addr_array[436:414] == addr_req_by_vga:
                data_out_to_vga.next = data_array[303:288]
            elif addr_array[413:391] == addr_req_by_vga:
                data_out_to_vga.next = data_array[287:272]
            elif addr_array[390:368] == addr_req_by_vga:
                data_out_to_vga.next = data_array[271:256]
            elif addr_array[367:345] == addr_req_by_vga:
                data_out_to_vga.next = data_array[255:240]
            elif addr_array[344:322] == addr_req_by_vga:
                data_out_to_vga.next = data_array[239:224]
            elif addr_array[321:299] == addr_req_by_vga:
                data_out_to_vga.next = data_array[223:208]
            elif addr_array[298:276] == addr_req_by_vga:
                data_out_to_vga.next = data_array[207:192]
            elif addr_array[275:253] == addr_req_by_vga:
                data_out_to_vga.next = data_array[191:176]
            elif addr_array[252:230] == addr_req_by_vga:
                data_out_to_vga.next = data_array[175:160]
            elif addr_array[229:207] == addr_req_by_vga:
                data_out_to_vga.next = data_array[159:144]
            elif addr_array[206:184] == addr_req_by_vga:
                data_out_to_vga.next = data_array[143:128]
            elif addr_array[183:161] == addr_req_by_vga:
                data_out_to_vga.next = data_array[127:112]
            elif addr_array[160:138] == addr_req_by_vga:
                data_out_to_vga.next = data_array[111:96]
            elif addr_array[137:115] == addr_req_by_vga:
                data_out_to_vga.next = data_array[95:80]
            elif addr_array[114:92] == addr_req_by_vga:
                data_out_to_vga.next = data_array[79:64]
            elif addr_array[91:69] == addr_req_by_vga:
                data_out_to_vga.next = data_array[63:48]
            elif addr_array[68:46] == addr_req_by_vga:
                data_out_to_vga.next = data_array[47:32]
            elif addr_array[45:23] == addr_req_by_vga:
                data_out_to_vga.next = data_array[31:16]
            elif addr_array[22:0] == addr_req_by_vga: # newest
                data_out_to_vga.next = data_array[15:0]
            else:
                vga_cache_miss.next = 1

    return main_process


clk = Signal(bool())
rst = ResetSignal(0, active=0, async=True)
# VGA: Avalon Memory Mapped Slave
read_request_from_vga = Signal(bool())
addr_req_by_vga = Signal(modbv(0)[23:])
data_out_to_vga = Signal(modbv(0)[16:])
# EXPORT
vga_cache_miss  = Signal(bool())
addr_of_data_to_vga = Signal(modbv(0)[23:])
oldest_stored_addr = Signal(modbv(0)[23:])
newest_stored_addr = Signal(modbv(0)[23:])
# SDRAM: Avalon Memory Mapped Master
read_req_to_sdram = Signal(bool())
valid_from_sdram = Signal(bool())
wait_req_from_sdram = Signal(bool())
addr_req_to_sdram = Signal(modbv(0)[23:])
data_in_from_sdram = Signal(modbv(0)[16:])

# convert to VHDL toVHDL(entity_name, port1, port2, port3...)
toVHDL(vga_fifo,
       clk,
       rst,
       read_request_from_vga ,
       addr_req_by_vga,
       data_out_to_vga,
       vga_cache_miss,
       oldest_stored_addr,
       newest_stored_addr,
       read_req_to_sdram,
       valid_from_sdram,
       wait_req_from_sdram,
       addr_req_to_sdram,
       data_in_from_sdram)