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hmenn/mux_4x1.v

Created December 10, 2016 21:27
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4 bit MUX with structural verilog
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mux_4x1.v
module mux_4x1(output out,input c0,input c1,input c2,input c3,input s1,input s0);
wire s0n,s1n; //s0 not, s1 not
wire w1,w2,w3,w4;
not n1(s0n,s0);
not n1(s1n,s1);
and and1(w1,c0,s1n,s0n);
and and2(w2,c1,s1n,s0);
and and3(w3,c2,s1,s0n);
and and4(w4,c3,s1,s0);
or or1(out,w1,w2,w3,w4);
endmodule
@prasannathapa

prasannathapa commented Oct 11, 2020 •
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//Better one

module mux_4x1(output out,input a, b, c, d, s0, s1);

  wire s0n,s1n; //s0 not, s1 not
  wire w1,w2,w3,w4;

  not n0(s0n,s0);
  not n1(s1n,s1);

  and and1(w1,a,s0n,s1n);
  and and2(w2,b,s0n,s1);
  and and3(w3,c,s0,s1n);
  and and4(w4,d,s0,s1);

  or or1(out,w1,w2,w3,w4);

endmodule

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