TD4のようなCPU

cpu4.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2015/10/02 14:40:00
// Design Name: 
// Module Name: cpu4
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cpu4(
    clk,
    reset,
    in,
    out
    );
    input  clk;
    input  reset;
    input  [3:0]in;
    output reg [3:0]out;

    //ROM 8bit 16word
    reg [7:0] rom [0:15];
    
    reg [3:0] pc ;
    reg [3:0] register_a;
    reg [3:0] register_b;
    reg carry_f;
    
    wire [3:0] im;
    wire [3:0] op;

    assign op = rom[pc][7:4];
    assign im = rom[pc][3:0];
       
    always @ (posedge clk) begin
        
        //レジスタAに任意の値を転送
        if (op == 4'b0011) begin
            register_a <= im;
        end         
        
        //レジスタBに任意の値を転送      
        if (op == 4'b0111) begin
            register_b <= im;
        end         
        
        //AレジスタにBを転送      
        if (op == 4'b0001) begin
            register_a <= register_b;
        end  
        
        //BレジスタにAを転送      
        if (op == 4'b0100) begin
            register_b <= register_a;
        end 
        
        //レジスタAに任意の値を加算
        if (op == 4'b0000) begin
            {carry_f, register_a} <= register_a + im;
        end
        
        //レジスタBに任意の値を加算
        if (op == 4'b0101) begin
            {carry_f, register_b} <= register_b + im;
        end
        
        //入力ポートの内容をレジスタAへ転送
        if (op == 4'b0010) begin
            register_a <= in;
        end
        
        //入力ポートの内容をレジスタBに転送
        if (op == 4'b0110) begin
            register_b <= in;
        end            
        
        //出力ポートに任意の値を転送
        if (op == 4'b1011) begin
            out <= im;
        end
        
        //出力ポートにレジスタBの値を転送
        if (op == 4'b1001) begin
            out <= register_b;
        end
        
        //指定したアドレスへジャンプ
        if (op == 4'b1111) begin
            pc <= im;
        end
        
        //Cフラグが1ではない時にジャンプ
        if (op == 4'b1110) begin
            if (carry_f == 0) begin
                pc <= im;
            end
            else if (carry_f == 1) begin
            end
        end
        
       //プログラムカウンタ
       if (op != 4'b1111) begin
            pc <= pc + 1;
       end 
        
        //初期化 Reset
        if (reset == 1) begin
            pc  <= 0;  
            out <= 0; 
            carry_f <= 0;    
        end
                
    end
  
  //ROM部分
    initial begin
        rom[0]  = 8'b10110011;
        rom[1]  = 8'b10110110;
        rom[2]  = 8'b10111100;
        rom[3]  = 8'b10110000;
        rom[4]  = 8'b11110000;
        rom[5]  = 8'b00000000;
        rom[6]  = 8'b00000000;
        rom[7]  = 8'b00000000;
        rom[8]  = 8'b00000000;
        rom[9]  = 8'b00000000;
        rom[10] = 8'b00000000;
        rom[11] = 8'b00000000;
        rom[12] = 8'b00000000;
        rom[13] = 8'b00000000;
        rom[14] = 8'b00000000;
        rom[15] = 8'b00000000;
    end
endmodule

module cpu4_top(
    clk,
    reset,
    in,
    out
    );
    
    input  clk;
    input  reset;
    input  [3:0]in;
    output [3:0]out;
    reg    sclk;
    reg    [31:0]buff;
    
    
    cpu4 cpu4(
        .clk(sclk),
        .reset(reset),
        .in(in),
        .out(out)
    );
    
    always @ (posedge clk) begin
        if (reset == 1) begin
            sclk = 0;
            buff = 0;
        end
        else if (reset == 0)begin
            buff = buff + 1;
        end
    
  //遅延処理    
        if (buff == 32'h07735940) begin
            sclk = ~sclk;
            buff = 0;
        end
    end
    
    
endmodule