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module tb_led01; | |
reg clk; | |
reg res; | |
wire led0; | |
wire led1; | |
wire led2; | |
wire led3; | |
led01 led01( | |
.clk(clk), |
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module led01( | |
clk, | |
res, | |
led0, | |
led1, | |
led2, | |
led3); | |
input clk; | |
input res; |
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#!/usr/bin/env python | |
# encoding: utf-8 | |
## Module infomation ### | |
# Python (3.4.4) | |
# numpy (1.10.2) | |
# PyAudio (0.2.9) | |
# pyqtgraph (0.9.10) | |
# PyQt4 (4.11.4) | |
# All 32bit edition |
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#!/usr/bin/env python | |
# encoding: utf-8 | |
## Module infomation ### | |
# Python (3.4.4) | |
# numpy (1.10.2) | |
# PyAudio (0.2.9) | |
# matplotlib (1.5.1) | |
# All 32bit edition | |
######################## |
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`timescale 1ns / 1ps | |
////////////////////////////////////////////////////////////////////////////////// | |
// Company: | |
// Engineer: | |
// | |
// Create Date: 2015/10/02 14:40:00 | |
// Design Name: | |
// Module Name: cpu4 | |
// Project Name: | |
// Target Devices: |