DCMI signal generator for Lattice ICEStick

dcmi_source.pcf

set_io clock 119
set_io reset 118
set_io h_valid 117
set_io v_valid 116
set_io pclk_out 115
set_io data[0] 44
set_io data[1] 45
set_io data[2] 47
set_io data[3] 48
set_io data[4] 56
set_io data[5] 60
set_io data[6] 61
set_io data[7] 62

dcmi_source.v

module DCMISource(
  input clock,
  input reset,
  output reg h_valid,
  output reg v_valid,
  output wire pclk_out,
  output reg [7:0] data);

  localparam V_PRE = 1;
  localparam V_SIZE = 600;
  localparam V_POST = 1;
  localparam H_PRE = 32;
  localparam H_SIZE = 1600;
  localparam H_POST = 32;
  localparam DELAY_H_VALID_LOW = 1'b1;

  reg pclk;
  reg [11:0] x_counter;
  reg [11:0] y_counter;
  reg [11:0] new_x_counter;
  reg [11:0] new_y_counter;
  reg new_h_valid;
  reg new_h_valid_delay;
  reg new_v_valid;
  reg [7:0] new_data;

  assign pclk_out = pclk & h_valid & v_valid;

  always @(posedge clock) begin
    if (!reset)
      begin
        pclk <= 1'b0;
        new_x_counter = 0;
        new_y_counter = 0;
        new_h_valid = 0;
        new_v_valid = 0;
      end
    else
      begin
        if (!pclk)
          pclk <= 1;
        else begin
          pclk <= 0;

          new_x_counter = x_counter + 12'b1;
          new_y_counter = y_counter;
          if (new_x_counter == H_PRE + H_SIZE + H_POST)
            begin
              new_x_counter = 0;
              new_y_counter = y_counter + 12'b1;
              if (new_y_counter == V_PRE + V_SIZE + V_POST)
                new_y_counter = 0;
            end

          new_v_valid = new_y_counter >= V_PRE && new_y_counter < V_PRE + V_SIZE;
          new_h_valid = new_x_counter >= H_PRE && new_x_counter < H_PRE + H_SIZE;

          if (new_v_valid && new_h_valid)
            new_data = {new_x_counter[0], new_x_counter[3:1], new_x_counter[7:4]};
          else
            new_data = 0;
        end
      end
    new_h_valid_delay <= new_h_valid;
    data <= new_data;
    h_valid <= new_h_valid | (DELAY_H_VALID_LOW & new_h_valid_delay);
    v_valid <= new_v_valid;
    x_counter <= new_x_counter;
    y_counter <= new_y_counter;
  end
endmodule

Makefile

SRC := dcmi_source.v
CONSTRAINTS := dcmi_source.pcf
NAME := dcmi_source
TOP := DCMISource

all: $(NAME).bin

$(NAME).blif: $(SRC)
	yosys -p 'synth_ice40 -top $(TOP) -blif $@' $<

$(NAME).asc: $(NAME).blif $(CONSTRAINTS)
	arachne-pnr -d 1k -p $(CONSTRAINTS) $(NAME).blif -o $@

$(NAME).bin: $(NAME).asc
	icepack $< $@

prog: $(NAME).bin
	iceprog $(NAME).bin

clean:
	rm -f $(NAME).bin $(NAME).asc $(NAME).blif

.PHONY: all prog clean