strcmp() with VHDL

strcmp.vhd

library ieee;
use     ieee.std_logic_1164.all;
use     std.textio.all;
entity  test is
end     test;
architecture model of test is
    function strcmp(s1,s2:string) return integer is
        alias    str_1 : string(1 to s1'length) is s1;
        alias    str_2 : string(1 to s2'length) is s2;
        variable i     : integer;
        variable ch_1  : integer;
        variable ch_2  : integer;
    begin
        i := 1;
        loop
            if (i <= str_1'high and i <= str_2'high) then
                if (str_1(i) = str_2(i)) then
                    i := i + 1;
                    next;
                end if;
            end if;
            if (i <= str_1'high) then
                ch_1 := character'pos(str_1(i));
            else
                ch_1 := 0;
            end if;
            if (i <= str_2'high) then
                ch_2 := character'pos(str_2(i));
            else
                ch_2 := 0;
            end if;
            exit;
        end loop;
        return (ch_1 - ch_2);
    end function;
begin
    process
    begin
        assert (strcmp(string'("ABC"), string'("ABC")) = 0) report "Test 1 NG";
        assert (strcmp(string'("ABC"), string'("AB" )) > 0) report "Test 2 NG";
        assert (strcmp(string'("AB" ), string'("ABC")) < 0) report "Test 3 NG";
        assert (strcmp(string'("AB" ), string'("ABB")) < 0) report "Test 4 NG";
        assert (strcmp(string'("ABC"), string'("ABA")) > 0) report "Test 5 NG";
        assert (strcmp(string'("ABA"), string'("ABC")) < 0) report "Test 6 NG";
        wait;
    end process;
end model;