dpu-load.md

dpu-load.md

Edge-AI-Platform-Tutorials for ZynqMP-FPGA-Linux

Install

fpga@debian-fpga:~/test$ dtc -I dts -O dtb -o fpga-load.dtb fpga-load.dts
fpga@debian-fpga:~/test$ dtc -I dts -O dtb -o dpu.dtb       dpu.dts
dpu.dtb: Warning (avoid_unnecessary_addr_size): /fragment@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
dpu.dtb: Warning (avoid_unnecessary_addr_size): /fragment@0/__overlay__: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
fpga@debian-fpga:~/test$ sudo mkdir /config/device-tree/overlays/fpga-load
fpga@debian-fpga:~/test$ sudo cp fpga-load.dtb /config/device-tree/overlays/fpga-load/dtbo
[   85.090972] fpga_manager fpga0: writing dpu_core.bin to Xilinx ZynqMP FPGA Manager
[   85.495277] fclkcfg: loading out-of-tree module taints kernel.
[   85.503529] fclkcfg amba_pl@0:fclk0: driver installed.
[   85.508694] fclkcfg amba_pl@0:fclk0: device name    : amba_pl@0:fclk0
[   85.515141] fclkcfg amba_pl@0:fclk0: clock  name    : pl0_ref
[   85.520886] fclkcfg amba_pl@0:fclk0: clock  rate    : 99999999
[   85.526744] fclkcfg amba_pl@0:fclk0: clock  enabled : 1
[   85.531971] fclkcfg amba_pl@0:fclk0: remove rate    : 1000000
[   85.537714] fclkcfg amba_pl@0:fclk0: remove enable  : 0
fpga@debian-fpga:~/test$ sudo insmod dpu.ko
fpga@debian-fpga:~/test$ sudo mkdir /config/device-tree/overlays/dpu
fpga@debian-fpga:~/test$ sudo cp dpu.dtb /config/device-tree/overlays/dpu/dtbo
[  145.457931] [DPU][3359]Found DPU signature addr = 0x8f000000 in device-tree
[  145.464914] [DPU][3359]Checking DPU signature at addr = 0x8ff00000,
[  145.471316] [DPU][3359]DPU signature checking done!

dpu.dts

/dts-v1/; /plugin/;
/ {
	fragment@0 {
		target-path = "/amba_pl@0";
		#address-cells = <2>;
		#size-cells = <2>;

		__overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;

			dpu {
				compatible = "xilinx,dpu";
				base-addr = <0x8f000000>;
				dpucore {
					compatible = "xilinx,dpucore";
					interrupt-parent = <&gic>;
					interrupts = <0 89 4>;
					core-num = <0x1>;
				};
	                };
		};
	};
};

fpga-load.dts

/dts-v1/; /plugin/;
/ {
	fragment@0 {
		target-path = "/fpga-full";
		__overlay__ {
			firmware-name = "dpu_core.bin";
		};
        };
	fragment@1 {
		target-path = "/amba_pl@0";
		__overlay__ {
			afi0 {
				compatible    = "xlnx,afi-fpga";
				config-afi    = <4 0>, <5 0>, <6 0>, <7 0>, <8 2>, <9 2>, <15 0>;
			};
			fclk0 {
				compatible    = "ikwzm,fclkcfg-0.10.a";
				clocks        = <&zynqmp_clk 0x47>;
				insert-rate   = "100000000";
				insert-enable = <1>;
				remove-rate   = "1000000";
				remove-enable = <0>;
			};
		};
	};
};