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imrehg/vab820-uboot.patch

Created October 23, 2014 01:19
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vab820-uboot.patch
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vab820-uboot.patch
diff --git a/board/freescale/mx6q_sabrelite/flash_header.S b/board/freescale/mx6q_sabrelite/flash_header.S
index ee6298f..27488de 100644
--- a/board/freescale/mx6q_sabrelite/flash_header.S
+++ b/board/freescale/mx6q_sabrelite/flash_header.S
@@ -25,6 +25,13 @@
# error "Must define the offset of flash header"
#endif
+// steven: use flash plug_in
+#define CONFIG_FLASH_PLUG_IN
+// steven: if not define CONFIG_FLASH_PLUG_IN, can define VAB820_2G or not
+//#define VAB820_2G
+
+#ifndef CONFIG_FLASH_PLUG_IN
+
#define CPU_2_BE_32(l) \
((((l) & 0x000000FF) << 24) | \
(((l) & 0x0000FF00) << 8) | \
@@ -56,56 +63,208 @@ plugin: .word 0x0
dcd_hdr: .word 0x40D802D2 /* Tag=0xD2, Len=90*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x04D402CC /* Tag=0xCC, Len=90*8 + 4, Param=0x04 */
-/* DCD */
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
+#ifdef VAB820_2G
+
+
+
+
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+// CAS
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+// RAS
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+// MDMISC
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+// MDCFG0
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x898E7955)
+// MDCFG1
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
+// MDCFG2
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008E1023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1390003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03200338)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x024A0314)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03280340)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03280270)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x342C3232)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x342E283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3E363C34)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x44344636)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x00190019)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001D)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x0015001F)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00110026)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00020030)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00020030)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00020030)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00020030)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00020030)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00020030)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00020030)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00020030)
+#else
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00020030)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00020030)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00020030)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00020030)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00020030)
+
+
+
+// Ken modified Nanya 1G registers based on VAB-820 R.1
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+
+// unknow register
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
-MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
-MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
@@ -118,56 +277,478 @@ MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
-MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x54597974)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xDB538F64)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
-
-MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x00591023)
MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP CS0_END
MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+// MDCTL
MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x02088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0288803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00048039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09308030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09308038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03340348)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x0236032C)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03340344)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x032C0300)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x32282E30)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x302A283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3A363E38)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x40303E36)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001C0013)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x0022001C)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00160025)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x000C001C)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+
+
+#endif
+
+#else
+
+
+#define ROM_API_TABLE_BASE_ADDR (0x000000C0)
+#define ROM_API_HWCNFG_SETUP_OFFSET (0x08)
+#define IRAM_FREE_START 0x00907000
+
+#define MXC_DCD_ITEM(i, addr, val) \
+ ldr r1, =val; \
+ ldr r0, =addr; \
+ str r1, [r0];
+
+
+
+.section ".text.flasheader", "x"
+origin:
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+
+/* First IVT to copy the plugin that initializes the system into OCRAM */
+ivt_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v: .long IRAM_FREE_START + (plugin_start - origin) /* Plugin entry point, address after the second IVT table */
+reserv1: .long 0x0
+dcd_ptr: .long 0x0
+boot_data_ptr: .long IRAM_FREE_START + (boot_data - origin) /*0x00907420*/
+self_ptr: .long IRAM_FREE_START + (ivt_header - origin)
+app_code_csf: .long 0x0
+reserv2: .long 0x0
+
+boot_data: .long IRAM_FREE_START
+image_len: .long 16*1024 /* plugin can be upto 16KB in size */
+plugin: .long 0x1 /* Enable plugin flag */
+
+/* Second IVT to give entry point into the bootloader copied to DDR */
+ivt2_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */
+app2_code_jump_v: .long _start /* Entry point for uboot */
+reserv3: .long 0x0
+dcd2_ptr: .long 0x0
+boot_data2_ptr: .long boot_data2
+self_ptr2: .long ivt2_header
+app_code_csf2: .long 0x0
+reserv4: .long 0x0
+
+boot_data2: .long TEXT_BASE
+image_len2: .long _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+plugin2: .long 0x0
+
+/* Here starts the plugin code */
+plugin_start:
+/* Save the return address and the function arguments */
+ push {r0-r4, lr}
+
+
+// CCM_BASE_ADDR = 0x020C4000
+//DDR clk
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00020324
+ str r1, [r0, #0x018]
+
+// vab820
+ ldr r0, =0x20e02fc
+ ldr r1, =0x05
+ str r1, [r0]
+ ldr r0, =0x20a0004
+ ldr r1, =0x00
+ str r1, [r0]
+ ldr r0, =0x20a0008
+ ldr r1, [r0]
+ and r1, #1
+ cmp r1, #0
+ bne Label_vab820_1
+
+
+
+// =============================================2GB start
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+// CAS
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+// RAS
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+// MDMISC
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
+
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+// MDCFG0
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x898E7955)
+// MDCFG1
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
+// MDCFG2
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x008E1023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
+// MR2
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
+// MR3
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
+// MR0
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
-
+// ZQ calibration
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
+// MPODTCTRL
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00000007)
MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00000007)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03200338)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x024A0314)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03280340)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03280270)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x342C3232)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x342E283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3E363C34)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x44344636)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x00190019)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001D)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x0015001F)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00110026)
+// MPMUR0
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+
+// =============================================2GB end
+ b Label_vab820_2
+
+
+
+
+Label_vab820_1:
+// =============================================1GB start
+// Ken modified Nanya 1G registers based on VAB-820 R.1
+
+#define VAB820_SDQSx 0x00000028
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, VAB820_SDQSx)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, VAB820_SDQSx)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, VAB820_SDQSx)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, VAB820_SDQSx)
+
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, VAB820_SDQSx)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, VAB820_SDQSx)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, VAB820_SDQSx)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, VAB820_SDQSx)
+
+#define VAB820_DQM 0x00000028
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, VAB820_DQM)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, VAB820_DQM)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, VAB820_DQM)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, VAB820_DQM)
+
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, VAB820_DQM)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, VAB820_DQM)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, VAB820_DQM)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, VAB820_DQM)
+
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00000028)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00000028)
+
+#define VAB820_SDCLKx 0x00000028
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, VAB820_SDCLKx)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, VAB820_SDCLKx)
+
+// unknow register
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00000028)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+#define VAB820_SDODTx 0x00000028
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, VAB820_SDODTx)
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, VAB820_SDODTx)
+
+#define VAB820_BxDS 0x28
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, VAB820_BxDS)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, VAB820_BxDS)
+
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, VAB820_BxDS)
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, VAB820_BxDS)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, VAB820_BxDS)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, VAB820_BxDS)
+
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, VAB820_BxDS)
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, VAB820_BxDS)
+
+#define VAB820_ADD_CTL_DS 0x00000028
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359)
-MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03650348)
-MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x4436383B)
-MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x39393341)
-MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x35373933)
-MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x48254A36)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, VAB820_ADD_CTL_DS)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
+
+MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
-MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
-MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)
+MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
+MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x54597974)
+MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xDB538F64)
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
+// MDOR
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x00591023)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
+// MDPDC
+MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
+// MDASP CS0_END
+MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
+// MDCTL
+MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0x831A0000)
+// MR2
+MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x02088032)
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0288803A)
+// MR3
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
+// MR1
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
+MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00048039)
+// MR0
+MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09308030)
+MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09308038)
+// ZQ calibration
+MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
+// ZQ
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
+//// final DDR setup
+// MMDC0_MDREF
+MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00007800)
+// MPODTCTRL
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
+MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
+//Read DQS Gating calibration
+MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x03340348)
+MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x0236032C)
+MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x03340344)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x032C0300)
+//Read calibration
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x32282E30)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x302A283A)
+//Write calibration
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x3A363E38)
+MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x40303E36)
+// MPWLDECTRLx
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001C0013)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x0022001C)
+MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00160025)
+MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x000C001C)
+// MPMUR0
MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
+// =============================================1GB end
+
+
+
+
+
+
+Label_vab820_2:
+/*
+ The following is to fill in those arguments for this ROM function
+ pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+
+ This function is used to copy data from the storage media into DDR.
+
+ start - Initial (possibly partial) image load address on entry. Final
+ image load address on exit.
+ bytes - Initial (possibly partial) image size on entry. Final image size
+ on exit.
+ boot_data - Initial @ref ivt Boot Data load address.
+*/
+ adr r0, DDR_DEST_ADDR
+ adr r1, COPY_SIZE
+ adr r2, BOOT_DATA
+
+/*
+ * check the _pu_irom_api_table for the address
+ * pu_irom_hwcnfg_setup is in 0x1fb5 ERIC : < what is the address in Rigel >
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+ ldr r3, =ROM_API_TABLE_BASE_ADDR
+ ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+ blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+ pop {r0-r4, lr}
+ ldr r5, DDR_DEST_ADDR
+ str r5, [r0]
+ ldr r5, COPY_SIZE
+ str r5, [r1]
+ mov r5, #0x400 /* Point to the second IVT table at offset 0x42C */
+ add r5, r5, #0x2C
+ str r5, [r2]
+ mov r0, #1
+
+ bx lr /* return back to ROM code */
+
+DDR_DEST_ADDR: .word TEXT_BASE
+COPY_SIZE: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+BOOT_DATA: .word TEXT_BASE
+ .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
+ .word 0
+/*********************************************************************/
+
+
+
#endif
+
+#endif
+
diff --git a/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
index 1b0679d..dbc65d8 100644
--- a/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
+++ b/board/freescale/mx6q_sabrelite/mx6q_sabrelite.c
@@ -99,10 +99,17 @@ static inline void setup_boot_device(void)
boot_dev = SATA_BOOT;
break;
case 0x3:
+// steven
+ if (bt_mem_type)
+ boot_dev = I2C_BOOT;
+ else
+ boot_dev = SPI_NOR_BOOT;
+#if 0
if (bt_mem_type)
boot_dev = SPI_NOR_BOOT;
else
boot_dev = I2C_BOOT;
+#endif
break;
case 0x4:
case 0x5:
@@ -174,8 +181,13 @@ void board_mmu_init(void)
int dram_init(void)
{
+ // Steven
+ ulong nRamSize = (1u * 1024 * 1024 * 1024);
+ u32 reg = readl(GPIO2_BASE_ADDR + GPIO_PSR);
+
+ if (!(reg&0x01)) { nRamSize = (2u * 1024 * 1024 * 1024); }
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[0].size = nRamSize;
return 0;
}
@@ -314,7 +326,8 @@ int board_eth_init(bd_t *bis)
#ifdef CONFIG_CMD_MMC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC3_BASE_ADDR, 1, 1, 1},
+// steven: USDHC3_BASE_ADDR -> USDHC2_BASE_ADDR
+ {USDHC2_BASE_ADDR, 1, 1, 1},
{USDHC4_BASE_ADDR, 1, 1, 1},
};
@@ -352,6 +365,11 @@ iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
+// steven
+ MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
+ MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
+ MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
+ MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
};
int usdhc_gpio_init(bd_t *bis)
@@ -362,10 +380,11 @@ int usdhc_gpio_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads,
+ // steven: mx6q_usdhc3_pads -> mx6q_usdhc2_pads
+ mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads,
sizeof
- (mx6q_usdhc3_pads) /
- sizeof(mx6q_usdhc3_pads
+ (mx6q_usdhc2_pads) /
+ sizeof(mx6q_usdhc2_pads
[0]));
break;
case 1:
@@ -434,6 +453,9 @@ int board_init(void)
#ifdef CONFIG_I2C_MXC
setup_i2c(CONFIG_SYS_I2C_PORT);
#endif
+// steven
+ /* Switch to 1GHZ */
+ clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK);
return 0;
}
@@ -489,8 +511,8 @@ iomux_v3_cfg_t enet_pads[] = {
MX6Q_PAD_RGMII_RD3__GPIO_6_29,
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
- MX6Q_PAD_GPIO_0__CCM_CLKO,
- MX6Q_PAD_GPIO_3__CCM_CLKO2,
+ //MX6Q_PAD_GPIO_0__CCM_CLKO,
+ //MX6Q_PAD_GPIO_3__CCM_CLKO2,
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
};
@@ -550,12 +572,22 @@ int mx6_rgmii_rework(char *devname, int phy_addr)
void enet_board_init(void)
{
+ // steven: vab820 enet's reset pin is the same as sabresd
+ unsigned int reg;
iomux_v3_cfg_t enet_reset =
+ (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 & ~MUX_PAD_CTRL_MASK)
+ | MUX_PAD_CTRL(0x88);
+
+/* iomux_v3_cfg_t enet_reset =
(MX6Q_PAD_EIM_D23__GPIO_3_23 &
~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x48);
+*/
+
+ /* phy reset: gpio1-25 */
+ // gpio1_25 to low
+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 25), 0);
+ //set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
- /* phy reset: gpio3-23 */
- set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 0);
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 30),
(CONFIG_FEC0_PHY_ADDR >> 2));
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 25), 1);
@@ -567,14 +599,20 @@ void enet_board_init(void)
set_gpio_output_val(GPIO6_BASE_ADDR, (1 << 24), 1);
udelay(500);
- set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
+
+ // gpio1_25 to high
+ set_gpio_output_val(GPIO1_BASE_ADDR, (1 << 25), 1);
+ //set_gpio_output_val(GPIO3_BASE_ADDR, (1 << 23), 1);
+
mxc_iomux_v3_setup_multiple_pads(enet_pads_final,
ARRAY_SIZE(enet_pads_final));
}
int checkboard(void)
{
- printf("Board: MX6Q-SABRELITE:[ ");
+ //Steven
+ //printf("Board: MX6Q-SABRELITE:[ ");
+ printf("Board: MX6Q-VAB820:[ ");
switch (__REG(SRC_BASE_ADDR + 0x8)) {
case 0x0001:
diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c
index 212abb7..ce7f617 100644
--- a/drivers/net/mxc_fec.c
+++ b/drivers/net/mxc_fec.c
@@ -286,6 +286,9 @@ static int mxc_fec_mii_read(char *devname, unsigned char addr,
return -1;
info = dev->priv;
fecp = (fec_t *) (info->iobase);
+// steven
+ fec_reset(dev);
+ mxc_fec_mii_init(fecp);
return __fec_mii_read(fecp, addr, reg, value);
}
@@ -299,6 +302,9 @@ static int mxc_fec_mii_write(char *devname, unsigned char addr,
return -1;
info = dev->priv;
fecp = (fec_t *) (info->iobase);
+// steven
+ fec_reset(dev);
+ mxc_fec_mii_init(fecp);
return __fec_mii_write(fecp, addr, reg, value);
}
diff --git a/include/configs/mx6q_sabrelite.h b/include/configs/mx6q_sabrelite.h
index b692c87..99a9fd2 100644
--- a/include/configs/mx6q_sabrelite.h
+++ b/include/configs/mx6q_sabrelite.h
@@ -24,6 +24,10 @@
#include <asm/arch/mx6.h>
+// steven
+//#define VAB820_FACTORY
+
+
/* High Level Configuration Options */
#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */
#define CONFIG_MXC
@@ -115,37 +119,45 @@
#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */
#define CONFIG_RD_LOADADDR 0x11000000
+// Steven
+#ifdef VAB820_FACTORY
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ethprime=FEC0\0" \
"ethaddr=00:01:02:03:04:05\0" \
"uboot=u-boot.bin\0" \
"kernel=uImage\0" \
- "bootargs=console=ttymxc1,115200\0" \
- "bootargs_base=setenv bootargs console=ttymxc1,115200\0" \
- "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
- "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
- "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666\0" \
- "bootcmd_net=dhcp; run bootargs_base bootargs_nfs;bootm\0" \
- "bootargs_mmc=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootwait rw " \
- "video=mxcfb0:dev=ldb,LDB-XGA,if=RGB666 " \
- "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24\0" \
- "bootcmd_mmc=run bootargs_base bootargs_mmc;mmc dev 1;" \
- "mmc read ${loadaddr} 0x800 0x2000;bootm\0" \
- "bootcmd=run bootcmd_mmc\0" \
- "clearenv=sf probe 1 && sf erase 0xc0000 0x2000 && " \
- "echo restored environment to factory default\0" \
- "upgradeu=for disk in 0 1 ; do mmc dev ${disk} ;" \
- "for fs in fat ext2 ; do " \
- "${fs}load mmc ${disk}:1 10008000 " \
- "/6q_upgrade && " \
- "source 10008000 ; " \
- "done ; " \
- "done\0" \
- "bootfile=_BOOT_FILE_PATH_IN_TFTP_\0" \
- "nfsroot=_ROOTFS_PATH_IN_NFS_\0"
-
+ "vkernel=/boot/uImage.vab820\0" \
+ "hdmi=video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32\0"\
+ "hdmilvds=video=mxcfb0:dev=hdmi,1920x1080@60,bpp=32 video=mxcfb1:dev=ldb,LDB-SXGA,if=RGB24 ldb=spl0\0"\
+ "bootargs_base=setenv bootargs console=ttymxc1,115200 ${hdmilvds} console=tty1,115200\0"\
+ "viewsfenv=sf probe 1 ; sf read 0x10800000 0xc0000 0x2000 ; md 0x10800000\0" \
+ "clearsfenv=sf probe 1 ; sf erase 0xc0000 0x2000 ; echo flash environment.\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p1 rootwait rw\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; mmc dev 1; ext2load mmc 1:1 $loadaddr $vkernel && bootm\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} root=/dev/mmcblk1p1 rootwait rw\0" \
+ "bootcmd_sd=run bootargs_base bootargs_sd; mmc dev 0; ext2load mmc 0:1 $loadaddr $vkernel && bootm\0" \
+ "bootcmd=run bootcmd_sd\0"
+#else
+// steven: default config
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "ethaddr=00:01:02:03:04:05\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "vkernel=/boot/uImage.vab820\0" \
+ "hdmi=video=mxcfb0:dev=hdmi,1920x1080M@60,bpp=32\0"\
+ "lvds=video=mxcfb0:dev=ldb,LDB-WSXGA+,if=RGB24 ldb=spl0\0"\
+ "bootargs_base=setenv bootargs console=ttymxc1,115200 ${hdmi} console=tty1,115200\0"\
+ "viewsfenv=sf probe 1 ; sf read 0x10800000 0xc0000 0x2000 ; md 0x10800000\0" \
+ "clearsfenv=sf probe 1 ; sf erase 0xc0000 0x2000 ; echo flash environment.\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs} root=/dev/mmcblk0p1 rootwait rw\0" \
+ "bootcmd_mmc=run bootargs_base bootargs_mmc; mmc dev 1; ext2load mmc 1:1 $loadaddr $vkernel && bootm\0" \
+ "bootargs_sd=setenv bootargs ${bootargs} root=/dev/mmcblk1p1 rootwait rw\0" \
+ "bootcmd_sd=run bootargs_base bootargs_sd; mmc dev 0; ext2load mmc 0:1 $loadaddr $vkernel && bootm\0" \
+ "bootcmd=run bootcmd_mmc\0"
+#endif
#define CONFIG_ARP_TIMEOUT 200UL
@@ -153,7 +165,9 @@
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "MX6Q SABRELITE U-Boot > "
+// Steven
+#define CONFIG_SYS_PROMPT "MX6Q VAB820 U-Boot > "
+
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
@@ -284,9 +298,10 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
-#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024)
-#define iomem_valid_addr(addr, size) \
- (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
+// Steven: DON'T access more than 1GB address on uboot
+#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024)
+//#define iomem_valid_addr(addr, size) \
+// (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
/*-----------------------------------------------------------------------
* FLASH and environment organization
@@ -294,9 +309,12 @@
#define CONFIG_SYS_NO_FLASH
/* Monitor at beginning of flash */
-/* #define CONFIG_FSL_ENV_IN_MMC */
/* #define CONFIG_FSL_ENV_IN_SATA */
-#define CONFIG_FSL_ENV_IN_SF
+#ifdef VAB820_FACTORY
+ #define CONFIG_FSL_ENV_IN_MMC
+#else
+ #define CONFIG_FSL_ENV_IN_SF
+#endif
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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