First prototype of Wavengine using FPGA

Clock.v

`timescale 1ns / 1ps

module clock(clk_in,rst,clk_out,clk_select_line);

input clk_in;
input [2:0]clk_select_line;
input rst;

output reg clk_out;

reg [21:0]counter;

always@(posedge clk_in)
begin
	if(rst == 1'b0)	
	begin
	counter <= 22'b0;
	end
	else
	begin
	counter <= counter + 22'b1;
	end
end

always@(*)
begin
	case (clk_select_line)
	3'b000 : clk_out = counter[0]; 
	3'b001 : clk_out = counter[1]; 
	3'b010 : clk_out = counter[3]; 
	3'b011 : clk_out = counter[6]; 
	3'b100 : clk_out = counter[9];
	3'b101 : clk_out = counter[13];
	3'b110 : clk_out = counter[17];
	3'b111 : clk_out = counter[21];
	endcase
end

endmodule

DDS_using_FPGA.v

`timescale 1ns / 1ps

module FPGA_SRAM(

input rst_b,																		//from TIVA	
input clk_CMOS,																	//from FPGA
input serial_data,																//from TIVA
input serial_clock,																//from TIVA
input output_enable_b,															//from TIVA
input rw_sig_from_TIVA,															//from TIVA
input [2:0]clock_speed_select,												//from TIVA
inout [13:0]data_in_out,														//to and from SRAM
input address_increment,														//from TIVA
input address_register_pulse,													//from TIVA
output [13:0]data_out, 															//to DAC from SRAM
output [15:0]address_out,														//to SRAM
output clk_out_dac																//to DAC

);

wire clk; //from internal configurable clock (Max 25 MHz)
wire [15:0]data_from_shift_register;
reg [16:0]address_counter; //1 extra bit to monitor the overflow
reg [13:0]data_register;
reg [15:0]address_register;
wire final_address_clock;  

assign clk_out_dac = final_address_clock;
assign data_out = (rw_sig_from_TIVA)?(data_register):(14'bz); //just a wire to the output of the FPGA 
assign final_address_clock = (rw_sig_from_TIVA)?(clk):(address_increment); 
//selection between 2 clocks , input clock generator and TIVA pulse generator

assign data_in_out = (~(output_enable_b|rw_sig_from_TIVA))?(data_from_shift_register[13:0]):(14'bz);
//asyncronous data bus with accepting the MSB 14 bits while in data mode , it is right shift !
//data is put to data_in_out nets only when both output_enable_b and rw_sig_from_TIVA are logic = 0

assign address_out = address_counter[15:0];
//the MSB is actually representing the zero occurance when the overflow occurs.
clock m0(.clk_in(clk_CMOS),.rst(rst_b),.clk_out(clk),.clk_select_line(clock_speed_select));
//fixed clock for testing purpose , approx 1 sec
shift_reg m1(.data_in(serial_data),.clock_in(serial_clock),.data_out(data_from_shift_register)); 
//this data_in_out has no provision for high impedance in shift_reg module unlike tested

always@(posedge final_address_clock)
begin
	if(rst_b == 1'b0)
	begin
		address_counter <= {1'b0,address_register};
	end
	else
	begin
		if(address_counter[16] == 1'b0)
		begin
			address_counter <= address_counter - 1'b1;
			data_register <= data_in_out;
		end
		else
		begin
			address_counter <= {1'b0,address_register}; 
		end
	end
end

always@(posedge serial_clock)
begin
	if(address_register_pulse == 1'b0)
	begin
	address_register <= {serial_data,address_register[15:1]};
	end
end

endmodule