foo.diff

diff --git a/drivers/video/msm/Kconfig b/drivers/video/msm/Kconfig
index 981f845..01edf92 100644
--- a/drivers/video/msm/Kconfig
+++ b/drivers/video/msm/Kconfig
@@ -1,997 +1,37 @@
-
-source "drivers/video/msm/vidc/Kconfig"
-
-config FB_MSM
-	tristate "MSM Framebuffer support"
-	depends on FB && ARCH_MSM
-	select FB_BACKLIGHT if FB_MSM_BACKLIGHT
-	select NEW_LEDS
-	select LEDS_CLASS
-	select FB_CFB_FILLRECT
-	select FB_CFB_COPYAREA
-	select FB_CFB_IMAGEBLIT
-	select SYNC
-	select SW_SYNC
-	---help---
-	  Support for MSM Framebuffer.
-
-if FB_MSM
-
-config FB_MSM_BACKLIGHT
-	bool "Support for backlight control"
-	default y
-	---help---
-	  Say Y here if you want to control the backlight of your display.
-
-config FB_MSM_LOGO
-	bool "MSM Frame Buffer Logo"
-	default n
-	---help---
-	  Show /initlogo.rle during boot.
-
-config FB_MSM_LCDC_HW
-	bool
-	default n
-
-config FB_MSM_TRIPLE_BUFFER
-	bool "Support for triple frame buffer"
-	default n
-
-config FB_MSM_MDP_HW
-	bool
-	default n
-
-config FB_MSM_MDSS_COMMON
-	bool
-
-choice
-	prompt "MDP HW version"
-	default FB_MSM_MDP22
-
-config FB_MSM_MDP22
-	select FB_MSM_MDP_HW
-	bool "MDP HW ver2.2"
-	---help---
-	  Support for MSM MDP HW revision 2.2
-	  Say Y here if this is msm7201 variant platform.
-
-config FB_MSM_MDP30
-	select FB_MSM_LCDC_HW
-	bool "MDP HW ver3.0"
-	---help---
-	  Support for MSM MDP HW revision 3.0
-	  Say Y here if this is msm7x25 variant platform.
-
-config FB_MSM_MDP303
-	depends on FB_MSM_MDP30
-	select FB_MSM_MDP_HW
-	bool "MDP HW ver3.03"
-	default n
-	---help---
-	  Support for MSM MDP HW revision 3.03. This is a new version of
-	  MDP3.0 which has the required functionality to support the features
-	  required for msm7x2xA platform.
-	  Say Y here if this is msm7x2xA variant platform.
-
-config FB_MSM_MDP31
-	select FB_MSM_LCDC_HW
-	select FB_MSM_MDP_HW
-	bool "MDP HW ver3.1"
-	---help---
-	  Support for MSM MDP HW revision 3.1
-	  Say Y here if this is msm8x50 variant platform.
-
-config FB_MSM_MDP40
-	select FB_MSM_LCDC_HW
-	select FB_MSM_MDP_HW
-	bool "MDP HW ver4.0"
-	---help---
-	  Support for MSM MDP HW revision 4.0
-	  Say Y here if this is msm7x30 variant platform.
-
-config FB_MSM_MDSS
-	bool "MDSS HW"
-	select FB_MSM_MDSS_COMMON
-	---help---
-	The Mobile Display Sub System (MDSS) driver supports devices which
-	contain MDSS hardware block.
-
-	The MDSS driver implements frame buffer interface to provide access to
-	the display hardware and provide a way for users to display graphics
-	on connected display panels.
-
-config FB_MSM_MDP_NONE
-	bool "MDP HW None"
-	---help---
-	  Say Y here if this is mdm platform.
-
-endchoice
-
-config FB_MSM_QPIC
-	bool
-	select FB_MSM_MDSS_COMMON
-
-config FB_MSM_EBI2
-	bool
-	default n
-
-config FB_MSM_MDDI
-	bool
-	default n
-
-config FB_MSM_MIPI_DSI
-	bool
-	default n
-
-config FB_MSM_LCDC
-	bool
-	default n
-
-config FB_MSM_LVDS
-	bool
-	default n
-
-config FB_MSM_OVERLAY
-	depends on FB_MSM_MDP40
-	bool "MDP4 overlay support"
-	default n
-
-config FB_MSM_DTV
-	depends on FB_MSM_OVERLAY
-	bool
-	default n
-
-config FB_MSM_EXTMDDI
-	bool
-	default n
-
-config FB_MSM_TVOUT
-	bool
-	default n
-
-config FB_MSM_MDDI_TOSHIBA_COMMON
-	bool
-	select FB_MSM_MDDI
-	default n
-
-config FB_MSM_MDDI_TOSHIBA_COMMON_VGA
-	bool
-	select FB_MSM_MDDI_TOSHIBA_COMMON
-	default n
-
-config FB_MSM_MDDI_ORISE
-	bool
-	select FB_MSM_MDDI
-	default n
-
-config FB_MSM_MDDI_QUICKVX
-	bool
-	select FB_MSM_MDDI
-	default n
-
-config FB_MSM_MDDI_AUTO_DETECT
-	bool
-	select FB_MSM_MDDI
-	default n
-
-config FB_MSM_LCDC_AUTO_DETECT
-	bool
-	select FB_MSM_LCDC
-	default n
-
-config FB_MSM_LCDC_PANEL
-	bool
-	select FB_MSM_LCDC
-	default n
-
-config FB_MSM_MIPI_DSI_TOSHIBA
-	bool
-	select FB_MSM_MIPI_DSI
-	default n
-
-config FB_MSM_MIPI_DSI_RENESAS
-	bool
-	select FB_MSM_MIPI_DSI
-	default n
-
-config FB_MSM_MIPI_DSI_TRULY
-	bool
-	select FB_MSM_MIPI_DSI
-
-config FB_MSM_MIPI_DSI_SIMULATOR
-	bool
-	select FB_MSM_MIPI_DSI
-	default n
-
-config FB_MSM_MIPI_DSI_NOVATEK
-        bool
-        select FB_MSM_MIPI_DSI
-        default n
-
-config FB_MSM_MIPI_DSI_NT35510
-	bool
-	select FB_MSM_MIPI_DSI
-
-config FB_MSM_MIPI_DSI_ORISE
-        bool
-        select FB_MSM_MIPI_DSI
-        default n
-
-config FB_MSM_MIPI_DSI_NT35516
-	bool
-	select FB_MSM_MIPI_DSI
-
-config FB_MSM_MIPI_DSI_TIANMA
-	bool
-	select FB_MSM_MIPI_DSI
-
-config FB_MSM_MIPI_DSI_TC358764_DSI2LVDS
-	bool
-	select FB_MSM_MIPI_DSI
-	---help---
-	  Support for Toshiba MIPI DSI-to-LVDS bridge.
-	  The chip supports 1366x768 24-bit
-	  using a single LVDS link
-	  and up to WUXGA 1920x1200 18-bit
-	  using a dual LVDS link.
-
-config FB_MSM_LCDC_ST15_WXGA
-    bool
-    select FB_MSM_LCDC_PANEL
-    default n
-
-config FB_MSM_LCDC_ST15_PANEL
-    depends on FB_MSM_LCDC_HW
-    bool "LCDC ST1.5 Panel"
-    select FB_MSM_LCDC_ST15_WXGA
-    ---help---
-      Support for ST1.5 WXGA (1366x768) panel
-
-config FB_MSM_LCDC_PRISM_WVGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_SAMSUNG_WSVGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_CHIMEI_WXGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_GORDON_VGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_TOSHIBA_WVGA_PT
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_TOSHIBA_FWVGA_PT
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_SHARP_WVGA_PT
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_AUO_WVGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_TRULY_HVGA_IPS3P2335
-        bool
-        select FB_MSM_LCDC_PANEL
-        default n
-
-config FB_MSM_LCDC_TRULY_HVGA_IPS3P2335_PT_PANEL
-        depends on FB_MSM_LCDC_HW
-        bool "LCDC Truly HVGA PT Panel"
-        select FB_MSM_LCDC_TRULY_HVGA_IPS3P2335
-        default n
-        ---help---
-        Support for LCDC Truly HVGA PT panel
-
-config FB_MSM_LCDC_SAMSUNG_OLED_PT
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_NT35582_WVGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LCDC_WXGA
-	bool
-	select FB_MSM_LCDC_PANEL
-	default n
-
-config FB_MSM_LVDS_CHIMEI_WXGA
-	bool
-	select FB_MSM_LVDS
-	default n
-
-config FB_MSM_LVDS_FRC_FHD
-	bool
-	select FB_MSM_LVDS
-	default n
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_TOSHIBA
-	default n
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_TOSHIBA
-	default n
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA
-	bool
-	select FB_MSM_MIPI_DSI_TOSHIBA
-	default n
-
-config FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
-	bool
-	select FB_MSM_MIPI_DSI_NOVATEK
-	default n
-
-config FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
-	bool
-	select FB_MSM_MIPI_DSI_NOVATEK
-	default n
-
-config FB_MSM_MIPI_ORISE_VIDEO_720P_PT
-	bool
-	select FB_MSM_MIPI_DSI_ORISE
-	default n
-
-config FB_MSM_MIPI_ORISE_CMD_720P_PT
-	bool
-	select FB_MSM_MIPI_DSI_ORISE
-	default n
-
-config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_RENESAS
-	default n
-
-config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_RENESAS
-	default n
-
-config FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_NT35510
-	default n
-
-config FB_MSM_MIPI_NT35510_CMD_WVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_NT35510
-	default n
-
-config FB_MSM_MIPI_NT35516_VIDEO_QHD_PT
-        bool
-        select FB_MSM_MIPI_DSI_NT35516
-        default n
-
-config FB_MSM_MIPI_NT35516_CMD_QHD_PT
-        bool
-        select FB_MSM_MIPI_DSI_NT35516
-        default n
-
-config FB_MSM_MIPI_TIANMA_CMD_HVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_TIANMA
-	default n
-
-config FB_MSM_MIPI_TIANMA_VIDEO_QHD_PT
-	bool
-	select FB_MSM_MIPI_DSI_TIANMA
-	default n
-
-config FB_MSM_MIPI_CHIMEI_WXGA
-	bool "LVDS Chimei WXGA Panel using Toshiba MIPI DSI-to-LVDS bridge."
-	select FB_MSM_MIPI_DSI_TC358764_DSI2LVDS
-	---help---
-	  Support for Chimei WXGA (1366x768) panel.
-	  The panel is using a serial LVDS input.
-	  The panel is connected to the host
-	  via Toshiba DSI-to-LVDS bridge.
-
-config FB_MSM_MIPI_CHIMEI_WUXGA
-	bool "LVDS Chimei WUXGA Panel using Toshiba MIPI DSI-to-LVDS bridge."
-	select FB_MSM_MIPI_DSI_TC358764_DSI2LVDS
-	---help---
-	  Support for Chimei WUXGA (1920x1200) panel.
-	  The panel is using a serial LVDS input.
-	  The panel is connected to the host
-	  via Toshiba DSI-to-LVDS bridge.
-
-config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
-	bool
-	select FB_MSM_MIPI_DSI_TRULY
-
-config FB_MSM_MIPI_SIMULATOR_VIDEO
-	bool
-	select FB_MSM_MIPI_DSI_SIMULATOR
-	default n
-
-config FB_MSM_NO_MDP_PIPE_CTRL
-	depends on FB_MSM_OVERLAY
-	bool "Do not use mdp_pipe_ctrl"
-	---help---
-	  Saying 'Y' here obsoletes the mdp_pipe_ctrl function,
-	  which was used to control mdp-related clocks. MDP4 vsync-driven
-	  screen updates will use a different clock control mechanism if
-	  this is selected.
-
-config FB_MSM_OVERLAY0_WRITEBACK
-	depends on FB_MSM_OVERLAY
-        bool "MDP overlay0 write back mode enable"
-	---help---
-	  Support for MDP4 OVERLAY0 write back mode
-
-
-config FB_MSM_OVERLAY1_WRITEBACK
-        depends on FB_MSM_OVERLAY
-        bool "MDP overlay1 write back mode enable"
-        ---help---
-          Support for MDP4 OVERLAY1 write back mode
-
-config FB_MSM_WRITEBACK_MSM_PANEL
-	depends on FB_MSM_OVERLAY
-        bool "MDP overlay write back panel enable"
-	---help---
-	  Support for MDP4 OVERLAY write back mode
-choice
-	prompt "LCD Panel"
-	default FB_MSM_MDDI_AUTO_DETECT
-
-config FB_MSM_LCDC_PRISM_WVGA_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Prism WVGA Panel"
-	select FB_MSM_LCDC_PRISM_WVGA
-	---help---
-	  Support for LCDC Prism WVGA (800x480) panel
-
-config FB_MSM_LCDC_SAMSUNG_WSVGA_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Samsung WSVGA Panel"
-	select FB_MSM_LCDC_SAMSUNG_WSVGA
-	---help---
-	  Support for LCDC Samsung WSVGA (1024x600) panel
-
-config FB_MSM_LCDC_CHIMEI_WXGA_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Chimei WXGA Panel"
-	select FB_MSM_LCDC_CHIMEI_WXGA
-	---help---
-	  Support for LCDC Chimei WXGA (1366x768) panel
-
-config FB_MSM_LCDC_GORDON_VGA_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Gordon VGA Panel"
-	select FB_MSM_LCDC_GORDON_VGA
-	---help---
-	  Support for LCDC Gordon VGA (480x640) panel
-
-config FB_MSM_LCDC_TOSHIBA_WVGA_PT_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Toshiba WVGA PT Panel"
-	select FB_MSM_LCDC_TOSHIBA_WVGA_PT
-	---help---
-	  Support for LCDC Toshiba WVGA PT (480x800) panel
-
-config FB_MSM_LCDC_TOSHIBA_FWVGA_PT_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Toshiba FWVGA PT Panel"
-	select FB_MSM_LCDC_TOSHIBA_FWVGA_PT
-	---help---
-	  Support for LCDC Toshiba FWVGA PT (480x864) panel. This
-	  configuration has to be selected to support the Toshiba
-	  FWVGA (480x864) portrait panel.
-
-config FB_MSM_LCDC_SHARP_WVGA_PT_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Sharp WVGA PT Panel"
-	select FB_MSM_LCDC_SHARP_WVGA_PT
-	---help---
-	  Support for LCDC Sharp WVGA PT (480x800) panel
-
-config FB_MSM_LCDC_AUO_WVGA_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC AUO WVGA Panel"
-	select FB_MSM_LCDC_AUO_WVGA
-	---help---
-	  Support for LCDC AUO WVGA(480x800) panel
-
-config FB_MSM_LCDC_NT35582_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC NT35582 WVGA Panel"
-	select FB_MSM_LCDC_NT35582_WVGA
-	---help---
-	  Support for LCDC NT35582 WVGA(480x800) panel
-
-config FB_MSM_LCDC_SAMSUNG_OLED_PT_PANEL
-	depends on FB_MSM_LCDC_HW
-	bool "LCDC Samsung OLED PT Panel"
-	select FB_MSM_LCDC_SAMSUNG_OLED_PT
-	---help---
-	  Support for LCDC Samsung OLED PT (480x800) panel
-
-config FB_MSM_LVDS_CHIMEI_WXGA_PANEL
-        bool "LVDS Chimei WXGA Panel"
-        select FB_MSM_LVDS_CHIMEI_WXGA
-        ---help---
-          Support for LVDS Chimei WXGA(1366x768) panel
-
-config FB_MSM_LVDS_FRC_FHD_PANEL
-	bool "LVDS FRC FHD Panel"
-	select FB_MSM_LVDS_FRC_FHD
-	---help---
-	  Support for LVDS Frc FHD(1920x1080) panel
-	  FRC(Frame Rate Converter) uses LVDS as input
-	  interface. It is treated as a HDMI panel with
-	  1920x1080 resolution.
-
-config FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-	depends on FB_MSM_LCDC_HW
-	bool "MDDI Panel Auto Detect + LCDC Prism WVGA"
-	select FB_MSM_MDDI_AUTO_DETECT
-	select FB_MSM_LCDC_PRISM_WVGA
-	select FB_MSM_LCDC_GORDON_VGA
-	select FB_MSM_LCDC_WXGA
-	select FB_MSM_LCDC_TOSHIBA_WVGA_PT
-	select FB_MSM_LCDC_TOSHIBA_FWVGA_PT
-	select FB_MSM_LCDC_SHARP_WVGA_PT
-	select FB_MSM_LCDC_ST15_WXGA
-	---help---
-	  Support for MDDI panel auto detect.
-	  If it can't find any MDDI panel, it will load an LCDC panel.
-
-config FB_MSM_MIPI_PANEL_DETECT
-	bool "MIPI Panel Detect"
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA
-	select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
-	select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
-	select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
-	select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
-	select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_NT35510_CMD_WVGA_PT
-	select FB_MSM_MIPI_ORISE_VIDEO_720P_PT
-	select FB_MSM_MIPI_ORISE_CMD_720P_PT
-	select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT
-	select FB_MSM_MIPI_NT35516_CMD_QHD_PT
-	select FB_MSM_MIPI_SIMULATOR_VIDEO
-	select FB_MSM_MIPI_CHIMEI_WXGA
-	select FB_MSM_MIPI_CHIMEI_WUXGA
-	---help---
-	  Support for MIPI panel auto detect
-
-config FB_MSM_MDDI_PANEL_AUTO_DETECT
-	bool "MDDI Panel Auto Detect"
-	select FB_MSM_MDDI_AUTO_DETECT
-	---help---
-	  Support for MDDI panel auto detect
-
-config FB_MSM_LCDC_PANEL_AUTO_DETECT
-	bool "LCDC Panel Auto Detect"
-	select FB_MSM_LCDC_AUTO_DETECT
-	select FB_MSM_LCDC_SAMSUNG_WSVGA
-	select FB_MSM_LCDC_AUO_WVGA
-	select FB_MSM_LCDC_NT35582_WVGA
-	select FB_MSM_LCDC_SAMSUNG_OLED_PT
-	---help---
-	  Support for LCDC panel auto detect
-
-config FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT
-	bool "LCDC + MIPI Panel Auto Detect"
-	select FB_MSM_LCDC_AUTO_DETECT
-	select FB_MSM_LCDC_SAMSUNG_WSVGA
-	select FB_MSM_LCDC_AUO_WVGA
-	select FB_MSM_LCDC_SAMSUNG_OLED_PT
-	select FB_MSM_LCDC_NT35582_WVGA
-	select FB_MSM_LCDC_TOSHIBA_FWVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
-	select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
-	select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
-	select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
-	select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
-	select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_NT35510_CMD_WVGA_PT
-	select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT
-	select FM_MSM_MIPI_NT35516_CMD_QHD_PT
-	select FB_MSM_MIPI_SIMULATOR_VIDEO
-	---help---
-	  Support for LCDC + MIPI panel auto detect
-
-config FB_MSM_LVDS_MIPI_PANEL_DETECT
-	bool "LVDS + MIPI Panel Auto Detect"
-	select FB_MSM_LVDS_CHIMEI_WXGA
-	select FB_MSM_LVDS_FRC_FHD
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA
-	select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
-	select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
-	select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
-	select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
-	select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT
-	select FB_MSM_MIPI_NT35510_CMD_WVGA_PT
-	select FB_MSM_MIPI_ORISE_VIDEO_720P_PT
-	select FB_MSM_MIPI_ORISE_CMD_720P_PT
-	select FB_MSM_MIPI_SIMULATOR_VIDEO
-	select FB_MSM_MIPI_CHIMEI_WXGA
-	select FB_MSM_MIPI_CHIMEI_WUXGA
-	---help---
-	  Support for LVDS + MIPI panel auto detect
-
-config FB_MSM_MDDI_PRISM_WVGA
-	bool "MDDI Prism WVGA Panel"
-	select FB_MSM_MDDI
-	---help---
-	  Support for MDDI Prism WVGA (800x480) panel
-
-config FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT
-	bool "MDDI Toshiba WVGA Portrait Panel"
-	select FB_MSM_MDDI_TOSHIBA_COMMON
-	---help---
-	  Support for MDDI Toshiba WVGA (480x800) panel
-
-config FB_MSM_MDDI_TOSHIBA_VGA
-	bool "MDDI Toshiba VGA Panel"
-	select FB_MSM_MDDI_TOSHIBA_COMMON_VGA
-	---help---
-	  Support for MDDI Toshiba VGA (480x640) and QCIF (176x220) panel
-
-config FB_MSM_MDDI_TOSHIBA_WVGA
-	bool "MDDI Toshiba WVGA panel"
-	select FB_MSM_MDDI_TOSHIBA_COMMON
-	---help---
-	  Support for MDDI Toshiba (800x480) WVGA panel
-
-config FB_MSM_MDDI_SHARP_QVGA_128x128
-	bool "MDDI Sharp QVGA Dual Panel"
-	select FB_MSM_MDDI
-	---help---
-	  Support for MDDI Sharp QVGA (240x320) and 128x128 dual panel
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT_PANEL
-	bool "MIPI Toshiba WVGA PT Panel"
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT_PANEL
-	bool "MIPI Toshiba WSVGA PT Panel"
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT
-
-config FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA_PANEL
-	bool "MIPI Toshiba WUXGA (1920x1200) Panel"
-	select FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA
-
-config FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT_PANEL
-	bool "MIPI NOVATEK VIDEO QHD PT Panel"
-	select FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT
-
-config FB_MSM_MIPI_NOVATEK_CMD_QHD_PT_PANEL
-	bool "MIPI NOVATEK CMD QHD PT Panel"
-	select FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
-
-config FB_MSM_MIPI_ORISE_VIDEO_720P_PT_PANEL
-	bool "MIPI ORISE VIDEO 720P PT Panel"
-	select FB_MSM_MIPI_ORISE_VIDEO_720P_PT
-
-config FB_MSM_MIPI_ORISE_CMD_720P_PT_PANEL
-	bool "MIPI ORISE CMD 720P PT Panel"
-	select FB_MSM_MIPI_ORISE_CMD_720P_PT
-
-config FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT_PANEL
-	bool "MIPI Renesas Video FWVGA PT Panel"
-	select FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT
-
-config FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT_PANEL
-	bool "MIPI Renesas Command FWVGA PT Panel"
-	select FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT
-
-config FB_MSM_MIPI_CHIMEI_WXGA_PANEL
-	bool "MIPI Chimei WXGA PT Panel"
-	select FB_MSM_MIPI_CHIMEI_WXGA
-
-config FB_MSM_MIPI_CHIMEI_WUXGA_PANEL
-	bool "MIPI Chimei WUXGA Panel"
-	select FB_MSM_MIPI_CHIMEI_WUXGA
-
-config FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT_PANEL
-	bool "MIPI Truly Video WVGA PT Panel"
-	select FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT
-
-config FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT_PANEL
-	bool "MIPI NT35510 Video WVGA PT Panel"
-	select FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT
-
-config FB_MSM_MIPI_NT35510_CMD_WVGA_PT_PANEL
-	bool "MIPI NT35510 Command WVGA PT Panel"
-	select FB_MSM_MIPI_NT35510_CMD_WVGA_PT
-
-config FB_MSM_MIPI_NT35516_VIDEO_QHD_PT_PANEL
-        bool "MIPI NT35516 Video qHD PT Panel"
-        select FB_MSM_MIPI_NT35516_VIDEO_QHD_PT
-
-config FB_MSM_MIPI_NT35516_CMD_QHD_PT_PANEL
-        bool "MIPI NT35516 Command qHD PT Panel"
-        select FB_MSM_MIPI_NT35516_CMD_QHD_PT
-
-config FB_MSM_MIPI_TIANMA_CMD_HVGA_PT_PANEL
-	bool "MIPI TIANMA CMD HVGA PT panel"
-	select FB_MSM_MIPI_TIANMA_CMD_HVGA_PT
+config FB_MSM_MDSS_WRITEBACK
+	bool "MDSS Writeback Panel"
 	---help---
-	Support for TIANMA CMD HVGA PT panel
+	The MDSS Writeback Panel provides support for routing the output of
+	MDSS frame buffer driver and MDP processing to memory.
 
-config FB_MSM_MIPI_SIMULATOR_VIDEO_PANEL
-	bool "MIPI Simulator Video Panel"
-	select FB_MSM_MIPI_SIMULATOR_VIDEO
-
-config FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF
-	bool "EBI2 TMD QVGA Epson QCIF Dual Panel"
-	select FB_MSM_EBI2
-	---help---
-	  Support for EBI2 TMD QVGA (240x320) and Epson QCIF (176x220) panel
-
-config FB_MSM_HDMI_AS_PRIMARY
-	depends on FB_MSM_HDMI_COMMON
-	bool "Use HDMI as primary panel"
-	---help---
-	Support for using HDMI as primary
-
-config FB_MSM_PANEL_NONE
-	bool "NONE"
-	---help---
-	  This will disable LCD panel
-endchoice
-
-choice
-	prompt "Secondary LCD Panel"
-	depends on  FB_MSM_MDP31
-	default FB_MSM_SECONDARY_PANEL_NONE
-
-config FB_MSM_LCDC_EXTERNAL_WXGA
-	depends on FB_MSM_MDP31
-	bool "External WXGA on LCDC"
-	select FB_MSM_LCDC_PANEL
-	---help---
-	  Support for external WXGA display (1280x720)
-
-config FB_MSM_HDMI_SII_EXTERNAL_720P
-	depends on FB_MSM_MDP31
-	bool "External SiI9022 HDMI 720P"
-	select FB_MSM_LCDC_PANEL
-	---help---
-	  Support for external HDMI 720p display (1280x720p)
-	  Using SiI9022 chipset
-
-config FB_MSM_SECONDARY_PANEL_NONE
-	bool "NONE"
-	---help---
-	  No secondary panel
-endchoice
-
-config FB_MSM_LCDC_DSUB
-	depends on FB_MSM_LCDC_SAMSUNG_WSVGA && FB_MSM_MDP40 && FB_MSM_LCDC_HW
-	bool "External DSUB support"
-	default n
-	---help---
-	  Support for external DSUB (VGA) display up to 1440x900.  The DSUB
-	  display shares the same video bus as the primary LCDC attached display.
-	  Typically only one of the two displays can be used at one time.
-
-config FB_MSM_EXT_INTERFACE_COMMON
-	bool
-	default n
-
-config FB_MSM_HDMI_COMMON
-	bool
-	default n
-
-config FB_MSM_HDMI_3D
-	bool
-	default n
-
-config FB_MSM_HDMI_ADV7520_PANEL
-	depends on FB_MSM_MDP40 && FB_MSM_OVERLAY
-        bool "LCDC HDMI ADV7520 720p Panel"
-        select FB_MSM_DTV
-        select FB_MSM_EXT_INTERFACE_COMMON
-	select FB_MSM_HDMI_COMMON
-	default n
-        ---help---
-        Support for LCDC 720p HDMI panel attached to ADV7520
-
-config FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-        depends on FB_MSM_HDMI_ADV7520_PANEL
-        bool "Use HDCP mode"
-        default y
-        ---help---
-          Support for HDCP mode for ADV7520 HDMI 720p Panel
-          Choose to enable HDCP
-
-
-config FB_MSM_HDMI_MSM_PANEL
-	depends on FB_MSM_MDP40
-	bool "MSM HDMI 1080p Panel"
-	select FB_MSM_DTV
-        select FB_MSM_EXT_INTERFACE_COMMON
-	select FB_MSM_HDMI_COMMON
-	select FB_MSM_HDMI_3D
-	default n
-	---help---
-	  Support for 480p/720p/1080i/1080p output through MSM HDMI
-
-config FB_MSM_HDMI_MSM_PANEL_DVI_SUPPORT
-	depends on FB_MSM_HDMI_MSM_PANEL
-	bool "Use DVI mode"
-	default n
-	---help---
-	  Support for DVI mode for MSM HDMI 1080p Panel
-
-config FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	depends on FB_MSM_HDMI_MSM_PANEL
-	bool "Enable CEC"
-	default n
-	---help---
-	  Support for HDMI CEC Feature
-	  Choose to enable CEC
-
-config FB_MSM_HDMI_MHL_9244
-	depends on FB_MSM_HDMI_MSM_PANEL
-	bool 'SI_MHL 9244 support'
+config FB_MSM_MDSS_HDMI_PANEL
+	depends on FB_MSM_MDSS
+	bool "MDSS HDMI Tx Panel"
 	default n
 	---help---
-	  Support the HDMI to MHL conversion.
-	  MHL (Mobile High-Definition Link) technology
-	  uses USB connector to output HDMI content
+	The MDSS HDMI Panel provides support for transmitting TMDS signals of
+	MDSS frame buffer data to connected hdmi compliant TVs, monitors etc.
 
-config FB_MSM_HDMI_MHL_8334
-	depends on FB_MSM_HDMI_MSM_PANEL
-	bool 'SI_MHL 8334 support '
+config FB_MSM_MDSS_HDMI_MHL_SII8334
+	depends on FB_MSM_MDSS_HDMI_PANEL
+	bool 'MHL SII8334 support '
 	default n
 	---help---
 	  Support the HDMI to MHL conversion.
 	  MHL (Mobile High-Definition Link) technology
 	  uses USB connector to output HDMI content
 
-choice
-	depends on  (FB_MSM_MDP22 || FB_MSM_MDP31 || FB_MSM_MDP40)
-	prompt "TVOut Region"
-	default FB_MSM_TVOUT_NONE
-
-config FB_MSM_TVOUT_NTSC_M
-	bool "NTSC M"
-	select FB_MSM_TVOUT
-        select FB_MSM_EXT_INTERFACE_COMMON
-	---help---
-	  Support for NTSC M region (North American and Korea)
-
-config FB_MSM_TVOUT_NTSC_J
-	bool "NTSC J"
-	select FB_MSM_TVOUT
-        select FB_MSM_EXT_INTERFACE_COMMON
-	---help---
-	  Support for NTSC J region (Japan)
-
-config FB_MSM_TVOUT_PAL_BDGHIN
-	bool "PAL BDGHIN"
-	select FB_MSM_TVOUT
-        select FB_MSM_EXT_INTERFACE_COMMON
-	---help---
-	  Support for PAL BDGHIN region (Non-argentina PAL-N)
-
-config FB_MSM_TVOUT_PAL_M
-	bool "PAL M"
-	select FB_MSM_TVOUT
-        select FB_MSM_EXT_INTERFACE_COMMON
-	---help---
-	  Support for PAL M region
-
-config FB_MSM_TVOUT_PAL_N
-	bool "PAL N"
-	select FB_MSM_TVOUT
-        select FB_MSM_EXT_INTERFACE_COMMON
-	---help---
-	  Support for PAL N region (Argentina PAL-N)
-
-config FB_MSM_TVOUT_NONE
-	bool "NONE"
-	---help---
-	  This will disable TV Out functionality.
-endchoice
-
-config FB_MSM_TVOUT_SVIDEO
-	bool "TVOut on S-video"
-	depends on FB_MSM_TVOUT
-	default n
-	---help---
-	  Selects whether the TVOut signal uses S-video.
-	  Choose n for composite output.
-
-choice
-	depends on  FB_MSM_MDP22
-	prompt "External MDDI"
-	default FB_MSM_EXTMDDI_SVGA
-
-config FB_MSM_EXTMDDI_SVGA
-	bool "External MDDI SVGA"
-	select FB_MSM_MDDI
-	select FB_MSM_EXTMDDI
-	---help---
-	  Support for MSM SVGA (800x600) external MDDI panel
-
-config FB_MSM_EXTMDDI_NONE
-	bool "NONE"
-	---help---
-	  This will disable External MDDI functionality.
-endchoice
-
-choice
-	prompt "Default framebuffer color depth"
-	depends on FB_MSM_MDP40 || FB_MSM_MDP31 || FB_MSM_MDP303
-	default FB_MSM_DEFAULT_DEPTH_RGBA8888
-
-config FB_MSM_DEFAULT_DEPTH_RGB565
-	bool "16 bits per pixel (RGB565)"
-
-config FB_MSM_DEFAULT_DEPTH_ARGB8888
-	bool "32 bits per pixel (ARGB8888)"
-
-config FB_MSM_DEFAULT_DEPTH_RGBA8888
-	bool "32 bits per pixel (RGBA8888)"
-
-endchoice
-
-config FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL
-	bool "EBI2 Epson QVGA Panel"
-	select FB_MSM_EBI2
-	default n
+config FB_MSM_MDSS_DSI_CTRL_STATUS
+	tristate "DSI controller status check feature"
 	---help---
-	  Support for EBI2 Epson QVGA (240x320) panel
+	  Check DSI controller status periodically (default period is 5
+	  seconds) by sending Bus-Turn-Around (BTA) command. If DSI controller
+	  fails to acknowledge the BTA command, it sends PANEL_ALIVE=0 status
+	  to HAL layer to reset the controller.
 
-config FB_MSM_EBI2_PANEL_DETECT
-	bool "EBI2 Panel Detect"
-	select FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL
-	default n
+config FB_MSM_MDSS_MDP3
+	depends on FB_MSM_MDSS
+	bool "MDP3 display controller"
 	---help---
-	  Support for EBI2 panel auto detect
-
-config FB_MSM_QPIC_ILI_QVGA_PANEL
-	bool "Qpic MIPI ILI QVGA Panel"
-	select FB_MSM_QPIC
-	---help---
-	  Support for MIPI ILI QVGA (240x320) panel
-	  ILI TECHNOLOGY 9341
-	  with on-chip full display RAM
-	  use parallel interface
-
-config FB_MSM_QPIC_PANEL_DETECT
-	bool "Qpic Panel Detect"
-	select FB_MSM_QPIC_ILI_QVGA_PANEL
-	---help---
-	  Support for Qpic panel auto detect
-
-if FB_MSM_MDSS
-	source "drivers/video/msm/mdss/Kconfig"
-endif
-endif
+	The MDP3 provides support for an older version display controller
+	included in latest display sub-system, known as MDSS.
diff --git a/drivers/video/msm/Makefile b/drivers/video/msm/Makefile
index 67c6b48..4eb1033 100644
--- a/drivers/video/msm/Makefile
+++ b/drivers/video/msm/Makefile
@@ -1,197 +1,46 @@
-ifeq ($(CONFIG_FB_MSM_MDSS_COMMON),y)
-obj-y += mdss/
-else
-obj-y := msm_fb.o
-
-obj-$(CONFIG_FB_MSM_LOGO) += logo.o
-obj-$(CONFIG_FB_BACKLIGHT) += msm_fb_bl.o
-
-ifeq ($(CONFIG_FB_MSM_MDP_HW),y)
-# MDP
-obj-y += mdp.o
-
-obj-$(CONFIG_DEBUG_FS) += mdp_debugfs.o
-
-ifeq ($(CONFIG_FB_MSM_MDP40),y)
-obj-y += mdp4_util.o
-else
-obj-y += mdp_hw_init.o
-obj-y += mdp_ppp.o
-ifeq ($(CONFIG_FB_MSM_MDP31),y)
-obj-y += mdp_ppp_v31.o
-else
-obj-y += mdp_ppp_v20.o
-endif
-endif
-
-ifeq ($(CONFIG_FB_MSM_OVERLAY),y)
-obj-y += mdp4_overlay.o
-obj-y += mdp4_overlay_lcdc.o
-ifeq ($(CONFIG_FB_MSM_MIPI_DSI),y)
-obj-y += mdp4_overlay_dsi_video.o
-obj-y += mdp4_overlay_dsi_cmd.o
-else
-obj-y += mdp4_overlay_mddi.o
-endif
-else
-obj-y += mdp_dma_lcdc.o
-endif
-
-obj-$(CONFIG_FB_MSM_MDP303) += mdp_dma_dsi_video.o
-
-ifeq ($(CONFIG_FB_MSM_DTV),y)
-obj-y += mdp4_dtv.o
-obj-y += mdp4_overlay_dtv.o
-endif
-
-obj-y += mdp_dma.o
-obj-y += mdp_dma_s.o
-obj-y += mdp_vsync.o
-obj-y += mdp_cursor.o
-obj-y += mdp_dma_tv.o
-obj-$(CONFIG_ARCH_MSM7X27A) += msm_dss_io_7x27a.o
-obj-$(CONFIG_ARCH_MSM8X60) += msm_dss_io_8x60.o
-obj-$(CONFIG_ARCH_MSM8960) += msm_dss_io_8960.o
-
-# EBI2
-obj-$(CONFIG_FB_MSM_EBI2) += ebi2_lcd.o
-
-# LCDC
-obj-$(CONFIG_FB_MSM_LCDC) += lcdc.o
-
-# LVDS
-obj-$(CONFIG_FB_MSM_LVDS) += lvds.o
-
-# MDDI
-msm_mddi-objs := mddi.o mddihost.o mddihosti.o
-obj-$(CONFIG_FB_MSM_MDDI) += msm_mddi.o
-
-# External MDDI
-msm_mddi_ext-objs := mddihost_e.o mddi_ext.o
-obj-$(CONFIG_FB_MSM_EXTMDDI) += msm_mddi_ext.o
-
-# MIPI gereric
-msm_mipi-objs := mipi_dsi.o mipi_dsi_host.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI) += msm_mipi.o
-
-# MIPI manufacture
-obj-$(CONFIG_FB_MSM_MIPI_DSI_TOSHIBA) += mipi_toshiba.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_NOVATEK) += mipi_novatek.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_ORISE) += mipi_orise.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_RENESAS) += mipi_renesas.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_TRULY) += mipi_truly.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35510) += mipi_NT35510.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_NT35516) += mipi_truly_tft540960_1_e.o
-obj-$(CONFIG_FB_MSM_MIPI_DSI_SIMULATOR) += mipi_simulator.o
-
-# MIPI Bridge
-obj-$(CONFIG_FB_MSM_MIPI_DSI_TC358764_DSI2LVDS) += mipi_tc358764_dsi2lvds.o
-
-# TVEnc
-obj-$(CONFIG_FB_MSM_TVOUT) += tvenc.o
-ifeq ($(CONFIG_FB_MSM_OVERLAY),y)
-obj-$(CONFIG_FB_MSM_TVOUT) += mdp4_overlay_atv.o
-endif
-
-# MSM FB Panel
-obj-y += msm_fb_panel.o
-obj-$(CONFIG_FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF) += ebi2_tmd20.o
-obj-$(CONFIG_FB_MSM_EBI2_TMD_QVGA_EPSON_QCIF) += ebi2_l2f.o
-
-ifeq ($(CONFIG_FB_MSM_MDDI_AUTO_DETECT),y)
-obj-y += mddi_prism.o
-obj-y += mddi_toshiba.o
-obj-y += mddi_toshiba_vga.o
-obj-y += mddi_toshiba_wvga_pt.o
-obj-y += mddi_toshiba_wvga.o
-obj-y += mddi_sharp.o
-obj-y += mddi_orise.o
-obj-y += mddi_quickvx.o
-else
-obj-$(CONFIG_FB_MSM_MDDI_PRISM_WVGA) += mddi_prism.o
-obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_COMMON) += mddi_toshiba.o
-obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_COMMON_VGA) += mddi_toshiba_vga.o
-obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA_PORTRAIT) += mddi_toshiba_wvga_pt.o
-obj-$(CONFIG_FB_MSM_MDDI_TOSHIBA_WVGA) += mddi_toshiba_wvga.o
-obj-$(CONFIG_FB_MSM_MDDI_SHARP_QVGA_128x128) += mddi_sharp.o
-obj-$(CONFIG_FB_MSM_MDDI_ORISE) += mddi_orise.o
-obj-$(CONFIG_FB_MSM_MDDI_QUICKVX) += mddi_quickvx.o
-endif
-
-ifeq ($(CONFIG_FB_MSM_MIPI_PANEL_DETECT),y)
-obj-y += mipi_toshiba_video_wvga_pt.o mipi_toshiba_video_wsvga_pt.o mipi_toshiba_video_wuxga.o
-obj-y += mipi_novatek_video_qhd_pt.o mipi_novatek_cmd_qhd_pt.o
-obj-y += mipi_orise_video_720p_pt.o mipi_orise_cmd_720p_pt.o
-obj-y += mipi_renesas_video_fwvga_pt.o mipi_renesas_cmd_fwvga_pt.o
-obj-y += mipi_NT35510_video_wvga_pt.o mipi_NT35510_cmd_wvga_pt.o
-obj-y += mipi_truly_tft540960_1_e_video_qhd_pt.o mipi_truly_tft540960_1_e_cmd_qhd_pt.o
-obj-y += mipi_chimei_wxga_pt.o
-obj-y += mipi_chimei_wuxga.o
-obj-y += mipi_truly_video_wvga_pt.o
-else
-obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WVGA_PT) += mipi_toshiba_video_wvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WSVGA_PT) += mipi_toshiba_video_wsvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_TOSHIBA_VIDEO_WUXGA) += mipi_toshiba_video_wuxga.o
-obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_VIDEO_QHD_PT) += mipi_novatek_video_qhd_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_ORISE_VIDEO_720P_PT) += mipi_orise_video_720p_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_ORISE_CMD_720P_PT) += mipi_orise_cmd_720p_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT) += mipi_novatek_cmd_qhd_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_RENESAS_CMD_FWVGA_PT) += mipi_renesas_cmd_fwvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_RENESAS_VIDEO_FWVGA_PT) += mipi_renesas_video_fwvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_TRULY_VIDEO_WVGA_PT) += mipi_truly_video_wvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_NT35510_CMD_WVGA_PT) += mipi_NT35510_cmd_wvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_NT35510_VIDEO_WVGA_PT) += mipi_NT35510_video_wvga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_NT35516_CMD_QHD_PT) += mipi_truly_tft540960_1_e_cmd_qhd_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_NT35516_VIDEO_QHD_PT) += mipi_truly_tft540960_1_e_video_qhd_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_SIMULATOR_VIDEO) += mipi_simulator_video.o
-obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WXGA) += mipi_chimei_wxga_pt.o
-obj-$(CONFIG_FB_MSM_MIPI_CHIMEI_WUXGA) += mipi_chimei_wuxga.o
-endif
-
-obj-$(CONFIG_FB_MSM_LCDC_PANEL) += lcdc_panel.o
-obj-$(CONFIG_FB_MSM_LCDC_PRISM_WVGA) += lcdc_prism.o
-obj-$(CONFIG_FB_MSM_LCDC_SAMSUNG_WSVGA) += lcdc_samsung_wsvga.o
-obj-$(CONFIG_FB_MSM_LCDC_CHIMEI_WXGA) += lcdc_chimei_wxga.o
-obj-$(CONFIG_FB_MSM_LCDC_NT35582_WVGA) += lcdc_nt35582_wvga.o
-obj-$(CONFIG_FB_MSM_LCDC_EXTERNAL_WXGA) += lcdc_external.o
-obj-$(CONFIG_FB_MSM_HDMI_SII_EXTERNAL_720P) += hdmi_sii9022.o
-obj-$(CONFIG_FB_MSM_LCDC_GORDON_VGA) += lcdc_gordon.o
-obj-$(CONFIG_FB_MSM_LCDC_WXGA) += lcdc_wxga.o
-obj-$(CONFIG_FB_MSM_LCDC_TOSHIBA_WVGA_PT) += lcdc_toshiba_wvga_pt.o
-obj-$(CONFIG_FB_MSM_LCDC_TOSHIBA_FWVGA_PT) += lcdc_toshiba_fwvga_pt.o
-obj-$(CONFIG_FB_MSM_LCDC_SHARP_WVGA_PT) += lcdc_sharp_wvga_pt.o
-obj-$(CONFIG_FB_MSM_LCDC_AUO_WVGA) += lcdc_auo_wvga.o
-obj-$(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) += lcdc_samsung_oled_pt.o
-obj-$(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) += adv7520.o
-obj-$(CONFIG_FB_MSM_LCDC_ST15_WXGA) += lcdc_st15.o
-obj-$(CONFIG_FB_MSM_LVDS_CHIMEI_WXGA) += lvds_chimei_wxga.o
-obj-$(CONFIG_FB_MSM_LVDS_FRC_FHD) += lvds_frc_fhd.o
-obj-$(CONFIG_FB_MSM_HDMI_MSM_PANEL) += hdmi_msm.o
-obj-$(CONFIG_FB_MSM_EXT_INTERFACE_COMMON) += external_common.o
-obj-$(CONFIG_FB_MSM_LCDC_TRULY_HVGA_IPS3P2335) += lcdc_truly_ips3p2335.o
-
-obj-$(CONFIG_FB_MSM_TVOUT) += tvout_msm.o
-
-ccflags-y := -I$(src)/mhl
-obj-$(CONFIG_FB_MSM_HDMI_MHL_8334) += mhl-8334.o
-mhl-8334-objs  += mhl/mhl_8334.o
-mhl-8334-objs  += mhl/mhl_i2c_utils.o
-
-obj-$(CONFIG_FB_MSM_EXTMDDI_SVGA) += mddi_ext_lcd.o
-
-obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_wfd_writeback_panel.o
-obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_wfd_writeback.o
-obj-$(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL) += mdp4_overlay_writeback.o
-else
-obj-$(CONFIG_FB_MSM_EBI2) += ebi2_host.o
-obj-$(CONFIG_FB_MSM_EBI2) += ebi2_lcd.o
-obj-y += msm_fb_panel.o
-obj-$(CONFIG_FB_MSM_EBI2_EPSON_S1D_QVGA_PANEL) += ebi2_epson_s1d_qvga.o
-endif
-endif
-
-obj-$(CONFIG_MSM_VIDC_1080P) += vidc/
-obj-$(CONFIG_MSM_VIDC_720P) += vidc/
-clean:
-	rm *.o .*cmd
+mdss-mdp3-objs = mdp3.o mdp3_dma.o mdp3_ctrl.o dsi_status_v2.o
+mdss-mdp3-objs += mdp3_ppp.o mdp3_ppp_hwio.o mdp3_ppp_data.o
+obj-$(CONFIG_FB_MSM_MDSS_MDP3) += mdss-mdp3.o
+
+mdss-mdp-objs := mdss_mdp.o mdss_mdp_ctl.o mdss_mdp_pipe.o mdss_mdp_util.o dsi_status_6g.o
+mdss-mdp-objs += mdss_mdp_pp.o
+mdss-mdp-objs += mdss_mdp_intf_video.o
+mdss-mdp-objs += mdss_mdp_intf_cmd.o
+mdss-mdp-objs += mdss_mdp_intf_writeback.o
+mdss-mdp-objs += mdss_mdp_rotator.o
+mdss-mdp-objs += mdss_mdp_overlay.o
+mdss-mdp-objs += mdss_mdp_splash_logo.o
+mdss-mdp-objs += mdss_mdp_wb.o
+obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o
+
+ifeq ($(CONFIG_FB_MSM_MDSS),y)
+obj-$(CONFIG_DEBUG_FS) += mdss_debug.o mdss_debug_xlog.o
+endif
+
+dsi-v2-objs = dsi_v2.o dsi_host_v2.o dsi_io_v2.o
+obj-$(CONFIG_FB_MSM_MDSS_MDP3) += dsi-v2.o
+
+mdss-dsi-objs := mdss_dsi.o mdss_dsi_host.o mdss_dsi_cmd.o mdss_dsi_status.o
+mdss-dsi-objs += mdss_dsi_panel.o
+mdss-dsi-objs += msm_mdss_io_8974.o
+obj-$(CONFIG_FB_MSM_MDSS) += mdss-dsi.o
+obj-$(CONFIG_FB_MSM_MDSS) += mdss_edp.o
+obj-$(CONFIG_FB_MSM_MDSS) += mdss_edp_aux.o
+
+obj-$(CONFIG_FB_MSM_MDSS) += mdss_io_util.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_tx.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_util.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_edid.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_hdcp.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_PANEL) += mdss_hdmi_cec.o
+obj-$(CONFIG_FB_MSM_MDSS_HDMI_MHL_SII8334) += mhl_sii8334.o mhl_msc.o
+
+obj-$(CONFIG_FB_MSM_MDSS_WRITEBACK) += mdss_wb.o
+
+mdss-qpic-objs := mdss_qpic.o mdss_fb.o mdss_qpic_panel.o
+obj-$(CONFIG_FB_MSM_QPIC) += mdss-qpic.o
+obj-$(CONFIG_FB_MSM_QPIC_ILI_QVGA_PANEL) += qpic_panel_ili_qvga.o
+
+obj-$(CONFIG_FB_MSM_MDSS) += mdss_fb.o
+
+obj-$(CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS) += mdss_dsi_status.o
diff --git a/drivers/video/msm/adv7520.c b/drivers/video/msm/adv7520.c
deleted file mode 100644
index 0e83d0f..0000000
--- a/drivers/video/msm/adv7520.c
+++ /dev/null
@@ -1,1035 +0,0 @@
-/* Copyright (c) 2010,2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/i2c.h>
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/adv7520.h>
-#include <linux/time.h>
-#include <linux/completion.h>
-#include <linux/wakelock.h>
-#include <linux/clk.h>
-#include <linux/pm_qos.h>
-
-#include <asm/atomic.h>
-
-#include <mach/cpuidle.h>
-
-#include "msm_fb.h"
-
-#define DEBUG
-#define DEV_DBG_PREFIX "HDMI: "
-
-#include "external_common.h"
-
-/* #define PORT_DEBUG */
-/* #define TESTING_FORCE_480p */
-
-#define HPD_DUTY_CYCLE	4 /*secs*/
-
-static struct external_common_state_type hdmi_common;
-
-static struct i2c_client *hclient;
-static struct clk *tv_enc_clk;
-
-static bool chip_power_on = FALSE;	/* For chip power on/off */
-static bool enable_5v_on = FALSE;
-static bool hpd_power_on = FALSE;
-static atomic_t comm_power_on;	/* For dtv power on/off (I2C) */
-static int suspend_count;
-
-static u8 reg[256];	/* HDMI panel registers */
-
-struct hdmi_data {
-	struct msm_hdmi_platform_data *pd;
-	struct work_struct isr_work;
-};
-static struct hdmi_data *dd;
-static struct work_struct hpd_timer_work;
-
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-static struct work_struct hdcp_handle_work;
-static int hdcp_activating;
-static DEFINE_MUTEX(hdcp_state_mutex);
-static int has_hdcp_hw_support = true;
-#endif
-
-static struct timer_list hpd_timer;
-static struct timer_list hpd_duty_timer;
-static struct work_struct hpd_duty_work;
-static unsigned int monitor_sense;
-static boolean hpd_cable_chg_detected;
-
-static struct pm_qos_request pm_qos_req;
-
-/* Change HDMI state */
-static void change_hdmi_state(int online)
-{
-	if (!external_common_state)
-		return;
-
-	mutex_lock(&external_common_state_hpd_mutex);
-	external_common_state->hpd_state = online;
-	mutex_unlock(&external_common_state_hpd_mutex);
-
-	if (!external_common_state->uevent_kobj)
-		return;
-
-	if (online) {
-		kobject_uevent(external_common_state->uevent_kobj,
-			KOBJ_ONLINE);
-		switch_set_state(&external_common_state->sdev, 1);
-	} else {
-		kobject_uevent(external_common_state->uevent_kobj,
-			KOBJ_OFFLINE);
-		switch_set_state(&external_common_state->sdev, 0);
-	}
-	DEV_INFO("adv7520_uevent: %d [suspend# %d]\n", online, suspend_count);
-}
-
-
-/*
- * Read a value from a register on ADV7520 device
- * If sucessfull returns value read , otherwise error.
- */
-static u8 adv7520_read_reg(struct i2c_client *client, u8 reg)
-{
-	int err;
-	struct i2c_msg msg[2];
-	u8 reg_buf[] = { reg };
-	u8 data_buf[] = { 0 };
-
-	if (!client->adapter)
-		return -ENODEV;
-	if (!atomic_read(&comm_power_on)) {
-		DEV_WARN("%s: WARN: missing GPIO power\n", __func__);
-		return -ENODEV;
-	}
-
-	msg[0].addr = client->addr;
-	msg[0].flags = 0;
-	msg[0].len = 1;
-	msg[0].buf = reg_buf;
-
-	msg[1].addr = client->addr;
-	msg[1].flags = I2C_M_RD;
-	msg[1].len = 1;
-	msg[1].buf = data_buf;
-
-	err = i2c_transfer(client->adapter, msg, 2);
-
-	if (err < 0) {
-		DEV_INFO("%s: I2C err: %d\n", __func__, err);
-		return err;
-	}
-
-#ifdef PORT_DEBUG
-	DEV_INFO("HDMI[%02x] [R] %02x\n", reg, data);
-#endif
-	return *data_buf;
-}
-
-/*
- * Write a value to a register on adv7520 device.
- * Returns zero if successful, or non-zero otherwise.
- */
-static int adv7520_write_reg(struct i2c_client *client, u8 reg, u8 val)
-{
-	int err;
-	struct i2c_msg msg[1];
-	unsigned char data[2];
-
-	if (!client->adapter)
-		return -ENODEV;
-	if (!atomic_read(&comm_power_on)) {
-		DEV_WARN("%s: WARN: missing GPIO power\n", __func__);
-		return -ENODEV;
-	}
-
-	msg->addr = client->addr;
-	msg->flags = 0;
-	msg->len = 2;
-	msg->buf = data;
-	data[0] = reg;
-	data[1] = val;
-
-	err = i2c_transfer(client->adapter, msg, 1);
-	if (err >= 0)
-		return 0;
-#ifdef PORT_DEBUG
-	DEV_INFO("HDMI[%02x] [W] %02x [%d]\n", reg, val, err);
-#endif
-	return err;
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-static void adv7520_close_hdcp_link(void)
-{
-	if (!external_common_state->hdcp_active && !hdcp_activating)
-		return;
-
-	DEV_INFO("HDCP: Close link\n");
-
-	reg[0xD5] = adv7520_read_reg(hclient, 0xD5);
-	reg[0xD5] &= 0xFE;
-	adv7520_write_reg(hclient, 0xD5, (u8)reg[0xD5]);
-
-	reg[0x16] = adv7520_read_reg(hclient, 0x16);
-	reg[0x16] &= 0xFE;
-	adv7520_write_reg(hclient, 0x16, (u8)reg[0x16]);
-
-	/* UnMute Audio */
-	adv7520_write_reg(hclient, 0x0C, (u8)0x84);
-
-	external_common_state->hdcp_active = FALSE;
-	mutex_lock(&hdcp_state_mutex);
-	hdcp_activating = FALSE;
-	mutex_unlock(&hdcp_state_mutex);
-}
-
-static void adv7520_comm_power(int on, int show);
-static void adv7520_hdcp_enable(struct work_struct *work)
-{
-	DEV_INFO("HDCP: Start reg[0xaf]=%02x (mute audio)\n", reg[0xaf]);
-
-	adv7520_comm_power(1, 1);
-
-	/* Mute Audio */
-	adv7520_write_reg(hclient, 0x0C, (u8)0xC3);
-
-	msleep(200);
-	/* Wait for BKSV ready interrupt */
-	/* Read BKSV's keys from HDTV */
-	reg[0xBF] = adv7520_read_reg(hclient, 0xBF);
-	reg[0xC0] = adv7520_read_reg(hclient, 0xC0);
-	reg[0xC1] = adv7520_read_reg(hclient, 0xC1);
-	reg[0xC2] = adv7520_read_reg(hclient, 0xC2);
-	reg[0xc3] = adv7520_read_reg(hclient, 0xC3);
-
-	DEV_DBG("HDCP: BKSV={%02x,%02x,%02x,%02x,%02x}\n", reg[0xbf], reg[0xc0],
-		reg[0xc1], reg[0xc2], reg[0xc3]);
-
-	/* Is SINK repeater */
-	reg[0xBE] = adv7520_read_reg(hclient, 0xBE);
-	if (~(reg[0xBE] & 0x40)) {
-		; /* compare with revocation list */
-		/* Check 20 1's and 20 zero's */
-	} else {
-		/* Don't implement HDCP if sink as a repeater */
-		adv7520_write_reg(hclient, 0x0C, (u8)0x84);
-		mutex_lock(&hdcp_state_mutex);
-		hdcp_activating = FALSE;
-		mutex_unlock(&hdcp_state_mutex);
-		DEV_WARN("HDCP: Sink Repeater (%02x), (unmute audio)\n",
-			reg[0xbe]);
-
-		adv7520_comm_power(0, 1);
-		return;
-	}
-
-	msleep(200);
-	reg[0xB8] = adv7520_read_reg(hclient, 0xB8);
-	DEV_INFO("HDCP: Status reg[0xB8] is %02x\n", reg[0xb8]);
-	if (reg[0xb8] & 0x40) {
-		/* UnMute Audio */
-		adv7520_write_reg(hclient, 0x0C, (u8)0x84);
-		DEV_INFO("HDCP: A/V content Encrypted (unmute audio)\n");
-		external_common_state->hdcp_active = TRUE;
-	}
-	adv7520_comm_power(0, 1);
-
-	mutex_lock(&hdcp_state_mutex);
-	hdcp_activating = FALSE;
-	mutex_unlock(&hdcp_state_mutex);
-}
-#endif
-
-static int adv7520_read_edid_block(int block, uint8 *edid_buf)
-{
-	u8 r = 0;
-	int ret;
-	struct i2c_msg msg[] = {
-		{ .addr = reg[0x43] >> 1,
-		  .flags = 0,
-		  .len = 1,
-		  .buf = &r },
-		{ .addr = reg[0x43] >> 1,
-		  .flags = I2C_M_RD,
-		  .len = 0x100,
-		  .buf = edid_buf } };
-
-	if (block > 0)
-		return 0;
-	ret = i2c_transfer(hclient->adapter, msg, 2);
-	DEV_DBG("EDID block: addr=%02x, ret=%d\n", reg[0x43] >> 1, ret);
-	return (ret < 2) ? -ENODEV : 0;
-}
-
-static void adv7520_read_edid(void)
-{
-	external_common_state->read_edid_block = adv7520_read_edid_block;
-	if (hdmi_common_read_edid()) {
-		u8 timeout;
-		DEV_INFO("%s: retry\n", __func__);
-		adv7520_write_reg(hclient, 0xc9, 0x13);
-		msleep(500);
-		timeout = (adv7520_read_reg(hclient, 0x96) & (1 << 2));
-		if (timeout) {
-			hdmi_common_read_edid();
-		}
-	}
-}
-
-static void adv7520_chip_on(void)
-{
-	if (!chip_power_on) {
-		/* Get the current register holding the power bit. */
-		unsigned long reg0xaf = adv7520_read_reg(hclient, 0xaf);
-
-		dd->pd->core_power(1, 1);
-
-		/* Set the HDMI select bit. */
-		set_bit(1, &reg0xaf);
-		DEV_INFO("%s: turn on chip power\n", __func__);
-		adv7520_write_reg(hclient, 0x41, 0x10);
-		adv7520_write_reg(hclient, 0xaf, (u8)reg0xaf);
-		chip_power_on = TRUE;
-	} else
-		DEV_INFO("%s: chip already has power\n", __func__);
-}
-
-static void adv7520_chip_off(void)
-{
-	if (chip_power_on) {
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-		if (has_hdcp_hw_support)
-			adv7520_close_hdcp_link();
-#endif
-
-		DEV_INFO("%s: turn off chip power\n", __func__);
-		adv7520_write_reg(hclient, 0x41, 0x50);
-		dd->pd->core_power(0, 1);
-		chip_power_on = FALSE;
-	} else
-		DEV_INFO("%s: chip is already off\n", __func__);
-
-	monitor_sense = 0;
-	hpd_cable_chg_detected = FALSE;
-
-	if (enable_5v_on) {
-		dd->pd->enable_5v(0);
-		enable_5v_on = FALSE;
-	}
-}
-
-/*  Power ON/OFF  ADV7520 chip */
-static void adv7520_isr_w(struct work_struct *work);
-static void adv7520_comm_power(int on, int show)
-{
-	if (!on)
-		atomic_dec(&comm_power_on);
-	dd->pd->comm_power(on, 0/*show*/);
-	if (on)
-		atomic_inc(&comm_power_on);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-static void adv7520_start_hdcp(void);
-#endif
-static int adv7520_power_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
-
-	clk_prepare_enable(tv_enc_clk);
-	external_common_state->dev = &pdev->dev;
-	if (mfd != NULL) {
-		DEV_INFO("adv7520_power: ON (%dx%d %d)\n",
-			mfd->var_xres, mfd->var_yres, mfd->var_pixclock);
-		hdmi_common_get_video_format_from_drv_data(mfd);
-	}
-
-	adv7520_comm_power(1, 1);
-	/* Check if HPD is signaled */
-	if (adv7520_read_reg(hclient, 0x42) & (1 << 6)) {
-		DEV_INFO("power_on: cable detected\n");
-		monitor_sense = adv7520_read_reg(hclient, 0xC6);
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-		if (has_hdcp_hw_support) {
-			if (!hdcp_activating)
-				adv7520_start_hdcp();
-		}
-#endif
-	} else
-		DEV_INFO("power_on: cable NOT detected\n");
-	adv7520_comm_power(0, 1);
-	pm_qos_update_request(&pm_qos_req, msm_cpuidle_get_deep_idle_latency());
-
-	return 0;
-}
-
-static int adv7520_power_off(struct platform_device *pdev)
-{
-	DEV_INFO("power_off\n");
-	adv7520_comm_power(1, 1);
-	adv7520_chip_off();
-	pm_qos_update_request(&pm_qos_req, PM_QOS_DEFAULT_VALUE);
-	adv7520_comm_power(0, 1);
-	clk_disable_unprepare(tv_enc_clk);
-	return 0;
-}
-
-
-/* AV7520 chip specific initialization */
-static void adv7520_chip_init(void)
-{
-	/* Initialize the variables used to read/write the ADV7520 chip. */
-	memset(&reg, 0xff, sizeof(reg));
-
-	/* Get the values from the "Fixed Registers That Must Be Set". */
-	reg[0x98] = adv7520_read_reg(hclient, 0x98);
-	reg[0x9c] = adv7520_read_reg(hclient, 0x9c);
-	reg[0x9d] = adv7520_read_reg(hclient, 0x9d);
-	reg[0xa2] = adv7520_read_reg(hclient, 0xa2);
-	reg[0xa3] = adv7520_read_reg(hclient, 0xa3);
-	reg[0xde] = adv7520_read_reg(hclient, 0xde);
-
-	/* Get the "HDMI/DVI Selection" register. */
-	reg[0xaf] = adv7520_read_reg(hclient, 0xaf);
-
-	/* Read Packet Memory I2C Address */
-	reg[0x45] = adv7520_read_reg(hclient, 0x45);
-
-	/* Hard coded values provided by ADV7520 data sheet. */
-	reg[0x98] = 0x03;
-	reg[0x9c] = 0x38;
-	reg[0x9d] = 0x61;
-	reg[0xa2] = 0x94;
-	reg[0xa3] = 0x94;
-	reg[0xde] = 0x88;
-
-	/* Set the HDMI select bit. */
-	reg[0xaf] |= 0x16;
-
-	/* Set the audio related registers. */
-	reg[0x01] = 0x00;
-	reg[0x02] = 0x2d;
-	reg[0x03] = 0x80;
-	reg[0x0a] = 0x4d;
-	reg[0x0b] = 0x0e;
-	reg[0x0c] = 0x84;
-	reg[0x0d] = 0x10;
-	reg[0x12] = 0x00;
-	reg[0x14] = 0x00;
-	reg[0x15] = 0x20;
-	reg[0x44] = 0x79;
-	reg[0x73] = 0x01;
-	reg[0x76] = 0x00;
-
-	/* Set 720p display related registers */
-	reg[0x16] = 0x00;
-
-	reg[0x18] = 0x46;
-	reg[0x55] = 0x00;
-	reg[0x3c] = 0x04;
-
-	/* Set Interrupt Mask register for HPD/HDCP */
-	reg[0x94] = 0xC0;
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-	if (has_hdcp_hw_support)
-		reg[0x95] = 0xC0;
-	else
-		reg[0x95] = 0x00;
-#else
-	reg[0x95] = 0x00;
-#endif
-	adv7520_write_reg(hclient, 0x94, reg[0x94]);
-	adv7520_write_reg(hclient, 0x95, reg[0x95]);
-
-	/* Set Packet Memory I2C Address */
-	reg[0x45] = 0x74;
-
-	/* Set the values from the "Fixed Registers That Must Be Set". */
-	adv7520_write_reg(hclient, 0x98, reg[0x98]);
-	adv7520_write_reg(hclient, 0x9c, reg[0x9c]);
-	adv7520_write_reg(hclient, 0x9d, reg[0x9d]);
-	adv7520_write_reg(hclient, 0xa2, reg[0xa2]);
-	adv7520_write_reg(hclient, 0xa3, reg[0xa3]);
-	adv7520_write_reg(hclient, 0xde, reg[0xde]);
-
-	/* Set the "HDMI/DVI Selection" register. */
-	adv7520_write_reg(hclient, 0xaf, reg[0xaf]);
-
-	/* Set EDID Monitor address */
-	reg[0x43] = 0x7E;
-	adv7520_write_reg(hclient, 0x43, reg[0x43]);
-
-	/* Enable the i2s audio input. */
-	adv7520_write_reg(hclient, 0x01, reg[0x01]);
-	adv7520_write_reg(hclient, 0x02, reg[0x02]);
-	adv7520_write_reg(hclient, 0x03, reg[0x03]);
-	adv7520_write_reg(hclient, 0x0a, reg[0x0a]);
-	adv7520_write_reg(hclient, 0x0b, reg[0x0b]);
-	adv7520_write_reg(hclient, 0x0c, reg[0x0c]);
-	adv7520_write_reg(hclient, 0x0d, reg[0x0d]);
-	adv7520_write_reg(hclient, 0x12, reg[0x12]);
-	adv7520_write_reg(hclient, 0x14, reg[0x14]);
-	adv7520_write_reg(hclient, 0x15, reg[0x15]);
-	adv7520_write_reg(hclient, 0x44, reg[0x44]);
-	adv7520_write_reg(hclient, 0x73, reg[0x73]);
-	adv7520_write_reg(hclient, 0x76, reg[0x76]);
-
-	/* Enable 720p display */
-	adv7520_write_reg(hclient, 0x16, reg[0x16]);
-	adv7520_write_reg(hclient, 0x18, reg[0x18]);
-	adv7520_write_reg(hclient, 0x55, reg[0x55]);
-	adv7520_write_reg(hclient, 0x3c, reg[0x3c]);
-
-	/* Set Packet Memory address to avoid conflict
-	with Bosch Accelerometer */
-	adv7520_write_reg(hclient, 0x45, reg[0x45]);
-
-	/* Ensure chip is in low-power state */
-	adv7520_write_reg(hclient, 0x41, 0x50);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-static void adv7520_start_hdcp(void)
-{
-	mutex_lock(&hdcp_state_mutex);
-	if (hdcp_activating) {
-		DEV_WARN("adv7520_timer: HDCP already"
-			" activating, skipping\n");
-		mutex_unlock(&hdcp_state_mutex);
-		return;
-	}
-	hdcp_activating = TRUE;
-	mutex_unlock(&hdcp_state_mutex);
-
-	del_timer(&hpd_duty_timer);
-
-	adv7520_comm_power(1, 1);
-
-	if (!enable_5v_on) {
-		dd->pd->enable_5v(1);
-		enable_5v_on = TRUE;
-		adv7520_chip_on();
-	}
-
-	/* request for HDCP */
-	reg[0xaf] = adv7520_read_reg(hclient, 0xaf);
-	reg[0xaf] |= 0x90;
-	adv7520_write_reg(hclient, 0xaf, reg[0xaf]);
-	reg[0xaf] = adv7520_read_reg(hclient, 0xaf);
-
-	reg[0xba] = adv7520_read_reg(hclient, 0xba);
-	reg[0xba] |= 0x10;
-	adv7520_write_reg(hclient, 0xba, reg[0xba]);
-	reg[0xba] = adv7520_read_reg(hclient, 0xba);
-	adv7520_comm_power(0, 1);
-
-	DEV_INFO("HDCP: reg[0xaf]=0x%02x, reg[0xba]=0x%02x, waiting for BKSV\n",
-				reg[0xaf], reg[0xba]);
-
-	/* will check for HDCP Error or BKSV ready */
-	mod_timer(&hpd_duty_timer, jiffies + HZ/2);
-}
-#endif
-
-static void adv7520_hpd_timer_w(struct work_struct *work)
-{
-	if (!external_common_state->hpd_feature_on) {
-		DEV_INFO("adv7520_timer: skipping, feature off\n");
-		return;
-	}
-
-	if ((monitor_sense & 0x4) && !external_common_state->hpd_state) {
-		int timeout;
-		DEV_DBG("adv7520_timer: Cable Detected\n");
-		adv7520_comm_power(1, 1);
-		adv7520_chip_on();
-
-		if (hpd_cable_chg_detected) {
-			hpd_cable_chg_detected = FALSE;
-			/* Ensure 5V to read EDID */
-			if (!enable_5v_on) {
-				dd->pd->enable_5v(1);
-				enable_5v_on = TRUE;
-			}
-			msleep(500);
-			timeout = (adv7520_read_reg(hclient, 0x96) & (1 << 2));
-			if (timeout) {
-				DEV_DBG("adv7520_timer: EDID-Ready..\n");
-				adv7520_read_edid();
-			} else
-				DEV_DBG("adv7520_timer: EDID TIMEOUT (C9=%02x)"
-					"\n", adv7520_read_reg(hclient, 0xC9));
-		}
-#ifdef TESTING_FORCE_480p
-		external_common_state->disp_mode_list.num_of_elements = 1;
-		external_common_state->disp_mode_list.disp_mode_list[0] =
-			HDMI_VFRMT_720x480p60_16_9;
-#endif
-		adv7520_comm_power(0, 1);
-#ifndef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-		/* HDMI_5V_EN not needed anymore */
-		if (enable_5v_on) {
-			DEV_DBG("adv7520_timer: EDID done, no HDCP, 5V not "
-				"needed anymore\n");
-			dd->pd->enable_5v(0);
-			enable_5v_on = FALSE;
-		}
-#endif
-		change_hdmi_state(1);
-	} else if (external_common_state->hpd_state) {
-		adv7520_comm_power(1, 1);
-		adv7520_chip_off();
-		adv7520_comm_power(0, 1);
-		DEV_DBG("adv7520_timer: Cable Removed\n");
-		change_hdmi_state(0);
-	}
-}
-
-static void adv7520_hpd_timer_f(unsigned long data)
-{
-	schedule_work(&hpd_timer_work);
-}
-
-static void adv7520_isr_w(struct work_struct *work)
-{
-	static int state_count;
-	static u8 last_reg0x96;
-	u8 reg0xc8;
-	u8 reg0x96;
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-	static u8 last_reg0x97;
-	u8 reg0x97 = 0;
-#endif
-	if (!external_common_state->hpd_feature_on) {
-		DEV_DBG("adv7520_irq: skipping, hpd off\n");
-		return;
-	}
-
-	adv7520_comm_power(1, 1);
-	reg0x96 = adv7520_read_reg(hclient, 0x96);
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-	if (has_hdcp_hw_support) {
-		reg0x97 = adv7520_read_reg(hclient, 0x97);
-		/* Clearing the Interrupts */
-		adv7520_write_reg(hclient, 0x97, reg0x97);
-	}
-#endif
-	/* Clearing the Interrupts */
-	adv7520_write_reg(hclient, 0x96, reg0x96);
-
-	if ((reg0x96 == 0xC0) || (reg0x96 & 0x40)) {
-#ifdef DEBUG
-		unsigned int hpd_state = adv7520_read_reg(hclient, 0x42);
-#endif
-		monitor_sense = adv7520_read_reg(hclient, 0xC6);
-		DEV_DBG("adv7520_irq: reg[0x42]=%02x && reg[0xC6]=%02x\n",
-			hpd_state, monitor_sense);
-
-		if (!enable_5v_on) {
-			dd->pd->enable_5v(1);
-			enable_5v_on = TRUE;
-		}
-		if (!hpd_power_on) {
-			dd->pd->core_power(1, 1);
-			hpd_power_on = TRUE;
-		}
-
-		/* Timer for catching interrupt debouning */
-		DEV_DBG("adv7520_irq: Timer in .5sec\n");
-		hpd_cable_chg_detected = TRUE;
-		mod_timer(&hpd_timer, jiffies + HZ/2);
-	}
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-	if (has_hdcp_hw_support) {
-		if (hdcp_activating) {
-			/* HDCP controller error Interrupt */
-			if (reg0x97 & 0x80) {
-				DEV_ERR("adv7520_irq: HDCP_ERROR\n");
-				state_count = 0;
-				adv7520_close_hdcp_link();
-			/* BKSV Ready interrupts */
-			} else if (reg0x97 & 0x40) {
-				DEV_INFO("adv7520_irq: BKSV keys ready, Begin"
-					" HDCP encryption\n");
-				state_count = 0;
-				schedule_work(&hdcp_handle_work);
-			} else if (++state_count > 2 && (monitor_sense & 0x4)) {
-				DEV_INFO("adv7520_irq: Still waiting for BKSV,"
-				"restart HDCP\n");
-				hdcp_activating = FALSE;
-				state_count = 0;
-				adv7520_chip_off();
-				adv7520_start_hdcp();
-			}
-			reg0xc8 = adv7520_read_reg(hclient, 0xc8);
-			DEV_INFO("adv7520_irq: DDC controller reg[0xC8]=0x%02x,"
-				"state_count=%d, monitor_sense=%x\n",
-				reg0xc8, state_count, monitor_sense);
-		} else if (!external_common_state->hdcp_active
-			&& (monitor_sense & 0x4)) {
-			DEV_INFO("adv7520_irq: start HDCP with"
-				" monitor sense\n");
-			state_count = 0;
-			adv7520_start_hdcp();
-		} else
-			state_count = 0;
-		if (last_reg0x97 != reg0x97 || last_reg0x96 != reg0x96)
-			DEV_DBG("adv7520_irq: reg[0x96]=%02x "
-				"reg[0x97]=%02x: HDCP: %d\n", reg0x96, reg0x97,
-				external_common_state->hdcp_active);
-		last_reg0x97 = reg0x97;
-	} else {
-		if (last_reg0x96 != reg0x96)
-			DEV_DBG("adv7520_irq: reg[0x96]=%02x\n", reg0x96);
-	}
-#else
-	if (last_reg0x96 != reg0x96)
-		DEV_DBG("adv7520_irq: reg[0x96]=%02x\n", reg0x96);
-#endif
-	last_reg0x96 = reg0x96;
-	adv7520_comm_power(0, 1);
-}
-
-static void adv7520_hpd_duty_work(struct work_struct *work)
-{
-	if (!external_common_state->hpd_feature_on) {
-		DEV_WARN("%s: hpd feature is off, skipping\n", __func__);
-		return;
-	}
-
-	dd->pd->core_power(1, 0);
-	msleep(10);
-	adv7520_isr_w(NULL);
-	dd->pd->core_power(0, 0);
-}
-
-static void adv7520_hpd_duty_timer_f(unsigned long data)
-{
-	if (!external_common_state->hpd_feature_on) {
-		DEV_WARN("%s: hpd feature is off, skipping\n", __func__);
-		return;
-	}
-
-	mod_timer(&hpd_duty_timer, jiffies + HPD_DUTY_CYCLE*HZ);
-	schedule_work(&hpd_duty_work);
-}
-
-static const struct i2c_device_id adv7520_id[] = {
-	{ ADV7520_DRV_NAME , 0},
-	{}
-};
-
-static struct msm_fb_panel_data hdmi_panel_data = {
-	.on  = adv7520_power_on,
-	.off = adv7520_power_off,
-};
-
-static struct platform_device hdmi_device = {
-	.name = ADV7520_DRV_NAME ,
-	.id   = 2,
-	.dev  = {
-		.platform_data = &hdmi_panel_data,
-		}
-};
-
-static void adv7520_ensure_init(void)
-{
-	static boolean init_done;
-	if (!init_done) {
-		int rc = dd->pd->init_irq();
-		if (rc) {
-			DEV_ERR("adv7520_init: init_irq: %d\n", rc);
-			return;
-		}
-
-		init_done = TRUE;
-	}
-	DEV_INFO("adv7520_init: chip init\n");
-	adv7520_comm_power(1, 1);
-	adv7520_chip_init();
-	adv7520_comm_power(0, 1);
-}
-
-static int adv7520_hpd_feature(int on)
-{
-	int rc = 0;
-
-	if (!on) {
-		if (enable_5v_on) {
-			dd->pd->enable_5v(0);
-			enable_5v_on = FALSE;
-		}
-		if (hpd_power_on) {
-			dd->pd->core_power(0, 1);
-			hpd_power_on = FALSE;
-		}
-
-		DEV_DBG("adv7520_hpd: %d: stop duty timer\n", on);
-		del_timer(&hpd_timer);
-		del_timer(&hpd_duty_timer);
-		external_common_state->hpd_state = 0;
-	}
-
-	if (on) {
-		dd->pd->core_power(1, 0);
-		adv7520_ensure_init();
-
-		adv7520_comm_power(1, 1);
-		monitor_sense = adv7520_read_reg(hclient, 0xC6);
-		DEV_DBG("adv7520_irq: reg[0xC6]=%02x\n", monitor_sense);
-		adv7520_comm_power(0, 1);
-		dd->pd->core_power(0, 0);
-
-		if (monitor_sense & 0x4) {
-			if (!enable_5v_on) {
-				dd->pd->enable_5v(1);
-				enable_5v_on = TRUE;
-			}
-			if (!hpd_power_on) {
-				dd->pd->core_power(1, 1);
-				hpd_power_on = TRUE;
-			}
-
-			hpd_cable_chg_detected = TRUE;
-			mod_timer(&hpd_timer, jiffies + HZ/2);
-		}
-
-		DEV_DBG("adv7520_hpd: %d start duty timer\n", on);
-		mod_timer(&hpd_duty_timer, jiffies + HZ/100);
-	}
-
-	DEV_INFO("adv7520_hpd: %d\n", on);
-	return rc;
-}
-
-static int __devinit
-	adv7520_probe(struct i2c_client *client, const struct i2c_device_id *id)
-{
-	int rc;
-	struct platform_device *fb_dev;
-
-	dd = kzalloc(sizeof *dd, GFP_KERNEL);
-	if (!dd) {
-		rc = -ENOMEM;
-		goto probe_exit;
-	}
-
-	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
-		return -ENODEV;
-
-	external_common_state->dev = &client->dev;
-
-	/* Init real i2c_client */
-	hclient = client;
-
-	i2c_set_clientdata(client, dd);
-	dd->pd = client->dev.platform_data;
-	if (!dd->pd) {
-		rc = -ENODEV;
-		goto probe_free;
-	}
-
-	INIT_WORK(&dd->isr_work, adv7520_isr_w);
-	INIT_WORK(&hpd_timer_work, adv7520_hpd_timer_w);
-#ifdef CONFIG_FB_MSM_HDMI_ADV7520_PANEL_HDCP_SUPPORT
-	if (dd->pd->check_hdcp_hw_support)
-		has_hdcp_hw_support = dd->pd->check_hdcp_hw_support();
-
-	if (has_hdcp_hw_support)
-		INIT_WORK(&hdcp_handle_work, adv7520_hdcp_enable);
-	else
-		DEV_INFO("%s: no hdcp hw support.\n", __func__);
-#endif
-
-	init_timer(&hpd_timer);
-	hpd_timer.function = adv7520_hpd_timer_f;
-	hpd_timer.data = (unsigned long)NULL;
-	hpd_timer.expires = 0xffffffff;
-	add_timer(&hpd_timer);
-
-	external_common_state->hpd_feature = adv7520_hpd_feature;
-	DEV_INFO("adv7520_probe: HPD detection on request\n");
-	init_timer(&hpd_duty_timer);
-	hpd_duty_timer.function = adv7520_hpd_duty_timer_f;
-	hpd_duty_timer.data = (unsigned long)NULL;
-	hpd_duty_timer.expires = 0xffffffff;
-	add_timer(&hpd_duty_timer);
-	INIT_WORK(&hpd_duty_work, adv7520_hpd_duty_work);
-	DEV_INFO("adv7520_probe: HPD detection ON (duty)\n");
-
-	fb_dev = msm_fb_add_device(&hdmi_device);
-
-	if (fb_dev) {
-		rc = external_common_state_create(fb_dev);
-		if (rc)
-			goto probe_free;
-	} else
-		DEV_ERR("adv7520_probe: failed to add fb device\n");
-
-	if (hdmi_prim_display)
-		external_common_state->sdev.name = "hdmi_as_primary";
-	else
-		external_common_state->sdev.name = "hdmi";
-
-	if (switch_dev_register(&external_common_state->sdev) < 0)
-		DEV_ERR("Hdmi switch registration failed\n");
-
-	return 0;
-
-probe_free:
-	kfree(dd);
-	dd = NULL;
-probe_exit:
-	return rc;
-
-}
-
-static int __devexit adv7520_remove(struct i2c_client *client)
-{
-	if (!client->adapter) {
-		DEV_ERR("%s: No HDMI Device\n", __func__);
-		return -ENODEV;
-	}
-	switch_dev_unregister(&external_common_state->sdev);
-	pm_qos_remove_request(&pm_qos_req);
-	kfree(dd);
-	dd = NULL;
-	return 0;
-}
-
-#ifdef CONFIG_SUSPEND
-static int adv7520_i2c_suspend(struct device *dev)
-{
-	DEV_INFO("%s\n", __func__);
-
-	++suspend_count;
-
-	if (external_common_state->hpd_feature_on) {
-		DEV_DBG("%s: stop duty timer\n", __func__);
-		del_timer(&hpd_duty_timer);
-		del_timer(&hpd_timer);
-	}
-
-	/* Turn off LDO8 and go into low-power state */
-	if (chip_power_on) {
-		DEV_DBG("%s: turn off power\n", __func__);
-		adv7520_comm_power(1, 1);
-		adv7520_write_reg(hclient, 0x41, 0x50);
-		adv7520_comm_power(0, 1);
-		dd->pd->core_power(0, 1);
-	}
-
-	return 0;
-}
-
-static int adv7520_i2c_resume(struct device *dev)
-{
-	DEV_INFO("%s\n", __func__);
-
-	/* Turn on LDO8 and go into normal-power state */
-	if (chip_power_on) {
-		DEV_DBG("%s: turn on power\n", __func__);
-		dd->pd->core_power(1, 1);
-		adv7520_comm_power(1, 1);
-		adv7520_write_reg(hclient, 0x41, 0x10);
-		adv7520_comm_power(0, 1);
-	}
-
-	if (external_common_state->hpd_feature_on) {
-		DEV_DBG("%s: start duty timer\n", __func__);
-		mod_timer(&hpd_duty_timer, jiffies + HPD_DUTY_CYCLE*HZ);
-	}
-
-	return 0;
-}
-#else
-#define adv7520_i2c_suspend	NULL
-#define adv7520_i2c_resume	NULL
-#endif
-
-static const struct dev_pm_ops adv7520_device_pm_ops = {
-	.suspend = adv7520_i2c_suspend,
-	.resume = adv7520_i2c_resume,
-};
-
-static struct i2c_driver hdmi_i2c_driver = {
-	.driver		= {
-		.name   = ADV7520_DRV_NAME,
-		.owner  = THIS_MODULE,
-		.pm     = &adv7520_device_pm_ops,
-	},
-	.probe		= adv7520_probe,
-	.id_table	= adv7520_id,
-	.remove		= __devexit_p(adv7520_remove),
-};
-
-static int __init adv7520_init(void)
-{
-	int rc;
-
-	pr_info("%s\n", __func__);
-	external_common_state = &hdmi_common;
-	external_common_state->video_resolution = HDMI_VFRMT_1280x720p60_16_9;
-
-	tv_enc_clk = clk_get(NULL, "tv_enc_clk");
-	if (IS_ERR(tv_enc_clk)) {
-		printk(KERN_ERR "error: can't get tv_enc_clk!\n");
-		return IS_ERR(tv_enc_clk);
-	}
-
-	HDMI_SETUP_LUT(640x480p60_4_3);		/* 25.20MHz */
-	HDMI_SETUP_LUT(720x480p60_16_9);	/* 27.03MHz */
-	HDMI_SETUP_LUT(1280x720p60_16_9);	/* 74.25MHz */
-
-	HDMI_SETUP_LUT(720x576p50_16_9);	/* 27.00MHz */
-	HDMI_SETUP_LUT(1280x720p50_16_9);	/* 74.25MHz */
-
-	hdmi_common_init_panel_info(&hdmi_panel_data.panel_info);
-
-	rc = i2c_add_driver(&hdmi_i2c_driver);
-	if (rc) {
-		pr_err("hdmi_init FAILED: i2c_add_driver rc=%d\n", rc);
-		goto init_exit;
-	}
-
-	if (machine_is_msm7x30_surf() || machine_is_msm8x55_surf()) {
-		short *hdtv_mux = (short *)ioremap(0x8e000170 , 0x100);
-		*hdtv_mux++ = 0x020b;
-		*hdtv_mux = 0x8000;
-		iounmap(hdtv_mux);
-	}
-	pm_qos_add_request(&pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
-				PM_QOS_DEFAULT_VALUE);
-
-	return 0;
-
-init_exit:
-	if (tv_enc_clk)
-		clk_put(tv_enc_clk);
-	return rc;
-}
-
-static void __exit adv7520_exit(void)
-{
-	i2c_del_driver(&hdmi_i2c_driver);
-}
-
-module_init(adv7520_init);
-module_exit(adv7520_exit);
-MODULE_LICENSE("GPL v2");
-MODULE_VERSION("0.1");
-MODULE_AUTHOR("Qualcomm Innovation Center, Inc.");
-MODULE_DESCRIPTION("ADV7520 HDMI driver");
diff --git a/drivers/video/msm/ebi2_epson_s1d_qvga.c b/drivers/video/msm/ebi2_epson_s1d_qvga.c
deleted file mode 100644
index 8db3cf9..0000000
--- a/drivers/video/msm/ebi2_epson_s1d_qvga.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-#include <linux/memory.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include "linux/proc_fs.h"
-
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-
-#define CMD_NOP_C							0x00
-#define CMD_SOFT_RESET_C					0x99
-#define CMD_DISPLAY_ON_C					0xAF
-#define CMD_DISPLAY_OFF_C					0xAE
-#define CMD_SET_DISPLAY_C					0xCA
-#define CMD_SET_DISPLAY_TIMING_C			0xA1
-#define CMD_SET_DATA_C						0xBC
-#define CMD_SET_START_ADDRESS_C				0x15
-#define CMD_SET_END_ADDRESS_C				0x75
-#define CMD_RAM_WRITE_C						0x5C
-#define CMD_RAM_READ_C						0x5D
-#define CMD_SET_AREA_SCROLLING_C			0xAA
-#define CMD_SET_DISPLAY_START_LINE_C		0xAB
-#define CMD_PARTIAL_DISPLAY_IN_C			0xA8
-#define CMD_PARTIAL_DISPLAY_OUT_C			0xA9
-#define CMD_SET_DISPLAY_DATA_INTERFACE_C	0x31
-#define CMD_SET_DISPLAY_COLOR_MODE_C		0x8B
-#define CMD_SELECT_MTP_ROM_MODE_C			0x65
-#define CMD_MTP_ROM_MODE_IN_C				0x67
-#define CMD_MTP_ROM_MODE_OUT_C				0x68
-#define CMD_MTP_ROM_OPERATION_IN_C			0x69
-#define CMD_MTP_ROM_OPERATION_OUT_C			0x70
-#define CMD_GATE_LINE_SCAN_MODE_C			0x6F
-#define CMD_SET_AC_OPERATION_DRIVE_C		0x8C
-#define CMD_SET_ELECTRONIC_CONTROL_C		0x20
-#define CMD_SET_POSITIVE_CORRECTION_CHARS_C	0x22
-#define CMD_SET_NEGATIVE_CORRECTION_CHARS_C	0x25
-#define CMD_SET_POWER_CONTROL_C				0x21
-#define CMD_SET_PARTIAL_POWER_CONTROL_C		0x23
-#define CMD_SET_8_COLOR_CONTROL_C			0x24
-#define CMD_SLEEP_IN_C						0x95
-#define CMD_SLEEP_OUT_C						0x94
-#define CMD_VDD_OFF_C						0x97
-#define CMD_VDD_ON_C						0x96
-#define CMD_STOP_OSCILLATION_C				0x93
-#define CMD_START_OSCILLATION_C				0x92
-#define CMD_TEST_SOURCE_C					0xFD
-#define CMD_TEST_FUSE_C						0xFE
-#define CMD_TEST_C							0xFF
-#define CMD_STATUS_READ_C					0xE8
-#define CMD_REVISION_READ_C					0xE9
-
-#define PANEL_WIDTH			240
-#define PANEL_HEIGHT		320
-#define ACTIVE_WIN_WIDTH	PANEL_WIDTH
-#define ACTIVE_WIN_HEIGHT	PANEL_HEIGHT
-
-#define ACTIVE_WIN_H_START	0
-#define ACTIVE_WIN_V_START	0
-
-#define DISP_CMD_OUT(cmd) outpw(DISP_CMD_PORT, (cmd << 1));
-#define DISP_DATA_OUT(data) outpw(DISP_DATA_PORT, (data << 1));
-#define DISP_DATA_IN() inpw(DISP_DATA_PORT);
-
-static void *DISP_CMD_PORT;
-static void *DISP_DATA_PORT;
-static boolean disp_initialized;
-static boolean display_on;
-static struct msm_panel_common_pdata *ebi2_epson_pdata;
-
-static void epson_s1d_disp_init(struct platform_device *pdev);
-static int epson_s1d_disp_off(struct platform_device *pdev);
-static int epson_s1d_disp_on(struct platform_device *pdev);
-static void epson_s1d_disp_set_rect(int x, int y, int xres, int yres);
-
-static void epson_s1d_disp_set_rect(int x, int y, int xres, int yres)
-{
-	int right, bottom;
-
-	if (!disp_initialized)
-		return;
-
-	right = x + xres - 1;
-	bottom = y + yres - 1;
-
-	x += ACTIVE_WIN_H_START;
-	y += ACTIVE_WIN_V_START;
-	right += ACTIVE_WIN_H_START;
-	bottom += ACTIVE_WIN_V_START;
-
-	if ((PANEL_WIDTH  > x) &&
-		(PANEL_HEIGHT > y) &&
-		(PANEL_WIDTH > right) &&
-		(PANEL_HEIGHT > bottom)) {
-		DISP_CMD_OUT(CMD_SET_START_ADDRESS_C);
-		DISP_DATA_OUT((uint8)x);
-		DISP_DATA_OUT((uint8)(y>>8));
-		DISP_DATA_OUT((uint8)y);
-
-		DISP_CMD_OUT(CMD_SET_END_ADDRESS_C);
-		DISP_DATA_OUT((uint8)right);
-		DISP_DATA_OUT((uint8)(bottom>>8));
-		DISP_DATA_OUT((uint8)bottom);
-		DISP_CMD_OUT(CMD_RAM_WRITE_C);
-	}
-}
-
-static void epson_s1d_disp_init(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	if (disp_initialized)
-		return;
-
-	mfd = platform_get_drvdata(pdev);
-
-	DISP_CMD_PORT = mfd->cmd_port;
-	DISP_DATA_PORT = mfd->data_port;
-
-	disp_initialized = TRUE;
-}
-
-static int epson_s1d_disp_off(struct platform_device *pdev)
-{
-	if (!disp_initialized)
-		epson_s1d_disp_init(pdev);
-
-	if (display_on) {
-		DISP_CMD_OUT(CMD_SOFT_RESET_C);
-		DISP_CMD_OUT(CMD_VDD_OFF_C);
-		display_on = FALSE;
-	}
-
-	return 0;
-}
-
-static int epson_s1d_disp_on(struct platform_device *pdev)
-{
-	int i;
-	if (!disp_initialized)
-		epson_s1d_disp_init(pdev);
-
-	if (!display_on) {
-		/* Enable Vdd regulator */
-		DISP_CMD_OUT(CMD_VDD_ON_C);
-		msleep(20);
-
-		/* Soft Reset before configuring display */
-		DISP_CMD_OUT(CMD_SOFT_RESET_C);
-		msleep(20);
-
-		/* Set display attributes */
-
-		/* GATESCAN */
-		DISP_CMD_OUT(CMD_GATE_LINE_SCAN_MODE_C);
-		DISP_DATA_OUT(0x0);
-
-		/* DISSET */
-		DISP_CMD_OUT(CMD_SET_DISPLAY_C);
-		DISP_DATA_OUT(0x31);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT((uint8)((PANEL_HEIGHT - 1)>>8));
-		DISP_DATA_OUT((uint8)(PANEL_HEIGHT - 1));
-		DISP_DATA_OUT(0x03);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x08);
-
-		/* VOLSET */
-		DISP_CMD_OUT(
-				   CMD_SET_ELECTRONIC_CONTROL_C);
-		DISP_DATA_OUT(0x10);
-		DISP_DATA_OUT(0x80);
-		DISP_DATA_OUT(0x11);
-		DISP_DATA_OUT(0x1B);
-		DISP_DATA_OUT(0x02);
-		DISP_DATA_OUT(0x0D);
-		DISP_DATA_OUT(0x00);
-
-		/* PWRCTL */
-		DISP_CMD_OUT(CMD_SET_POWER_CONTROL_C);
-		DISP_DATA_OUT(0x01);
-		DISP_DATA_OUT(0x24);
-		DISP_DATA_OUT(0x0F);
-		DISP_DATA_OUT(0xFE);
-		DISP_DATA_OUT(0x33);
-		DISP_DATA_OUT(0x31);
-		DISP_DATA_OUT(0xFF);
-		DISP_DATA_OUT(0x03);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x77);
-		DISP_DATA_OUT(0x33);
-		DISP_DATA_OUT(0x11);
-		DISP_DATA_OUT(0x44);
-		DISP_DATA_OUT(0x00);
-
-		/* PPWRCTL */
-		DISP_CMD_OUT(CMD_SET_PARTIAL_POWER_CONTROL_C);
-		DISP_DATA_OUT(0x33);
-		DISP_DATA_OUT(0xFF);
-		DISP_DATA_OUT(0x03);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x44);
-		DISP_DATA_OUT(0x00);
-
-		/* SPLOUT */
-		DISP_CMD_OUT(CMD_SLEEP_OUT_C);
-		msleep(100);
-
-		/* DATSET */
-		DISP_CMD_OUT(CMD_SET_DATA_C);
-		DISP_DATA_OUT(0x00);
-
-		/* DISTMEMSET */
-		DISP_CMD_OUT(CMD_SET_DISPLAY_TIMING_C);
-		DISP_DATA_OUT(0x01);
-		DISP_DATA_OUT(0x2E);
-		DISP_DATA_OUT(0x0A);
-		DISP_DATA_OUT(0x2C);
-		DISP_DATA_OUT(0x23);
-		DISP_DATA_OUT(0x2F);
-		DISP_DATA_OUT(0x00);
-
-		/* GAMSETP */
-		DISP_CMD_OUT(CMD_SET_POSITIVE_CORRECTION_CHARS_C);
-		DISP_DATA_OUT(0x37);
-		DISP_DATA_OUT(0xFF);
-		DISP_DATA_OUT(0x7F);
-		DISP_DATA_OUT(0x15);
-		DISP_DATA_OUT(0x37);
-		DISP_DATA_OUT(0x05);
-
-		/* GAMSETN */
-		DISP_CMD_OUT(CMD_SET_NEGATIVE_CORRECTION_CHARS_C);
-		DISP_DATA_OUT(0x37);
-		DISP_DATA_OUT(0xFF);
-		DISP_DATA_OUT(0x7F);
-		DISP_DATA_OUT(0x15);
-		DISP_DATA_OUT(0x37);
-		DISP_DATA_OUT(0x05);
-
-		/* ACDRIVE */
-		DISP_CMD_OUT(CMD_SET_AC_OPERATION_DRIVE_C);
-		DISP_DATA_OUT(0x00);
-
-		/* TEST */
-		DISP_CMD_OUT(CMD_TEST_C);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x01);
-
-		/* COLMOD */
-		DISP_CMD_OUT(CMD_SET_DISPLAY_COLOR_MODE_C);
-		DISP_DATA_OUT(0x00);
-
-		/* STADDSET */
-		DISP_CMD_OUT(CMD_SET_START_ADDRESS_C);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x00);
-
-		/* EDADDSET */
-		DISP_CMD_OUT(CMD_SET_END_ADDRESS_C);
-		DISP_DATA_OUT(0xEF);
-		DISP_DATA_OUT(0x01);
-		DISP_DATA_OUT(0x3F);
-
-		/* Set Display Start Line */
-		DISP_CMD_OUT(CMD_SET_DISPLAY_START_LINE_C);
-		DISP_DATA_OUT(0x00);
-
-		/* Set Display Data Interface */
-		DISP_CMD_OUT(CMD_SET_DISPLAY_DATA_INTERFACE_C);
-		DISP_DATA_OUT(0x00);
-		DISP_DATA_OUT(0x04);
-
-		epson_s1d_disp_set_rect(0,
-						 0,
-						 ACTIVE_WIN_WIDTH,
-						 ACTIVE_WIN_HEIGHT);
-
-		for (i = 0; i < (ACTIVE_WIN_WIDTH * ACTIVE_WIN_HEIGHT); i++)
-			outpdw(DISP_DATA_PORT, 0);
-
-		/* DISON */
-		DISP_CMD_OUT(CMD_DISPLAY_ON_C);
-		msleep(60);
-
-		display_on = TRUE;
-	}
-
-	return 0;
-}
-
-static int epson_s1d_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		ebi2_epson_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = epson_s1d_probe,
-	.driver = {
-		.name   = "ebi2_epson_s1d_qvga",
-	},
-};
-
-static struct msm_fb_panel_data epson_s1d_panel_data = {
-	.on = epson_s1d_disp_on,
-	.off = epson_s1d_disp_off,
-	.set_rect = epson_s1d_disp_set_rect,
-};
-
-static struct platform_device this_device = {
-	.name   = "ebi2_epson_s1d_qvga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &epson_s1d_panel_data,
-	}
-};
-
-static int __init epson_s1d_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &epson_s1d_panel_data.panel_info;
-		pinfo->xres = PANEL_WIDTH;
-		pinfo->yres = PANEL_HEIGHT;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = EBI2_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->wait_cycle = 0x048423E8;
-		pinfo->bpp = 18;
-		pinfo->fb_num = 2;
-		pinfo->lcd.vsync_enable = FALSE;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-
-	return ret;
-}
-
-module_init(epson_s1d_init);
diff --git a/drivers/video/msm/ebi2_host.c b/drivers/video/msm/ebi2_host.c
deleted file mode 100644
index bebc36e..0000000
--- a/drivers/video/msm/ebi2_host.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/hrtimer.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/pm_runtime.h>
-#include <linux/regulator/consumer.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <mach/clk.h>
-#include <mach/hardware.h>
-#include "msm_fb.h"
-
-struct mdp_ccs mdp_ccs_rgb2yuv;
-struct mdp_ccs mdp_ccs_yuv2rgb;
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-static int ebi2_host_resource_initialized;
-static struct msm_panel_common_pdata *ebi2_host_pdata;
-
-static int ebi2_host_probe(struct platform_device *pdev);
-static int ebi2_host_remove(struct platform_device *pdev);
-
-static int ebi2_host_runtime_suspend(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: suspending...\n");
-	return 0;
-}
-
-static int ebi2_host_runtime_resume(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: resuming...\n");
-	return 0;
-}
-
-static const struct dev_pm_ops ebi2_host_dev_pm_ops = {
-	.runtime_suspend = ebi2_host_runtime_suspend,
-	.runtime_resume = ebi2_host_runtime_resume,
-};
-
-
-static struct platform_driver ebi2_host_driver = {
-	.probe = ebi2_host_probe,
-	.remove = ebi2_host_remove,
-	.shutdown = NULL,
-	.driver = {
-		/*
-		 * Simulate mdp hw
-		 */
-		.name = "mdp",
-		.pm = &ebi2_host_dev_pm_ops,
-	},
-};
-
-void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state,
-		   boolean isr)
-{
-	return;
-}
-int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req)
-{
-	return 0;
-}
-int mdp_start_histogram(struct fb_info *info)
-{
-	return 0;
-}
-int mdp_stop_histogram(struct fb_info *info)
-{
-	return 0;
-}
-void mdp_refresh_screen(unsigned long data)
-{
-	return;
-}
-
-static int ebi2_host_off(struct platform_device *pdev)
-{
-	int ret;
-	ret = panel_next_off(pdev);
-	return ret;
-}
-
-static int ebi2_host_on(struct platform_device *pdev)
-{
-	int ret;
-	ret = panel_next_on(pdev);
-	return ret;
-}
-
-
-static int ebi2_host_probe(struct platform_device *pdev)
-{
-	struct platform_device *msm_fb_dev = NULL;
-	struct msm_fb_data_type *mfd;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-
-	if ((pdev->id == 0) && (pdev->num_resources > 0)) {
-
-		ebi2_host_pdata = pdev->dev.platform_data;
-
-		ebi2_host_resource_initialized = 1;
-		return 0;
-	}
-
-	ebi2_host_resource_initialized = 1;
-	if (!ebi2_host_resource_initialized)
-		return -EPERM;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	msm_fb_dev = platform_device_alloc("msm_fb", pdev->id);
-	if (!msm_fb_dev)
-		return -ENOMEM;
-
-	/* link to the latest pdev */
-	mfd->pdev = msm_fb_dev;
-
-	if (ebi2_host_pdata) {
-		mfd->mdp_rev = ebi2_host_pdata->mdp_rev;
-		mfd->mem_hid = ebi2_host_pdata->mem_hid;
-	}
-
-	/* add panel data */
-	if (platform_device_add_data
-	    (msm_fb_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		pr_err("ebi2_host_probe: platform_device_add_data failed!\n");
-		rc = -ENOMEM;
-		goto ebi2_host_probe_err;
-	}
-	/* data chain */
-	pdata = msm_fb_dev->dev.platform_data;
-	pdata->on = ebi2_host_on;
-	pdata->off = ebi2_host_off;
-	pdata->next = pdev;
-
-	/* set driver data */
-	platform_set_drvdata(msm_fb_dev, mfd);
-
-	rc = platform_device_add(msm_fb_dev);
-	if (rc)
-		goto ebi2_host_probe_err;
-
-	pm_runtime_set_active(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
-
-	pdev_list[pdev_list_cnt++] = pdev;
-	return 0;
-
-ebi2_host_probe_err:
-	platform_device_put(msm_fb_dev);
-	return rc;
-}
-
-void mdp_set_dma_pan_info(struct fb_info *info, struct mdp_dirty_region *dirty,
-			  boolean sync)
-{
-	struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
-	struct fb_info *fbi = mfd->fbi;
-	struct msm_panel_info *panel_info = &mfd->panel_info;
-	MDPIBUF *iBuf;
-	int bpp = info->var.bits_per_pixel / 8;
-	int yres, remainder;
-
-	if (panel_info->mode2_yres != 0) {
-		yres = panel_info->mode2_yres;
-		remainder = (fbi->fix.line_length*yres)%PAGE_SIZE;
-	} else {
-		yres = panel_info->yres;
-		remainder = (fbi->fix.line_length*yres)%PAGE_SIZE;
-	}
-
-	if (!remainder)
-		remainder = PAGE_SIZE;
-
-	down(&mfd->sem);
-
-	iBuf = &mfd->ibuf;
-	/* use virtual address */
-	iBuf->buf = (uint8 *) fbi->screen_base;
-
-	if (fbi->var.yoffset < yres) {
-		iBuf->buf += fbi->var.xoffset * bpp;
-	} else if (fbi->var.yoffset >= yres && fbi->var.yoffset < 2 * yres) {
-		iBuf->buf += fbi->var.xoffset * bpp + yres *
-		fbi->fix.line_length + PAGE_SIZE - remainder;
-	} else {
-		iBuf->buf += fbi->var.xoffset * bpp + 2 * yres *
-		fbi->fix.line_length + 2 * (PAGE_SIZE - remainder);
-	}
-
-	iBuf->ibuf_width = info->var.xres_virtual;
-	iBuf->bpp = bpp;
-
-	iBuf->vsync_enable = sync;
-
-	if (dirty) {
-		/*
-		 * ToDo: dirty region check inside var.xoffset+xres
-		 * <-> var.yoffset+yres
-		 */
-		iBuf->dma_x = dirty->xoffset % info->var.xres;
-		iBuf->dma_y = dirty->yoffset % info->var.yres;
-		iBuf->dma_w = dirty->width;
-		iBuf->dma_h = dirty->height;
-	} else {
-		iBuf->dma_x = 0;
-		iBuf->dma_y = 0;
-		iBuf->dma_w = info->var.xres;
-		iBuf->dma_h = info->var.yres;
-	}
-	mfd->ibuf_flushed = FALSE;
-	up(&mfd->sem);
-}
-
-void mdp_dma_pan_update(struct fb_info *info)
-{
-	struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
-	MDPIBUF *iBuf;
-	int i, j;
-	uint32 data;
-	uint8 *src;
-	struct msm_fb_panel_data *pdata =
-	    (struct msm_fb_panel_data *)mfd->pdev->dev.platform_data;
-	struct fb_info *fbi = mfd->fbi;
-
-	iBuf = &mfd->ibuf;
-
-	invalidate_caches((unsigned long)fbi->screen_base,
-		(unsigned long)info->fix.smem_len,
-		(unsigned long)info->fix.smem_start);
-
-	pdata->set_rect(iBuf->dma_x, iBuf->dma_y, iBuf->dma_w,
-			iBuf->dma_h);
-	for (i = 0; i < iBuf->dma_h; i++) {
-		src = iBuf->buf + (fbi->fix.line_length * (iBuf->dma_y + i))
-			+ (iBuf->dma_x * iBuf->bpp);
-		for (j = 0; j < iBuf->dma_w; j++) {
-			data = (uint32)(*src++ >> 2) << 12;
-			data |= (uint32)(*src++ >> 2) << 6;
-			data |= (uint32)(*src++ >> 2);
-			data = ((data&0x1FF)<<16) | ((data&0x3FE00)>>9);
-			outpdw(mfd->data_port, data);
-		}
-	}
-}
-
-static int ebi2_host_remove(struct platform_device *pdev)
-{
-	pm_runtime_disable(&pdev->dev);
-
-	return 0;
-}
-
-static int ebi2_host_register_driver(void)
-{
-	return platform_driver_register(&ebi2_host_driver);
-}
-
-static int __init ebi2_host_driver_init(void)
-{
-	int ret;
-
-	ret = ebi2_host_register_driver();
-	if (ret) {
-		pr_err("ebi2_host_register_driver() failed!\n");
-		return ret;
-	}
-
-	return 0;
-}
-
-module_init(ebi2_host_driver_init);
diff --git a/drivers/video/msm/ebi2_l2f.c b/drivers/video/msm/ebi2_l2f.c
deleted file mode 100644
index 2e944be..0000000
--- a/drivers/video/msm/ebi2_l2f.c
+++ /dev/null
@@ -1,566 +0,0 @@
-/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-#include <linux/memory.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include "linux/proc_fs.h"
-
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-
-/* The following are for MSM5100 on Gator
-*/
-#ifdef FEATURE_PM1000
-#include "pm1000.h"
-#endif /* FEATURE_PM1000 */
-/* The following are for MSM6050 on Bambi
-*/
-#ifdef FEATURE_PMIC_LCDKBD_LED_DRIVER
-#include "pm.h"
-#endif /* FEATURE_PMIC_LCDKBD_LED_DRIVER */
-
-#ifdef DISP_DEVICE_18BPP
-#undef DISP_DEVICE_18BPP
-#define DISP_DEVICE_16BPP
-#endif
-
-#define QCIF_WIDTH        176
-#define QCIF_HEIGHT       220
-
-static void *DISP_CMD_PORT;
-static void *DISP_DATA_PORT;
-
-#define DISP_CMD_DISON    0xaf
-#define DISP_CMD_DISOFF   0xae
-#define DISP_CMD_DISNOR   0xa6
-#define DISP_CMD_DISINV   0xa7
-#define DISP_CMD_DISCTL   0xca
-#define DISP_CMD_GCP64    0xcb
-#define DISP_CMD_GCP16    0xcc
-#define DISP_CMD_GSSET    0xcd
-#define DISP_GS_2       0x02
-#define DISP_GS_16      0x01
-#define DISP_GS_64      0x00
-#define DISP_CMD_SLPIN    0x95
-#define DISP_CMD_SLPOUT   0x94
-#define DISP_CMD_SD_PSET  0x75
-#define DISP_CMD_MD_PSET  0x76
-#define DISP_CMD_SD_CSET  0x15
-#define DISP_CMD_MD_CSET  0x16
-#define DISP_CMD_DATCTL   0xbc
-#define DISP_DATCTL_666 0x08
-#define DISP_DATCTL_565 0x28
-#define DISP_DATCTL_444 0x38
-#define DISP_CMD_RAMWR    0x5c
-#define DISP_CMD_RAMRD    0x5d
-#define DISP_CMD_PTLIN    0xa8
-#define DISP_CMD_PTLOUT   0xa9
-#define DISP_CMD_ASCSET   0xaa
-#define DISP_CMD_SCSTART  0xab
-#define DISP_CMD_VOLCTL   0xc6
-#define DISP_VOLCTL_TONE 0x80
-#define DISP_CMD_NOp      0x25
-#define DISP_CMD_OSSEL    0xd0
-#define DISP_CMD_3500KSET 0xd1
-#define DISP_CMD_3500KEND 0xd2
-#define DISP_CMD_14MSET   0xd3
-#define DISP_CMD_14MEND   0xd4
-
-#define DISP_CMD_OUT(cmd) outpw(DISP_CMD_PORT, cmd);
-
-#define DISP_DATA_OUT(data) outpw(DISP_DATA_PORT, data);
-
-#define DISP_DATA_IN() inpw(DISP_DATA_PORT);
-
-/* Epson device column number starts at 2
-*/
-#define DISP_SET_RECT(ulhc_row, lrhc_row, ulhc_col, lrhc_col) \
-	  DISP_CMD_OUT(DISP_CMD_SD_PSET) \
-	  DISP_DATA_OUT((ulhc_row) & 0xFF) \
-	  DISP_DATA_OUT((ulhc_row) >> 8) \
-	  DISP_DATA_OUT((lrhc_row) & 0xFF) \
-	  DISP_DATA_OUT((lrhc_row) >> 8) \
-	  DISP_CMD_OUT(DISP_CMD_SD_CSET) \
-	  DISP_DATA_OUT(((ulhc_col)+2) & 0xFF) \
-	  DISP_DATA_OUT(((ulhc_col)+2) >> 8) \
-	  DISP_DATA_OUT(((lrhc_col)+2) & 0xFF) \
-	  DISP_DATA_OUT(((lrhc_col)+2) >> 8)
-
-#define DISP_MIN_CONTRAST      0
-#define DISP_MAX_CONTRAST      127
-#define DISP_DEFAULT_CONTRAST  80
-
-#define DISP_MIN_BACKLIGHT     0
-#define DISP_MAX_BACKLIGHT     15
-#define DISP_DEFAULT_BACKLIGHT 2
-
-#define WAIT_SEC(sec) mdelay((sec)/1000)
-
-static word disp_area_start_row;
-static word disp_area_end_row;
-static byte disp_contrast = DISP_DEFAULT_CONTRAST;
-static boolean disp_powered_up;
-static boolean disp_initialized = FALSE;
-/* For some reason the contrast set at init time is not good. Need to do
- * it again
- */
-static boolean display_on = FALSE;
-static void epsonQcif_disp_init(struct platform_device *pdev);
-static void epsonQcif_disp_set_contrast(word contrast);
-static void epsonQcif_disp_set_display_area(word start_row, word end_row);
-static int epsonQcif_disp_off(struct platform_device *pdev);
-static int epsonQcif_disp_on(struct platform_device *pdev);
-static void epsonQcif_disp_set_rect(int x, int y, int xres, int yres);
-
-volatile word databack;
-static void epsonQcif_disp_init(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	int i;
-
-	if (disp_initialized)
-		return;
-
-	mfd = platform_get_drvdata(pdev);
-
-	DISP_CMD_PORT = mfd->cmd_port;
-	DISP_DATA_PORT = mfd->data_port;
-
-	/* Sleep in */
-	DISP_CMD_OUT(DISP_CMD_SLPIN);
-
-	/* Display off */
-	DISP_CMD_OUT(DISP_CMD_DISOFF);
-
-	/* Display normal */
-	DISP_CMD_OUT(DISP_CMD_DISNOR);
-
-	/* Set data mode */
-	DISP_CMD_OUT(DISP_CMD_DATCTL);
-	DISP_DATA_OUT(DISP_DATCTL_565);
-
-	/* Set display timing */
-	DISP_CMD_OUT(DISP_CMD_DISCTL);
-	DISP_DATA_OUT(0x1c);	/* p1 */
-	DISP_DATA_OUT(0x02);	/* p1 */
-	DISP_DATA_OUT(0x82);	/* p2 */
-	DISP_DATA_OUT(0x00);	/* p3 */
-	DISP_DATA_OUT(0x00);	/* p4 */
-	DISP_DATA_OUT(0xe0);	/* p5 */
-	DISP_DATA_OUT(0x00);	/* p5 */
-	DISP_DATA_OUT(0xdc);	/* p6 */
-	DISP_DATA_OUT(0x00);	/* p6 */
-	DISP_DATA_OUT(0x02);	/* p7 */
-	DISP_DATA_OUT(0x00);	/* p8 */
-
-	/* Set 64 gray scale level */
-	DISP_CMD_OUT(DISP_CMD_GCP64);
-	DISP_DATA_OUT(0x08);	/* p01 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x2a);	/* p02 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x4e);	/* p03 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x6b);	/* p04 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x88);	/* p05 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0xa3);	/* p06 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0xba);	/* p07 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0xd1);	/* p08 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0xe5);	/* p09 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0xf3);	/* p10 */
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x03);	/* p11 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x13);	/* p12 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x22);	/* p13 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x2f);	/* p14 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x3b);	/* p15 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x46);	/* p16 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x51);	/* p17 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x5b);	/* p18 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x64);	/* p19 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x6c);	/* p20 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x74);	/* p21 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x7c);	/* p22 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x83);	/* p23 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x8a);	/* p24 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x91);	/* p25 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x98);	/* p26 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x9f);	/* p27 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xa6);	/* p28 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xac);	/* p29 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xb2);	/* p30 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xb7);	/* p31 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xbc);	/* p32 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xc1);	/* p33 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xc6);	/* p34 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xcb);	/* p35 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xd0);	/* p36 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xd4);	/* p37 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xd8);	/* p38 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xdc);	/* p39 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xe0);	/* p40 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xe4);	/* p41 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xe8);	/* p42 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xec);	/* p43 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xf0);	/* p44 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xf4);	/* p45 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xf8);	/* p46 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xfb);	/* p47 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xfe);	/* p48 */
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0x01);	/* p49 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x03);	/* p50 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x05);	/* p51 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x07);	/* p52 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x09);	/* p53 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x0b);	/* p54 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x0d);	/* p55 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x0f);	/* p56 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x11);	/* p57 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x13);	/* p58 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x15);	/* p59 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x17);	/* p60 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x19);	/* p61 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x1b);	/* p62 */
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x1c);	/* p63 */
-	DISP_DATA_OUT(0x02);
-
-	/* Set 16 gray scale level */
-	DISP_CMD_OUT(DISP_CMD_GCP16);
-	DISP_DATA_OUT(0x1a);	/* p01 */
-	DISP_DATA_OUT(0x32);	/* p02 */
-	DISP_DATA_OUT(0x42);	/* p03 */
-	DISP_DATA_OUT(0x4c);	/* p04 */
-	DISP_DATA_OUT(0x58);	/* p05 */
-	DISP_DATA_OUT(0x5f);	/* p06 */
-	DISP_DATA_OUT(0x66);	/* p07 */
-	DISP_DATA_OUT(0x6b);	/* p08 */
-	DISP_DATA_OUT(0x70);	/* p09 */
-	DISP_DATA_OUT(0x74);	/* p10 */
-	DISP_DATA_OUT(0x78);	/* p11 */
-	DISP_DATA_OUT(0x7b);	/* p12 */
-	DISP_DATA_OUT(0x7e);	/* p13 */
-	DISP_DATA_OUT(0x80);	/* p14 */
-	DISP_DATA_OUT(0x82);	/* p15 */
-
-	/* Set DSP column */
-	DISP_CMD_OUT(DISP_CMD_MD_CSET);
-	DISP_DATA_OUT(0xff);
-	DISP_DATA_OUT(0x03);
-	DISP_DATA_OUT(0xff);
-	DISP_DATA_OUT(0x03);
-
-	/* Set DSP page */
-	DISP_CMD_OUT(DISP_CMD_MD_PSET);
-	DISP_DATA_OUT(0xff);
-	DISP_DATA_OUT(0x01);
-	DISP_DATA_OUT(0xff);
-	DISP_DATA_OUT(0x01);
-
-	/* Set ARM column */
-	DISP_CMD_OUT(DISP_CMD_SD_CSET);
-	DISP_DATA_OUT(0x02);
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT((QCIF_WIDTH + 1) & 0xFF);
-	DISP_DATA_OUT((QCIF_WIDTH + 1) >> 8);
-
-	/* Set ARM page */
-	DISP_CMD_OUT(DISP_CMD_SD_PSET);
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT(0x00);
-	DISP_DATA_OUT((QCIF_HEIGHT - 1) & 0xFF);
-	DISP_DATA_OUT((QCIF_HEIGHT - 1) >> 8);
-
-	/* Set 64 gray scales */
-	DISP_CMD_OUT(DISP_CMD_GSSET);
-	DISP_DATA_OUT(DISP_GS_64);
-
-	DISP_CMD_OUT(DISP_CMD_OSSEL);
-	DISP_DATA_OUT(0);
-
-	/* Sleep out */
-	DISP_CMD_OUT(DISP_CMD_SLPOUT);
-
-	WAIT_SEC(40000);
-
-	/* Initialize power IC */
-	DISP_CMD_OUT(DISP_CMD_VOLCTL);
-	DISP_DATA_OUT(DISP_VOLCTL_TONE);
-
-	WAIT_SEC(40000);
-
-	/* Set electronic volume, d'xx */
-	DISP_CMD_OUT(DISP_CMD_VOLCTL);
-	DISP_DATA_OUT(DISP_DEFAULT_CONTRAST);	/* value from 0 to 127 */
-
-	/* Initialize display data */
-	DISP_SET_RECT(0, (QCIF_HEIGHT - 1), 0, (QCIF_WIDTH - 1));
-	DISP_CMD_OUT(DISP_CMD_RAMWR);
-	for (i = 0; i < QCIF_HEIGHT * QCIF_WIDTH; i++)
-		DISP_DATA_OUT(0xffff);
-
-	DISP_CMD_OUT(DISP_CMD_RAMRD);
-	databack = DISP_DATA_IN();
-	databack = DISP_DATA_IN();
-	databack = DISP_DATA_IN();
-	databack = DISP_DATA_IN();
-
-	WAIT_SEC(80000);
-
-	DISP_CMD_OUT(DISP_CMD_DISON);
-
-	disp_area_start_row = 0;
-	disp_area_end_row = QCIF_HEIGHT - 1;
-	disp_powered_up = TRUE;
-	disp_initialized = TRUE;
-	epsonQcif_disp_set_display_area(0, QCIF_HEIGHT - 1);
-	display_on = TRUE;
-}
-
-static void epsonQcif_disp_set_rect(int x, int y, int xres, int yres)
-{
-	if (!disp_initialized)
-		return;
-
-	DISP_SET_RECT(y, y + yres - 1, x, x + xres - 1);
-	DISP_CMD_OUT(DISP_CMD_RAMWR);
-}
-
-static void epsonQcif_disp_set_display_area(word start_row, word end_row)
-{
-	if (!disp_initialized)
-		return;
-
-	if ((start_row == disp_area_start_row)
-	    && (end_row == disp_area_end_row))
-		return;
-	disp_area_start_row = start_row;
-	disp_area_end_row = end_row;
-
-	/* Range checking
-	 */
-	if (end_row >= QCIF_HEIGHT)
-		end_row = QCIF_HEIGHT - 1;
-	if (start_row > end_row)
-		start_row = end_row;
-
-	/* When display is not the full screen, gray scale is set to
-	 ** 2; otherwise it is set to 64.
-	 */
-	if ((start_row == 0) && (end_row == (QCIF_HEIGHT - 1))) {
-		/* The whole screen */
-		DISP_CMD_OUT(DISP_CMD_PTLOUT);
-		WAIT_SEC(10000);
-		DISP_CMD_OUT(DISP_CMD_DISOFF);
-		WAIT_SEC(100000);
-		DISP_CMD_OUT(DISP_CMD_GSSET);
-		DISP_DATA_OUT(DISP_GS_64);
-		WAIT_SEC(100000);
-		DISP_CMD_OUT(DISP_CMD_DISON);
-	} else {
-		/* partial screen */
-		DISP_CMD_OUT(DISP_CMD_PTLIN);
-		DISP_DATA_OUT(start_row);
-		DISP_DATA_OUT(start_row >> 8);
-		DISP_DATA_OUT(end_row);
-		DISP_DATA_OUT(end_row >> 8);
-		DISP_CMD_OUT(DISP_CMD_GSSET);
-		DISP_DATA_OUT(DISP_GS_2);
-	}
-}
-
-static int epsonQcif_disp_off(struct platform_device *pdev)
-{
-	if (!disp_initialized)
-		epsonQcif_disp_init(pdev);
-
-	if (display_on) {
-		DISP_CMD_OUT(DISP_CMD_DISOFF);
-		DISP_CMD_OUT(DISP_CMD_SLPIN);
-		display_on = FALSE;
-	}
-
-	return 0;
-}
-
-static int epsonQcif_disp_on(struct platform_device *pdev)
-{
-	if (!disp_initialized)
-		epsonQcif_disp_init(pdev);
-
-	if (!display_on) {
-		DISP_CMD_OUT(DISP_CMD_SLPOUT);
-		WAIT_SEC(40000);
-		DISP_CMD_OUT(DISP_CMD_DISON);
-		epsonQcif_disp_set_contrast(disp_contrast);
-		display_on = TRUE;
-	}
-
-	return 0;
-}
-
-static void epsonQcif_disp_set_contrast(word contrast)
-{
-	if (!disp_initialized)
-		return;
-
-	/* Initialize power IC, d'24 */
-	DISP_CMD_OUT(DISP_CMD_VOLCTL);
-	DISP_DATA_OUT(DISP_VOLCTL_TONE);
-
-	WAIT_SEC(40000);
-
-	/* Set electronic volume, d'xx */
-	DISP_CMD_OUT(DISP_CMD_VOLCTL);
-	if (contrast > 127)
-		contrast = 127;
-	DISP_DATA_OUT(contrast);	/* value from 0 to 127 */
-	disp_contrast = (byte) contrast;
-}				/* End disp_set_contrast */
-
-static void epsonQcif_disp_clear_screen_area(
-	word start_row, word end_row, word start_column, word end_column) {
-	int32 i;
-
-	/* Clear the display screen */
-	DISP_SET_RECT(start_row, end_row, start_column, end_column);
-	DISP_CMD_OUT(DISP_CMD_RAMWR);
-	i = (end_row - start_row + 1) * (end_column - start_column + 1);
-	for (; i > 0; i--)
-		DISP_DATA_OUT(0xffff);
-}
-
-static int __init epsonQcif_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = epsonQcif_probe,
-	.driver = {
-		.name   = "ebi2_epson_qcif",
-	},
-};
-
-static struct msm_fb_panel_data epsonQcif_panel_data = {
-	.on = epsonQcif_disp_on,
-	.off = epsonQcif_disp_off,
-	.set_rect = epsonQcif_disp_set_rect,
-};
-
-static struct platform_device this_device = {
-	.name   = "ebi2_epson_qcif",
-	.id	= 0,
-	.dev	= {
-		.platform_data = &epsonQcif_panel_data,
-	}
-};
-
-static int __init epsonQcif_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &epsonQcif_panel_data.panel_info;
-		pinfo->xres = QCIF_WIDTH;
-		pinfo->yres = QCIF_HEIGHT;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = EBI2_PANEL;
-		pinfo->pdest = DISPLAY_2;
-		pinfo->wait_cycle = 0x808000;
-		pinfo->bpp = 16;
-		pinfo->fb_num = 2;
-		pinfo->lcd.vsync_enable = FALSE;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-
-	return ret;
-}
-
-module_init(epsonQcif_init);
diff --git a/drivers/video/msm/ebi2_lcd.c b/drivers/video/msm/ebi2_lcd.c
deleted file mode 100644
index a19763c..0000000
--- a/drivers/video/msm/ebi2_lcd.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/uaccess.h>
-#include <linux/workqueue.h>
-#include <linux/string.h>
-#include <linux/version.h>
-#include <linux/proc_fs.h>
-#include <linux/vmalloc.h>
-#include <linux/debugfs.h>
-
-#include "msm_fb.h"
-
-static int ebi2_lcd_probe(struct platform_device *pdev);
-static int ebi2_lcd_remove(struct platform_device *pdev);
-
-static int ebi2_lcd_runtime_suspend(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: suspending...\n");
-	return 0;
-}
-
-static int ebi2_lcd_runtime_resume(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: resuming...\n");
-	return 0;
-}
-
-static struct dev_pm_ops ebi2_lcd_dev_pm_ops = {
-	.runtime_suspend = ebi2_lcd_runtime_suspend,
-	.runtime_resume = ebi2_lcd_runtime_resume,
-};
-
-static struct platform_driver ebi2_lcd_driver = {
-	.probe = ebi2_lcd_probe,
-	.remove = ebi2_lcd_remove,
-	.suspend = NULL,
-	.resume = NULL,
-	.shutdown = NULL,
-	.driver = {
-		   .name = "ebi2_lcd",
-		   .pm = &ebi2_lcd_dev_pm_ops,
-		   },
-};
-
-static void *ebi2_base;
-static void *ebi2_lcd_cfg0;
-static void *ebi2_lcd_cfg1;
-static void __iomem *lcd01_base;
-static void __iomem *lcd02_base;
-static int lcd01_base_phys;
-static int ebi2_lcd_resource_initialized;
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-static struct lcdc_platform_data *ebi2_pdata;
-
-static int ebi2_lcd_on(struct platform_device *pdev)
-{
-	int ret;
-
-	if (ebi2_pdata && ebi2_pdata->lcdc_power_save)
-		ebi2_pdata->lcdc_power_save(1);
-
-	ret = panel_next_on(pdev);
-	return ret;
-}
-
-static int ebi2_lcd_off(struct platform_device *pdev)
-{
-	int ret;
-
-	ret = panel_next_off(pdev);
-
-	if (ebi2_pdata && ebi2_pdata->lcdc_power_save)
-		ebi2_pdata->lcdc_power_save(0);
-
-	return ret;
-}
-
-static int ebi2_lcd_probe(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	struct platform_device *mdp_dev = NULL;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc, i, hw_version;
-
-	if (pdev->id == 0) {
-		for (i = 0; i < pdev->num_resources; i++) {
-			if (!strncmp(pdev->resource[i].name, "base", 4)) {
-				ebi2_base = ioremap(pdev->resource[i].start,
-						pdev->resource[i].end -
-						pdev->resource[i].start + 1);
-				if (!ebi2_base) {
-					printk(KERN_ERR
-						"ebi2_base ioremap failed!\n");
-					return -ENOMEM;
-				}
-				ebi2_lcd_cfg0 = (void *)(ebi2_base + 0x20);
-				ebi2_lcd_cfg1 = (void *)(ebi2_base + 0x24);
-			} else if (!strncmp(pdev->resource[i].name,
-						"lcd01", 5)) {
-				lcd01_base_phys = pdev->resource[i].start;
-				lcd01_base = ioremap(pdev->resource[i].start,
-						pdev->resource[i].end -
-						pdev->resource[i].start + 1);
-				if (!lcd01_base) {
-					printk(KERN_ERR
-						"lcd01_base ioremap failed!\n");
-					return -ENOMEM;
-				}
-			} else if (!strncmp(pdev->resource[i].name,
-						"lcd02", 5)) {
-				lcd02_base = ioremap(pdev->resource[i].start,
-						pdev->resource[i].end -
-						pdev->resource[i].start + 1);
-				if (!lcd02_base) {
-					printk(KERN_ERR
-						"lcd02_base ioremap failed!\n");
-					return -ENOMEM;
-				}
-			}
-		}
-		ebi2_pdata = pdev->dev.platform_data;
-		ebi2_lcd_resource_initialized = 1;
-
-		return 0;
-	}
-
-	if (!ebi2_lcd_resource_initialized)
-		return -EPERM;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	if (ebi2_base == NULL)
-		return -ENOMEM;
-
-	mdp_dev = platform_device_alloc("mdp", pdev->id);
-	if (!mdp_dev)
-		return -ENOMEM;
-
-	/* link to the latest pdev */
-	mfd->pdev = mdp_dev;
-	mfd->dest = DISPLAY_LCD;
-
-	/* add panel data */
-	if (platform_device_add_data
-	    (mdp_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		printk(KERN_ERR "ebi2_lcd_probe: platform_device_add_data failed!\n");
-		platform_device_put(mdp_dev);
-		return -ENOMEM;
-	}
-
-	/* data chain */
-	pdata = mdp_dev->dev.platform_data;
-	pdata->on = ebi2_lcd_on;
-	pdata->off = ebi2_lcd_off;
-	pdata->next = pdev;
-
-	/* get/set panel specific fb info */
-	mfd->panel_info = pdata->panel_info;
-
-	hw_version = inp32((int)ebi2_base + 8);
-
-	if (mfd->panel_info.bpp == 24)
-		mfd->fb_imgType = MDP_RGB_888;
-	else if (mfd->panel_info.bpp == 18)
-		mfd->fb_imgType = MDP_RGB_888;
-	else
-		mfd->fb_imgType = MDP_RGB_565;
-
-	/* config msm ebi2 lcd register */
-	if (mfd->panel_info.pdest == DISPLAY_1) {
-		outp32(ebi2_base,
-		       (inp32(ebi2_base) & (~(EBI2_PRIM_LCD_CLR))) |
-		       EBI2_PRIM_LCD_SEL);
-		/*
-		 * current design has one set of cfg0/1 register to control
-		 * both EBI2 channels. so, we're using the PRIM channel to
-		 * configure both.
-		 */
-		outp32(ebi2_lcd_cfg0, mfd->panel_info.wait_cycle);
-		if (hw_version < 0x2020) {
-			if (mfd->panel_info.bpp == 18)
-				outp32(ebi2_lcd_cfg1, 0x01000000);
-			else
-				outp32(ebi2_lcd_cfg1, 0x0);
-		}
-	} else {
-#ifdef DEBUG_EBI2_LCD
-		/*
-		 * confliting with QCOM SURF FPGA CS.
-		 * OEM should enable below for their CS mapping
-		 */
-		 outp32(ebi2_base, (inp32(ebi2_base)&(~(EBI2_SECD_LCD_CLR)))
-					|EBI2_SECD_LCD_SEL);
-#endif
-	}
-
-	/*
-	 * map cs (chip select) address
-	 */
-	if (mfd->panel_info.pdest == DISPLAY_1) {
-		mfd->cmd_port = lcd01_base;
-		if (hw_version >= 0x2020) {
-			mfd->data_port =
-				(void *)((uint32) mfd->cmd_port + 0x80);
-			mfd->data_port_phys =
-				(void *)(lcd01_base_phys + 0x80);
-		} else {
-			mfd->data_port =
-			    (void *)((uint32) mfd->cmd_port +
-				    EBI2_PRIM_LCD_RS_PIN);
-			mfd->data_port_phys =
-			    (void *)(LCD_PRIM_BASE_PHYS + EBI2_PRIM_LCD_RS_PIN);
-		}
-	} else {
-		mfd->cmd_port = lcd01_base;
-		mfd->data_port =
-		    (void *)((uint32) mfd->cmd_port + EBI2_SECD_LCD_RS_PIN);
-		mfd->data_port_phys =
-		    (void *)(LCD_SECD_BASE_PHYS + EBI2_SECD_LCD_RS_PIN);
-	}
-
-	/*
-	 * set driver data
-	 */
-	platform_set_drvdata(mdp_dev, mfd);
-
-	/*
-	 * register in mdp driver
-	 */
-	rc = platform_device_add(mdp_dev);
-	if (rc) {
-		goto ebi2_lcd_probe_err;
-	}
-
-	pm_runtime_set_active(&pdev->dev);
-	pm_runtime_enable(&pdev->dev);
-
-
-	pdev_list[pdev_list_cnt++] = pdev;
-	return 0;
-
-      ebi2_lcd_probe_err:
-	platform_device_put(mdp_dev);
-	return rc;
-}
-
-static int ebi2_lcd_remove(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return 0;
-
-	if (mfd->key != MFD_KEY)
-		return 0;
-
-	iounmap(mfd->cmd_port);
-	pm_runtime_disable(&pdev->dev);
-	return 0;
-}
-
-static int ebi2_lcd_register_driver(void)
-{
-	return platform_driver_register(&ebi2_lcd_driver);
-}
-
-static int __init ebi2_lcd_driver_init(void)
-{
-	return ebi2_lcd_register_driver();
-}
-
-module_init(ebi2_lcd_driver_init);
diff --git a/drivers/video/msm/ebi2_tmd20.c b/drivers/video/msm/ebi2_tmd20.c
deleted file mode 100644
index 7c7b0ef..0000000
--- a/drivers/video/msm/ebi2_tmd20.c
+++ /dev/null
@@ -1,1120 +0,0 @@
-/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-#include <linux/memory.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include "linux/proc_fs.h"
-
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-
-/* #define TMD20QVGA_LCD_18BPP */
-#define QVGA_WIDTH        240
-#define QVGA_HEIGHT       320
-
-#ifdef TMD20QVGA_LCD_18BPP
-#define DISP_QVGA_18BPP(x)  ((((x)<<2) & 0x3FC00)|(( (x)<<1)& 0x1FE))
-#define DISP_REG(name)  uint32 register_##name;
-#define OUTPORT(x, y)  outpdw(x, y)
-#define INPORT(x)   inpdw(x)
-#else
-#define DISP_QVGA_18BPP(x)  (x)
-#define DISP_REG(name)  uint16 register_##name;
-#define OUTPORT(x, y)  outpw(x, y)
-#define INPORT(x)   intpw(x)
-#endif
-
-static void *DISP_CMD_PORT;
-static void *DISP_DATA_PORT;
-
-#define DISP_RNTI         0x10
-
-#define DISP_CMD_OUT(cmd) OUTPORT(DISP_CMD_PORT, DISP_QVGA_18BPP(cmd))
-#define DISP_DATA_OUT(data) OUTPORT(DISP_DATA_PORT, data)
-#define DISP_DATA_IN() INPORT(DISP_DATA_PORT)
-
-#if (defined(TMD20QVGA_LCD_18BPP))
-#define DISP_DATA_OUT_16TO18BPP(x) \
-	DISP_DATA_OUT((((x)&0xf800)<<2|((x)&0x80000)>>3) \
-		     | (((x)&0x7e0)<<1) \
-		     | (((x)&0x1F)<<1|((x)&0x10)>>4))
-#else
-#define DISP_DATA_OUT_16TO18BPP(x) \
-	DISP_DATA_OUT(x)
-#endif
-
-#define DISP_WRITE_OUT(addr, data) \
-   register_##addr = DISP_QVGA_18BPP(data); \
-   DISP_CMD_OUT(addr); \
-   DISP_DATA_OUT(register_##addr);
-
-#define DISP_UPDATE_VALUE(addr, bitmask, data) \
-   DISP_WRITE_OUT(##addr, (register_##addr & ~(bitmask)) | (data));
-
-#define DISP_VAL_IF(bitvalue, bitmask) \
-   ((bitvalue) ? (bitmask) : 0)
-
-/* QVGA = 256 x 320 */
-/* actual display is 240 x 320...offset by 0x10 */
-#define DISP_ROW_COL_TO_ADDR(row, col) ((row) * 0x100 + col)
-#define DISP_SET_RECT(ulhc_row, lrhc_row, ulhc_col, lrhc_col) \
-   { \
-   DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \
-   DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, (lrhc_col) + tmd20qvga_panel_offset); \
-   DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, (ulhc_row)); \
-   DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, (lrhc_row)); \
-   DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, (ulhc_col) + tmd20qvga_panel_offset); \
-   DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, (ulhc_row)); \
-   }
-
-#define WAIT_MSEC(msec) mdelay(msec)
-
-/*
- * TMD QVGA Address
- */
-/* Display Control */
-#define DISP_START_OSCILLATION_ADDR     0x000
-DISP_REG(DISP_START_OSCILLATION_ADDR)
-#define DISP_DRIVER_OUTPUT_CTL_ADDR     0x001
-    DISP_REG(DISP_DRIVER_OUTPUT_CTL_ADDR)
-#define DISP_LCD_DRIVING_SIG_ADDR     0x002
-    DISP_REG(DISP_LCD_DRIVING_SIG_ADDR)
-#define DISP_ENTRY_MODE_ADDR            0x003
-    DISP_REG(DISP_ENTRY_MODE_ADDR)
-#define DISP_DISPLAY_CTL_1_ADDR         0x007
-    DISP_REG(DISP_DISPLAY_CTL_1_ADDR)
-#define DISP_DISPLAY_CTL_2_ADDR         0x008
-    DISP_REG(DISP_DISPLAY_CTL_2_ADDR)
-
-/* DISPLAY MODE 0x009 partial display not supported */
-#define DISP_POWER_SUPPLY_INTF_ADDR     0x00A
-    DISP_REG(DISP_POWER_SUPPLY_INTF_ADDR)
-
-/* DISPLAY MODE 0x00B xZoom feature is not supported */
-#define DISP_EXT_DISPLAY_CTL_1_ADDR     0x00C
-    DISP_REG(DISP_EXT_DISPLAY_CTL_1_ADDR)
-
-#define DISP_FRAME_CYCLE_CTL_ADDR       0x00D
-    DISP_REG(DISP_FRAME_CYCLE_CTL_ADDR)
-
-#define DISP_EXT_DISPLAY_CTL_2_ADDR     0x00E
-    DISP_REG(DISP_EXT_DISPLAY_CTL_2_ADDR)
-
-#define DISP_EXT_DISPLAY_CTL_3_ADDR     0x00F
-    DISP_REG(DISP_EXT_DISPLAY_CTL_3_ADDR)
-
-#define DISP_LTPS_CTL_1_ADDR            0x012
-    DISP_REG(DISP_LTPS_CTL_1_ADDR)
-#define DISP_LTPS_CTL_2_ADDR            0x013
-    DISP_REG(DISP_LTPS_CTL_2_ADDR)
-#define DISP_LTPS_CTL_3_ADDR            0x014
-    DISP_REG(DISP_LTPS_CTL_3_ADDR)
-#define DISP_LTPS_CTL_4_ADDR            0x018
-    DISP_REG(DISP_LTPS_CTL_4_ADDR)
-#define DISP_LTPS_CTL_5_ADDR            0x019
-    DISP_REG(DISP_LTPS_CTL_5_ADDR)
-#define DISP_LTPS_CTL_6_ADDR            0x01A
-    DISP_REG(DISP_LTPS_CTL_6_ADDR)
-#define DISP_AMP_SETTING_ADDR           0x01C
-    DISP_REG(DISP_AMP_SETTING_ADDR)
-#define DISP_MODE_SETTING_ADDR          0x01D
-    DISP_REG(DISP_MODE_SETTING_ADDR)
-#define DISP_POFF_LN_SETTING_ADDR       0x01E
-    DISP_REG(DISP_POFF_LN_SETTING_ADDR)
-/* Power Contol */
-#define DISP_POWER_CTL_1_ADDR           0x100
-    DISP_REG(DISP_POWER_CTL_1_ADDR)
-#define DISP_POWER_CTL_2_ADDR           0x101
-    DISP_REG(DISP_POWER_CTL_2_ADDR)
-#define DISP_POWER_CTL_3_ADDR           0x102
-    DISP_REG(DISP_POWER_CTL_3_ADDR)
-#define DISP_POWER_CTL_4_ADDR           0x103
-    DISP_REG(DISP_POWER_CTL_4_ADDR)
-#define DISP_POWER_CTL_5_ADDR           0x104
-    DISP_REG(DISP_POWER_CTL_5_ADDR)
-#define DISP_POWER_CTL_6_ADDR           0x105
-    DISP_REG(DISP_POWER_CTL_6_ADDR)
-#define DISP_POWER_CTL_7_ADDR           0x106
-    DISP_REG(DISP_POWER_CTL_7_ADDR)
-/* RAM Access */
-#define DISP_RAM_ADDR_SET_1_ADDR        0x200
-    DISP_REG(DISP_RAM_ADDR_SET_1_ADDR)
-#define DISP_RAM_ADDR_SET_2_ADDR        0x201
-    DISP_REG(DISP_RAM_ADDR_SET_2_ADDR)
-#define DISP_CMD_RAMRD                  DISP_CMD_RAMWR
-#define DISP_CMD_RAMWR                  0x202
-    DISP_REG(DISP_CMD_RAMWR)
-#define DISP_RAM_DATA_MASK_1_ADDR       0x203
-    DISP_REG(DISP_RAM_DATA_MASK_1_ADDR)
-#define DISP_RAM_DATA_MASK_2_ADDR       0x204
-    DISP_REG(DISP_RAM_DATA_MASK_2_ADDR)
-/* Gamma Control, Contrast, Gray Scale Setting */
-#define DISP_GAMMA_CONTROL_1_ADDR       0x300
-    DISP_REG(DISP_GAMMA_CONTROL_1_ADDR)
-#define DISP_GAMMA_CONTROL_2_ADDR       0x301
-    DISP_REG(DISP_GAMMA_CONTROL_2_ADDR)
-#define DISP_GAMMA_CONTROL_3_ADDR       0x302
-    DISP_REG(DISP_GAMMA_CONTROL_3_ADDR)
-#define DISP_GAMMA_CONTROL_4_ADDR       0x303
-    DISP_REG(DISP_GAMMA_CONTROL_4_ADDR)
-#define DISP_GAMMA_CONTROL_5_ADDR       0x304
-    DISP_REG(DISP_GAMMA_CONTROL_5_ADDR)
-/* Coordinate Control */
-#define DISP_VERT_SCROLL_CTL_1_ADDR     0x400
-    DISP_REG(DISP_VERT_SCROLL_CTL_1_ADDR)
-#define DISP_VERT_SCROLL_CTL_2_ADDR     0x401
-    DISP_REG(DISP_VERT_SCROLL_CTL_2_ADDR)
-#define DISP_SCREEN_1_DRV_POS_1_ADDR    0x402
-    DISP_REG(DISP_SCREEN_1_DRV_POS_1_ADDR)
-#define DISP_SCREEN_1_DRV_POS_2_ADDR    0x403
-    DISP_REG(DISP_SCREEN_1_DRV_POS_2_ADDR)
-#define DISP_SCREEN_2_DRV_POS_1_ADDR    0x404
-    DISP_REG(DISP_SCREEN_2_DRV_POS_1_ADDR)
-#define DISP_SCREEN_2_DRV_POS_2_ADDR    0x405
-    DISP_REG(DISP_SCREEN_2_DRV_POS_2_ADDR)
-#define DISP_HORZ_RAM_ADDR_POS_1_ADDR   0x406
-    DISP_REG(DISP_HORZ_RAM_ADDR_POS_1_ADDR)
-#define DISP_HORZ_RAM_ADDR_POS_2_ADDR   0x407
-    DISP_REG(DISP_HORZ_RAM_ADDR_POS_2_ADDR)
-#define DISP_VERT_RAM_ADDR_POS_1_ADDR   0x408
-    DISP_REG(DISP_VERT_RAM_ADDR_POS_1_ADDR)
-#define DISP_VERT_RAM_ADDR_POS_2_ADDR   0x409
-    DISP_REG(DISP_VERT_RAM_ADDR_POS_2_ADDR)
-#define DISP_TMD_700_ADDR               0x700	/*  0x700 */
-    DISP_REG(DISP_TMD_700_ADDR)
-#define DISP_TMD_015_ADDR               0x015	/*  0x700 */
-    DISP_REG(DISP_TMD_015_ADDR)
-#define DISP_TMD_305_ADDR               0x305	/*  0x700 */
-    DISP_REG(DISP_TMD_305_ADDR)
-
-/*
- * TMD QVGA Bit Definations
- */
-
-#define DISP_BIT_IB15              0x8000
-#define DISP_BIT_IB14              0x4000
-#define DISP_BIT_IB13              0x2000
-#define DISP_BIT_IB12              0x1000
-#define DISP_BIT_IB11              0x0800
-#define DISP_BIT_IB10              0x0400
-#define DISP_BIT_IB09              0x0200
-#define DISP_BIT_IB08              0x0100
-#define DISP_BIT_IB07              0x0080
-#define DISP_BIT_IB06              0x0040
-#define DISP_BIT_IB05              0x0020
-#define DISP_BIT_IB04              0x0010
-#define DISP_BIT_IB03              0x0008
-#define DISP_BIT_IB02              0x0004
-#define DISP_BIT_IB01              0x0002
-#define DISP_BIT_IB00              0x0001
-/*
- * Display Control
- * DISP_START_OSCILLATION_ADDR     Start Oscillation
- * DISP_DRIVER_OUTPUT_CTL_ADDR     Driver Output Control
- */
-#define DISP_BITMASK_SS            DISP_BIT_IB08
-#define DISP_BITMASK_NL5           DISP_BIT_IB05
-#define DISP_BITMASK_NL4           DISP_BIT_IB04
-#define DISP_BITMASK_NL3           DISP_BIT_IB03
-#define DISP_BITMASK_NL2           DISP_BIT_IB02
-#define DISP_BITMASK_NL1           DISP_BIT_IB01
-#define DISP_BITMASK_NL0           DISP_BIT_IB00
-/* DISP_LCD_DRIVING_SIG_ADDR       LCD Driving Signal Setting */
-#define DISP_BITMASK_BC            DISP_BIT_IB09
-/* DISP_ENTRY_MODE_ADDR            Entry Mode */
-#define DISP_BITMASK_TRI           DISP_BIT_IB15
-#define DISP_BITMASK_DFM1          DISP_BIT_IB14
-#define DISP_BITMASK_DFM0          DISP_BIT_IB13
-#define DISP_BITMASK_BGR           DISP_BIT_IB12
-#define DISP_BITMASK_HWM0          DISP_BIT_IB08
-#define DISP_BITMASK_ID1           DISP_BIT_IB05
-#define DISP_BITMASK_ID0           DISP_BIT_IB04
-#define DISP_BITMASK_AM            DISP_BIT_IB03
-/* DISP_DISPLAY_CTL_1_ADDR         Display Control (1) */
-#define DISP_BITMASK_COL1          DISP_BIT_IB15
-#define DISP_BITMASK_COL0          DISP_BIT_IB14
-#define DISP_BITMASK_VLE2          DISP_BIT_IB10
-#define DISP_BITMASK_VLE1          DISP_BIT_IB09
-#define DISP_BITMASK_SPT           DISP_BIT_IB08
-#define DISP_BITMASK_PT1           DISP_BIT_IB07
-#define DISP_BITMASK_PT0           DISP_BIT_IB06
-#define DISP_BITMASK_REV           DISP_BIT_IB02
-/* DISP_DISPLAY_CTL_2_ADDR         Display Control (2) */
-#define DISP_BITMASK_FP3           DISP_BIT_IB11
-#define DISP_BITMASK_FP2           DISP_BIT_IB10
-#define DISP_BITMASK_FP1           DISP_BIT_IB09
-#define DISP_BITMASK_FP0           DISP_BIT_IB08
-#define DISP_BITMASK_BP3           DISP_BIT_IB03
-#define DISP_BITMASK_BP2           DISP_BIT_IB02
-#define DISP_BITMASK_BP1           DISP_BIT_IB01
-#define DISP_BITMASK_BP0           DISP_BIT_IB00
-/* DISP_POWER_SUPPLY_INTF_ADDR     Power Supply IC Interface Control */
-#define DISP_BITMASK_CSE           DISP_BIT_IB12
-#define DISP_BITMASK_TE            DISP_BIT_IB08
-#define DISP_BITMASK_IX3           DISP_BIT_IB03
-#define DISP_BITMASK_IX2           DISP_BIT_IB02
-#define DISP_BITMASK_IX1           DISP_BIT_IB01
-#define DISP_BITMASK_IX0           DISP_BIT_IB00
-/* DISP_EXT_DISPLAY_CTL_1_ADDR     External Display Interface Control (1) */
-#define DISP_BITMASK_RM            DISP_BIT_IB08
-#define DISP_BITMASK_DM1           DISP_BIT_IB05
-#define DISP_BITMASK_DM0           DISP_BIT_IB04
-#define DISP_BITMASK_RIM1          DISP_BIT_IB01
-#define DISP_BITMASK_RIM0          DISP_BIT_IB00
-/* DISP_FRAME_CYCLE_CTL_ADDR       Frame Frequency Adjustment Control */
-#define DISP_BITMASK_DIVI1         DISP_BIT_IB09
-#define DISP_BITMASK_DIVI0         DISP_BIT_IB08
-#define DISP_BITMASK_RTNI4         DISP_BIT_IB04
-#define DISP_BITMASK_RTNI3         DISP_BIT_IB03
-#define DISP_BITMASK_RTNI2         DISP_BIT_IB02
-#define DISP_BITMASK_RTNI1         DISP_BIT_IB01
-#define DISP_BITMASK_RTNI0         DISP_BIT_IB00
-/* DISP_EXT_DISPLAY_CTL_2_ADDR     External Display Interface Control (2) */
-#define DISP_BITMASK_DIVE1         DISP_BIT_IB09
-#define DISP_BITMASK_DIVE0         DISP_BIT_IB08
-#define DISP_BITMASK_RTNE7         DISP_BIT_IB07
-#define DISP_BITMASK_RTNE6         DISP_BIT_IB06
-#define DISP_BITMASK_RTNE5         DISP_BIT_IB05
-#define DISP_BITMASK_RTNE4         DISP_BIT_IB04
-#define DISP_BITMASK_RTNE3         DISP_BIT_IB03
-#define DISP_BITMASK_RTNE2         DISP_BIT_IB02
-#define DISP_BITMASK_RTNE1         DISP_BIT_IB01
-#define DISP_BITMASK_RTNE0         DISP_BIT_IB00
-/* DISP_EXT_DISPLAY_CTL_3_ADDR     External Display Interface Control (3) */
-#define DISP_BITMASK_VSPL          DISP_BIT_IB04
-#define DISP_BITMASK_HSPL          DISP_BIT_IB03
-#define DISP_BITMASK_VPL           DISP_BIT_IB02
-#define DISP_BITMASK_EPL           DISP_BIT_IB01
-#define DISP_BITMASK_DPL           DISP_BIT_IB00
-/* DISP_LTPS_CTL_1_ADDR            LTPS Interface Control (1) */
-#define DISP_BITMASK_CLWI3         DISP_BIT_IB11
-#define DISP_BITMASK_CLWI2         DISP_BIT_IB10
-#define DISP_BITMASK_CLWI1         DISP_BIT_IB09
-#define DISP_BITMASK_CLWI0         DISP_BIT_IB08
-#define DISP_BITMASK_CLTI1         DISP_BIT_IB01
-#define DISP_BITMASK_CLTI0         DISP_BIT_IB00
-/* DISP_LTPS_CTL_2_ADDR            LTPS Interface Control (2) */
-#define DISP_BITMASK_OEVBI1        DISP_BIT_IB09
-#define DISP_BITMASK_OEVBI0        DISP_BIT_IB08
-#define DISP_BITMASK_OEVFI1        DISP_BIT_IB01
-#define DISP_BITMASK_OEVFI0        DISP_BIT_IB00
-/* DISP_LTPS_CTL_3_ADDR            LTPS Interface Control (3) */
-#define DISP_BITMASK_SHI1          DISP_BIT_IB01
-#define DISP_BITMASK_SHI0          DISP_BIT_IB00
-/* DISP_LTPS_CTL_4_ADDR            LTPS Interface Control (4) */
-#define DISP_BITMASK_CLWE5         DISP_BIT_IB13
-#define DISP_BITMASK_CLWE4         DISP_BIT_IB12
-#define DISP_BITMASK_CLWE3         DISP_BIT_IB11
-#define DISP_BITMASK_CLWE2         DISP_BIT_IB10
-#define DISP_BITMASK_CLWE1         DISP_BIT_IB09
-#define DISP_BITMASK_CLWE0         DISP_BIT_IB08
-#define DISP_BITMASK_CLTE3         DISP_BIT_IB03
-#define DISP_BITMASK_CLTE2         DISP_BIT_IB02
-#define DISP_BITMASK_CLTE1         DISP_BIT_IB01
-#define DISP_BITMASK_CLTE0         DISP_BIT_IB00
-/* DISP_LTPS_CTL_5_ADDR            LTPS Interface Control (5) */
-#define DISP_BITMASK_OEVBE3        DISP_BIT_IB11
-#define DISP_BITMASK_OEVBE2        DISP_BIT_IB10
-#define DISP_BITMASK_OEVBE1        DISP_BIT_IB09
-#define DISP_BITMASK_OEVBE0        DISP_BIT_IB08
-#define DISP_BITMASK_OEVFE3        DISP_BIT_IB03
-#define DISP_BITMASK_OEVFE2        DISP_BIT_IB02
-#define DISP_BITMASK_OEVFE1        DISP_BIT_IB01
-#define DISP_BITMASK_OEVFE0        DISP_BIT_IB00
-/* DISP_LTPS_CTL_6_ADDR            LTPS Interface Control (6) */
-#define DISP_BITMASK_SHE3          DISP_BIT_IB03
-#define DISP_BITMASK_SHE2          DISP_BIT_IB02
-#define DISP_BITMASK_SHE1          DISP_BIT_IB01
-#define DISP_BITMASK_SHE0          DISP_BIT_IB00
-/* DISP_AMP_SETTING_ADDR           Amplify Setting */
-#define DISP_BITMASK_ABSW1         DISP_BIT_IB01
-#define DISP_BITMASK_ABSW0         DISP_BIT_IB00
-/* DISP_MODE_SETTING_ADDR          Mode Setting */
-#define DISP_BITMASK_DSTB          DISP_BIT_IB02
-#define DISP_BITMASK_STB           DISP_BIT_IB00
-/* DISP_POFF_LN_SETTING_ADDR       Power Off Line Setting */
-#define DISP_BITMASK_POFH3         DISP_BIT_IB03
-#define DISP_BITMASK_POFH2         DISP_BIT_IB02
-#define DISP_BITMASK_POFH1         DISP_BIT_IB01
-#define DISP_BITMASK_POFH0         DISP_BIT_IB00
-
-/* Power Contol */
-/* DISP_POWER_CTL_1_ADDR           Power Control (1) */
-#define DISP_BITMASK_PO            DISP_BIT_IB11
-#define DISP_BITMASK_VCD           DISP_BIT_IB09
-#define DISP_BITMASK_VSC           DISP_BIT_IB08
-#define DISP_BITMASK_CON           DISP_BIT_IB07
-#define DISP_BITMASK_ASW1          DISP_BIT_IB06
-#define DISP_BITMASK_ASW0          DISP_BIT_IB05
-#define DISP_BITMASK_OEV           DISP_BIT_IB04
-#define DISP_BITMASK_OEVE          DISP_BIT_IB03
-#define DISP_BITMASK_FR            DISP_BIT_IB02
-#define DISP_BITMASK_D1            DISP_BIT_IB01
-#define DISP_BITMASK_D0            DISP_BIT_IB00
-/* DISP_POWER_CTL_2_ADDR           Power Control (2) */
-#define DISP_BITMASK_DC4           DISP_BIT_IB15
-#define DISP_BITMASK_DC3           DISP_BIT_IB14
-#define DISP_BITMASK_SAP2          DISP_BIT_IB13
-#define DISP_BITMASK_SAP1          DISP_BIT_IB12
-#define DISP_BITMASK_SAP0          DISP_BIT_IB11
-#define DISP_BITMASK_BT2           DISP_BIT_IB10
-#define DISP_BITMASK_BT1           DISP_BIT_IB09
-#define DISP_BITMASK_BT0           DISP_BIT_IB08
-#define DISP_BITMASK_DC2           DISP_BIT_IB07
-#define DISP_BITMASK_DC1           DISP_BIT_IB06
-#define DISP_BITMASK_DC0           DISP_BIT_IB05
-#define DISP_BITMASK_AP2           DISP_BIT_IB04
-#define DISP_BITMASK_AP1           DISP_BIT_IB03
-#define DISP_BITMASK_AP0           DISP_BIT_IB02
-/* DISP_POWER_CTL_3_ADDR           Power Control (3) */
-#define DISP_BITMASK_VGL4          DISP_BIT_IB10
-#define DISP_BITMASK_VGL3          DISP_BIT_IB09
-#define DISP_BITMASK_VGL2          DISP_BIT_IB08
-#define DISP_BITMASK_VGL1          DISP_BIT_IB07
-#define DISP_BITMASK_VGL0          DISP_BIT_IB06
-#define DISP_BITMASK_VGH4          DISP_BIT_IB04
-#define DISP_BITMASK_VGH3          DISP_BIT_IB03
-#define DISP_BITMASK_VGH2          DISP_BIT_IB02
-#define DISP_BITMASK_VGH1          DISP_BIT_IB01
-#define DISP_BITMASK_VGH0          DISP_BIT_IB00
-/* DISP_POWER_CTL_4_ADDR           Power Control (4) */
-#define DISP_BITMASK_VC2           DISP_BIT_IB02
-#define DISP_BITMASK_VC1           DISP_BIT_IB01
-#define DISP_BITMASK_VC0           DISP_BIT_IB00
-/* DISP_POWER_CTL_5_ADDR           Power Control (5) */
-#define DISP_BITMASK_VRL3          DISP_BIT_IB11
-#define DISP_BITMASK_VRL2          DISP_BIT_IB10
-#define DISP_BITMASK_VRL1          DISP_BIT_IB09
-#define DISP_BITMASK_VRL0          DISP_BIT_IB08
-#define DISP_BITMASK_PON           DISP_BIT_IB04
-#define DISP_BITMASK_VRH3          DISP_BIT_IB03
-#define DISP_BITMASK_VRH2          DISP_BIT_IB02
-#define DISP_BITMASK_VRH1          DISP_BIT_IB01
-#define DISP_BITMASK_VRH0          DISP_BIT_IB00
-/* DISP_POWER_CTL_6_ADDR           Power Control (6) */
-#define DISP_BITMASK_VCOMG         DISP_BIT_IB13
-#define DISP_BITMASK_VDV4          DISP_BIT_IB12
-#define DISP_BITMASK_VDV3          DISP_BIT_IB11
-#define DISP_BITMASK_VDV2          DISP_BIT_IB10
-#define DISP_BITMASK_VDV1          DISP_BIT_IB09
-#define DISP_BITMASK_VDV0          DISP_BIT_IB08
-#define DISP_BITMASK_VCM4          DISP_BIT_IB04
-#define DISP_BITMASK_VCM3          DISP_BIT_IB03
-#define DISP_BITMASK_VCM2          DISP_BIT_IB02
-#define DISP_BITMASK_VCM1          DISP_BIT_IB01
-#define DISP_BITMASK_VCM0          DISP_BIT_IB00
-/* RAM Access */
-/* DISP_RAM_ADDR_SET_1_ADDR        RAM Address Set (1) */
-#define DISP_BITMASK_AD7           DISP_BIT_IB07
-#define DISP_BITMASK_AD6           DISP_BIT_IB06
-#define DISP_BITMASK_AD5           DISP_BIT_IB05
-#define DISP_BITMASK_AD4           DISP_BIT_IB04
-#define DISP_BITMASK_AD3           DISP_BIT_IB03
-#define DISP_BITMASK_AD2           DISP_BIT_IB02
-#define DISP_BITMASK_AD1           DISP_BIT_IB01
-#define DISP_BITMASK_AD0           DISP_BIT_IB00
-/* DISP_RAM_ADDR_SET_2_ADDR        RAM Address Set (2) */
-#define DISP_BITMASK_AD16          DISP_BIT_IB08
-#define DISP_BITMASK_AD15          DISP_BIT_IB07
-#define DISP_BITMASK_AD14          DISP_BIT_IB06
-#define DISP_BITMASK_AD13          DISP_BIT_IB05
-#define DISP_BITMASK_AD12          DISP_BIT_IB04
-#define DISP_BITMASK_AD11          DISP_BIT_IB03
-#define DISP_BITMASK_AD10          DISP_BIT_IB02
-#define DISP_BITMASK_AD9           DISP_BIT_IB01
-#define DISP_BITMASK_AD8           DISP_BIT_IB00
-/*
- * DISP_CMD_RAMWR       RAM Data Read/Write
- * Use Data Bit Configuration
- */
-/* DISP_RAM_DATA_MASK_1_ADDR       RAM Write Data Mask (1) */
-#define DISP_BITMASK_WM11          DISP_BIT_IB13
-#define DISP_BITMASK_WM10          DISP_BIT_IB12
-#define DISP_BITMASK_WM9           DISP_BIT_IB11
-#define DISP_BITMASK_WM8           DISP_BIT_IB10
-#define DISP_BITMASK_WM7           DISP_BIT_IB09
-#define DISP_BITMASK_WM6           DISP_BIT_IB08
-#define DISP_BITMASK_WM5           DISP_BIT_IB05
-#define DISP_BITMASK_WM4           DISP_BIT_IB04
-#define DISP_BITMASK_WM3           DISP_BIT_IB03
-#define DISP_BITMASK_WM2           DISP_BIT_IB02
-#define DISP_BITMASK_WM1           DISP_BIT_IB01
-#define DISP_BITMASK_WM0           DISP_BIT_IB00
-/* DISP_RAM_DATA_MASK_2_ADDR       RAM Write Data Mask (2) */
-#define DISP_BITMASK_WM17          DISP_BIT_IB05
-#define DISP_BITMASK_WM16          DISP_BIT_IB04
-#define DISP_BITMASK_WM15          DISP_BIT_IB03
-#define DISP_BITMASK_WM14          DISP_BIT_IB02
-#define DISP_BITMASK_WM13          DISP_BIT_IB01
-#define DISP_BITMASK_WM12          DISP_BIT_IB00
-/*Gamma Control */
-/* DISP_GAMMA_CONTROL_1_ADDR       Gamma Control (1) */
-#define DISP_BITMASK_PKP12         DISP_BIT_IB10
-#define DISP_BITMASK_PKP11         DISP_BIT_IB08
-#define DISP_BITMASK_PKP10         DISP_BIT_IB09
-#define DISP_BITMASK_PKP02         DISP_BIT_IB02
-#define DISP_BITMASK_PKP01         DISP_BIT_IB01
-#define DISP_BITMASK_PKP00         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_2_ADDR       Gamma Control (2) */
-#define DISP_BITMASK_PKP32         DISP_BIT_IB10
-#define DISP_BITMASK_PKP31         DISP_BIT_IB09
-#define DISP_BITMASK_PKP30         DISP_BIT_IB08
-#define DISP_BITMASK_PKP22         DISP_BIT_IB02
-#define DISP_BITMASK_PKP21         DISP_BIT_IB01
-#define DISP_BITMASK_PKP20         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_3_ADDR       Gamma Control (3) */
-#define DISP_BITMASK_PKP52         DISP_BIT_IB10
-#define DISP_BITMASK_PKP51         DISP_BIT_IB09
-#define DISP_BITMASK_PKP50         DISP_BIT_IB08
-#define DISP_BITMASK_PKP42         DISP_BIT_IB02
-#define DISP_BITMASK_PKP41         DISP_BIT_IB01
-#define DISP_BITMASK_PKP40         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_4_ADDR       Gamma Control (4) */
-#define DISP_BITMASK_PRP12         DISP_BIT_IB10
-#define DISP_BITMASK_PRP11         DISP_BIT_IB08
-#define DISP_BITMASK_PRP10         DISP_BIT_IB09
-#define DISP_BITMASK_PRP02         DISP_BIT_IB02
-#define DISP_BITMASK_PRP01         DISP_BIT_IB01
-#define DISP_BITMASK_PRP00         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_5_ADDR       Gamma Control (5) */
-#define DISP_BITMASK_VRP14         DISP_BIT_IB12
-#define DISP_BITMASK_VRP13         DISP_BIT_IB11
-#define DISP_BITMASK_VRP12         DISP_BIT_IB10
-#define DISP_BITMASK_VRP11         DISP_BIT_IB08
-#define DISP_BITMASK_VRP10         DISP_BIT_IB09
-#define DISP_BITMASK_VRP03         DISP_BIT_IB03
-#define DISP_BITMASK_VRP02         DISP_BIT_IB02
-#define DISP_BITMASK_VRP01         DISP_BIT_IB01
-#define DISP_BITMASK_VRP00         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_6_ADDR       Gamma Control (6) */
-#define DISP_BITMASK_PKN12         DISP_BIT_IB10
-#define DISP_BITMASK_PKN11         DISP_BIT_IB08
-#define DISP_BITMASK_PKN10         DISP_BIT_IB09
-#define DISP_BITMASK_PKN02         DISP_BIT_IB02
-#define DISP_BITMASK_PKN01         DISP_BIT_IB01
-#define DISP_BITMASK_PKN00         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_7_ADDR       Gamma Control (7) */
-#define DISP_BITMASK_PKN32         DISP_BIT_IB10
-#define DISP_BITMASK_PKN31         DISP_BIT_IB08
-#define DISP_BITMASK_PKN30         DISP_BIT_IB09
-#define DISP_BITMASK_PKN22         DISP_BIT_IB02
-#define DISP_BITMASK_PKN21         DISP_BIT_IB01
-#define DISP_BITMASK_PKN20         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_8_ADDR       Gamma Control (8) */
-#define DISP_BITMASK_PKN52         DISP_BIT_IB10
-#define DISP_BITMASK_PKN51         DISP_BIT_IB08
-#define DISP_BITMASK_PKN50         DISP_BIT_IB09
-#define DISP_BITMASK_PKN42         DISP_BIT_IB02
-#define DISP_BITMASK_PKN41         DISP_BIT_IB01
-#define DISP_BITMASK_PKN40         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_9_ADDR       Gamma Control (9) */
-#define DISP_BITMASK_PRN12         DISP_BIT_IB10
-#define DISP_BITMASK_PRN11         DISP_BIT_IB08
-#define DISP_BITMASK_PRN10         DISP_BIT_IB09
-#define DISP_BITMASK_PRN02         DISP_BIT_IB02
-#define DISP_BITMASK_PRN01         DISP_BIT_IB01
-#define DISP_BITMASK_PRN00         DISP_BIT_IB00
-/* DISP_GAMMA_CONTROL_10_ADDR      Gamma Control (10) */
-#define DISP_BITMASK_VRN14         DISP_BIT_IB12
-#define DISP_BITMASK_VRN13         DISP_BIT_IB11
-#define DISP_BITMASK_VRN12         DISP_BIT_IB10
-#define DISP_BITMASK_VRN11         DISP_BIT_IB08
-#define DISP_BITMASK_VRN10         DISP_BIT_IB09
-#define DISP_BITMASK_VRN03         DISP_BIT_IB03
-#define DISP_BITMASK_VRN02         DISP_BIT_IB02
-#define DISP_BITMASK_VRN01         DISP_BIT_IB01
-#define DISP_BITMASK_VRN00         DISP_BIT_IB00
-/* Coordinate Control */
-/* DISP_VERT_SCROLL_CTL_1_ADDR     Vertical Scroll Control (1) */
-#define DISP_BITMASK_VL18          DISP_BIT_IB08
-#define DISP_BITMASK_VL17          DISP_BIT_IB07
-#define DISP_BITMASK_VL16          DISP_BIT_IB06
-#define DISP_BITMASK_VL15          DISP_BIT_IB05
-#define DISP_BITMASK_VL14          DISP_BIT_IB04
-#define DISP_BITMASK_VL13          DISP_BIT_IB03
-#define DISP_BITMASK_VL12          DISP_BIT_IB02
-#define DISP_BITMASK_VL11          DISP_BIT_IB01
-#define DISP_BITMASK_VL10          DISP_BIT_IB00
-/* DISP_VERT_SCROLL_CTL_2_ADDR     Vertical Scroll Control (2) */
-#define DISP_BITMASK_VL28          DISP_BIT_IB08
-#define DISP_BITMASK_VL27          DISP_BIT_IB07
-#define DISP_BITMASK_VL26          DISP_BIT_IB06
-#define DISP_BITMASK_VL25          DISP_BIT_IB05
-#define DISP_BITMASK_VL24          DISP_BIT_IB04
-#define DISP_BITMASK_VL23          DISP_BIT_IB03
-#define DISP_BITMASK_VL22          DISP_BIT_IB02
-#define DISP_BITMASK_VL21          DISP_BIT_IB01
-#define DISP_BITMASK_VL20          DISP_BIT_IB00
-/* DISP_SCREEN_1_DRV_POS_1_ADDR    First Screen Driving Position (1) */
-#define DISP_BITMASK_SS18          DISP_BIT_IB08
-#define DISP_BITMASK_SS17          DISP_BIT_IB07
-#define DISP_BITMASK_SS16          DISP_BIT_IB06
-#define DISP_BITMASK_SS15          DISP_BIT_IB05
-#define DISP_BITMASK_SS14          DISP_BIT_IB04
-#define DISP_BITMASK_SS13          DISP_BIT_IB03
-#define DISP_BITMASK_SS12          DISP_BIT_IB02
-#define DISP_BITMASK_SS11          DISP_BIT_IB01
-#define DISP_BITMASK_SS10          DISP_BIT_IB00
-/* DISP_SCREEN_1_DRV_POS_2_ADDR    First Screen Driving Position (2) */
-#define DISP_BITMASK_SE18          DISP_BIT_IB08
-#define DISP_BITMASK_SE17          DISP_BIT_IB07
-#define DISP_BITMASK_SE16          DISP_BIT_IB06
-#define DISP_BITMASK_SE15          DISP_BIT_IB05
-#define DISP_BITMASK_SE14          DISP_BIT_IB04
-#define DISP_BITMASK_SE13          DISP_BIT_IB03
-#define DISP_BITMASK_SE12          DISP_BIT_IB02
-#define DISP_BITMASK_SE11          DISP_BIT_IB01
-#define DISP_BITMASK_SE10          DISP_BIT_IB00
-/* DISP_SCREEN_2_DRV_POS_1_ADDR    Second Screen Driving Position (1) */
-#define DISP_BITMASK_SS28          DISP_BIT_IB08
-#define DISP_BITMASK_SS27          DISP_BIT_IB07
-#define DISP_BITMASK_SS26          DISP_BIT_IB06
-#define DISP_BITMASK_SS25          DISP_BIT_IB05
-#define DISP_BITMASK_SS24          DISP_BIT_IB04
-#define DISP_BITMASK_SS23          DISP_BIT_IB03
-#define DISP_BITMASK_SS22          DISP_BIT_IB02
-#define DISP_BITMASK_SS21          DISP_BIT_IB01
-#define DISP_BITMASK_SS20          DISP_BIT_IB00
-/* DISP_SCREEN_3_DRV_POS_2_ADDR    Second Screen Driving Position (2) */
-#define DISP_BITMASK_SE28          DISP_BIT_IB08
-#define DISP_BITMASK_SE27          DISP_BIT_IB07
-#define DISP_BITMASK_SE26          DISP_BIT_IB06
-#define DISP_BITMASK_SE25          DISP_BIT_IB05
-#define DISP_BITMASK_SE24          DISP_BIT_IB04
-#define DISP_BITMASK_SE23          DISP_BIT_IB03
-#define DISP_BITMASK_SE22          DISP_BIT_IB02
-#define DISP_BITMASK_SE21          DISP_BIT_IB01
-#define DISP_BITMASK_SE20          DISP_BIT_IB00
-/* DISP_HORZ_RAM_ADDR_POS_1_ADDR   Horizontal RAM Address Position (1) */
-#define DISP_BITMASK_HSA7          DISP_BIT_IB07
-#define DISP_BITMASK_HSA6          DISP_BIT_IB06
-#define DISP_BITMASK_HSA5          DISP_BIT_IB05
-#define DISP_BITMASK_HSA4          DISP_BIT_IB04
-#define DISP_BITMASK_HSA3          DISP_BIT_IB03
-#define DISP_BITMASK_HSA2          DISP_BIT_IB02
-#define DISP_BITMASK_HSA1          DISP_BIT_IB01
-#define DISP_BITMASK_HSA0          DISP_BIT_IB00
-/* DISP_HORZ_RAM_ADDR_POS_2_ADDR   Horizontal RAM Address Position (2) */
-#define DISP_BITMASK_HEA7          DISP_BIT_IB07
-#define DISP_BITMASK_HEA6          DISP_BIT_IB06
-#define DISP_BITMASK_HEA5          DISP_BIT_IB05
-#define DISP_BITMASK_HEA4          DISP_BIT_IB04
-#define DISP_BITMASK_HEA3          DISP_BIT_IB03
-#define DISP_BITMASK_HEA2          DISP_BIT_IB02
-#define DISP_BITMASK_HEA1          DISP_BIT_IB01
-#define DISP_BITMASK_HEA0          DISP_BIT_IB00
-/* DISP_VERT_RAM_ADDR_POS_1_ADDR   Vertical RAM Address Position (1) */
-#define DISP_BITMASK_VSA8          DISP_BIT_IB08
-#define DISP_BITMASK_VSA7          DISP_BIT_IB07
-#define DISP_BITMASK_VSA6          DISP_BIT_IB06
-#define DISP_BITMASK_VSA5          DISP_BIT_IB05
-#define DISP_BITMASK_VSA4          DISP_BIT_IB04
-#define DISP_BITMASK_VSA3          DISP_BIT_IB03
-#define DISP_BITMASK_VSA2          DISP_BIT_IB02
-#define DISP_BITMASK_VSA1          DISP_BIT_IB01
-#define DISP_BITMASK_VSA0          DISP_BIT_IB00
-/* DISP_VERT_RAM_ADDR_POS_2_ADDR   Vertical RAM Address Position (2) */
-#define DISP_BITMASK_VEA8          DISP_BIT_IB08
-#define DISP_BITMASK_VEA7          DISP_BIT_IB07
-#define DISP_BITMASK_VEA6          DISP_BIT_IB06
-#define DISP_BITMASK_VEA5          DISP_BIT_IB05
-#define DISP_BITMASK_VEA4          DISP_BIT_IB04
-#define DISP_BITMASK_VEA3          DISP_BIT_IB03
-#define DISP_BITMASK_VEA2          DISP_BIT_IB02
-#define DISP_BITMASK_VEA1          DISP_BIT_IB01
-#define DISP_BITMASK_VEA0          DISP_BIT_IB00
-static word disp_area_start_row;
-static word disp_area_end_row;
-static boolean disp_initialized = FALSE;
-/* For some reason the contrast set at init time is not good. Need to do
-* it again
-*/
-static boolean display_on = FALSE;
-
-static uint32 tmd20qvga_lcd_rev;
-uint16 tmd20qvga_panel_offset;
-
-#ifdef DISP_DEVICE_8BPP
-static word convert_8_to_16_tbl[256] = {
-	0x0000, 0x2000, 0x4000, 0x6000, 0x8000, 0xA000, 0xC000, 0xE000,
-	0x0100, 0x2100, 0x4100, 0x6100, 0x8100, 0xA100, 0xC100, 0xE100,
-	0x0200, 0x2200, 0x4200, 0x6200, 0x8200, 0xA200, 0xC200, 0xE200,
-	0x0300, 0x2300, 0x4300, 0x6300, 0x8300, 0xA300, 0xC300, 0xE300,
-	0x0400, 0x2400, 0x4400, 0x6400, 0x8400, 0xA400, 0xC400, 0xE400,
-	0x0500, 0x2500, 0x4500, 0x6500, 0x8500, 0xA500, 0xC500, 0xE500,
-	0x0600, 0x2600, 0x4600, 0x6600, 0x8600, 0xA600, 0xC600, 0xE600,
-	0x0700, 0x2700, 0x4700, 0x6700, 0x8700, 0xA700, 0xC700, 0xE700,
-	0x0008, 0x2008, 0x4008, 0x6008, 0x8008, 0xA008, 0xC008, 0xE008,
-	0x0108, 0x2108, 0x4108, 0x6108, 0x8108, 0xA108, 0xC108, 0xE108,
-	0x0208, 0x2208, 0x4208, 0x6208, 0x8208, 0xA208, 0xC208, 0xE208,
-	0x0308, 0x2308, 0x4308, 0x6308, 0x8308, 0xA308, 0xC308, 0xE308,
-	0x0408, 0x2408, 0x4408, 0x6408, 0x8408, 0xA408, 0xC408, 0xE408,
-	0x0508, 0x2508, 0x4508, 0x6508, 0x8508, 0xA508, 0xC508, 0xE508,
-	0x0608, 0x2608, 0x4608, 0x6608, 0x8608, 0xA608, 0xC608, 0xE608,
-	0x0708, 0x2708, 0x4708, 0x6708, 0x8708, 0xA708, 0xC708, 0xE708,
-	0x0010, 0x2010, 0x4010, 0x6010, 0x8010, 0xA010, 0xC010, 0xE010,
-	0x0110, 0x2110, 0x4110, 0x6110, 0x8110, 0xA110, 0xC110, 0xE110,
-	0x0210, 0x2210, 0x4210, 0x6210, 0x8210, 0xA210, 0xC210, 0xE210,
-	0x0310, 0x2310, 0x4310, 0x6310, 0x8310, 0xA310, 0xC310, 0xE310,
-	0x0410, 0x2410, 0x4410, 0x6410, 0x8410, 0xA410, 0xC410, 0xE410,
-	0x0510, 0x2510, 0x4510, 0x6510, 0x8510, 0xA510, 0xC510, 0xE510,
-	0x0610, 0x2610, 0x4610, 0x6610, 0x8610, 0xA610, 0xC610, 0xE610,
-	0x0710, 0x2710, 0x4710, 0x6710, 0x8710, 0xA710, 0xC710, 0xE710,
-	0x0018, 0x2018, 0x4018, 0x6018, 0x8018, 0xA018, 0xC018, 0xE018,
-	0x0118, 0x2118, 0x4118, 0x6118, 0x8118, 0xA118, 0xC118, 0xE118,
-	0x0218, 0x2218, 0x4218, 0x6218, 0x8218, 0xA218, 0xC218, 0xE218,
-	0x0318, 0x2318, 0x4318, 0x6318, 0x8318, 0xA318, 0xC318, 0xE318,
-	0x0418, 0x2418, 0x4418, 0x6418, 0x8418, 0xA418, 0xC418, 0xE418,
-	0x0518, 0x2518, 0x4518, 0x6518, 0x8518, 0xA518, 0xC518, 0xE518,
-	0x0618, 0x2618, 0x4618, 0x6618, 0x8618, 0xA618, 0xC618, 0xE618,
-	0x0718, 0x2718, 0x4718, 0x6718, 0x8718, 0xA718, 0xC718, 0xE718
-};
-#endif /* DISP_DEVICE_8BPP */
-
-static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres);
-static void tmd20qvga_disp_init(struct platform_device *pdev);
-static void tmd20qvga_disp_set_contrast(void);
-static void tmd20qvga_disp_set_display_area(word start_row, word end_row);
-static int tmd20qvga_disp_off(struct platform_device *pdev);
-static int tmd20qvga_disp_on(struct platform_device *pdev);
-static void tmd20qvga_set_revId(int);
-
-/* future use */
-void tmd20qvga_disp_clear_screen_area(word start_row, word end_row,
-				      word start_column, word end_column);
-
-static void tmd20qvga_set_revId(int id)
-{
-
-	tmd20qvga_lcd_rev = id;
-
-	if (tmd20qvga_lcd_rev == 1)
-		tmd20qvga_panel_offset = 0x10;
-	else
-		tmd20qvga_panel_offset = 0;
-}
-
-static void tmd20qvga_disp_init(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	if (disp_initialized)
-		return;
-
-	mfd = platform_get_drvdata(pdev);
-
-	DISP_CMD_PORT = mfd->cmd_port;
-	DISP_DATA_PORT = mfd->data_port;
-
-#ifdef TMD20QVGA_LCD_18BPP
-	tmd20qvga_set_revId(2);
-#else
-	tmd20qvga_set_revId(1);
-#endif
-
-	disp_initialized = TRUE;
-	tmd20qvga_disp_set_contrast();
-	tmd20qvga_disp_set_display_area(0, QVGA_HEIGHT - 1);
-}
-
-static void tmd20qvga_disp_set_rect(int x, int y, int xres, int yres)
-{
-	if (!disp_initialized)
-		return;
-
-	DISP_SET_RECT(y, y + yres - 1, x, x + xres - 1);
-
-	DISP_CMD_OUT(DISP_CMD_RAMWR);
-}
-
-static void tmd20qvga_disp_set_display_area(word start_row, word end_row)
-{
-	word start_driving = start_row;
-	word end_driving = end_row;
-
-	if (!disp_initialized)
-		return;
-
-	/* Range checking
-	 */
-	if (end_driving >= QVGA_HEIGHT)
-		end_driving = QVGA_HEIGHT - 1;
-	if (start_driving > end_driving) {
-		/* Probably Backwards Switch */
-		start_driving = end_driving;
-		end_driving = start_row;	/* Has not changed */
-		if (end_driving >= QVGA_HEIGHT)
-			end_driving = QVGA_HEIGHT - 1;
-	}
-
-	if ((start_driving == disp_area_start_row)
-	    && (end_driving == disp_area_end_row))
-		return;
-
-	disp_area_start_row = start_driving;
-	disp_area_end_row = end_driving;
-
-	DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR,
-		       DISP_VAL_IF(start_driving & 0x100,
-				   DISP_BITMASK_SS18) |
-		       DISP_VAL_IF(start_driving & 0x080,
-				   DISP_BITMASK_SS17) |
-		       DISP_VAL_IF(start_driving & 0x040,
-				   DISP_BITMASK_SS16) |
-		       DISP_VAL_IF(start_driving & 0x020,
-				   DISP_BITMASK_SS15) |
-		       DISP_VAL_IF(start_driving & 0x010,
-				   DISP_BITMASK_SS14) |
-		       DISP_VAL_IF(start_driving & 0x008,
-				   DISP_BITMASK_SS13) |
-		       DISP_VAL_IF(start_driving & 0x004,
-				   DISP_BITMASK_SS12) |
-		       DISP_VAL_IF(start_driving & 0x002,
-				   DISP_BITMASK_SS11) |
-		       DISP_VAL_IF(start_driving & 0x001, DISP_BITMASK_SS10));
-
-	DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR,
-			DISP_VAL_IF(end_driving & 0x100, DISP_BITMASK_SE18) |
-			DISP_VAL_IF(end_driving & 0x080, DISP_BITMASK_SE17) |
-			DISP_VAL_IF(end_driving & 0x040, DISP_BITMASK_SE16) |
-			DISP_VAL_IF(end_driving & 0x020, DISP_BITMASK_SE15) |
-			DISP_VAL_IF(end_driving & 0x010, DISP_BITMASK_SE14) |
-			DISP_VAL_IF(end_driving & 0x008, DISP_BITMASK_SE13) |
-			DISP_VAL_IF(end_driving & 0x004, DISP_BITMASK_SE12) |
-			DISP_VAL_IF(end_driving & 0x002, DISP_BITMASK_SE11) |
-			DISP_VAL_IF(end_driving & 0x001, DISP_BITMASK_SE10));
-}
-
-static int tmd20qvga_disp_off(struct platform_device *pdev)
-{
-	if (!disp_initialized)
-		tmd20qvga_disp_init(pdev);
-
-	if (display_on) {
-		if (tmd20qvga_lcd_rev == 2) {
-			DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000A);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFEE);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xF812);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xE811);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC011);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x4011);
-			WAIT_MSEC(20);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0010);
-
-		} else {
-			DISP_WRITE_OUT(DISP_POFF_LN_SETTING_ADDR, 0x000F);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFE);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BED);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(40);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x00CD);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(20);
-			DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0);
-		}
-
-		DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0004);
-		DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0000);
-
-		display_on = FALSE;
-	}
-
-	return 0;
-}
-
-static int tmd20qvga_disp_on(struct platform_device *pdev)
-{
-	if (!disp_initialized)
-		tmd20qvga_disp_init(pdev);
-
-	if (!display_on) {
-		/* Deep Stand-by -> Stand-by */
-		DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
-		WAIT_MSEC(1);
-		DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
-		WAIT_MSEC(1);
-		DISP_CMD_OUT(DISP_START_OSCILLATION_ADDR);
-		WAIT_MSEC(1);
-
-		/* OFF -> Deep Stan-By -> Stand-by */
-		/* let's change the state from "Stand-by" to "Sleep" */
-		DISP_WRITE_OUT(DISP_MODE_SETTING_ADDR, 0x0005);
-		WAIT_MSEC(1);
-
-		/* Sleep -> Displaying */
-		DISP_WRITE_OUT(DISP_START_OSCILLATION_ADDR, 0x0001);
-		DISP_WRITE_OUT(DISP_DRIVER_OUTPUT_CTL_ADDR, 0x0127);
-		DISP_WRITE_OUT(DISP_LCD_DRIVING_SIG_ADDR, 0x200);
-		/* fast write mode */
-		DISP_WRITE_OUT(DISP_ENTRY_MODE_ADDR, 0x0130);
-		if (tmd20qvga_lcd_rev == 2)
-			DISP_WRITE_OUT(DISP_TMD_700_ADDR, 0x0003);
-		/* back porch = 14 + front porch = 2 --> 16 lines */
-		if (tmd20qvga_lcd_rev == 2) {
-#ifdef TMD20QVGA_LCD_18BPP
-			/* 256k color */
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0000);
-#else
-			/* 65k color */
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4000);
-#endif
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x0302);
-		} else {
-#ifdef TMD20QVGA_LCD_18BPP
-			/* 256k color */
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x0004);
-#else
-			/* 65k color */
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_1_ADDR, 0x4004);
-#endif
-			DISP_WRITE_OUT(DISP_DISPLAY_CTL_2_ADDR, 0x020E);
-		}
-		/* 16 bit one transfer */
-		if (tmd20qvga_lcd_rev == 2) {
-			DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0302);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0102);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_TMD_015_ADDR, 0x2000);
-
-			DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0304);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0101);
-			DISP_WRITE_OUT(DISP_TMD_305_ADDR, 0);
-
-			DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x077D);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0005);
-			DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0015);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xC010);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x0001);
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0xFFFE);
-			WAIT_MSEC(60);
-		} else {
-			DISP_WRITE_OUT(DISP_EXT_DISPLAY_CTL_1_ADDR, 0x0001);
-			DISP_WRITE_OUT(DISP_FRAME_CYCLE_CTL_ADDR, 0x0010);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_1_ADDR, 0x0301);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_2_ADDR, 0x0001);
-			DISP_WRITE_OUT(DISP_LTPS_CTL_3_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_AMP_SETTING_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0507);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0405);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0607);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0502);
-			DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0301);
-			DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_1_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_SCREEN_1_DRV_POS_2_ADDR, 0x013F);
-			DISP_WRITE_OUT(DISP_POWER_CTL_3_ADDR, 0x0795);
-
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0102);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_4_ADDR, 0x0450);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0103);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_5_ADDR, 0x0008);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0104);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_6_ADDR, 0x0C00);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0105);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_7_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0106);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0801);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(1);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x001F);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101);
-			WAIT_MSEC(60);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_2_ADDR, 0x009F);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0101);
-			WAIT_MSEC(10);
-
-			DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_1_ADDR, 0x0010);
-			DISP_WRITE_OUT(DISP_HORZ_RAM_ADDR_POS_2_ADDR, 0x00FF);
-			DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_1_ADDR, 0x0000);
-			DISP_WRITE_OUT(DISP_VERT_RAM_ADDR_POS_2_ADDR, 0x013F);
-			/* RAM starts at address 0x10 */
-			DISP_WRITE_OUT(DISP_RAM_ADDR_SET_1_ADDR, 0x0010);
-			DISP_WRITE_OUT(DISP_RAM_ADDR_SET_2_ADDR, 0x0000);
-
-			/* lcd controller uses internal clock, not ext. vsync */
-			DISP_CMD_OUT(DISP_CMD_RAMWR);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0881);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(40);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BE1);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-			WAIT_MSEC(40);
-
-			DISP_WRITE_OUT(DISP_POWER_CTL_1_ADDR, 0x0BFF);
-			DISP_WRITE_OUT(DISP_POWER_SUPPLY_INTF_ADDR, 0x0100);
-		}
-		display_on = TRUE;
-	}
-
-	return 0;
-}
-
-static void tmd20qvga_disp_set_contrast(void)
-{
-#if (defined(TMD20QVGA_LCD_18BPP))
-
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR, 0x0302);
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR, 0x0403);
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07);
-
-#else
-	int newcontrast = 0x46;
-
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_1_ADDR, 0x0403);
-
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_2_ADDR,
-			DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP20) |
-			DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP21) |
-			DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP22) |
-			DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP30) |
-			DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP31) |
-			DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP32));
-
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_3_ADDR,
-			DISP_VAL_IF(newcontrast & 0x0010, DISP_BITMASK_PKP40) |
-			DISP_VAL_IF(newcontrast & 0x0020, DISP_BITMASK_PKP41) |
-			DISP_VAL_IF(newcontrast & 0x0040, DISP_BITMASK_PKP42) |
-			DISP_VAL_IF(newcontrast & 0x0001, DISP_BITMASK_PKP50) |
-			DISP_VAL_IF(newcontrast & 0x0002, DISP_BITMASK_PKP51) |
-			DISP_VAL_IF(newcontrast & 0x0004, DISP_BITMASK_PKP52));
-
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_4_ADDR, 0x0303);
-	DISP_WRITE_OUT(DISP_GAMMA_CONTROL_5_ADDR, 0x0F07);
-
-#endif /* defined(TMD20QVGA_LCD_18BPP) */
-
-}	/* End disp_set_contrast */
-
-void tmd20qvga_disp_clear_screen_area
-    (word start_row, word end_row, word start_column, word end_column) {
-	int32 i;
-
-	/* Clear the display screen */
-	DISP_SET_RECT(start_row, end_row, start_column, end_column);
-	DISP_CMD_OUT(DISP_CMD_RAMWR);
-	i = (end_row - start_row + 1) * (end_column - start_column + 1);
-	for (; i > 0; i--)
-		DISP_DATA_OUT_16TO18BPP(0x0);
-}
-
-static int __init tmd20qvga_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = tmd20qvga_probe,
-	.driver = {
-		.name   = "ebi2_tmd_qvga",
-	},
-};
-
-static struct msm_fb_panel_data tmd20qvga_panel_data = {
-	.on = tmd20qvga_disp_on,
-	.off = tmd20qvga_disp_off,
-	.set_rect = tmd20qvga_disp_set_rect,
-};
-
-static struct platform_device this_device = {
-	.name   = "ebi2_tmd_qvga",
-	.id	= 0,
-	.dev	= {
-		.platform_data = &tmd20qvga_panel_data,
-	}
-};
-
-static int __init tmd20qvga_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &tmd20qvga_panel_data.panel_info;
-		pinfo->xres = 240;
-		pinfo->yres = 320;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = EBI2_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->wait_cycle = 0x808000;
-#ifdef TMD20QVGA_LCD_18BPP
-		pinfo->bpp = 18;
-#else
-		pinfo->bpp = 16;
-#endif
-		pinfo->fb_num = 2;
-		pinfo->lcd.vsync_enable = TRUE;
-		pinfo->lcd.refx100 = 6000;
-		pinfo->lcd.v_back_porch = 16;
-		pinfo->lcd.v_front_porch = 4;
-		pinfo->lcd.v_pulse_width = 0;
-		pinfo->lcd.hw_vsync_mode = FALSE;
-		pinfo->lcd.vsync_notifier_period = 0;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-
-	return ret;
-}
-
-module_init(tmd20qvga_init);
-
diff --git a/drivers/video/msm/external_common.c b/drivers/video/msm/external_common.c
deleted file mode 100644
index 7aeca6e..0000000
--- a/drivers/video/msm/external_common.c
+++ /dev/null
@@ -1,2269 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/mutex.h>
-
-/* #define DEBUG */
-#define DEV_DBG_PREFIX "EXT_COMMON: "
-
-/* The start of the data block collection within the CEA Extension Version 3 */
-#define DBC_START_OFFSET 4
-
-#include "msm_fb.h"
-#include "hdmi_msm.h"
-#include "external_common.h"
-#include "mhl_api.h"
-
-#include "mdp.h"
-
-struct external_common_state_type *external_common_state;
-EXPORT_SYMBOL(external_common_state);
-DEFINE_MUTEX(external_common_state_hpd_mutex);
-EXPORT_SYMBOL(external_common_state_hpd_mutex);
-
-
-static int atoi(const char *name)
-{
-	int val = 0;
-
-	for (;; name++) {
-		switch (*name) {
-		case '0' ... '9':
-			val = 10*val+(*name-'0');
-			break;
-		default:
-			return val;
-		}
-	}
-}
-
-#ifdef DEBUG_EDID
-/*
- * Block 0 - 1920x1080p, 1360x768p
- * Block 1 - 1280x720p, 1920x540i, 720x480p
- */
-const char edid_blk0[0x100] = {
-0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x4C, 0x2D, 0x03, 0x05, 0x00,
-0x00, 0x00, 0x00, 0x30, 0x12, 0x01, 0x03, 0x80, 0x10, 0x09, 0x78, 0x0A, 0xEE,
-0x91, 0xA3, 0x54, 0x4C, 0x99, 0x26, 0x0F, 0x50, 0x54, 0xBD, 0xEF, 0x80, 0x71,
-0x4F, 0x81, 0x00, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0x95, 0x0F, 0xB3, 0x00,
-0xA9, 0x40, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45,
-0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x66, 0x21, 0x50, 0xB0, 0x51, 0x00,
-0x1B, 0x30, 0x40, 0x70, 0x36, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x00,
-0x00, 0x00, 0xFD, 0x00, 0x18, 0x4B, 0x1A, 0x51, 0x17, 0x00, 0x0A, 0x20, 0x20,
-0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x53, 0x41, 0x4D, 0x53,
-0x55, 0x4E, 0x47, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x8F};
-
-const char edid_blk1[0x100] = {
-0x02, 0x03, 0x1E, 0xF1, 0x46, 0x90, 0x04, 0x05, 0x03, 0x20, 0x22, 0x23, 0x09,
-0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0xE2, 0x00, 0x0F, 0x67, 0x03, 0x0C, 0x00,
-0x10, 0x00, 0xB8, 0x2D, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E,
-0x28, 0x55, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x80, 0x18,
-0x71, 0x1C, 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xA0, 0x5A, 0x00, 0x00, 0x00,
-0x9E, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00,
-0xA0, 0x5A, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDF};
-#endif /* DEBUG_EDID */
-
-#define DMA_E_BASE 0xB0000
-void mdp_vid_quant_set(void)
-{
-	if ((external_common_state->video_resolution == \
-		HDMI_VFRMT_720x480p60_4_3) || \
-		(external_common_state->video_resolution == \
-		HDMI_VFRMT_720x480p60_16_9)) {
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00EB0010);
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00EB0010);
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00EB0010);
-	} else {
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x70, 0x00FF0000);
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x74, 0x00FF0000);
-		MDP_OUTP(MDP_BASE + DMA_E_BASE + 0x78, 0x00FF0000);
-	}
-}
-
-const char *video_format_2string(uint32 format)
-{
-	switch (format) {
-	default:
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-	case HDMI_VFRMT_640x480p60_4_3:    return " 640x 480 p60  4/3";
-	case HDMI_VFRMT_720x480p60_4_3:    return " 720x 480 p60  4/3";
-	case HDMI_VFRMT_720x480p60_16_9:   return " 720x 480 p60 16/9";
-	case HDMI_VFRMT_1280x720p60_16_9:  return "1280x 720 p60 16/9";
-	case HDMI_VFRMT_1920x1080i60_16_9: return "1920x1080 i60 16/9";
-	case HDMI_VFRMT_1440x480i60_4_3:   return "1440x 480 i60  4/3";
-	case HDMI_VFRMT_1440x480i60_16_9:  return "1440x 480 i60 16/9";
-	case HDMI_VFRMT_1440x240p60_4_3:   return "1440x 240 p60  4/3";
-	case HDMI_VFRMT_1440x240p60_16_9:  return "1440x 240 p60 16/9";
-	case HDMI_VFRMT_2880x480i60_4_3:   return "2880x 480 i60  4/3";
-	case HDMI_VFRMT_2880x480i60_16_9:  return "2880x 480 i60 16/9";
-	case HDMI_VFRMT_2880x240p60_4_3:   return "2880x 240 p60  4/3";
-	case HDMI_VFRMT_2880x240p60_16_9:  return "2880x 240 p60 16/9";
-	case HDMI_VFRMT_1440x480p60_4_3:   return "1440x 480 p60  4/3";
-	case HDMI_VFRMT_1440x480p60_16_9:  return "1440x 480 p60 16/9";
-	case HDMI_VFRMT_1920x1080p60_16_9: return "1920x1080 p60 16/9";
-	case HDMI_VFRMT_720x576p50_4_3:    return " 720x 576 p50  4/3";
-	case HDMI_VFRMT_720x576p50_16_9:   return " 720x 576 p50 16/9";
-	case HDMI_VFRMT_1280x720p50_16_9:  return "1280x 720 p50 16/9";
-	case HDMI_VFRMT_1920x1080i50_16_9: return "1920x1080 i50 16/9";
-	case HDMI_VFRMT_1440x576i50_4_3:   return "1440x 576 i50  4/3";
-	case HDMI_VFRMT_1440x576i50_16_9:  return "1440x 576 i50 16/9";
-	case HDMI_VFRMT_1440x288p50_4_3:   return "1440x 288 p50  4/3";
-	case HDMI_VFRMT_1440x288p50_16_9:  return "1440x 288 p50 16/9";
-	case HDMI_VFRMT_2880x576i50_4_3:   return "2880x 576 i50  4/3";
-	case HDMI_VFRMT_2880x576i50_16_9:  return "2880x 576 i50 16/9";
-	case HDMI_VFRMT_2880x288p50_4_3:   return "2880x 288 p50  4/3";
-	case HDMI_VFRMT_2880x288p50_16_9:  return "2880x 288 p50 16/9";
-	case HDMI_VFRMT_1440x576p50_4_3:   return "1440x 576 p50  4/3";
-	case HDMI_VFRMT_1440x576p50_16_9:  return "1440x 576 p50 16/9";
-	case HDMI_VFRMT_1920x1080p50_16_9: return "1920x1080 p50 16/9";
-	case HDMI_VFRMT_1920x1080p24_16_9: return "1920x1080 p24 16/9";
-	case HDMI_VFRMT_1920x1080p25_16_9: return "1920x1080 p25 16/9";
-	case HDMI_VFRMT_1920x1080p30_16_9: return "1920x1080 p30 16/9";
-	case HDMI_VFRMT_2880x480p60_4_3:   return "2880x 480 p60  4/3";
-	case HDMI_VFRMT_2880x480p60_16_9:  return "2880x 480 p60 16/9";
-	case HDMI_VFRMT_2880x576p50_4_3:   return "2880x 576 p50  4/3";
-	case HDMI_VFRMT_2880x576p50_16_9:  return "2880x 576 p50 16/9";
-	case HDMI_VFRMT_1920x1250i50_16_9: return "1920x1250 i50 16/9";
-	case HDMI_VFRMT_1920x1080i100_16_9:return "1920x1080 i100 16/9";
-	case HDMI_VFRMT_1280x720p100_16_9: return "1280x 720 p100 16/9";
-	case HDMI_VFRMT_720x576p100_4_3:   return " 720x 576 p100  4/3";
-	case HDMI_VFRMT_720x576p100_16_9:  return " 720x 576 p100 16/9";
-	case HDMI_VFRMT_1440x576i100_4_3:  return "1440x 576 i100  4/3";
-	case HDMI_VFRMT_1440x576i100_16_9: return "1440x 576 i100 16/9";
-	case HDMI_VFRMT_1920x1080i120_16_9:return "1920x1080 i120 16/9";
-	case HDMI_VFRMT_1280x720p120_16_9: return "1280x 720 p120 16/9";
-	case HDMI_VFRMT_720x480p120_4_3:   return " 720x 480 p120  4/3";
-	case HDMI_VFRMT_720x480p120_16_9:  return " 720x 480 p120 16/9";
-	case HDMI_VFRMT_1440x480i120_4_3:  return "1440x 480 i120  4/3";
-	case HDMI_VFRMT_1440x480i120_16_9: return "1440x 480 i120 16/9";
-	case HDMI_VFRMT_720x576p200_4_3:   return " 720x 576 p200  4/3";
-	case HDMI_VFRMT_720x576p200_16_9:  return " 720x 576 p200 16/9";
-	case HDMI_VFRMT_1440x576i200_4_3:  return "1440x 576 i200  4/3";
-	case HDMI_VFRMT_1440x576i200_16_9: return "1440x 576 i200 16/9";
-	case HDMI_VFRMT_720x480p240_4_3:   return " 720x 480 p240  4/3";
-	case HDMI_VFRMT_720x480p240_16_9:  return " 720x 480 p240 16/9";
-	case HDMI_VFRMT_1440x480i240_4_3:  return "1440x 480 i240  4/3";
-	case HDMI_VFRMT_1440x480i240_16_9: return "1440x 480 i240 16/9";
-#elif defined(CONFIG_FB_MSM_TVOUT)
-	case TVOUT_VFRMT_NTSC_M_720x480i:     return "NTSC_M_720x480i";
-	case TVOUT_VFRMT_NTSC_J_720x480i:     return "NTSC_J_720x480i";
-	case TVOUT_VFRMT_PAL_BDGHIN_720x576i: return "PAL_BDGHIN_720x576i";
-	case TVOUT_VFRMT_PAL_M_720x480i:      return "PAL_M_720x480i";
-	case TVOUT_VFRMT_PAL_N_720x480i:      return "PAL_N_720x480i";
-#endif
-
-	}
-}
-EXPORT_SYMBOL(video_format_2string);
-
-static ssize_t external_common_rda_video_mode_str(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n",
-		video_format_2string(external_common_state->video_resolution));
-	DEV_DBG("%s: '%s'\n", __func__,
-		video_format_2string(external_common_state->video_resolution));
-	return ret;
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-struct hdmi_disp_mode_timing_type
-	hdmi_common_supported_video_mode_lut[HDMI_VFRMT_MAX] = {
-	HDMI_SETTINGS_640x480p60_4_3,
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p24_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p25_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p30_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1250i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x1024p60_5_4)
-};
-EXPORT_SYMBOL(hdmi_common_supported_video_mode_lut);
-
-struct hdmi_disp_mode_timing_type
-	hdmi_mhl_supported_video_mode_lut[HDMI_VFRMT_MAX] = {
-	HDMI_SETTINGS_640x480p60_4_3,
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p60_16_9),
-	HDMI_SETTINGS_1280x720p60_16_9,
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x240p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480i60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x240p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x288p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x288p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080p50_16_9),
-	HDMI_SETTINGS_1920x1080p24_16_9,
-	HDMI_SETTINGS_1920x1080p25_16_9,
-	HDMI_SETTINGS_1920x1080p30_16_9,
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x480p60_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_2880x576p50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1250i50_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i100_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1920x1080i120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1280x720p120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i120_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x576p200_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x576i200_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_720x480p240_16_9),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_4_3),
-	VFRMT_NOT_SUPPORTED(HDMI_VFRMT_1440x480i240_16_9),
-	HDMI_SETTINGS_1280x1024p60_5_4
-};
-EXPORT_SYMBOL(hdmi_mhl_supported_video_mode_lut);
-
-static ssize_t hdmi_common_rda_edid_modes(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = 0;
-	int i;
-
-	buf[0] = 0;
-	if (external_common_state->disp_mode_list.num_of_elements) {
-		uint32 *video_mode = external_common_state->disp_mode_list
-			.disp_mode_list;
-		for (i = 0; i < external_common_state->disp_mode_list
-			.num_of_elements; ++i) {
-			if (ret > 0)
-				ret += snprintf(buf+ret, PAGE_SIZE-ret, ",%d",
-					*video_mode++ + 1);
-			else
-				ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
-					*video_mode++ + 1);
-		}
-	} else
-		ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
-			external_common_state->video_resolution+1);
-
-	DEV_DBG("%s: '%s'\n", __func__, buf);
-	ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_edid_physical_address(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->physical_address);
-
-	DEV_DBG("%s: '%d'\n", __func__,
-			external_common_state->physical_address);
-	return ret;
-}
-
-
-static ssize_t hdmi_common_rda_edid_scan_info(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d, %d, %d\n",
-		external_common_state->pt_scan_info,
-		external_common_state->it_scan_info,
-		external_common_state->ce_scan_info);
-	DEV_DBG("%s: '%s'\n", __func__, buf);
-	return ret;
-}
-
-static ssize_t hdmi_common_wta_vendor_name(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	uint8 *s = (uint8 *) buf;
-	uint8 *d = external_common_state->spd_vendor_name;
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	ret = (ret > 8) ? 8 : ret;
-
-	memset(external_common_state->spd_vendor_name, 0, 8);
-	while (*s) {
-		if (*s & 0x60 && *s ^ 0x7f) {
-			*d = *s;
-		} else {
-			/* stop copying if control character found */
-			break;
-		}
-
-		if (++s > (uint8 *) (buf + ret))
-			break;
-
-		d++;
-	}
-
-	DEV_DBG("%s: '%s'\n", __func__,
-			external_common_state->spd_vendor_name);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_vendor_name(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n",
-		external_common_state->spd_vendor_name);
-	DEV_DBG("%s: '%s'\n", __func__,
-			external_common_state->spd_vendor_name);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_wta_product_description(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	uint8 *s = (uint8 *) buf;
-	uint8 *d = external_common_state->spd_product_description;
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	ret = (ret > 16) ? 16 : ret;
-
-	memset(external_common_state->spd_product_description, 0, 16);
-	while (*s) {
-		if (*s & 0x60 && *s ^ 0x7f) {
-			*d = *s;
-		} else {
-			/* stop copying if control character found */
-			break;
-		}
-
-		if (++s > (uint8 *) (buf + ret))
-			break;
-
-		d++;
-	}
-
-	DEV_DBG("%s: '%s'\n", __func__,
-			external_common_state->spd_product_description);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_product_description(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%s\n",
-		external_common_state->spd_product_description);
-	DEV_DBG("%s: '%s'\n", __func__,
-			external_common_state->spd_product_description);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_edid_3d_modes(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = 0;
-	int i;
-	char buff_3d[128];
-
-	buf[0] = 0;
-	if (external_common_state->disp_mode_list.num_of_elements) {
-		uint32 *video_mode = external_common_state->disp_mode_list
-			.disp_mode_list;
-		uint32 *video_3d_mode = external_common_state->disp_mode_list
-			.disp_3d_mode_list;
-		for (i = 0; i < external_common_state->disp_mode_list
-			.num_of_elements; ++i) {
-			video_3d_format_2string(*video_3d_mode++, buff_3d);
-			if (ret > 0)
-				ret += snprintf(buf+ret, PAGE_SIZE-ret,
-					",%d=%s",
-					*video_mode++ + 1, buff_3d);
-			else
-				ret += snprintf(buf+ret, PAGE_SIZE-ret,
-					"%d=%s",
-					*video_mode++ + 1, buff_3d);
-		}
-	} else
-		ret += snprintf(buf+ret, PAGE_SIZE-ret, "%d",
-			external_common_state->video_resolution+1);
-
-	DEV_DBG("%s: '%s'\n", __func__, buf);
-	ret += snprintf(buf+ret, PAGE_SIZE-ret, "\n");
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_hdcp(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->hdcp_active);
-	DEV_DBG("%s: '%d'\n", __func__,
-		external_common_state->hdcp_active);
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_hpd(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret;
-	if (external_common_state->hpd_feature) {
-		ret = snprintf(buf, PAGE_SIZE, "%d\n",
-			external_common_state->hpd_feature_on);
-		DEV_DBG("%s: '%d'\n", __func__,
-			external_common_state->hpd_feature_on);
-	} else {
-		ret = snprintf(buf, PAGE_SIZE, "-1\n");
-		DEV_DBG("%s: 'not supported'\n", __func__);
-	}
-	return ret;
-}
-
-static ssize_t hdmi_common_wta_hpd(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	int hpd;
-	if (hdmi_prim_display)
-		hpd = 1;
-	else
-		hpd = atoi(buf);
-
-	if (external_common_state->hpd_feature) {
-		if (hpd == 0 && external_common_state->hpd_feature_on) {
-			external_common_state->hpd_feature(0);
-			external_common_state->hpd_feature_on = 0;
-			DEV_DBG("%s: '%d'\n", __func__,
-				external_common_state->hpd_feature_on);
-		} else if (hpd == 1 && !external_common_state->hpd_feature_on) {
-			external_common_state->hpd_feature(1);
-			external_common_state->hpd_feature_on = 1;
-			DEV_DBG("%s: '%d'\n", __func__,
-				external_common_state->hpd_feature_on);
-		} else {
-			DEV_DBG("%s: '%d' (unchanged)\n", __func__,
-				external_common_state->hpd_feature_on);
-		}
-	} else {
-		DEV_DBG("%s: 'not supported'\n", __func__);
-	}
-
-	return ret;
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-/*
- * This interface for CEC feature is defined to suit
- * the current requirements. However, the actual functionality is
- * added to accommodate different interfaces
- */
-static ssize_t hdmi_msm_rda_cec(struct device *dev,
-				 struct device_attribute *attr, char *buf)
-{
-	/* 0x028C CEC_CTRL */
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		(HDMI_INP(0x028C) & BIT(0)));
-	return ret;
-}
-
-static ssize_t hdmi_msm_wta_cec(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	int cec = atoi(buf);
-
-	if (cec != 0) {
-		mutex_lock(&hdmi_msm_state_mutex);
-		hdmi_msm_state->cec_enabled = true;
-		hdmi_msm_state->cec_logical_addr = 4;
-
-		/* flush CEC queue */
-		hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
-		hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
-		hdmi_msm_state->cec_queue_full = false;
-		memset(hdmi_msm_state->cec_queue_rd, 0,
-			sizeof(struct hdmi_msm_cec_msg)*CEC_QUEUE_SIZE);
-
-		mutex_unlock(&hdmi_msm_state_mutex);
-		hdmi_msm_cec_init();
-		hdmi_msm_cec_write_logical_addr(
-			hdmi_msm_state->cec_logical_addr);
-		DEV_DBG("CEC enabled\n");
-	} else {
-		mutex_lock(&hdmi_msm_state_mutex);
-		hdmi_msm_state->cec_enabled = false;
-		hdmi_msm_state->cec_logical_addr = 15;
-		mutex_unlock(&hdmi_msm_state_mutex);
-		hdmi_msm_cec_write_logical_addr(
-			hdmi_msm_state->cec_logical_addr);
-		/* 0x028C CEC_CTRL */
-		HDMI_OUTP(0x028C, 0);
-		DEV_DBG("CEC disabled\n");
-	}
-	return ret;
-}
-
-static ssize_t hdmi_msm_rda_cec_logical_addr(struct device *dev,
-				 struct device_attribute *attr, char *buf)
-{
-	ssize_t ret;
-
-	mutex_lock(&hdmi_msm_state_mutex);
-	ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		hdmi_msm_state->cec_logical_addr);
-	mutex_unlock(&hdmi_msm_state_mutex);
-	return ret;
-}
-
-static ssize_t hdmi_msm_wta_cec_logical_addr(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-
-#ifdef DRVR_ONLY_CECT_NO_DAEMON
-	/*
-	 * Only for testing
-	 */
-	hdmi_msm_cec_one_touch_play();
-	return 0;
-#else
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	int logical_addr = atoi(buf);
-
-	if (logical_addr < 0 || logical_addr > 15)
-		return -EINVAL;
-
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->cec_logical_addr = logical_addr;
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	hdmi_msm_cec_write_logical_addr(logical_addr);
-
-	return ret;
-#endif
-}
-
-static ssize_t hdmi_msm_rda_cec_frame(struct device *dev,
-				 struct device_attribute *attr, char *buf)
-{
-	mutex_lock(&hdmi_msm_state_mutex);
-	if (hdmi_msm_state->cec_queue_rd == hdmi_msm_state->cec_queue_wr
-	    && !hdmi_msm_state->cec_queue_full) {
-		mutex_unlock(&hdmi_msm_state_mutex);
-		DEV_ERR("CEC message queue is empty\n");
-		return -EBUSY;
-	}
-	memcpy(buf, hdmi_msm_state->cec_queue_rd++,
-		sizeof(struct hdmi_msm_cec_msg));
-	hdmi_msm_state->cec_queue_full = false;
-	if (hdmi_msm_state->cec_queue_rd == CEC_QUEUE_END)
-		hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	return sizeof(struct hdmi_msm_cec_msg);
-}
-
-static ssize_t hdmi_msm_wta_cec_frame(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	int i;
-	int retry = ((struct hdmi_msm_cec_msg *) buf)->retransmit;
-
-	for (i = 0; i < RETRANSMIT_MAX_NUM; i++) {
-		hdmi_msm_cec_msg_send((struct hdmi_msm_cec_msg *) buf);
-		if (hdmi_msm_state->cec_frame_wr_status
-		    & CEC_STATUS_WR_ERROR && retry--) {
-			mutex_lock(&hdmi_msm_state_mutex);
-			if (hdmi_msm_state->fsm_reset_done)
-				retry++;
-			mutex_unlock(&hdmi_msm_state_mutex);
-			msleep(20);
-		} else
-			break;
-	}
-
-	if (hdmi_msm_state->cec_frame_wr_status & CEC_STATUS_WR_DONE)
-		return sizeof(struct hdmi_msm_cec_msg);
-	else
-		return -EINVAL;
-}
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-static ssize_t hdmi_common_rda_3d_present(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->present_3d);
-	DEV_DBG("%s: '%d'\n", __func__,
-			external_common_state->present_3d);
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_hdcp_present(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->present_hdcp);
-	DEV_DBG("%s: '%d'\n", __func__,
-			external_common_state->present_hdcp);
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_FB_MSM_HDMI_3D
-static ssize_t hdmi_3d_rda_format_3d(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->format_3d);
-	DEV_DBG("%s: '%d'\n", __func__,
-		external_common_state->format_3d);
-	return ret;
-}
-
-static ssize_t hdmi_3d_wta_format_3d(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	int format_3d = atoi(buf);
-
-	if (format_3d >= 0 && format_3d <= 2) {
-		if (format_3d != external_common_state->format_3d) {
-			external_common_state->format_3d = format_3d;
-			if (external_common_state->switch_3d)
-				external_common_state->switch_3d(format_3d);
-			DEV_DBG("%s: '%d'\n", __func__,
-				external_common_state->format_3d);
-		} else {
-			DEV_DBG("%s: '%d' (unchanged)\n", __func__,
-				external_common_state->format_3d);
-		}
-	} else {
-		DEV_DBG("%s: '%d' (unknown)\n", __func__, format_3d);
-	}
-
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-static DEVICE_ATTR(cec, S_IRUGO | S_IWUSR,
-	hdmi_msm_rda_cec,
-	hdmi_msm_wta_cec);
-
-static DEVICE_ATTR(cec_logical_addr, S_IRUGO | S_IWUSR,
-	hdmi_msm_rda_cec_logical_addr,
-	hdmi_msm_wta_cec_logical_addr);
-
-static DEVICE_ATTR(cec_rd_frame, S_IRUGO,
-	hdmi_msm_rda_cec_frame,	NULL);
-
-static DEVICE_ATTR(cec_wr_frame, S_IWUSR,
-	NULL, hdmi_msm_wta_cec_frame);
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-
-static ssize_t external_common_rda_video_mode(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->video_resolution+1);
-	DEV_DBG("%s: '%d'\n", __func__,
-			external_common_state->video_resolution+1);
-	return ret;
-}
-
-static ssize_t external_common_wta_video_mode(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	uint32 video_mode;
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-	const struct hdmi_disp_mode_timing_type *disp_mode;
-#endif
-	mutex_lock(&external_common_state_hpd_mutex);
-	if (!external_common_state->hpd_state) {
-		mutex_unlock(&external_common_state_hpd_mutex);
-		DEV_INFO("%s: FAILED: display off or cable disconnected\n",
-			__func__);
-		return ret;
-	}
-	mutex_unlock(&external_common_state_hpd_mutex);
-
-	video_mode = atoi(buf)-1;
-	DEV_INFO("%s: video_mode is %d\n", __func__, video_mode);
-	kobject_uevent(external_common_state->uevent_kobj, KOBJ_OFFLINE);
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-	disp_mode = hdmi_common_get_supported_mode(video_mode);
-	if (!disp_mode) {
-		DEV_INFO("%s: FAILED: mode not supported (%d)\n",
-			__func__, video_mode);
-		return ret;
-	}
-	external_common_state->disp_mode_list.num_of_elements = 1;
-	external_common_state->disp_mode_list.disp_mode_list[0] = video_mode;
-#elif defined(CONFIG_FB_MSM_TVOUT)
-	external_common_state->video_resolution = video_mode;
-#endif
-	DEV_DBG("%s: 'mode=%d %s' successful (sending OFF/ONLINE)\n", __func__,
-		video_mode, video_format_2string(video_mode));
-	kobject_uevent(external_common_state->uevent_kobj, KOBJ_ONLINE);
-	return ret;
-}
-
-static ssize_t external_common_rda_connected(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret;
-	mutex_lock(&external_common_state_hpd_mutex);
-	ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->hpd_state);
-	DEV_DBG("%s: '%d'\n", __func__,
-		external_common_state->hpd_state);
-	mutex_unlock(&external_common_state_hpd_mutex);
-	return ret;
-}
-
-static ssize_t external_common_rda_hdmi_mode(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret;
-
-	ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		external_common_state->hdmi_sink);
-
-	DEV_DBG("%s: '%d'\n", __func__,
-		external_common_state->hdmi_sink);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_hdmi_primary(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "%d\n",
-		hdmi_prim_display);
-	DEV_DBG("%s: '%d'\n", __func__,	hdmi_prim_display);
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_audio_data_block(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	int adb_size	= 0;
-	int adb_count	= 0;
-	ssize_t ret	= 0;
-	char *data	= buf;
-
-	if (!external_common_state)
-		return 0;
-
-	adb_count = 1;
-	adb_size  = external_common_state->adb_size;
-	ret       = sizeof(adb_count) + sizeof(adb_size) + adb_size;
-
-	if (ret > PAGE_SIZE) {
-		DEV_DBG("%s: Insufficient buffer size\n", __func__);
-		return 0;
-	}
-
-	/* Currently only extracting one audio data block */
-	memcpy(data, &adb_count, sizeof(adb_count));
-	data += sizeof(adb_count);
-	memcpy(data, &adb_size, sizeof(adb_size));
-	data += sizeof(adb_size);
-	memcpy(data, external_common_state->audio_data_block,
-			external_common_state->adb_size);
-
-	print_hex_dump(KERN_DEBUG, "AUDIO DATA BLOCK: ", DUMP_PREFIX_NONE,
-			32, 8, buf, ret, false);
-
-	return ret;
-}
-
-static ssize_t hdmi_common_rda_spkr_alloc_data_block(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	int sadb_size	= 0;
-	int sadb_count	= 0;
-	ssize_t ret	= 0;
-	char *data	= buf;
-
-	if (!external_common_state)
-		return 0;
-
-	sadb_count = 1;
-	sadb_size  = external_common_state->sadb_size;
-	ret        = sizeof(sadb_count) + sizeof(sadb_size) + sadb_size;
-
-	if (ret > PAGE_SIZE) {
-		DEV_DBG("%s: Insufficient buffer size\n", __func__);
-		return 0;
-	}
-
-	/* Currently only extracting one speaker allocation data block */
-	memcpy(data, &sadb_count, sizeof(sadb_count));
-	data += sizeof(sadb_count);
-	memcpy(data, &sadb_size, sizeof(sadb_size));
-	data += sizeof(sadb_size);
-	memcpy(data, external_common_state->spkr_alloc_data_block,
-			external_common_state->sadb_size);
-
-	print_hex_dump(KERN_DEBUG, "SPKR ALLOC DATA BLOCK: ", DUMP_PREFIX_NONE,
-			32, 8, buf, ret, false);
-
-	return ret;
-}
-
-static DEVICE_ATTR(video_mode, S_IRUGO | S_IWUGO,
-	external_common_rda_video_mode, external_common_wta_video_mode);
-static DEVICE_ATTR(video_mode_str, S_IRUGO, external_common_rda_video_mode_str,
-	NULL);
-static DEVICE_ATTR(connected, S_IRUGO, external_common_rda_connected, NULL);
-static DEVICE_ATTR(hdmi_mode, S_IRUGO, external_common_rda_hdmi_mode, NULL);
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-static DEVICE_ATTR(edid_modes, S_IRUGO, hdmi_common_rda_edid_modes, NULL);
-static DEVICE_ATTR(hpd, S_IRUGO | S_IWUGO, hdmi_common_rda_hpd,
-	hdmi_common_wta_hpd);
-static DEVICE_ATTR(hdcp, S_IRUGO, hdmi_common_rda_hdcp, NULL);
-static DEVICE_ATTR(pa, S_IRUGO,
-	hdmi_common_rda_edid_physical_address, NULL);
-static DEVICE_ATTR(scan_info, S_IRUGO,
-	hdmi_common_rda_edid_scan_info, NULL);
-static DEVICE_ATTR(vendor_name, S_IRUGO | S_IWUSR, hdmi_common_rda_vendor_name,
-	hdmi_common_wta_vendor_name);
-static DEVICE_ATTR(product_description, S_IRUGO | S_IWUSR,
-	hdmi_common_rda_product_description,
-	hdmi_common_wta_product_description);
-static DEVICE_ATTR(edid_3d_modes, S_IRUGO,
-	hdmi_common_rda_edid_3d_modes, NULL);
-static DEVICE_ATTR(3d_present, S_IRUGO, hdmi_common_rda_3d_present, NULL);
-static DEVICE_ATTR(hdcp_present, S_IRUGO, hdmi_common_rda_hdcp_present, NULL);
-#endif
-#ifdef CONFIG_FB_MSM_HDMI_3D
-static DEVICE_ATTR(format_3d, S_IRUGO | S_IWUGO, hdmi_3d_rda_format_3d,
-	hdmi_3d_wta_format_3d);
-#endif
-static DEVICE_ATTR(hdmi_primary, S_IRUGO, hdmi_common_rda_hdmi_primary, NULL);
-static DEVICE_ATTR(audio_data_block, S_IRUGO, hdmi_common_rda_audio_data_block,
-	NULL);
-static DEVICE_ATTR(spkr_alloc_data_block, S_IRUGO,
-	hdmi_common_rda_spkr_alloc_data_block, NULL);
-
-static struct attribute *external_common_fs_attrs[] = {
-	&dev_attr_video_mode.attr,
-	&dev_attr_video_mode_str.attr,
-	&dev_attr_connected.attr,
-	&dev_attr_hdmi_mode.attr,
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-	&dev_attr_edid_modes.attr,
-	&dev_attr_hdcp.attr,
-	&dev_attr_hpd.attr,
-	&dev_attr_pa.attr,
-	&dev_attr_scan_info.attr,
-	&dev_attr_vendor_name.attr,
-	&dev_attr_product_description.attr,
-	&dev_attr_edid_3d_modes.attr,
-	&dev_attr_3d_present.attr,
-	&dev_attr_hdcp_present.attr,
-#endif
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	&dev_attr_format_3d.attr,
-#endif
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	&dev_attr_cec.attr,
-	&dev_attr_cec_logical_addr.attr,
-	&dev_attr_cec_rd_frame.attr,
-	&dev_attr_cec_wr_frame.attr,
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-	&dev_attr_hdmi_primary.attr,
-	&dev_attr_audio_data_block.attr,
-	&dev_attr_spkr_alloc_data_block.attr,
-	NULL,
-};
-static struct attribute_group external_common_fs_attr_group = {
-	.attrs = external_common_fs_attrs,
-};
-
-/* create external interface kobject and initialize */
-int external_common_state_create(struct platform_device *pdev)
-{
-	int rc;
-	struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
-	if (!mfd) {
-		DEV_ERR("%s: mfd not found\n", __func__);
-		return -ENODEV;
-	}
-	if (!mfd->fbi) {
-		DEV_ERR("%s: mfd->fbi not found\n", __func__);
-		return -ENODEV;
-	}
-	if (!mfd->fbi->dev) {
-		DEV_ERR("%s: mfd->fbi->dev not found\n", __func__);
-		return -ENODEV;
-	}
-	rc = sysfs_create_group(&mfd->fbi->dev->kobj,
-		&external_common_fs_attr_group);
-	if (rc) {
-		DEV_ERR("%s: sysfs group creation failed, rc=%d\n", __func__,
-			rc);
-		return rc;
-	}
-	external_common_state->uevent_kobj = &mfd->fbi->dev->kobj;
-	DEV_ERR("%s: sysfs group %p\n", __func__,
-		external_common_state->uevent_kobj);
-
-	kobject_uevent(external_common_state->uevent_kobj, KOBJ_ADD);
-	DEV_DBG("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
-	return 0;
-}
-EXPORT_SYMBOL(external_common_state_create);
-
-void external_common_state_remove(void)
-{
-	if (external_common_state->uevent_kobj)
-		sysfs_remove_group(external_common_state->uevent_kobj,
-			&external_common_fs_attr_group);
-	external_common_state->uevent_kobj = NULL;
-}
-EXPORT_SYMBOL(external_common_state_remove);
-
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-/* The Logic ID for HDMI TX Core. Currently only support 1 HDMI TX Core. */
-struct hdmi_edid_video_mode_property_type {
-	uint32	video_code;
-	uint32	active_h;
-	uint32	active_v;
-	boolean	interlaced;
-	uint32	total_h;
-	uint32	total_blank_h;
-	uint32	total_v;
-	uint32	total_blank_v;
-	/* Must divide by 1000 to get the frequency */
-	uint32	freq_h;
-	/* Must divide by 1000 to get the frequency */
-	uint32	freq_v;
-	/* Must divide by 1000 to get the frequency */
-	uint32	pixel_freq;
-	/* Must divide by 1000 to get the frequency */
-	uint32	refresh_rate;
-	boolean	aspect_ratio_4_3;
-};
-
-/* LUT is sorted from lowest Active H to highest Active H - ease searching */
-static struct hdmi_edid_video_mode_property_type
-	hdmi_edid_disp_mode_lut[] = {
-
-	/* All 640 H Active */
-	{HDMI_VFRMT_640x480p60_4_3, 640, 480, FALSE, 800, 160, 525, 45,
-	 31465, 59940, 25175, 59940, TRUE},
-	{HDMI_VFRMT_640x480p60_4_3, 640, 480, FALSE, 800, 160, 525, 45,
-	 31500, 60000, 25200, 60000, TRUE},
-
-	/* All 720 H Active */
-	{HDMI_VFRMT_720x576p50_4_3,  720, 576, FALSE, 864, 144, 625, 49,
-	 31250, 50000, 27000, 50000, TRUE},
-	{HDMI_VFRMT_720x480p60_4_3,  720, 480, FALSE, 858, 138, 525, 45,
-	 31465, 59940, 27000, 59940, TRUE},
-	{HDMI_VFRMT_720x480p60_4_3,  720, 480, FALSE, 858, 138, 525, 45,
-	 31500, 60000, 27030, 60000, TRUE},
-	{HDMI_VFRMT_720x576p100_4_3, 720, 576, FALSE, 864, 144, 625, 49,
-	 62500, 100000, 54000, 100000, TRUE},
-	{HDMI_VFRMT_720x480p120_4_3, 720, 480, FALSE, 858, 138, 525, 45,
-	 62937, 119880, 54000, 119880, TRUE},
-	{HDMI_VFRMT_720x480p120_4_3, 720, 480, FALSE, 858, 138, 525, 45,
-	 63000, 120000, 54054, 120000, TRUE},
-	{HDMI_VFRMT_720x576p200_4_3, 720, 576, FALSE, 864, 144, 625, 49,
-	 125000, 200000, 108000, 200000, TRUE},
-	{HDMI_VFRMT_720x480p240_4_3, 720, 480, FALSE, 858, 138, 525, 45,
-	 125874, 239760, 108000, 239000, TRUE},
-	{HDMI_VFRMT_720x480p240_4_3, 720, 480, FALSE, 858, 138, 525, 45,
-	 126000, 240000, 108108, 240000, TRUE},
-
-	/* All 1280 H Active */
-	{HDMI_VFRMT_1280x720p50_16_9,  1280, 720, FALSE, 1980, 700, 750, 30,
-	 37500, 50000, 74250, 50000, FALSE},
-	{HDMI_VFRMT_1280x720p60_16_9,  1280, 720, FALSE, 1650, 370, 750, 30,
-	 44955, 59940, 74176, 59940, FALSE},
-	{HDMI_VFRMT_1280x720p60_16_9,  1280, 720, FALSE, 1650, 370, 750, 30,
-	 45000, 60000, 74250, 60000, FALSE},
-	{HDMI_VFRMT_1280x720p100_16_9, 1280, 720, FALSE, 1980, 700, 750, 30,
-	 75000, 100000, 148500, 100000, FALSE},
-	{HDMI_VFRMT_1280x720p120_16_9, 1280, 720, FALSE, 1650, 370, 750, 30,
-	 89909, 119880, 148352, 119880, FALSE},
-	{HDMI_VFRMT_1280x720p120_16_9, 1280, 720, FALSE, 1650, 370, 750, 30,
-	 90000, 120000, 148500, 120000, FALSE},
-	{HDMI_VFRMT_1280x1024p60_5_4, 1280, 1024, FALSE, 1688, 408, 1066, 42,
-	 63981, 60020, 108000, 60000, FALSE},
-
-	/* All 1440 H Active */
-	{HDMI_VFRMT_1440x576i50_4_3, 1440, 576, TRUE,  1728, 288, 625, 24,
-	 15625, 50000, 27000, 50000, TRUE},
-	{HDMI_VFRMT_720x288p50_4_3,  1440, 288, FALSE, 1728, 288, 312, 24,
-	 15625, 50080, 27000, 50000, TRUE},
-	{HDMI_VFRMT_720x288p50_4_3,  1440, 288, FALSE, 1728, 288, 313, 25,
-	 15625, 49920, 27000, 50000, TRUE},
-	{HDMI_VFRMT_720x288p50_4_3,  1440, 288, FALSE, 1728, 288, 314, 26,
-	 15625, 49761, 27000, 50000, TRUE},
-	{HDMI_VFRMT_1440x576p50_4_3, 1440, 576, FALSE, 1728, 288, 625, 49,
-	 31250, 50000, 54000, 50000, TRUE},
-	{HDMI_VFRMT_1440x480i60_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 15734, 59940, 27000, 59940, TRUE},
-	{HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 262, 22,
-	 15734, 60054, 27000, 59940, TRUE},
-	{HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 263, 23,
-	 15734, 59826, 27000, 59940, TRUE},
-	{HDMI_VFRMT_1440x480p60_4_3, 1440, 480, FALSE, 1716, 276, 525, 45,
-	 31469, 59940, 54000, 59940, TRUE},
-	{HDMI_VFRMT_1440x480i60_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 15750, 60000, 27027, 60000, TRUE},
-	{HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 262, 22,
-	 15750, 60115, 27027, 60000, TRUE},
-	{HDMI_VFRMT_1440x240p60_4_3, 1440, 240, FALSE, 1716, 276, 263, 23,
-	 15750, 59886, 27027, 60000, TRUE},
-	{HDMI_VFRMT_1440x480p60_4_3, 1440, 480, FALSE, 1716, 276, 525, 45,
-	 31500, 60000, 54054, 60000, TRUE},
-	{HDMI_VFRMT_1440x576i100_4_3, 1440, 576, TRUE,  1728, 288, 625, 24,
-	 31250, 100000, 54000, 100000, TRUE},
-	{HDMI_VFRMT_1440x480i120_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 31469, 119880, 54000, 119880, TRUE},
-	{HDMI_VFRMT_1440x480i120_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 31500, 120000, 54054, 120000, TRUE},
-	{HDMI_VFRMT_1440x576i200_4_3, 1440, 576, TRUE,  1728, 288, 625, 24,
-	 62500, 200000, 108000, 200000, TRUE},
-	{HDMI_VFRMT_1440x480i240_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 62937, 239760, 108000, 239000, TRUE},
-	{HDMI_VFRMT_1440x480i240_4_3, 1440, 480, TRUE,  1716, 276, 525, 22,
-	 63000, 240000, 108108, 240000, TRUE},
-
-	/* All 1920 H Active */
-	{HDMI_VFRMT_1920x1080p60_16_9, 1920, 1080, FALSE, 2200, 280, 1125,
-	 45, 67433, 59940, 148352, 59940, FALSE},
-	{HDMI_VFRMT_1920x1080p60_16_9, 1920, 1080, TRUE,  2200, 280, 1125,
-	 45, 67500, 60000, 148500, 60000, FALSE},
-	{HDMI_VFRMT_1920x1080p50_16_9, 1920, 1080, FALSE, 2640, 720, 1125,
-	 45, 56250, 50000, 148500, 50000, FALSE},
-	{HDMI_VFRMT_1920x1080p24_16_9, 1920, 1080, FALSE, 2750, 830, 1125,
-	 45, 26973, 23976, 74176, 24000, FALSE},
-	{HDMI_VFRMT_1920x1080p24_16_9, 1920, 1080, FALSE, 2750, 830, 1125,
-	 45, 27000, 24000, 74250, 24000, FALSE},
-	{HDMI_VFRMT_1920x1080p25_16_9, 1920, 1080, FALSE, 2640, 720, 1125,
-	 45, 28125, 25000, 74250, 25000, FALSE},
-	{HDMI_VFRMT_1920x1080p30_16_9, 1920, 1080, FALSE, 2200, 280, 1125,
-	 45, 33716, 29970, 74176, 30000, FALSE},
-	{HDMI_VFRMT_1920x1080p30_16_9, 1920, 1080, FALSE, 2200, 280, 1125,
-	 45, 33750, 30000, 74250, 30000, FALSE},
-	{HDMI_VFRMT_1920x1080i50_16_9, 1920, 1080, TRUE,  2304, 384, 1250,
-	 85, 31250, 50000, 72000, 50000, FALSE},
-	{HDMI_VFRMT_1920x1080i60_16_9, 1920, 1080, TRUE,  2200, 280, 1125,
-	 22, 33716, 59940, 74176, 59940, FALSE},
-	{HDMI_VFRMT_1920x1080i60_16_9, 1920, 1080, TRUE,  2200, 280, 1125,
-	 22, 33750, 60000, 74250, 60000, FALSE},
-	{HDMI_VFRMT_1920x1080i100_16_9, 1920, 1080, TRUE,  2640, 720, 1125,
-	 22, 56250, 100000, 148500, 100000, FALSE},
-	{HDMI_VFRMT_1920x1080i120_16_9, 1920, 1080, TRUE,  2200, 280, 1125,
-	 22, 67432, 119880, 148352, 119980, FALSE},
-	{HDMI_VFRMT_1920x1080i120_16_9, 1920, 1080, TRUE,  2200, 280, 1125,
-	 22, 67500, 120000, 148500, 120000, FALSE},
-
-	/* All 2880 H Active */
-	{HDMI_VFRMT_2880x576i50_4_3, 2880, 576, TRUE,  3456, 576, 625, 24,
-	 15625, 50000, 54000, 50000, TRUE},
-	{HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 312, 24,
-	 15625, 50080, 54000, 50000, TRUE},
-	{HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 313, 25,
-	 15625, 49920, 54000, 50000, TRUE},
-	{HDMI_VFRMT_2880x288p50_4_3, 2880, 576, FALSE, 3456, 576, 314, 26,
-	 15625, 49761, 54000, 50000, TRUE},
-	{HDMI_VFRMT_2880x576p50_4_3, 2880, 576, FALSE, 3456, 576, 625, 49,
-	 31250, 50000, 108000, 50000, TRUE},
-	{HDMI_VFRMT_2880x480i60_4_3, 2880, 480, TRUE,  3432, 552, 525, 22,
-	 15734, 59940, 54000, 59940, TRUE},
-	{HDMI_VFRMT_2880x240p60_4_3, 2880, 480, FALSE, 3432, 552, 262, 22,
-	 15734, 60054, 54000, 59940, TRUE},
-	{HDMI_VFRMT_2880x240p60_4_3, 2880, 480, FALSE, 3432, 552, 263, 23,
-	 15734, 59940, 54000, 59940, TRUE},
-	{HDMI_VFRMT_2880x480p60_4_3, 2880, 480, FALSE, 3432, 552, 525, 45,
-	 31469, 59940, 108000, 59940, TRUE},
-	{HDMI_VFRMT_2880x480i60_4_3, 2880, 480, TRUE,  3432, 552, 525, 22,
-	 15750, 60000, 54054, 60000, TRUE},
-	{HDMI_VFRMT_2880x240p60_4_3, 2880, 240, FALSE, 3432, 552, 262, 22,
-	 15750, 60115, 54054, 60000, TRUE},
-	{HDMI_VFRMT_2880x240p60_4_3, 2880, 240, FALSE, 3432, 552, 262, 23,
-	 15750, 59886, 54054, 60000, TRUE},
-	{HDMI_VFRMT_2880x480p60_4_3, 2880, 480, FALSE, 3432, 552, 525, 45,
-	 31500, 60000, 108108, 60000, TRUE},
-};
-
-static const uint8 *hdmi_edid_find_block(const uint8 *in_buf,
-		uint32 start_offset, uint8 type, uint8 *len)
-{
-	/* the start of data block collection, start of Video Data Block */
-	uint32 offset = start_offset;
-	uint32 end_dbc_offset = in_buf[2];
-
-	*len = 0;
-
-	/*edid buffer 1, byte 2 being 4 means no non-DTD/Data block collection
-	  present.
-	  edid buffer 1, byte 2 being 0 menas no non-DTD/DATA block collection
-	  present and no DTD data present.*/
-	if ((end_dbc_offset == 0) || (end_dbc_offset == 4)) {
-		DEV_WARN("EDID: no DTD or non-DTD data present\n");
-		return NULL;
-	}
-	while (offset < end_dbc_offset) {
-		uint8 block_len = in_buf[offset] & 0x1F;
-		if ((in_buf[offset] >> 5) == type) {
-			*len = block_len;
-			DEV_DBG("EDID: block=%d found @ %d with length=%d\n",
-				type, offset, block_len);
-			return in_buf+offset;
-		}
-		offset += 1 + block_len;
-	}
-	DEV_WARN("EDID: type=%d block not found in EDID block\n", type);
-	return NULL;
-}
-
-static void hdmi_edid_extract_vendor_id(const uint8 *in_buf,
-	char *vendor_id)
-{
-	uint32 id_codes = ((uint32)in_buf[8] << 8) + in_buf[9];
-
-	vendor_id[0] = 'A' - 1 + ((id_codes >> 10) & 0x1F);
-	vendor_id[1] = 'A' - 1 + ((id_codes >> 5) & 0x1F);
-	vendor_id[2] = 'A' - 1 + (id_codes & 0x1F);
-	vendor_id[3] = 0;
-}
-
-static uint32 hdmi_edid_extract_ieee_reg_id(const uint8 *in_buf)
-{
-	uint8 len;
-	const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3,
-			&len);
-
-	if (vsd == NULL)
-		return 0;
-
-	DEV_DBG("EDID: VSD PhyAddr=%04x, MaxTMDS=%dMHz\n",
-		((uint32)vsd[4] << 8) + (uint32)vsd[5], (uint32)vsd[7] * 5);
-	external_common_state->physical_address =
-		((uint16)vsd[4] << 8) + (uint16)vsd[5];
-	return ((uint32)vsd[3] << 16) + ((uint32)vsd[2] << 8) + (uint32)vsd[1];
-}
-
-#define HDMI_VSDB_3D_DATA_OFFSET(vsd) \
-	(!((vsd)[8] & BIT(7)) ? 9 : (!((vsd)[8] & BIT(6)) ? 11 : 13))
-
-static void hdmi_edid_extract_3d_present(const uint8 *in_buf)
-{
-	uint8 len, offset;
-	const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3,
-			&len);
-
-	external_common_state->present_3d = 0;
-	if (vsd == NULL || len < 9) {
-		DEV_DBG("EDID[3D]: block-id 3 not found or not long enough\n");
-		return;
-	}
-
-	offset = HDMI_VSDB_3D_DATA_OFFSET(vsd);
-	DEV_DBG("EDID: 3D present @ %d = %02x\n", offset, vsd[offset]);
-	if (vsd[offset] >> 7) { /* 3D format indication present */
-		DEV_INFO("EDID: 3D present, 3D-len=%d\n", vsd[offset+1] & 0x1F);
-		external_common_state->present_3d = 1;
-	}
-}
-
-
-static void hdmi_edid_extract_latency_fields(const uint8 *in_buf)
-{
-	uint8 len;
-	const uint8 *vsd = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 3,
-			&len);
-
-	if (vsd == NULL || len < 12 || !(vsd[8] & BIT(7))) {
-		external_common_state->video_latency = (uint16)-1;
-		external_common_state->audio_latency = (uint16)-1;
-		DEV_DBG("EDID: No audio/video latency present\n");
-	} else {
-		external_common_state->video_latency = vsd[9];
-		external_common_state->audio_latency = vsd[10];
-		DEV_DBG("EDID: video-latency=%04x, audio-latency=%04x\n",
-			external_common_state->video_latency,
-			external_common_state->audio_latency);
-	}
-}
-
-static void hdmi_edid_extract_speaker_allocation_data(const uint8 *in_buf)
-{
-	uint8 len;
-	const uint8 *sadb = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 4,
-			&len);
-
-	if (sadb == NULL)
-		return;
-
-	if (len != MAX_SPKR_ALLOC_DATA_BLOCK_SIZE)
-		return;
-
-	memcpy(external_common_state->spkr_alloc_data_block, sadb + 1, len);
-	external_common_state->sadb_size = len;
-}
-
-static void hdmi_edid_extract_audio_data_blocks(const uint8 *in_buf)
-{
-	uint8 len;
-	const uint8 *adb = hdmi_edid_find_block(in_buf, DBC_START_OFFSET, 1,
-			&len);
-
-	if (external_common_state->audio_data_block == NULL)
-		return;
-
-	if (len > MAX_AUDIO_DATA_BLOCK_SIZE)
-		return;
-
-	memcpy(external_common_state->audio_data_block, adb + 1, len);
-	external_common_state->adb_size = len;
-}
-
-static void hdmi_edid_extract_extended_data_blocks(const uint8 *in_buf)
-{
-	uint8 len = 0;
-	uint32 start_offset = DBC_START_OFFSET;
-
-	/* A Tage code of 7 identifies extended data blocks */
-	uint8 const *etag = hdmi_edid_find_block(in_buf, start_offset, 7, &len);
-
-	while (etag != NULL) {
-		/* The extended data block should at least be 2 bytes long */
-		if (len < 2) {
-			DEV_DBG("EDID: Found an extended data block of length"
-				"less than 2 bytes. Ignoring ...\n");
-		} else {
-			/*
-			 * The second byte of the extended data block has the
-			 * extended tag code
-			 */
-			switch (etag[1]) {
-			case 0:
-				/* Video Capability Data Block */
-				DEV_DBG("EDID: VCDB=%02X %02X\n", etag[1],
-						etag[2]);
-
-				/*
-				 * Check if the sink specifies underscan
-				 * support for:
-				 * BIT 5: preferred video format
-				 * BIT 3: IT video format
-				 * BIT 1: CE video format
-				 */
-				external_common_state->pt_scan_info = (etag[2] &
-							(BIT(4) | BIT(5))) >> 4;
-				external_common_state->it_scan_info = (etag[2] &
-							(BIT(3) | BIT(2))) >> 2;
-				external_common_state->ce_scan_info = etag[2] &
-							(BIT(1) | BIT(0));
-				DEV_DBG("EDID: Scan Information (pt|it|ce): "
-					"(%d|%d|%d)",
-					external_common_state->pt_scan_info,
-					external_common_state->it_scan_info,
-					external_common_state->ce_scan_info);
-				break;
-			default:
-				DEV_DBG("EDID: Extend Tag Code %d not"
-						"supported\n", etag[1]);
-				break;
-			}
-		}
-
-		/* There could be more that one extended data block */
-		start_offset = etag - in_buf + len + 1;
-		etag = hdmi_edid_find_block(in_buf, start_offset, 7, &len);
-	}
-}
-
-static void hdmi_edid_detail_desc(const uint8 *data_buf, uint32 *disp_mode)
-{
-	boolean	aspect_ratio_4_3    = FALSE;
-	boolean	interlaced          = FALSE;
-	uint32	active_h            = 0;
-	uint32	active_v            = 0;
-	uint32	blank_h             = 0;
-	uint32	blank_v             = 0;
-	uint32	ndx                 = 0;
-	uint32	max_num_of_elements = 0;
-	uint32	img_size_h          = 0;
-	uint32	img_size_v          = 0;
-
-	/* See VESA Spec */
-	/* EDID_TIMING_DESC_UPPER_H_NIBBLE[0x4]: Relative Offset to the EDID
-	 *   detailed timing descriptors - Upper 4 bit for each H active/blank
-	 *   field */
-	/* EDID_TIMING_DESC_H_ACTIVE[0x2]: Relative Offset to the EDID detailed
-	 *   timing descriptors - H active */
-	active_h = ((((uint32)data_buf[0x4] >> 0x4) & 0xF) << 8)
-		| data_buf[0x2];
-
-	/* EDID_TIMING_DESC_H_BLANK[0x3]: Relative Offset to the EDID detailed
-	 *   timing descriptors - H blank */
-	blank_h = (((uint32)data_buf[0x4] & 0xF) << 8)
-		| data_buf[0x3];
-
-	/* EDID_TIMING_DESC_UPPER_V_NIBBLE[0x7]: Relative Offset to the EDID
-	 *   detailed timing descriptors - Upper 4 bit for each V active/blank
-	 *   field */
-	/* EDID_TIMING_DESC_V_ACTIVE[0x5]: Relative Offset to the EDID detailed
-	 *   timing descriptors - V active */
-	active_v = ((((uint32)data_buf[0x7] >> 0x4) & 0xF) << 8)
-		| data_buf[0x5];
-
-	/* EDID_TIMING_DESC_V_BLANK[0x6]: Relative Offset to the EDID detailed
-	 *   timing descriptors - V blank */
-	blank_v = (((uint32)data_buf[0x7] & 0xF) << 8)
-		| data_buf[0x6];
-
-	/* EDID_TIMING_DESC_IMAGE_SIZE_UPPER_NIBBLE[0xE]: Relative Offset to the
-	 *   EDID detailed timing descriptors - Image Size upper nibble
-	 *   V and H */
-	/* EDID_TIMING_DESC_H_IMAGE_SIZE[0xC]: Relative Offset to the EDID
-	 *   detailed timing descriptors - H image size */
-	/* EDID_TIMING_DESC_V_IMAGE_SIZE[0xD]: Relative Offset to the EDID
-	 *   detailed timing descriptors - V image size */
-	img_size_h = ((((uint32)data_buf[0xE] >> 0x4) & 0xF) << 8)
-		| data_buf[0xC];
-	img_size_v = (((uint32)data_buf[0xE] & 0xF) << 8)
-		| data_buf[0xD];
-
-	/*
-	 * aspect ratio as 4:3 if within specificed range , rathaer than being
-	 * absolute value
-	 */
-	aspect_ratio_4_3 = (abs(img_size_h * 3 - img_size_v * 4) < 5) ? 1 : 0;
-
-	max_num_of_elements  = sizeof(hdmi_edid_disp_mode_lut)
-		/ sizeof(*hdmi_edid_disp_mode_lut);
-
-	/* EDID_TIMING_DESC_INTERLACE[0x11:7]: Relative Offset to the EDID
-	 *   detailed timing descriptors - Interlace flag */
-	DEV_DBG("Interlaced mode byte data_buf[0x11]=[%x]\n", data_buf[0x11]);
-	/*
-	 * CEA 861-D: interlaced bit is bit[7] of byte[0x11]
-	 */
-	interlaced = (data_buf[0x11] & 0x80) >> 7;
-
-	DEV_DBG("%s: A[%ux%u] B[%ux%u] V[%ux%u] %s\n", __func__,
-		active_h, active_v, blank_h, blank_v, img_size_h, img_size_v,
-		interlaced ? "i" : "p");
-
-	*disp_mode = HDMI_VFRMT_FORCE_32BIT;
-	while (ndx < max_num_of_elements) {
-		const struct hdmi_edid_video_mode_property_type *edid =
-			hdmi_edid_disp_mode_lut+ndx;
-
-		if ((interlaced    == edid->interlaced)    &&
-			(active_h  == edid->active_h)      &&
-			(blank_h   == edid->total_blank_h) &&
-			(blank_v   == edid->total_blank_v) &&
-			((active_v == edid->active_v) ||
-			 (active_v == (edid->active_v + 1)))
-		) {
-			if (edid->aspect_ratio_4_3 && !aspect_ratio_4_3)
-				/* Aspect ratio 16:9 */
-				*disp_mode = edid->video_code + 1;
-			else
-				/* Aspect ratio 4:3 */
-				*disp_mode = edid->video_code;
-
-			DEV_DBG("%s: mode found:%d\n", __func__, *disp_mode);
-			break;
-		}
-		++ndx;
-	}
-	if (ndx == max_num_of_elements)
-		DEV_INFO("%s: *no mode* found\n", __func__);
-}
-
-static void add_supported_video_format(
-	struct hdmi_disp_mode_list_type *disp_mode_list,
-	uint32 video_format)
-{
-	const struct hdmi_disp_mode_timing_type *timing;
-	boolean supported = false;
-	boolean mhl_supported = true;
-
-	if (video_format >= HDMI_VFRMT_MAX)
-		return;
-
-	timing = hdmi_common_get_supported_mode(video_format);
-	supported = timing != NULL;
-	DEV_DBG("EDID: format: %d [%s], %s\n",
-		video_format, video_format_2string(video_format),
-		supported ? "Supported" : "Not-Supported");
-
-	if (mhl_is_enabled()) {
-		const struct hdmi_disp_mode_timing_type *mhl_timing =
-			hdmi_mhl_get_supported_mode(video_format);
-		mhl_supported = mhl_timing != NULL;
-		DEV_DBG("EDID: format: %d [%s], %s by MHL\n",
-			video_format, video_format_2string(video_format),
-			mhl_supported ? "Supported" : "Not-Supported");
-	}
-
-	if (supported && mhl_supported) {
-		disp_mode_list->disp_mode_list[
-			disp_mode_list->num_of_elements++] = video_format;
-		if (video_format == external_common_state->video_resolution) {
-			DEV_DBG("%s: Default resolution %d [%s] supported\n",
-					__func__, video_format,
-					video_format_2string(video_format));
-			external_common_state->default_res_supported = true;
-		}
-	}
-}
-
-const char *single_video_3d_format_2string(uint32 format)
-{
-	switch (format) {
-	case TOP_AND_BOTTOM: return "TAB";
-	case FRAME_PACKING: return "FP";
-	case SIDE_BY_SIDE_HALF: return "SSH";
-	}
-	return "";
-}
-
-ssize_t video_3d_format_2string(uint32 format, char *buf)
-{
-	ssize_t ret, len = 0;
-	ret = snprintf(buf, PAGE_SIZE, "%s",
-		single_video_3d_format_2string(format & FRAME_PACKING));
-	len += ret;
-
-	if (len && (format & TOP_AND_BOTTOM))
-		ret = snprintf(buf + len, PAGE_SIZE - len, ":%s",
-			single_video_3d_format_2string(
-				format & TOP_AND_BOTTOM));
-	else
-		ret = snprintf(buf + len, PAGE_SIZE - len, "%s",
-			single_video_3d_format_2string(
-				format & TOP_AND_BOTTOM));
-	len += ret;
-
-	if (len && (format & SIDE_BY_SIDE_HALF))
-		ret = snprintf(buf + len, PAGE_SIZE - len, ":%s",
-			single_video_3d_format_2string(
-				format & SIDE_BY_SIDE_HALF));
-	else
-		ret = snprintf(buf + len, PAGE_SIZE - len, "%s",
-			single_video_3d_format_2string(
-				format & SIDE_BY_SIDE_HALF));
-	len += ret;
-
-	return len;
-}
-
-static void add_supported_3d_format(
-	struct hdmi_disp_mode_list_type *disp_mode_list,
-	uint32 video_format,
-	uint32 video_3d_format)
-{
-	char string[128];
-	boolean added = FALSE;
-	int i;
-	for (i = 0; i < disp_mode_list->num_of_elements; ++i) {
-		if (disp_mode_list->disp_mode_list[i] == video_format) {
-			disp_mode_list->disp_3d_mode_list[i] |=
-				video_3d_format;
-			added = TRUE;
-			break;
-		}
-	}
-	video_3d_format_2string(video_3d_format, string);
-	DEV_DBG("EDID[3D]: format: %d [%s], %s %s\n",
-		video_format, video_format_2string(video_format),
-		string, added ? "added" : "NOT added");
-}
-
-static void hdmi_edid_get_display_vsd_3d_mode(const uint8 *data_buf,
-	struct hdmi_disp_mode_list_type *disp_mode_list,
-	uint32 num_og_cea_blocks)
-{
-	uint8 len, offset, present_multi_3d, hdmi_vic_len;
-	int hdmi_3d_len;
-	uint16 structure_all, structure_mask;
-	const uint8 *vsd = num_og_cea_blocks ?
-		hdmi_edid_find_block(data_buf+0x80, DBC_START_OFFSET,
-				3, &len) : NULL;
-	int i;
-
-	offset = HDMI_VSDB_3D_DATA_OFFSET(vsd);
-	present_multi_3d = (vsd[offset] & 0x60) >> 5;
-
-	offset += 1;
-	hdmi_vic_len = (vsd[offset] >> 5) & 0x7;
-	hdmi_3d_len = vsd[offset] & 0x1F;
-	DEV_DBG("EDID[3D]: HDMI_VIC_LEN = %d, HDMI_3D_LEN = %d\n",
-		hdmi_vic_len, hdmi_3d_len);
-
-	offset += (hdmi_vic_len + 1);
-	if (present_multi_3d == 1 || present_multi_3d == 2) {
-		DEV_DBG("EDID[3D]: multi 3D present (%d)\n", present_multi_3d);
-		/* 3d_structure_all */
-		structure_all = (vsd[offset] << 8) | vsd[offset + 1];
-		offset += 2;
-		hdmi_3d_len -= 2;
-		if (present_multi_3d == 2) {
-			/* 3d_structure_mask */
-			structure_mask = (vsd[offset] << 8) | vsd[offset + 1];
-			offset += 2;
-			hdmi_3d_len -= 2;
-		} else
-			structure_mask = 0xffff;
-
-		i = 0;
-		while (i < 16) {
-			if (i >= disp_mode_list->disp_multi_3d_mode_list_cnt)
-				break;
-
-			if (!(structure_mask & BIT(i))) {
-				++i;
-				continue;
-			}
-
-			/* BIT0: FRAME PACKING */
-			if (structure_all & BIT(0))
-				add_supported_3d_format(disp_mode_list,
-					disp_mode_list->
-						disp_multi_3d_mode_list[i],
-					FRAME_PACKING);
-
-			/* BIT6: TOP AND BOTTOM */
-			if (structure_all & BIT(6))
-				add_supported_3d_format(disp_mode_list,
-					disp_mode_list->
-						disp_multi_3d_mode_list[i],
-					TOP_AND_BOTTOM);
-
-			/* BIT8: SIDE BY SIDE HALF */
-			if (structure_all & BIT(8))
-				add_supported_3d_format(disp_mode_list,
-					disp_mode_list->
-						disp_multi_3d_mode_list[i],
-					SIDE_BY_SIDE_HALF);
-
-			++i;
-		}
-	}
-
-	i = 0;
-	while (hdmi_3d_len > 0) {
-		DEV_DBG("EDID[3D]: 3D_Structure_%d @ %d: %02x\n",
-			i + 1, offset, vsd[offset]);
-
-		if ((vsd[offset] >> 4) >=
-			disp_mode_list->disp_multi_3d_mode_list_cnt) {
-			if ((vsd[offset] & 0x0F) >= 8) {
-				offset += 1;
-				hdmi_3d_len -= 1;
-				DEV_DBG("EDID[3D]: 3D_Detail_%d @ %d: %02x\n",
-					i + 1, offset, vsd[offset]);
-			}
-			i += 1;
-			offset += 1;
-			hdmi_3d_len -= 1;
-			continue;
-		}
-
-		switch (vsd[offset] & 0x0F) {
-		case 0:
-			/* 0000b: FRAME PACKING */
-			add_supported_3d_format(disp_mode_list,
-				disp_mode_list->disp_multi_3d_mode_list
-					[vsd[offset] >> 4],
-				FRAME_PACKING);
-			break;
-		case 6:
-			/* 0110b: TOP AND BOTTOM */
-			add_supported_3d_format(disp_mode_list,
-				disp_mode_list->disp_multi_3d_mode_list
-					[vsd[offset] >> 4],
-				TOP_AND_BOTTOM);
-			break;
-		case 8:
-			/* 1000b: SIDE BY SIDE HALF */
-			add_supported_3d_format(disp_mode_list,
-				disp_mode_list->disp_multi_3d_mode_list
-					[vsd[offset] >> 4],
-				SIDE_BY_SIDE_HALF);
-			break;
-		}
-		if ((vsd[offset] & 0x0F) >= 8) {
-			offset += 1;
-			hdmi_3d_len -= 1;
-			DEV_DBG("EDID[3D]: 3D_Detail_%d @ %d: %02x\n",
-				i + 1, offset, vsd[offset]);
-		}
-		i += 1;
-		offset += 1;
-		hdmi_3d_len -= 1;
-	}
-}
-
-static void hdmi_edid_get_display_mode(const uint8 *data_buf,
-	struct hdmi_disp_mode_list_type *disp_mode_list,
-	uint32 num_og_cea_blocks)
-{
-	uint8 i			= 0, offset = 0, std_blk = 0;
-	uint32 video_format	= HDMI_VFRMT_640x480p60_4_3;
-	boolean has480p		= FALSE;
-	uint8 len;
-	const uint8 *edid_blk0 = &data_buf[0x0];
-	const uint8 *edid_blk1 = &data_buf[0x80];
-	const uint8 *svd = num_og_cea_blocks ?
-		hdmi_edid_find_block(data_buf+0x80, DBC_START_OFFSET,
-				2, &len) : NULL;
-	boolean has60hz_mode	= FALSE;
-	boolean has50hz_mode	= FALSE;
-
-
-	disp_mode_list->num_of_elements = 0;
-	disp_mode_list->disp_multi_3d_mode_list_cnt = 0;
-	if (svd != NULL) {
-		++svd;
-		for (i = 0; i < len; ++i, ++svd) {
-			/* Subtract 1 because it is zero based in the driver,
-			 * while the Video identification code is 1 based in the
-			 * CEA_861D spec */
-			video_format = (*svd & 0x7F) - 1;
-			add_supported_video_format(disp_mode_list,
-				video_format);
-			/* Make a note of the preferred video format */
-			if (i == 0) {
-				external_common_state->preferred_video_format =
-					video_format;
-			}
-			if (i < 16) {
-				disp_mode_list->disp_multi_3d_mode_list[i]
-					= video_format;
-				disp_mode_list->disp_multi_3d_mode_list_cnt++;
-			}
-
-			if (video_format <= HDMI_VFRMT_1920x1080p60_16_9 ||
-				video_format == HDMI_VFRMT_2880x480p60_4_3 ||
-				video_format == HDMI_VFRMT_2880x480p60_16_9)
-				has60hz_mode = TRUE;
-
-			if ((video_format >= HDMI_VFRMT_720x576p50_4_3 &&
-				video_format <= HDMI_VFRMT_1920x1080p50_16_9) ||
-				video_format == HDMI_VFRMT_2880x576p50_4_3 ||
-				video_format == HDMI_VFRMT_2880x576p50_16_9 ||
-				video_format == HDMI_VFRMT_1920x1250i50_16_9)
-				has50hz_mode = TRUE;
-			if (video_format == HDMI_VFRMT_640x480p60_4_3)
-				has480p = TRUE;
-		}
-	} else if (!num_og_cea_blocks) {
-		/* Detailed timing descriptors */
-		uint32 desc_offset = 0;
-		/* Maximum 4 timing descriptor in block 0 - No CEA
-		 * extension in this case */
-		/* EDID_FIRST_TIMING_DESC[0x36] - 1st detailed timing
-		 *   descriptor */
-		/* EDID_DETAIL_TIMING_DESC_BLCK_SZ[0x12] - Each detailed timing
-		 *   descriptor has block size of 18 */
-		while (4 > i && 0 != edid_blk0[0x36+desc_offset]) {
-			hdmi_edid_detail_desc(edid_blk0+0x36+desc_offset,
-				&video_format);
-			DEV_DBG("[%s:%d] Block-0 Adding vid fmt = [%s]\n",
-				__func__, __LINE__,
-				video_format_2string(video_format));
-			add_supported_video_format(disp_mode_list,
-				video_format);
-			if (video_format == HDMI_VFRMT_640x480p60_4_3)
-				has480p = TRUE;
-			/* Make a note of the preferred video format */
-			if (i == 0) {
-				external_common_state->preferred_video_format =
-					video_format;
-			}
-			desc_offset += 0x12;
-			++i;
-		}
-	} else if (1 == num_og_cea_blocks) {
-		uint32 desc_offset = 0;
-
-		/*
-		 * Read from both block 0 and block 1
-		 * Read EDID block[0] as above
-		 */
-		while (4 > i && 0 != edid_blk0[0x36+desc_offset]) {
-			hdmi_edid_detail_desc(edid_blk0+0x36+desc_offset,
-				&video_format);
-			DEV_DBG("[%s:%d] Block-0 Adding vid fmt = [%s]\n",
-				__func__, __LINE__,
-				video_format_2string(video_format));
-			add_supported_video_format(disp_mode_list,
-				video_format);
-			if (video_format == HDMI_VFRMT_640x480p60_4_3)
-				has480p = TRUE;
-			/* Make a note of the preferred video format */
-			if (i == 0) {
-				external_common_state->preferred_video_format =
-					video_format;
-			}
-			desc_offset += 0x12;
-			++i;
-		}
-
-		/* Parse block 1 - CEA extension byte offset of first
-		 * detailed timing generation - offset is relevant to
-		 * the offset of block 1 */
-
-		/* EDID_CEA_EXTENSION_FIRST_DESC[0x82]: Offset to CEA
-		 * extension first timing desc - indicate the offset of
-		 * the first detailed timing descriptor */
-		 /* EDID_BLOCK_SIZE = 0x80  Each page size in the EDID ROM */
-		desc_offset = edid_blk1[0x02];
-		while (0 != edid_blk1[desc_offset]) {
-			hdmi_edid_detail_desc(edid_blk1+desc_offset,
-				&video_format);
-			DEV_DBG("[%s:%d] Block-1 Adding vid fmt = [%s]\n",
-				__func__, __LINE__,
-				video_format_2string(video_format));
-			add_supported_video_format(disp_mode_list,
-				video_format);
-			if (video_format == HDMI_VFRMT_640x480p60_4_3)
-				has480p = TRUE;
-			/* Make a note of the preferred video format */
-			if (i == 0) {
-				external_common_state->preferred_video_format =
-					video_format;
-			}
-			desc_offset += 0x12;
-			++i;
-		}
-	}
-
-
-	/*
-	 * Check SD Timings if it contains 1280x1024@60Hz.
-	 * SD Timing can be max 8 with 2 byte in size.
-	 */
-	std_blk = 0;
-	offset  = 0;
-	while (std_blk < 8) {
-		if ((edid_blk0[0x26 + offset] == 0x81) &&
-			(edid_blk0[0x26 + offset + 1] == 0x80)) {
-			add_supported_video_format(disp_mode_list,
-					HDMI_VFRMT_1280x1024p60_5_4);
-			break;
-		} else {
-			offset += 2;
-		}
-		std_blk++;
-	}
-
-	/* check if the EDID revision is 4 (version 1.4) */
-	if (edid_blk0[0x13] == 4) {
-		uint8  start = 0x36;
-
-		i = 0;
-
-		/* Check each of 4 - 18 bytes descriptors */
-		while (i < 4) {
-			uint8  itrate   = start;
-			uint32 header_1 = 0;
-			uint8  header_2 = 0;
-
-			/*
-			 * First 5 bytes are header.
-			 * If they match 0x000000F700, it means its an
-			 * established Timing III descriptor.
-			 */
-			header_1 = edid_blk0[itrate++];
-			header_1 = header_1 << 8 | edid_blk0[itrate++];
-			header_1 = header_1 << 8 | edid_blk0[itrate++];
-			header_1 = header_1 << 8 | edid_blk0[itrate++];
-			header_2 = edid_blk0[itrate];
-
-			if (header_1 == 0x000000F7 &&
-			    header_2 == 0x00) {
-				itrate++; /* VESA DMT Standard Version (0x0A)*/
-				itrate++; /* First set of supported formats */
-				itrate++; /* Second set of supported formats */
-				/* BIT(1) indicates 1280x1024@60Hz */
-				if (edid_blk0[itrate] & 0x02) {
-					add_supported_video_format(
-						disp_mode_list,
-						HDMI_VFRMT_1280x1024p60_5_4);
-					break;
-				}
-			}
-			i++;
-			start += 0x12;
-		}
-	}
-
-	/* mandaroty 3d format */
-	if (external_common_state->present_3d) {
-		if (has60hz_mode) {
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1920x1080p24_16_9,
-				FRAME_PACKING | TOP_AND_BOTTOM);
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1280x720p60_16_9,
-				FRAME_PACKING | TOP_AND_BOTTOM);
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1920x1080i60_16_9,
-				SIDE_BY_SIDE_HALF);
-		}
-		if (has50hz_mode) {
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1920x1080p24_16_9,
-				FRAME_PACKING | TOP_AND_BOTTOM);
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1280x720p50_16_9,
-				FRAME_PACKING | TOP_AND_BOTTOM);
-			add_supported_3d_format(disp_mode_list,
-				HDMI_VFRMT_1920x1080i50_16_9,
-				SIDE_BY_SIDE_HALF);
-		}
-
-		/* 3d format described in Vendor Specific Data */
-		hdmi_edid_get_display_vsd_3d_mode(data_buf, disp_mode_list,
-			num_og_cea_blocks);
-	}
-
-	if (!has480p)
-		/* Need to add default 640 by 480 timings, in case not described
-		 * in the EDID structure.
-		 * All DTV sink devices should support this mode */
-		add_supported_video_format(disp_mode_list,
-			HDMI_VFRMT_640x480p60_4_3);
-}
-
-static int hdmi_common_read_edid_block(int block, uint8 *edid_buf)
-{
-	uint32 ndx, check_sum, print_len;
-#ifdef DEBUG
-	const u8 *b = edid_buf;
-#endif
-	int status = external_common_state->read_edid_block(block, edid_buf);
-	if (status)
-		goto error;
-
-	/* Calculate checksum */
-	check_sum = 0;
-	for (ndx = 0; ndx < 0x80; ++ndx)
-		check_sum += edid_buf[ndx];
-
-	if (check_sum & 0xFF) {
-		DEV_ERR("%s: failed CHECKSUM (read:%x, expected:%x)\n",
-			__func__, (uint8)edid_buf[0x7F], (uint8)check_sum);
-#ifdef DEBUG
-		for (ndx = 0; ndx < 0x100; ndx += 16)
-			DEV_DBG("EDID[%02x-%02x] %02x %02x %02x %02x  "
-				"%02x %02x %02x %02x    %02x %02x %02x %02x  "
-				"%02x %02x %02x %02x\n", ndx, ndx+15,
-				b[ndx+0], b[ndx+1], b[ndx+2], b[ndx+3],
-				b[ndx+4], b[ndx+5], b[ndx+6], b[ndx+7],
-				b[ndx+8], b[ndx+9], b[ndx+10], b[ndx+11],
-				b[ndx+12], b[ndx+13], b[ndx+14], b[ndx+15]);
-#endif
-		status = -EPROTO;
-		goto error;
-	}
-	print_len = 0x80;
-	for (ndx = 0; ndx < print_len; ndx += 16)
-		DEV_DBG("EDID[%02x-%02x] %02x %02x %02x %02x  "
-			"%02x %02x %02x %02x    %02x %02x %02x %02x  "
-			"%02x %02x %02x %02x\n", ndx, ndx+15,
-			b[ndx+0], b[ndx+1], b[ndx+2], b[ndx+3],
-			b[ndx+4], b[ndx+5], b[ndx+6], b[ndx+7],
-			b[ndx+8], b[ndx+9], b[ndx+10], b[ndx+11],
-			b[ndx+12], b[ndx+13], b[ndx+14], b[ndx+15]);
-
-
-error:
-	return status;
-}
-
-static boolean check_edid_header(const uint8 *edid_buf)
-{
-	return (edid_buf[0] == 0x00) && (edid_buf[1] == 0xff)
-		&& (edid_buf[2] == 0xff) && (edid_buf[3] == 0xff)
-		&& (edid_buf[4] == 0xff) && (edid_buf[5] == 0xff)
-		&& (edid_buf[6] == 0xff) && (edid_buf[7] == 0x00);
-}
-
-int hdmi_common_read_edid(void)
-{
-	int status = 0;
-	uint32 cea_extension_ver = 0;
-	uint32 num_og_cea_blocks  = 0;
-	uint32 ieee_reg_id = 0;
-	uint32 i = 1;
-	char vendor_id[5];
-	/* EDID_BLOCK_SIZE[0x80] Each page size in the EDID ROM */
-	uint8 edid_buf[0x80 * 4];
-
-	external_common_state->pt_scan_info = 0;
-	external_common_state->it_scan_info = 0;
-	external_common_state->ce_scan_info = 0;
-	external_common_state->preferred_video_format = 0;
-	external_common_state->present_3d = 0;
-	memset(&external_common_state->disp_mode_list, 0,
-		sizeof(external_common_state->disp_mode_list));
-	memset(edid_buf, 0, sizeof(edid_buf));
-	external_common_state->default_res_supported = false;
-	memset(external_common_state->audio_data_block, 0,
-		sizeof(external_common_state->audio_data_block));
-	memset(external_common_state->spkr_alloc_data_block, 0,
-		sizeof(external_common_state->spkr_alloc_data_block));
-	external_common_state->adb_size = 0;
-	external_common_state->sadb_size = 0;
-
-	status = hdmi_common_read_edid_block(0, edid_buf);
-	if (status || !check_edid_header(edid_buf)) {
-		if (!status)
-			status = -EPROTO;
-		DEV_ERR("%s: edid read block(0) failed: %d "
-			"[%02x%02x%02x%02x%02x%02x%02x%02x]\n", __func__,
-			status,
-			edid_buf[0], edid_buf[1], edid_buf[2], edid_buf[3],
-			edid_buf[4], edid_buf[5], edid_buf[6], edid_buf[7]);
-		goto error;
-	}
-	hdmi_edid_extract_vendor_id(edid_buf, vendor_id);
-
-	/* EDID_CEA_EXTENSION_FLAG[0x7E] - CEC extension byte */
-	num_og_cea_blocks = edid_buf[0x7E];
-
-	DEV_DBG("[JSR] (%s): No. of CEA blocks is  [%u]\n", __func__,
-		num_og_cea_blocks);
-	/* Find out any CEA extension blocks following block 0 */
-	switch (num_og_cea_blocks) {
-	case 0: /* No CEA extension */
-		external_common_state->hdmi_sink = false;
-		DEV_DBG("HDMI DVI mode: %s\n",
-			external_common_state->hdmi_sink ? "no" : "yes");
-		break;
-	case 1: /* Read block 1 */
-		status = hdmi_common_read_edid_block(1, &edid_buf[0x80]);
-		if (status) {
-			DEV_ERR("%s: ddc read block(1) failed: %d\n", __func__,
-				status);
-			goto error;
-		}
-		if (edid_buf[0x80] != 2)
-			num_og_cea_blocks = 0;
-		if (num_og_cea_blocks) {
-			ieee_reg_id =
-				hdmi_edid_extract_ieee_reg_id(edid_buf+0x80);
-			if (ieee_reg_id == 0x0c03)
-				external_common_state->hdmi_sink = TRUE ;
-			else
-				external_common_state->hdmi_sink = FALSE ;
-			hdmi_edid_extract_latency_fields(edid_buf+0x80);
-			hdmi_edid_extract_speaker_allocation_data(
-				edid_buf+0x80);
-			hdmi_edid_extract_audio_data_blocks(edid_buf+0x80);
-			hdmi_edid_extract_3d_present(edid_buf+0x80);
-			hdmi_edid_extract_extended_data_blocks(edid_buf+0x80);
-		}
-		break;
-	case 2:
-	case 3:
-	case 4:
-		for (i = 1; i <= num_og_cea_blocks; i++) {
-			if (!(i % 2)) {
-					status = hdmi_common_read_edid_block(i,
-								edid_buf+0x00);
-					if (status) {
-						DEV_ERR("%s: ddc read block(%d)"
-						"failed: %d\n", __func__, i,
-							status);
-						goto error;
-					}
-			} else {
-				status = hdmi_common_read_edid_block(i,
-							edid_buf+0x80);
-				if (status) {
-					DEV_ERR("%s: ddc read block(%d)"
-					"failed:%d\n", __func__, i,
-						status);
-					goto error;
-				}
-			}
-		}
-		break;
-	default:
-		DEV_ERR("%s: ddc read failed, not supported multi-blocks: %d\n",
-			__func__, num_og_cea_blocks);
-		status = -EPROTO;
-		goto error;
-	}
-
-	if (num_og_cea_blocks) {
-		/* EDID_CEA_EXTENSION_VERSION[0x81]: Offset to CEA extension
-		 * version number - v1,v2,v3 (v1 is seldom, v2 is obsolete,
-		 * v3 most common) */
-		cea_extension_ver = edid_buf[0x81];
-	}
-
-	/* EDID_VERSION[0x12] - EDID Version */
-	/* EDID_REVISION[0x13] - EDID Revision */
-	DEV_INFO("EDID (V=%d.%d, #CEABlocks=%d[V%d], ID=%s, IEEE=%04x, "
-		"EDID-Ext=0x%02x)\n", edid_buf[0x12], edid_buf[0x13],
-		num_og_cea_blocks, cea_extension_ver, vendor_id, ieee_reg_id,
-		edid_buf[0x80]);
-
-	hdmi_edid_get_display_mode(edid_buf,
-		&external_common_state->disp_mode_list, num_og_cea_blocks);
-
-	return 0;
-
-error:
-	external_common_state->disp_mode_list.num_of_elements = 1;
-	external_common_state->disp_mode_list.disp_mode_list[0] =
-		external_common_state->video_resolution;
-	return status;
-}
-EXPORT_SYMBOL(hdmi_common_read_edid);
-
-bool hdmi_common_get_video_format_from_drv_data(struct msm_fb_data_type *mfd)
-{
-	uint32 format =  external_common_state->video_resolution;
-	struct fb_var_screeninfo *var = &mfd->fbi->var;
-	bool changed = TRUE;
-
-	if (var->reserved[3]) {
-		format = var->reserved[3]-1;
-		DEV_DBG("reserved format is %d\n", format);
-	} else if (hdmi_prim_resolution) {
-		format = hdmi_prim_resolution - 1;
-	} else {
-		DEV_DBG("detecting resolution from %dx%d use var->reserved[3]"
-			" to specify mode", mfd->var_xres, mfd->var_yres);
-		switch (mfd->var_xres) {
-		default:
-		case  640:
-			format = HDMI_VFRMT_640x480p60_4_3;
-			break;
-		case  720:
-			format = (mfd->var_yres == 480)
-				? HDMI_VFRMT_720x480p60_16_9
-				: HDMI_VFRMT_720x576p50_16_9;
-			break;
-		case 1280:
-			if (mfd->var_yres == 1024)
-				format = HDMI_VFRMT_1280x1024p60_5_4;
-			else if (mfd->var_frame_rate == 50000)
-				format = HDMI_VFRMT_1280x720p50_16_9;
-			else
-				format = HDMI_VFRMT_1280x720p60_16_9;
-			break;
-		case 1440:
-			format = (mfd->var_yres == 240) /* interlaced has half
-							   of y res.
-							*/
-				? HDMI_VFRMT_1440x480i60_16_9
-				: HDMI_VFRMT_1440x576i50_16_9;
-			break;
-		case 1920:
-			if (mfd->var_yres == 540) {/* interlaced */
-				format = HDMI_VFRMT_1920x1080i60_16_9;
-			} else if (mfd->var_yres == 1080) {
-				if (mfd->var_frame_rate == 50000)
-					format = HDMI_VFRMT_1920x1080p50_16_9;
-				else if (mfd->var_frame_rate == 24000)
-					format = HDMI_VFRMT_1920x1080p24_16_9;
-				else if (mfd->var_frame_rate == 25000)
-					format = HDMI_VFRMT_1920x1080p25_16_9;
-				else if (mfd->var_frame_rate == 30000)
-					format = HDMI_VFRMT_1920x1080p30_16_9;
-				else
-					format = HDMI_VFRMT_1920x1080p60_16_9;
-			}
-			break;
-		}
-	}
-
-	changed = external_common_state->video_resolution != format;
-	if (external_common_state->video_resolution != format)
-		DEV_DBG("switching %s => %s", video_format_2string(
-			external_common_state->video_resolution),
-			video_format_2string(format));
-	else
-		DEV_DBG("resolution %s", video_format_2string(
-			external_common_state->video_resolution));
-	external_common_state->video_resolution = format;
-	return changed;
-}
-EXPORT_SYMBOL(hdmi_common_get_video_format_from_drv_data);
-
-const struct hdmi_disp_mode_timing_type *hdmi_common_get_mode(uint32 mode)
-{
-	if (mode >= HDMI_VFRMT_MAX)
-		return NULL;
-
-	return &hdmi_common_supported_video_mode_lut[mode];
-}
-EXPORT_SYMBOL(hdmi_common_get_mode);
-
-const struct hdmi_disp_mode_timing_type *hdmi_common_get_supported_mode(
-	uint32 mode)
-{
-	const struct hdmi_disp_mode_timing_type *ret
-		= hdmi_common_get_mode(mode);
-
-	if (ret == NULL || !ret->supported)
-		return NULL;
-	return ret;
-}
-EXPORT_SYMBOL(hdmi_common_get_supported_mode);
-
-const struct hdmi_disp_mode_timing_type *hdmi_mhl_get_mode(uint32 mode)
-{
-	if (mode >= HDMI_VFRMT_MAX)
-		return NULL;
-
-	return &hdmi_mhl_supported_video_mode_lut[mode];
-}
-EXPORT_SYMBOL(hdmi_mhl_get_mode);
-
-const struct hdmi_disp_mode_timing_type *hdmi_mhl_get_supported_mode(
-	uint32 mode)
-{
-	const struct hdmi_disp_mode_timing_type *ret
-		= hdmi_mhl_get_mode(mode);
-
-	if (ret == NULL || !ret->supported)
-		return NULL;
-	return ret;
-}
-EXPORT_SYMBOL(hdmi_mhl_get_supported_mode);
-
-void hdmi_common_init_panel_info(struct msm_panel_info *pinfo)
-{
-	const struct hdmi_disp_mode_timing_type *timing =
-		hdmi_common_get_supported_mode(
-		external_common_state->video_resolution);
-
-	if (timing == NULL)
-		return;
-
-	pinfo->xres = timing->active_h;
-	pinfo->yres = timing->active_v;
-	pinfo->clk_rate = timing->pixel_freq*1000;
-	pinfo->frame_rate = 60;
-
-	pinfo->lcdc.h_back_porch = timing->back_porch_h;
-	pinfo->lcdc.h_front_porch = timing->front_porch_h;
-	pinfo->lcdc.h_pulse_width = timing->pulse_width_h;
-	pinfo->lcdc.v_back_porch = timing->back_porch_v;
-	pinfo->lcdc.v_front_porch = timing->front_porch_v;
-	pinfo->lcdc.v_pulse_width = timing->pulse_width_v;
-
-	pinfo->type = DTV_PANEL;
-	pinfo->pdest = DISPLAY_2;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	if (hdmi_prim_display)
-		pinfo->fb_num = 2;
-	else
-		pinfo->fb_num = 1;
-
-	/* blk */
-	pinfo->lcdc.border_clr = 0;
-	/* blue */
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-}
-EXPORT_SYMBOL(hdmi_common_init_panel_info);
-#endif
diff --git a/drivers/video/msm/external_common.h b/drivers/video/msm/external_common.h
deleted file mode 100644
index d117898..0000000
--- a/drivers/video/msm/external_common.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __EXTERNAL_COMMON_H__
-#define __EXTERNAL_COMMON_H__
-#include <linux/switch.h>
-
-#ifdef DEBUG
-#ifndef DEV_DBG_PREFIX
-#define DEV_DBG_PREFIX "EXT_INTERFACE: "
-#endif
-#define DEV_DBG(args...)	pr_debug(DEV_DBG_PREFIX args)
-#else
-#define DEV_DBG(args...)	(void)0
-#endif /* DEBUG */
-#define DEV_INFO(args...)	dev_info(external_common_state->dev, args)
-#define DEV_WARN(args...)	dev_warn(external_common_state->dev, args)
-#define DEV_ERR(args...)	dev_err(external_common_state->dev, args)
-
-#ifdef CONFIG_FB_MSM_TVOUT
-#define TVOUT_VFRMT_NTSC_M_720x480i		0
-#define TVOUT_VFRMT_NTSC_J_720x480i		1
-#define TVOUT_VFRMT_PAL_BDGHIN_720x576i		2
-#define TVOUT_VFRMT_PAL_M_720x480i		3
-#define TVOUT_VFRMT_PAL_N_720x480i		4
-#elif defined(CONFIG_FB_MSM_HDMI_COMMON)
-/* all video formats defined by EIA CEA 861D */
-#define HDMI_VFRMT_640x480p60_4_3	0
-#define HDMI_VFRMT_720x480p60_4_3	1
-#define HDMI_VFRMT_720x480p60_16_9	2
-#define HDMI_VFRMT_1280x720p60_16_9	3
-#define HDMI_VFRMT_1920x1080i60_16_9	4
-#define HDMI_VFRMT_720x480i60_4_3	5
-#define HDMI_VFRMT_1440x480i60_4_3	HDMI_VFRMT_720x480i60_4_3
-#define HDMI_VFRMT_720x480i60_16_9	6
-#define HDMI_VFRMT_1440x480i60_16_9	HDMI_VFRMT_720x480i60_16_9
-#define HDMI_VFRMT_720x240p60_4_3	7
-#define HDMI_VFRMT_1440x240p60_4_3	HDMI_VFRMT_720x240p60_4_3
-#define HDMI_VFRMT_720x240p60_16_9	8
-#define HDMI_VFRMT_1440x240p60_16_9	HDMI_VFRMT_720x240p60_16_9
-#define HDMI_VFRMT_2880x480i60_4_3	9
-#define HDMI_VFRMT_2880x480i60_16_9	10
-#define HDMI_VFRMT_2880x240p60_4_3	11
-#define HDMI_VFRMT_2880x240p60_16_9	12
-#define HDMI_VFRMT_1440x480p60_4_3	13
-#define HDMI_VFRMT_1440x480p60_16_9	14
-#define HDMI_VFRMT_1920x1080p60_16_9	15
-#define HDMI_VFRMT_720x576p50_4_3	16
-#define HDMI_VFRMT_720x576p50_16_9	17
-#define HDMI_VFRMT_1280x720p50_16_9	18
-#define HDMI_VFRMT_1920x1080i50_16_9	19
-#define HDMI_VFRMT_720x576i50_4_3	20
-#define HDMI_VFRMT_1440x576i50_4_3	HDMI_VFRMT_720x576i50_4_3
-#define HDMI_VFRMT_720x576i50_16_9	21
-#define HDMI_VFRMT_1440x576i50_16_9	HDMI_VFRMT_720x576i50_16_9
-#define HDMI_VFRMT_720x288p50_4_3	22
-#define HDMI_VFRMT_1440x288p50_4_3	HDMI_VFRMT_720x288p50_4_3
-#define HDMI_VFRMT_720x288p50_16_9	23
-#define HDMI_VFRMT_1440x288p50_16_9	HDMI_VFRMT_720x288p50_16_9
-#define HDMI_VFRMT_2880x576i50_4_3	24
-#define HDMI_VFRMT_2880x576i50_16_9	25
-#define HDMI_VFRMT_2880x288p50_4_3	26
-#define HDMI_VFRMT_2880x288p50_16_9	27
-#define HDMI_VFRMT_1440x576p50_4_3	28
-#define HDMI_VFRMT_1440x576p50_16_9	29
-#define HDMI_VFRMT_1920x1080p50_16_9	30
-#define HDMI_VFRMT_1920x1080p24_16_9	31
-#define HDMI_VFRMT_1920x1080p25_16_9	32
-#define HDMI_VFRMT_1920x1080p30_16_9	33
-#define HDMI_VFRMT_2880x480p60_4_3	34
-#define HDMI_VFRMT_2880x480p60_16_9	35
-#define HDMI_VFRMT_2880x576p50_4_3	36
-#define HDMI_VFRMT_2880x576p50_16_9	37
-#define HDMI_VFRMT_1920x1250i50_16_9	38
-#define HDMI_VFRMT_1920x1080i100_16_9	39
-#define HDMI_VFRMT_1280x720p100_16_9	40
-#define HDMI_VFRMT_720x576p100_4_3	41
-#define HDMI_VFRMT_720x576p100_16_9	42
-#define HDMI_VFRMT_720x576i100_4_3	43
-#define HDMI_VFRMT_1440x576i100_4_3	HDMI_VFRMT_720x576i100_4_3
-#define HDMI_VFRMT_720x576i100_16_9	44
-#define HDMI_VFRMT_1440x576i100_16_9	HDMI_VFRMT_720x576i100_16_9
-#define HDMI_VFRMT_1920x1080i120_16_9	45
-#define HDMI_VFRMT_1280x720p120_16_9	46
-#define HDMI_VFRMT_720x480p120_4_3	47
-#define HDMI_VFRMT_720x480p120_16_9	48
-#define HDMI_VFRMT_720x480i120_4_3	49
-#define HDMI_VFRMT_1440x480i120_4_3	HDMI_VFRMT_720x480i120_4_3
-#define HDMI_VFRMT_720x480i120_16_9	50
-#define HDMI_VFRMT_1440x480i120_16_9	HDMI_VFRMT_720x480i120_16_9
-#define HDMI_VFRMT_720x576p200_4_3	51
-#define HDMI_VFRMT_720x576p200_16_9	52
-#define HDMI_VFRMT_720x576i200_4_3	53
-#define HDMI_VFRMT_1440x576i200_4_3	HDMI_VFRMT_720x576i200_4_3
-#define HDMI_VFRMT_720x576i200_16_9	54
-#define HDMI_VFRMT_1440x576i200_16_9	HDMI_VFRMT_720x576i200_16_9
-#define HDMI_VFRMT_720x480p240_4_3	55
-#define HDMI_VFRMT_720x480p240_16_9	56
-#define HDMI_VFRMT_720x480i240_4_3	57
-#define HDMI_VFRMT_1440x480i240_4_3	HDMI_VFRMT_720x480i240_4_3
-#define HDMI_VFRMT_720x480i240_16_9	58
-#define HDMI_VFRMT_1440x480i240_16_9	HDMI_VFRMT_720x480i240_16_9
-#define HDMI_VFRMT_FORCE_32BIT		0x7FFFFFFF
-
-/* Video Identification Codes from 65-127 are reserved for the future */
-#define HDMI_VFRMT_END			127
-
-/* VESA DMT TIMINGS */
-/* DMT ID: 23h, STD code: (81h, 80h), also a part of Established Timing III */
-#define HDMI_VFRMT_1280x1024p60_5_4	(HDMI_VFRMT_END + 1)
-#define DMT_VFRMT_END                   HDMI_VFRMT_1280x1024p60_5_4
-
-#define HDMI_VFRMT_MAX	                (DMT_VFRMT_END + 1)
-
-
-extern int ext_resolution;
-
-struct hdmi_disp_mode_timing_type {
-	uint32	video_format;
-	uint32	active_h;
-	uint32	front_porch_h;
-	uint32	pulse_width_h;
-	uint32	back_porch_h;
-	boolean	active_low_h;
-	uint32	active_v;
-	uint32	front_porch_v;
-	uint32	pulse_width_v;
-	uint32	back_porch_v;
-	boolean	active_low_v;
-	/* Must divide by 1000 to get the actual frequency in MHZ */
-	uint32	pixel_freq;
-	/* Must divide by 1000 to get the actual frequency in HZ */
-	uint32	refresh_rate;
-	boolean	interlaced;
-	boolean	supported;
-};
-
-#define HDMI_SETTINGS_640x480p60_4_3					\
-	{HDMI_VFRMT_640x480p60_4_3,      640,  16,  96,  48,  TRUE,	\
-	 480, 10, 2, 33, TRUE, 25200, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_720x480p60_4_3					\
-	{HDMI_VFRMT_720x480p60_4_3,      720,  16,  62,  60,  TRUE,	\
-	 480, 9, 6, 30,  TRUE, 27030, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_720x480p60_16_9					\
-	{HDMI_VFRMT_720x480p60_16_9,     720,  16,  62,  60,  TRUE,	\
-	 480, 9, 6, 30,  TRUE, 27030, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_1280x720p60_16_9					\
-	{HDMI_VFRMT_1280x720p60_16_9,    1280, 110, 40,  220, FALSE,	\
-	 720, 5, 5, 20, FALSE, 74250, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_1920x1080i60_16_9					\
-	{HDMI_VFRMT_1920x1080i60_16_9,   1920, 88,  44,  148, FALSE,	\
-	 540, 2, 5, 5, FALSE, 74250, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_1440x480i60_4_3					\
-	{HDMI_VFRMT_1440x480i60_4_3,     1440, 38,  124, 114, TRUE,	\
-	 240, 4, 3, 15, TRUE, 27000, 60000, TRUE, TRUE}
-#define HDMI_SETTINGS_1440x480i60_16_9					\
-	{HDMI_VFRMT_1440x480i60_16_9,    1440, 38,  124, 114, TRUE,	\
-	 240, 4, 3, 15, TRUE, 27000, 60000, TRUE, TRUE}
-#define HDMI_SETTINGS_1920x1080p60_16_9					\
-	{HDMI_VFRMT_1920x1080p60_16_9,   1920, 88,  44,  148,  FALSE,	\
-	 1080, 4, 5, 36, FALSE, 148500, 60000, FALSE, TRUE}
-#define HDMI_SETTINGS_720x576p50_4_3					\
-	{HDMI_VFRMT_720x576p50_4_3,      720,  12,  64,  68,   TRUE,	\
-	 576,  5, 5, 39, TRUE, 27000, 50000, FALSE, TRUE}
-#define HDMI_SETTINGS_720x576p50_16_9					\
-	{HDMI_VFRMT_720x576p50_16_9,     720,  12,  64,  68,   TRUE,	\
-	 576,  5, 5, 39, TRUE, 27000, 50000, FALSE, TRUE}
-#define HDMI_SETTINGS_1280x720p50_16_9					\
-	{HDMI_VFRMT_1280x720p50_16_9,    1280, 440, 40,  220,  FALSE,	\
-	 720,  5, 5, 20, FALSE, 74250, 50000, FALSE, TRUE}
-#define HDMI_SETTINGS_1440x576i50_4_3					\
-	{HDMI_VFRMT_1440x576i50_4_3,     1440, 24,  126, 138,  TRUE,	\
-	 288,  2, 3, 19, TRUE, 27000, 50000, TRUE, TRUE}
-#define HDMI_SETTINGS_1440x576i50_16_9					\
-	{HDMI_VFRMT_1440x576i50_16_9,    1440, 24,  126, 138,  TRUE,	\
-	 288,  2, 3, 19, TRUE, 27000, 50000, TRUE, TRUE}
-#define HDMI_SETTINGS_1920x1080p50_16_9					\
-	{HDMI_VFRMT_1920x1080p50_16_9,   1920,  528,  44,  148,  FALSE,	\
-	 1080, 4, 5, 36, FALSE, 148500, 50000, FALSE, TRUE}
-#define HDMI_SETTINGS_1920x1080p24_16_9					\
-	{HDMI_VFRMT_1920x1080p24_16_9,   1920,  638,  44,  148,  FALSE,	\
-	 1080, 4, 5, 36, FALSE, 74250, 24000, FALSE, TRUE}
-#define HDMI_SETTINGS_1920x1080p25_16_9					\
-	{HDMI_VFRMT_1920x1080p25_16_9,   1920,  528,  44,  148,  FALSE,	\
-	 1080, 4, 5, 36, FALSE, 74250, 25000, FALSE, TRUE}
-#define HDMI_SETTINGS_1920x1080p30_16_9					\
-	{HDMI_VFRMT_1920x1080p30_16_9,   1920,  88,   44,  148,  FALSE,	\
-	 1080, 4, 5, 36, FALSE, 74250, 30000, FALSE, TRUE}
-#define HDMI_SETTINGS_1280x1024p60_5_4					\
-	{HDMI_VFRMT_1280x1024p60_5_4,   1280,  48,  112,  248,  FALSE, \
-	 1024, 1, 3, 38, FALSE, 108000, 60000, FALSE, TRUE}
-
-/* A lookup table for all the supported display modes by the HDMI
- * hardware and driver.  Use HDMI_SETUP_LUT in the module init to
- * setup the LUT with the supported modes. */
-extern struct hdmi_disp_mode_timing_type
-	hdmi_common_supported_video_mode_lut[HDMI_VFRMT_MAX];
-
-/* Structure that encapsulates all the supported display modes by the HDMI sink
- * device */
-struct hdmi_disp_mode_list_type {
-	uint32	disp_mode_list[HDMI_VFRMT_MAX];
-#define TOP_AND_BOTTOM		0x10
-#define FRAME_PACKING		0x20
-#define SIDE_BY_SIDE_HALF	0x40
-	uint32	disp_3d_mode_list[HDMI_VFRMT_MAX];
-	uint32	disp_multi_3d_mode_list[16];
-	uint32	disp_multi_3d_mode_list_cnt;
-	uint32	num_of_elements;
-};
-#endif
-
-/*
- * As per the CEA-861E spec, there can be a total of 10 short audio
- * descriptors with each SAD being 3 bytes long.
- * Thus, the maximum length of the audio data block would be 30 bytes
- */
-#define MAX_AUDIO_DATA_BLOCK_SIZE	30
-#define MAX_SPKR_ALLOC_DATA_BLOCK_SIZE	3
-
-struct external_common_state_type {
-	boolean hpd_state;
-	struct kobject *uevent_kobj;
-	uint32 video_resolution;
-	boolean default_res_supported;
-	struct device *dev;
-	struct switch_dev sdev;
-	struct switch_dev audio_sdev;
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	boolean format_3d;
-	void (*switch_3d)(boolean on);
-#endif
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-	boolean hdcp_active;
-	boolean hpd_feature_on;
-	boolean hdmi_sink;
-	struct hdmi_disp_mode_list_type disp_mode_list;
-	uint16 video_latency, audio_latency;
-	uint16 physical_address;
-	uint32 preferred_video_format;
-	uint8 pt_scan_info;
-	uint8 it_scan_info;
-	uint8 ce_scan_info;
-	uint8 spd_vendor_name[8];
-	uint8 spd_product_description[16];
-	boolean present_3d;
-	boolean present_hdcp;
-	uint8 audio_data_block[MAX_AUDIO_DATA_BLOCK_SIZE];
-	int adb_size;
-	uint8 spkr_alloc_data_block[MAX_SPKR_ALLOC_DATA_BLOCK_SIZE];
-	int sadb_size;
-	int (*read_edid_block)(int block, uint8 *edid_buf);
-	int (*hpd_feature)(int on);
-#endif
-};
-
-/* The external interface driver needs to initialize the common state. */
-extern struct external_common_state_type *external_common_state;
-extern struct mutex external_common_state_hpd_mutex;
-extern struct mutex hdmi_msm_state_mutex;
-
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-#define VFRMT_NOT_SUPPORTED(VFRMT) \
-	{VFRMT, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FALSE}
-#define HDMI_SETUP_LUT(MODE) do {					\
-		struct hdmi_disp_mode_timing_type mode			\
-			= HDMI_SETTINGS_ ## MODE;			\
-		hdmi_common_supported_video_mode_lut[mode.video_format]	\
-			= mode;						\
-	} while (0)
-
-int hdmi_common_read_edid(void);
-const char *video_format_2string(uint32 format);
-bool hdmi_common_get_video_format_from_drv_data(struct msm_fb_data_type *mfd);
-const struct hdmi_disp_mode_timing_type *hdmi_common_get_mode(uint32 mode);
-const struct hdmi_disp_mode_timing_type *hdmi_common_get_supported_mode(
-	uint32 mode);
-const struct hdmi_disp_mode_timing_type *hdmi_mhl_get_mode(uint32 mode);
-const struct hdmi_disp_mode_timing_type *hdmi_mhl_get_supported_mode(
-	uint32 mode);
-void hdmi_common_init_panel_info(struct msm_panel_info *pinfo);
-
-ssize_t video_3d_format_2string(uint32 format, char *buf);
-#endif
-
-int external_common_state_create(struct platform_device *pdev);
-void external_common_state_remove(void);
-
-#endif /* __EXTERNAL_COMMON_H__ */
diff --git a/drivers/video/msm/hdmi_msm.c b/drivers/video/msm/hdmi_msm.c
deleted file mode 100644
index fa57992..0000000
--- a/drivers/video/msm/hdmi_msm.c
+++ /dev/null
@@ -1,4989 +0,0 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-/* #define DEBUG */
-#define DEV_DBG_PREFIX "HDMI: "
-/* #define REG_DUMP */
-
-#define CEC_MSG_PRINT
-#define TOGGLE_CEC_HARDWARE_FSM
-
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <mach/msm_hdmi_audio.h>
-#include <mach/clk.h>
-#include <mach/msm_iomap.h>
-#include <mach/socinfo.h>
-
-#include "msm_fb.h"
-#include "hdmi_msm.h"
-
-/* Supported HDMI Audio channels */
-#define MSM_HDMI_AUDIO_CHANNEL_2		0
-#define MSM_HDMI_AUDIO_CHANNEL_4		1
-#define MSM_HDMI_AUDIO_CHANNEL_6		2
-#define MSM_HDMI_AUDIO_CHANNEL_8		3
-#define MSM_HDMI_AUDIO_CHANNEL_MAX		4
-#define MSM_HDMI_AUDIO_CHANNEL_FORCE_32BIT	0x7FFFFFFF
-
-/* Supported HDMI Audio sample rates */
-#define MSM_HDMI_SAMPLE_RATE_32KHZ		0
-#define MSM_HDMI_SAMPLE_RATE_44_1KHZ		1
-#define MSM_HDMI_SAMPLE_RATE_48KHZ		2
-#define MSM_HDMI_SAMPLE_RATE_88_2KHZ		3
-#define MSM_HDMI_SAMPLE_RATE_96KHZ		4
-#define MSM_HDMI_SAMPLE_RATE_176_4KHZ		5
-#define MSM_HDMI_SAMPLE_RATE_192KHZ		6
-#define MSM_HDMI_SAMPLE_RATE_MAX		7
-#define MSM_HDMI_SAMPLE_RATE_FORCE_32BIT	0x7FFFFFFF
-
-static int msm_hdmi_sample_rate = MSM_HDMI_SAMPLE_RATE_48KHZ;
-
-/* HDMI/HDCP Registers */
-#define HDCP_DDC_STATUS		0x0128
-#define HDCP_DDC_CTRL_0		0x0120
-#define HDCP_DDC_CTRL_1		0x0124
-#define HDMI_DDC_CTRL		0x020C
-
-#define HPD_EVENT_OFFLINE 0
-#define HPD_EVENT_ONLINE  1
-
-#define SWITCH_SET_HDMI_AUDIO(d, force) \
-	do {\
-		if (!hdmi_msm_is_dvi_mode() &&\
-			((force) ||\
-			 (external_common_state->audio_sdev.state != (d)))) {\
-			switch_set_state(&external_common_state->audio_sdev,\
-					(d));\
-			DEV_INFO("%s: hdmi_audio state switched to %d\n",\
-				__func__,\
-				external_common_state->audio_sdev.state);\
-		} \
-	} while (0)
-
-struct workqueue_struct *hdmi_work_queue;
-struct hdmi_msm_state_type *hdmi_msm_state;
-
-/* Enable HDCP by default */
-static bool hdcp_feature_on = true;
-
-DEFINE_MUTEX(hdmi_msm_state_mutex);
-EXPORT_SYMBOL(hdmi_msm_state_mutex);
-static DEFINE_MUTEX(hdcp_auth_state_mutex);
-
-static void hdmi_msm_dump_regs(const char *prefix);
-
-static void hdmi_msm_hdcp_enable(void);
-static void hdmi_msm_turn_on(void);
-static int hdmi_msm_audio_off(void);
-static int hdmi_msm_read_edid(void);
-static void hdmi_msm_hpd_off(void);
-static boolean hdmi_msm_is_dvi_mode(void);
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-
-static void hdmi_msm_cec_line_latch_detect(void);
-
-#ifdef TOGGLE_CEC_HARDWARE_FSM
-static boolean msg_send_complete = TRUE;
-static boolean msg_recv_complete = TRUE;
-#endif
-
-#define HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE	BIT(16)
-#define HDMI_MSM_CEC_REFTIMER_REFTIMER(___t)	(((___t)&0xFFFF) << 0)
-
-#define HDMI_MSM_CEC_TIME_SIGNAL_FREE_TIME(___t)	(((___t)&0x1FF) << 7)
-#define HDMI_MSM_CEC_TIME_ENABLE			BIT(0)
-
-#define HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(___la)	(((___la)&0xFF) << 0)
-
-#define HDMI_MSM_CEC_CTRL_LINE_OE			BIT(9)
-#define HDMI_MSM_CEC_CTRL_FRAME_SIZE(___sz)		(((___sz)&0x1F) << 4)
-#define HDMI_MSM_CEC_CTRL_SOFT_RESET		BIT(2)
-#define HDMI_MSM_CEC_CTRL_SEND_TRIG			BIT(1)
-#define HDMI_MSM_CEC_CTRL_ENABLE			BIT(0)
-
-#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK		BIT(7)
-#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK		BIT(6)
-#define HDMI_MSM_CEC_INT_FRAME_RD_DONE_INT		BIT(6)
-#define HDMI_MSM_CEC_INT_MONITOR_MASK		BIT(5)
-#define HDMI_MSM_CEC_INT_MONITOR_ACK		BIT(4)
-#define HDMI_MSM_CEC_INT_MONITOR_INT		BIT(4)
-#define HDMI_MSM_CEC_INT_FRAME_ERROR_MASK		BIT(3)
-#define HDMI_MSM_CEC_INT_FRAME_ERROR_ACK		BIT(2)
-#define HDMI_MSM_CEC_INT_FRAME_ERROR_INT		BIT(2)
-#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK		BIT(1)
-#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK		BIT(0)
-#define HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT		BIT(0)
-
-#define HDMI_MSM_CEC_FRAME_WR_SUCCESS(___st)         (((___st)&0xB) ==\
-		(HDMI_MSM_CEC_INT_FRAME_WR_DONE_INT |\
-			HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK |\
-			HDMI_MSM_CEC_INT_FRAME_ERROR_MASK))
-
-#define HDMI_MSM_CEC_RETRANSMIT_NUM(___num)		(((___num)&0xF) << 4)
-#define HDMI_MSM_CEC_RETRANSMIT_ENABLE		BIT(0)
-
-#define HDMI_MSM_CEC_WR_DATA_DATA(___d)		(((___d)&0xFF) << 8)
-
-
-void hdmi_msm_cec_init(void)
-{
-	/* 0x02A8 CEC_REFTIMER */
-	HDMI_OUTP(0x02A8,
-		HDMI_MSM_CEC_REFTIMER_REFTIMER_ENABLE
-		| HDMI_MSM_CEC_REFTIMER_REFTIMER(27 * 50)
-		);
-
-	/*
-	 * 0x02A0 CEC_ADDR
-	 * Starting with a default address of 4
-	 */
-	HDMI_OUTP(0x02A0, HDMI_MSM_CEC_ADDR_LOGICAL_ADDR(4));
-
-	hdmi_msm_state->first_monitor = 0;
-	hdmi_msm_state->fsm_reset_done = false;
-
-	/* 0x029C CEC_INT */
-	/* Enable CEC interrupts */
-	HDMI_OUTP(0x029C,					\
-		  HDMI_MSM_CEC_INT_FRAME_WR_DONE_MASK		\
-		  | HDMI_MSM_CEC_INT_FRAME_ERROR_MASK		\
-		  | HDMI_MSM_CEC_INT_MONITOR_MASK		\
-		  | HDMI_MSM_CEC_INT_FRAME_RD_DONE_MASK);
-
-	HDMI_OUTP(0x02B0, 0x7FF << 4 | 1);
-
-	/*
-	 * Slight adjustment to logic 1 low periods on read,
-	 * CEC Test 8.2-3 was failing, 8 for the
-	 * BIT_1_ERR_RANGE_HI = 8 => 750us, the test used 775us,
-	 * so increased this to 9 which => 800us.
-	 */
-	/*
-	 * CEC latch up issue - To fire monitor interrupt
-	 * for every start of message
-	 */
-	HDMI_OUTP(0x02E0, 0x880000);
-
-	/*
-	 * Slight adjustment to logic 0 low period on write
-	 */
-	HDMI_OUTP(0x02DC, 0x8888A888);
-
-	/*
-	 * Enable Signal Free Time counter and set to 7 bit periods
-	 */
-	HDMI_OUTP(0x02A4, 0x1 | (7 * 0x30) << 7);
-
-	/* 0x028C CEC_CTRL */
-	HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-}
-
-void hdmi_msm_cec_write_logical_addr(int addr)
-{
-	/* 0x02A0 CEC_ADDR
-	 *   LOGICAL_ADDR       7:0  NUM
-	 */
-	HDMI_OUTP(0x02A0, addr & 0xFF);
-}
-
-void hdmi_msm_dump_cec_msg(struct hdmi_msm_cec_msg *msg)
-{
-#ifdef CEC_MSG_PRINT
-	int i;
-	DEV_DBG("sender_id     : %d", msg->sender_id);
-	DEV_DBG("recvr_id     : %d", msg->recvr_id);
-	if (msg->frame_size < 2) {
-		DEV_DBG("polling message");
-		return;
-	}
-	DEV_DBG("opcode      : %02x", msg->opcode);
-	for (i = 0; i < msg->frame_size - 2; i++)
-		DEV_DBG("operand(%2d) : %02x", i + 1, msg->operand[i]);
-#endif /* CEC_MSG_PRINT */
-}
-
-void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg)
-{
-	int i;
-	uint32 timeout_count = 1;
-	int retry = 10;
-
-	boolean frameType = (msg->recvr_id == 15 ? BIT(0) : 0);
-
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->fsm_reset_done = false;
-	mutex_unlock(&hdmi_msm_state_mutex);
-#ifdef TOGGLE_CEC_HARDWARE_FSM
-	msg_send_complete = FALSE;
-#endif
-
-	INIT_COMPLETION(hdmi_msm_state->cec_frame_wr_done);
-	hdmi_msm_state->cec_frame_wr_status = 0;
-
-	/* 0x0294 HDMI_MSM_CEC_RETRANSMIT */
-	HDMI_OUTP(0x0294,
-#ifdef DRVR_ONLY_CECT_NO_DAEMON
-		HDMI_MSM_CEC_RETRANSMIT_NUM(msg->retransmit)
-		| (msg->retransmit > 0) ? HDMI_MSM_CEC_RETRANSMIT_ENABLE : 0);
-#else
-		HDMI_MSM_CEC_RETRANSMIT_NUM(0) |
-			HDMI_MSM_CEC_RETRANSMIT_ENABLE);
-#endif
-
-	/* 0x028C CEC_CTRL */
-	HDMI_OUTP(0x028C, 0x1 | msg->frame_size << 4);
-
-	/* 0x0290 CEC_WR_DATA */
-
-	/* header block */
-	HDMI_OUTP(0x0290,
-		HDMI_MSM_CEC_WR_DATA_DATA(msg->sender_id << 4 | msg->recvr_id)
-		| frameType);
-
-	/* data block 0 : opcode */
-	HDMI_OUTP(0x0290,
-		HDMI_MSM_CEC_WR_DATA_DATA(msg->frame_size < 2 ? 0 : msg->opcode)
-		| frameType);
-
-	/* data block 1-14 : operand 0-13 */
-	for (i = 0; i < msg->frame_size - 1; i++)
-		HDMI_OUTP(0x0290,
-			HDMI_MSM_CEC_WR_DATA_DATA(msg->operand[i])
-			| (msg->recvr_id == 15 ? BIT(0) : 0));
-
-	for (; i < 14; i++)
-		HDMI_OUTP(0x0290,
-			HDMI_MSM_CEC_WR_DATA_DATA(0)
-			| (msg->recvr_id == 15 ? BIT(0) : 0));
-
-	while ((HDMI_INP(0x0298) & 1) && retry--) {
-		DEV_DBG("CEC line is busy(%d)\n", retry);
-		schedule();
-	}
-
-	/* 0x028C CEC_CTRL */
-	HDMI_OUTP(0x028C,
-		  HDMI_MSM_CEC_CTRL_LINE_OE
-		  | HDMI_MSM_CEC_CTRL_FRAME_SIZE(msg->frame_size)
-		  | HDMI_MSM_CEC_CTRL_SEND_TRIG
-		  | HDMI_MSM_CEC_CTRL_ENABLE);
-
-	timeout_count = wait_for_completion_interruptible_timeout(
-		&hdmi_msm_state->cec_frame_wr_done, HZ);
-
-	if (!timeout_count) {
-		hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_TMOUT;
-		DEV_ERR("%s: timedout", __func__);
-		hdmi_msm_dump_cec_msg(msg);
-	} else {
-		DEV_DBG("CEC write frame done (frame len=%d)",
-			msg->frame_size);
-		hdmi_msm_dump_cec_msg(msg);
-	}
-
-#ifdef TOGGLE_CEC_HARDWARE_FSM
-	if (!msg_recv_complete) {
-		/* Toggle CEC hardware FSM */
-		HDMI_OUTP(0x028C, 0x0);
-		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-		msg_recv_complete = TRUE;
-	}
-	msg_send_complete = TRUE;
-#else
-	HDMI_OUTP(0x028C, 0x0);
-	HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-#endif
-}
-
-void hdmi_msm_cec_line_latch_detect(void)
-{
-	/*
-	 * CECT 9-5-1
-	 * The timer period needs to be changed to appropriate value
-	 */
-	/*
-	 * Timedout without RD_DONE, WR_DONE or ERR_INT
-	 * Toggle CEC hardware FSM
-	 */
-	mutex_lock(&hdmi_msm_state_mutex);
-	if (hdmi_msm_state->first_monitor == 1) {
-		DEV_WARN("CEC line is probably latched up - CECT 9-5-1");
-		if (!msg_recv_complete)
-			hdmi_msm_state->fsm_reset_done = true;
-		HDMI_OUTP(0x028C, 0x0);
-		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-		hdmi_msm_state->first_monitor = 0;
-	}
-	mutex_unlock(&hdmi_msm_state_mutex);
-}
-
-void hdmi_msm_cec_msg_recv(void)
-{
-	uint32 data;
-	int i;
-#ifdef DRVR_ONLY_CECT_NO_DAEMON
-	struct hdmi_msm_cec_msg temp_msg;
-#endif
-	mutex_lock(&hdmi_msm_state_mutex);
-	if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd
-		&& hdmi_msm_state->cec_queue_full) {
-		mutex_unlock(&hdmi_msm_state_mutex);
-		DEV_ERR("CEC message queue is overflowing\n");
-#ifdef DRVR_ONLY_CECT_NO_DAEMON
-		/*
-		 * Without CEC daemon:
-		 * Compliance tests fail once the queue gets filled up.
-		 * so reset the pointers to the start of the queue.
-		 */
-		hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
-		hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
-		hdmi_msm_state->cec_queue_full = false;
-#else
-		return;
-#endif
-	}
-	if (hdmi_msm_state->cec_queue_wr == NULL) {
-		DEV_ERR("%s: wp is NULL\n", __func__);
-		return;
-	}
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	/* 0x02AC CEC_RD_DATA */
-	data = HDMI_INP(0x02AC);
-
-	hdmi_msm_state->cec_queue_wr->sender_id = (data & 0xF0) >> 4;
-	hdmi_msm_state->cec_queue_wr->recvr_id = (data & 0x0F);
-	hdmi_msm_state->cec_queue_wr->frame_size = (data & 0x1F00) >> 8;
-	DEV_DBG("Recvd init=[%u] dest=[%u] size=[%u]\n",
-		hdmi_msm_state->cec_queue_wr->sender_id,
-		hdmi_msm_state->cec_queue_wr->recvr_id,
-		hdmi_msm_state->cec_queue_wr->frame_size);
-
-	if (hdmi_msm_state->cec_queue_wr->frame_size < 1) {
-		DEV_ERR("%s: invalid message (frame length = %d)",
-			__func__, hdmi_msm_state->cec_queue_wr->frame_size);
-		return;
-	} else if (hdmi_msm_state->cec_queue_wr->frame_size == 1) {
-		DEV_DBG("%s: polling message (dest[%x] <- init[%x])",
-			__func__,
-			hdmi_msm_state->cec_queue_wr->recvr_id,
-			hdmi_msm_state->cec_queue_wr->sender_id);
-		return;
-	}
-
-	/* data block 0 : opcode */
-	data = HDMI_INP(0x02AC);
-	hdmi_msm_state->cec_queue_wr->opcode = data & 0xFF;
-
-	/* data block 1-14 : operand 0-13 */
-	for (i = 0; i < hdmi_msm_state->cec_queue_wr->frame_size - 2; i++) {
-		data = HDMI_INP(0x02AC);
-		hdmi_msm_state->cec_queue_wr->operand[i] = data & 0xFF;
-	}
-
-	for (; i < 14; i++)
-		hdmi_msm_state->cec_queue_wr->operand[i] = 0;
-
-	DEV_DBG("CEC read frame done\n");
-	DEV_DBG("=======================================\n");
-	hdmi_msm_dump_cec_msg(hdmi_msm_state->cec_queue_wr);
-	DEV_DBG("=======================================\n");
-
-#ifdef DRVR_ONLY_CECT_NO_DAEMON
-	switch (hdmi_msm_state->cec_queue_wr->opcode) {
-	case 0x64:
-		/* Set OSD String */
-		DEV_INFO("Recvd OSD Str=[%x]\n",\
-			hdmi_msm_state->cec_queue_wr->operand[3]);
-		break;
-	case 0x83:
-		/* Give Phy Addr */
-		DEV_INFO("Recvd a Give Phy Addr cmd\n");
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		/* Setup a frame for sending out phy addr */
-		temp_msg.sender_id = 0x4;
-
-		/* Broadcast */
-		temp_msg.recvr_id = 0xf;
-		temp_msg.opcode = 0x84;
-		i = 0;
-		temp_msg.operand[i++] = 0x10;
-		temp_msg.operand[i++] = 0x00;
-		temp_msg.operand[i++] = 0x04;
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-	case 0xFF:
-		/* Abort */
-		DEV_INFO("Recvd an abort cmd 0xFF\n");
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-
-		/*feature abort */
-		temp_msg.opcode = 0x00;
-		temp_msg.operand[i++] =
-			hdmi_msm_state->cec_queue_wr->opcode;
-
-		/*reason for abort = "Refused" */
-		temp_msg.operand[i++] = 0x04;
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_dump_cec_msg(&temp_msg);
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-	case 0x046:
-		/* Give OSD name */
-		DEV_INFO("Recvd cmd 0x046\n");
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-
-		/* OSD Name */
-		temp_msg.opcode = 0x47;
-
-		/* Display control byte */
-		temp_msg.operand[i++] = 0x00;
-		temp_msg.operand[i++] = 'H';
-		temp_msg.operand[i++] = 'e';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = ' ';
-		temp_msg.operand[i++] = 'W';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = 'r';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'd';
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-	case 0x08F:
-		/* Give Device Power status */
-		DEV_INFO("Recvd a Power status message\n");
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-
-		/* OSD String */
-		temp_msg.opcode = 0x90;
-		temp_msg.operand[i++] = 'H';
-		temp_msg.operand[i++] = 'e';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = ' ';
-		temp_msg.operand[i++] = 'W';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = 'r';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'd';
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-	case 0x080:
-		/* Routing Change cmd */
-	case 0x086:
-		/* Set Stream Path */
-		DEV_INFO("Recvd Set Stream\n");
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-
-		/*Broadcast this message*/
-		temp_msg.recvr_id = 0xf;
-		i = 0;
-		temp_msg.opcode = 0x82; /* Active Source */
-		temp_msg.operand[i++] = 0x10;
-		temp_msg.operand[i++] = 0x00;
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-
-		/*
-		 * sending <Image View On> message
-		 */
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-		/* opcode for Image View On */
-		temp_msg.opcode = 0x04;
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-	case 0x44:
-		/* User Control Pressed */
-		DEV_INFO("User Control Pressed\n");
-		break;
-	case 0x45:
-		/* User Control Released */
-		DEV_INFO("User Control Released\n");
-		break;
-	default:
-		DEV_INFO("Recvd an unknown cmd = [%u]\n",
-			hdmi_msm_state->cec_queue_wr->opcode);
-#ifdef __SEND_ABORT__
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-		/* opcode for feature abort */
-		temp_msg.opcode = 0x00;
-		temp_msg.operand[i++] =
-			hdmi_msm_state->cec_queue_wr->opcode;
-		/*reason for abort = "Unrecognized opcode" */
-		temp_msg.operand[i++] = 0x00;
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-#else
-		memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-		temp_msg.sender_id = 0x4;
-		temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-		i = 0;
-		/* OSD String */
-		temp_msg.opcode = 0x64;
-		temp_msg.operand[i++] = 0x0;
-		temp_msg.operand[i++] = 'H';
-		temp_msg.operand[i++] = 'e';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = ' ';
-		temp_msg.operand[i++] = 'W';
-		temp_msg.operand[i++] = 'o';
-		temp_msg.operand[i++] = 'r';
-		temp_msg.operand[i++] = 'l';
-		temp_msg.operand[i++] = 'd';
-		temp_msg.frame_size = i + 2;
-		hdmi_msm_cec_msg_send(&temp_msg);
-		break;
-#endif /* __SEND_ABORT__ */
-	}
-
-#endif /* DRVR_ONLY_CECT_NO_DAEMON */
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->cec_queue_wr++;
-	if (hdmi_msm_state->cec_queue_wr == CEC_QUEUE_END)
-		hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
-	if (hdmi_msm_state->cec_queue_wr == hdmi_msm_state->cec_queue_rd)
-		hdmi_msm_state->cec_queue_full = true;
-	mutex_unlock(&hdmi_msm_state_mutex);
-	DEV_DBG("Exiting %s()\n", __func__);
-}
-
-void hdmi_msm_cec_one_touch_play(void)
-{
-	struct hdmi_msm_cec_msg temp_msg;
-	uint32 i = 0;
-	memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-	temp_msg.sender_id = 0x4;
-	/*
-	 * Broadcast this message
-	 */
-	temp_msg.recvr_id = 0xf;
-	i = 0;
-	/* Active Source */
-	temp_msg.opcode = 0x82;
-	temp_msg.operand[i++] = 0x10;
-	temp_msg.operand[i++] = 0x00;
-	/*temp_msg.operand[i++] = 0x04;*/
-	temp_msg.frame_size = i + 2;
-	hdmi_msm_cec_msg_send(&temp_msg);
-	/*
-	 * sending <Image View On> message
-	 */
-	memset(&temp_msg, 0x00, sizeof(struct hdmi_msm_cec_msg));
-	temp_msg.sender_id = 0x4;
-	temp_msg.recvr_id = hdmi_msm_state->cec_queue_wr->sender_id;
-	i = 0;
-	/* Image View On */
-	temp_msg.opcode = 0x04;
-	temp_msg.frame_size = i + 2;
-	hdmi_msm_cec_msg_send(&temp_msg);
-
-}
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-uint32 hdmi_msm_get_io_base(void)
-{
-	return (uint32)MSM_HDMI_BASE;
-}
-EXPORT_SYMBOL(hdmi_msm_get_io_base);
-
-/* Table indicating the video format supported by the HDMI TX Core v1.0 */
-/* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
-static void hdmi_msm_setup_video_mode_lut(void)
-{
-	HDMI_SETUP_LUT(640x480p60_4_3);
-	HDMI_SETUP_LUT(720x480p60_4_3);
-	HDMI_SETUP_LUT(720x480p60_16_9);
-	HDMI_SETUP_LUT(1280x720p60_16_9);
-	HDMI_SETUP_LUT(1920x1080i60_16_9);
-	HDMI_SETUP_LUT(1440x480i60_4_3);
-	HDMI_SETUP_LUT(1440x480i60_16_9);
-	HDMI_SETUP_LUT(1920x1080p60_16_9);
-	HDMI_SETUP_LUT(720x576p50_4_3);
-	HDMI_SETUP_LUT(720x576p50_16_9);
-	HDMI_SETUP_LUT(1280x720p50_16_9);
-	HDMI_SETUP_LUT(1440x576i50_4_3);
-	HDMI_SETUP_LUT(1440x576i50_16_9);
-	HDMI_SETUP_LUT(1920x1080p50_16_9);
-	HDMI_SETUP_LUT(1920x1080p24_16_9);
-	HDMI_SETUP_LUT(1920x1080p25_16_9);
-	HDMI_SETUP_LUT(1920x1080p30_16_9);
-	HDMI_SETUP_LUT(1280x1024p60_5_4);
-}
-
-#ifdef PORT_DEBUG
-const char *hdmi_msm_name(uint32 offset)
-{
-	switch (offset) {
-	case 0x0000: return "CTRL";
-	case 0x0020: return "AUDIO_PKT_CTRL1";
-	case 0x0024: return "ACR_PKT_CTRL";
-	case 0x0028: return "VBI_PKT_CTRL";
-	case 0x002C: return "INFOFRAME_CTRL0";
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	case 0x0034: return "GEN_PKT_CTRL";
-#endif
-	case 0x003C: return "ACP";
-	case 0x0040: return "GC";
-	case 0x0044: return "AUDIO_PKT_CTRL2";
-	case 0x0048: return "ISRC1_0";
-	case 0x004C: return "ISRC1_1";
-	case 0x0050: return "ISRC1_2";
-	case 0x0054: return "ISRC1_3";
-	case 0x0058: return "ISRC1_4";
-	case 0x005C: return "ISRC2_0";
-	case 0x0060: return "ISRC2_1";
-	case 0x0064: return "ISRC2_2";
-	case 0x0068: return "ISRC2_3";
-	case 0x006C: return "AVI_INFO0";
-	case 0x0070: return "AVI_INFO1";
-	case 0x0074: return "AVI_INFO2";
-	case 0x0078: return "AVI_INFO3";
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	case 0x0084: return "GENERIC0_HDR";
-	case 0x0088: return "GENERIC0_0";
-	case 0x008C: return "GENERIC0_1";
-#endif
-	case 0x00C4: return "ACR_32_0";
-	case 0x00C8: return "ACR_32_1";
-	case 0x00CC: return "ACR_44_0";
-	case 0x00D0: return "ACR_44_1";
-	case 0x00D4: return "ACR_48_0";
-	case 0x00D8: return "ACR_48_1";
-	case 0x00E4: return "AUDIO_INFO0";
-	case 0x00E8: return "AUDIO_INFO1";
-	case 0x0110: return "HDCP_CTRL";
-	case 0x0114: return "HDCP_DEBUG_CTRL";
-	case 0x0118: return "HDCP_INT_CTRL";
-	case 0x011C: return "HDCP_LINK0_STATUS";
-	case 0x012C: return "HDCP_ENTROPY_CTRL0";
-	case 0x0130: return "HDCP_RESET";
-	case 0x0134: return "HDCP_RCVPORT_DATA0";
-	case 0x0138: return "HDCP_RCVPORT_DATA1";
-	case 0x013C: return "HDCP_RCVPORT_DATA2";
-	case 0x0144: return "HDCP_RCVPORT_DATA3";
-	case 0x0148: return "HDCP_RCVPORT_DATA4";
-	case 0x014C: return "HDCP_RCVPORT_DATA5";
-	case 0x0150: return "HDCP_RCVPORT_DATA6";
-	case 0x0168: return "HDCP_RCVPORT_DATA12";
-	case 0x01D0: return "AUDIO_CFG";
-	case 0x0208: return "USEC_REFTIMER";
-	case 0x020C: return "DDC_CTRL";
-	case 0x0214: return "DDC_INT_CTRL";
-	case 0x0218: return "DDC_SW_STATUS";
-	case 0x021C: return "DDC_HW_STATUS";
-	case 0x0220: return "DDC_SPEED";
-	case 0x0224: return "DDC_SETUP";
-	case 0x0228: return "DDC_TRANS0";
-	case 0x022C: return "DDC_TRANS1";
-	case 0x0238: return "DDC_DATA";
-	case 0x0250: return "HPD_INT_STATUS";
-	case 0x0254: return "HPD_INT_CTRL";
-	case 0x0258: return "HPD_CTRL";
-	case 0x025C: return "HDCP_ENTROPY_CTRL1";
-	case 0x027C: return "DDC_REF";
-	case 0x0284: return "HDCP_SW_UPPER_AKSV";
-	case 0x0288: return "HDCP_SW_LOWER_AKSV";
-	case 0x02B4: return "ACTIVE_H";
-	case 0x02B8: return "ACTIVE_V";
-	case 0x02BC: return "ACTIVE_V_F2";
-	case 0x02C0: return "TOTAL";
-	case 0x02C4: return "V_TOTAL_F2";
-	case 0x02C8: return "FRAME_CTRL";
-	case 0x02CC: return "AUD_INT";
-	case 0x0300: return "PHY_REG0";
-	case 0x0304: return "PHY_REG1";
-	case 0x0308: return "PHY_REG2";
-	case 0x030C: return "PHY_REG3";
-	case 0x0310: return "PHY_REG4";
-	case 0x0314: return "PHY_REG5";
-	case 0x0318: return "PHY_REG6";
-	case 0x031C: return "PHY_REG7";
-	case 0x0320: return "PHY_REG8";
-	case 0x0324: return "PHY_REG9";
-	case 0x0328: return "PHY_REG10";
-	case 0x032C: return "PHY_REG11";
-	case 0x0330: return "PHY_REG12";
-	default: return "???";
-	}
-}
-
-void hdmi_outp(uint32 offset, uint32 value)
-{
-	uint32 in_val;
-
-	outpdw(MSM_HDMI_BASE+offset, value);
-	in_val = inpdw(MSM_HDMI_BASE+offset);
-	DEV_DBG("HDMI[%04x] => %08x [%08x] %s\n",
-		offset, value, in_val, hdmi_msm_name(offset));
-}
-
-uint32 hdmi_inp(uint32 offset)
-{
-	uint32 value = inpdw(MSM_HDMI_BASE+offset);
-	DEV_DBG("HDMI[%04x] <= %08x %s\n",
-		offset, value, hdmi_msm_name(offset));
-	return value;
-}
-#endif /* DEBUG */
-
-static void hdmi_msm_turn_on(void);
-static int hdmi_msm_audio_off(void);
-static int hdmi_msm_read_edid(void);
-static void hdmi_msm_hpd_off(void);
-
-static bool hdmi_ready(void)
-{
-	return MSM_HDMI_BASE &&
-			hdmi_msm_state &&
-				hdmi_msm_state->hdmi_app_clk &&
-					hdmi_msm_state->hpd_initialized;
-}
-
-static void hdmi_msm_send_event(boolean on)
-{
-	char *envp[2];
-
-	/* QDSP OFF preceding the HPD event notification */
-	envp[0] = "HDCP_STATE=FAIL";
-	envp[1] = NULL;
-	DEV_ERR("hdmi: HDMI HPD: QDSP OFF\n");
-	kobject_uevent_env(external_common_state->uevent_kobj,
-			   KOBJ_CHANGE, envp);
-
-	if (on) {
-		/* Build EDID table */
-		hdmi_msm_read_edid();
-		switch_set_state(&external_common_state->sdev, 1);
-		DEV_INFO("%s: hdmi state switched to %d\n", __func__,
-				external_common_state->sdev.state);
-
-		DEV_INFO("HDMI HPD: CONNECTED: send ONLINE\n");
-		kobject_uevent(external_common_state->uevent_kobj, KOBJ_ONLINE);
-		if (!hdmi_msm_state->hdcp_enable) {
-			/* Send Audio for HDMI Compliance Cases*/
-			envp[0] = "HDCP_STATE=PASS";
-			envp[1] = NULL;
-			DEV_INFO("HDMI HPD: sense : send HDCP_PASS\n");
-			kobject_uevent_env(external_common_state->uevent_kobj,
-				KOBJ_CHANGE, envp);
-		}
-	} else {
-		switch_set_state(&external_common_state->sdev, 0);
-		DEV_INFO("%s: hdmi state switch to %d\n", __func__,
-				external_common_state->sdev.state);
-		DEV_INFO("hdmi: HDMI HPD: sense DISCONNECTED: send OFFLINE\n");
-		kobject_uevent(external_common_state->uevent_kobj,
-			KOBJ_OFFLINE);
-	}
-
-	if (!completion_done(&hdmi_msm_state->hpd_event_processed))
-		complete(&hdmi_msm_state->hpd_event_processed);
-}
-
-static void hdmi_msm_hpd_state_work(struct work_struct *work)
-{
-	if (!hdmi_ready()) {
-		DEV_ERR("hdmi: %s: ignored, probe failed\n", __func__);
-		return;
-	}
-
-	hdmi_msm_send_event(external_common_state->hpd_state);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-static void hdmi_msm_cec_latch_work(struct work_struct *work)
-{
-	hdmi_msm_cec_line_latch_detect();
-}
-#endif
-
-static void hdcp_deauthenticate(void);
-static void hdmi_msm_hdcp_reauth_work(struct work_struct *work)
-{
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	/* Don't process recursive actions */
-	mutex_lock(&hdmi_msm_state_mutex);
-	if (hdmi_msm_state->hdcp_activating) {
-		mutex_unlock(&hdmi_msm_state_mutex);
-		return;
-	}
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	/*
-	 * Reauth=>deauth, hdcp_auth
-	 * hdcp_auth=>turn_on() which calls
-	 * HDMI Core reset without informing the Audio QDSP
-	 * this can do bad things to video playback on the HDTV
-	 * Therefore, as surprising as it may sound do reauth
-	 * only if the device is HDCP-capable
-	 */
-	hdcp_deauthenticate();
-	mutex_lock(&hdcp_auth_state_mutex);
-	hdmi_msm_state->reauth = TRUE;
-	mutex_unlock(&hdcp_auth_state_mutex);
-	mod_timer(&hdmi_msm_state->hdcp_timer, jiffies + HZ/2);
-}
-
-static void hdmi_msm_hdcp_work(struct work_struct *work)
-{
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	/* Only re-enable if cable still connected */
-	mutex_lock(&external_common_state_hpd_mutex);
-	if (external_common_state->hpd_state &&
-	    !(hdmi_msm_state->full_auth_done)) {
-		mutex_unlock(&external_common_state_hpd_mutex);
-		if (hdmi_msm_state->reauth == TRUE) {
-			DEV_DBG("%s: Starting HDCP re-authentication\n",
-					__func__);
-			hdmi_msm_turn_on();
-		} else {
-			DEV_DBG("%s: Starting HDCP authentication\n", __func__);
-			hdmi_msm_hdcp_enable();
-		}
-	} else {
-		mutex_unlock(&external_common_state_hpd_mutex);
-		DEV_DBG("%s: HDMI not connected or HDCP already active\n",
-				__func__);
-		hdmi_msm_state->reauth = FALSE;
-	}
-}
-
-int hdmi_msm_process_hdcp_interrupts(void)
-{
-	int rc = -1;
-	uint32 hdcp_int_val;
-	char *envp[2];
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return -EINVAL;
-	}
-
-	/* HDCP_INT_CTRL[0x0118]
-	 *    [0] AUTH_SUCCESS_INT	[R]	HDCP Authentication Success
-	 *		interrupt status
-	 *    [1] AUTH_SUCCESS_ACK	[W]	Acknowledge bit for HDCP
-	 *		Authentication Success bit - write 1 to clear
-	 *    [2] AUTH_SUCCESS_MASK	[R/W]	Mask bit for HDCP Authentication
-	 *		Success interrupt - set to 1 to enable interrupt */
-	hdcp_int_val = HDMI_INP_ND(0x0118);
-	if ((hdcp_int_val & (1 << 2)) && (hdcp_int_val & (1 << 0))) {
-		/* AUTH_SUCCESS_INT */
-		HDMI_OUTP(0x0118, (hdcp_int_val | (1 << 1)) & ~(1 << 0));
-		DEV_INFO("HDCP: AUTH_SUCCESS_INT received\n");
-		complete_all(&hdmi_msm_state->hdcp_success_done);
-		return 0;
-	}
-
-	/*    [4] AUTH_FAIL_INT		[R]	HDCP Authentication Lost
-	 *		interrupt Status
-	 *    [5] AUTH_FAIL_ACK		[W]	Acknowledge bit for HDCP
-	 *		Authentication Lost bit - write 1 to clear
-	 *    [6] AUTH_FAIL_MASK	[R/W]	Mask bit fo HDCP Authentication
-	 *		Lost interrupt set to 1 to enable interrupt
-	 *    [7] AUTH_FAIL_INFO_ACK	[W]	Acknowledge bit for HDCP
-	 *		Authentication Failure Info field - write 1 to clear */
-	if ((hdcp_int_val & (1 << 6)) && (hdcp_int_val & (1 << 4))) {
-		/* AUTH_FAIL_INT */
-		/* Clear and Disable */
-		uint32 link_status = HDMI_INP_ND(0x011C);
-		HDMI_OUTP(0x0118, (hdcp_int_val | (1 << 5))
-			& ~((1 << 6) | (1 << 4)));
-		DEV_INFO("HDCP: AUTH_FAIL_INT received, LINK0_STATUS=0x%08x\n",
-			link_status);
-		if (hdmi_msm_state->full_auth_done) {
-			SWITCH_SET_HDMI_AUDIO(0, 0);
-
-			envp[0] = "HDCP_STATE=FAIL";
-			envp[1] = NULL;
-			DEV_INFO("HDMI HPD:QDSP OFF\n");
-			kobject_uevent_env(external_common_state->uevent_kobj,
-			KOBJ_CHANGE, envp);
-
-			mutex_lock(&hdcp_auth_state_mutex);
-			hdmi_msm_state->full_auth_done = FALSE;
-			mutex_unlock(&hdcp_auth_state_mutex);
-			/* Calling reauth only when authentication
-			 * is sucessful or else we always go into
-			 * the reauth loop. Also, No need to reauthenticate
-			 * if authentication failed because of cable disconnect
-			 */
-			if (((link_status & 0xF0) >> 4) != 0x7) {
-				DEV_DBG("Reauthenticate From %s HDCP FAIL INT ",
-					__func__);
-				queue_work(hdmi_work_queue,
-				    &hdmi_msm_state->hdcp_reauth_work);
-			} else {
-				DEV_INFO("HDCP: HDMI cable disconnected\n");
-			}
-		}
-
-		/* Clear AUTH_FAIL_INFO as well */
-		HDMI_OUTP(0x0118, (hdcp_int_val | (1 << 7)));
-		return 0;
-	}
-
-	/*    [8] DDC_XFER_REQ_INT	[R]	HDCP DDC Transfer Request
-	 *		interrupt status
-	 *    [9] DDC_XFER_REQ_ACK	[W]	Acknowledge bit for HDCP DDC
-	 *		Transfer Request bit - write 1 to clear
-	 *   [10] DDC_XFER_REQ_MASK	[R/W]	Mask bit for HDCP DDC Transfer
-	 *		Request interrupt - set to 1 to enable interrupt */
-	if ((hdcp_int_val & (1 << 10)) && (hdcp_int_val & (1 << 8))) {
-		/* DDC_XFER_REQ_INT */
-		HDMI_OUTP_ND(0x0118, (hdcp_int_val | (1 << 9)) & ~(1 << 8));
-		if (!(hdcp_int_val & (1 << 12)))
-			return 0;
-	}
-	/*   [12] DDC_XFER_DONE_INT	[R]	HDCP DDC Transfer done interrupt
-	 *		status
-	 *   [13] DDC_XFER_DONE_ACK	[W]	Acknowledge bit for HDCP DDC
-	 *		Transfer done bit - write 1 to clear
-	 *   [14] DDC_XFER_DONE_MASK	[R/W]	Mask bit for HDCP DDC Transfer
-	 *		done interrupt - set to 1 to enable interrupt */
-	if ((hdcp_int_val & (1 << 14)) && (hdcp_int_val & (1 << 12))) {
-		/* DDC_XFER_DONE_INT */
-		HDMI_OUTP_ND(0x0118, (hdcp_int_val | (1 << 13)) & ~(1 << 12));
-		DEV_INFO("HDCP: DDC_XFER_DONE received\n");
-		return 0;
-	}
-
-	return rc;
-}
-
-static irqreturn_t hdmi_msm_isr(int irq, void *dev_id)
-{
-	uint32 hpd_int_status;
-	uint32 hpd_int_ctrl;
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	uint32 cec_intr_status;
-#endif
-	uint32 ddc_int_ctrl;
-	uint32 audio_int_val;
-	static uint32 fifo_urun_int_occurred;
-	static uint32 sample_drop_int_occurred;
-	const uint32 occurrence_limit = 5;
-
-	if (!hdmi_ready()) {
-		DEV_DBG("ISR ignored, probe failed\n");
-		return IRQ_HANDLED;
-	}
-
-	/* Process HPD Interrupt */
-	/* HDMI_HPD_INT_STATUS[0x0250] */
-	hpd_int_status = HDMI_INP_ND(0x0250);
-	/* HDMI_HPD_INT_CTRL[0x0254] */
-	hpd_int_ctrl = HDMI_INP_ND(0x0254);
-	if ((hpd_int_ctrl & (1 << 2)) && (hpd_int_status & (1 << 0))) {
-		/*
-		 * Got HPD interrupt. Ack the interrupt and disable any
-		 * further HPD interrupts until we process this interrupt.
-		 */
-		HDMI_OUTP(0x0254, ((hpd_int_ctrl | (BIT(0))) & ~BIT(2)));
-
-		external_common_state->hpd_state =
-			(HDMI_INP(0x0250) & BIT(1)) >> 1;
-		DEV_DBG("%s: Queuing work to handle HPD %s event\n", __func__,
-				external_common_state->hpd_state ? "connect" :
-				"disconnect");
-		queue_work(hdmi_work_queue, &hdmi_msm_state->hpd_state_work);
-		return IRQ_HANDLED;
-	}
-
-	/* Process DDC Interrupts */
-	/* HDMI_DDC_INT_CTRL[0x0214] */
-	ddc_int_ctrl = HDMI_INP_ND(0x0214);
-	if ((ddc_int_ctrl & (1 << 2)) && (ddc_int_ctrl & (1 << 0))) {
-		/* SW_DONE INT occured, clr it */
-		HDMI_OUTP_ND(0x0214, ddc_int_ctrl | (1 << 1));
-		complete(&hdmi_msm_state->ddc_sw_done);
-		return IRQ_HANDLED;
-	}
-
-	/* FIFO Underrun Int is enabled */
-	/* HDMI_AUD_INT[0x02CC]
-	 *   [3] AUD_SAM_DROP_MASK [R/W]
-	 *   [2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
-	 *   [1] AUD_FIFO_URUN_MASK [R/W]
-	 *   [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R] */
-	audio_int_val = HDMI_INP_ND(0x02CC);
-	if ((audio_int_val & (1 << 1)) && (audio_int_val & (1 << 0))) {
-		/* FIFO Underrun occured, clr it */
-		HDMI_OUTP(0x02CC, audio_int_val | (1 << 0));
-
-		++fifo_urun_int_occurred;
-		DEV_INFO("HDMI AUD_FIFO_URUN: %d\n", fifo_urun_int_occurred);
-
-		if (fifo_urun_int_occurred >= occurrence_limit) {
-			HDMI_OUTP(0x02CC, HDMI_INP(0x02CC) & ~(1 << 1));
-			DEV_INFO("HDMI AUD_FIFO_URUN: INT has been disabled "
-				"by the ISR after %d occurences...\n",
-				fifo_urun_int_occurred);
-		}
-		return IRQ_HANDLED;
-	}
-
-	/* Audio Sample Drop int is enabled */
-	if ((audio_int_val & (1 << 3)) && (audio_int_val & (1 << 2))) {
-		/* Audio Sample Drop occured, clr it */
-		HDMI_OUTP(0x02CC, audio_int_val | (1 << 2));
-		DEV_DBG("%s: AUD_SAM_DROP", __func__);
-
-		++sample_drop_int_occurred;
-		if (sample_drop_int_occurred >= occurrence_limit) {
-			HDMI_OUTP(0x02CC, HDMI_INP(0x02CC) & ~(1 << 3));
-			DEV_INFO("HDMI AUD_SAM_DROP: INT has been disabled "
-				"by the ISR after %d occurences...\n",
-				sample_drop_int_occurred);
-		}
-		return IRQ_HANDLED;
-	}
-
-	if (!hdmi_msm_process_hdcp_interrupts())
-		return IRQ_HANDLED;
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	/* Process CEC Interrupt */
-	/* HDMI_MSM_CEC_INT[0x029C] */
-	cec_intr_status = HDMI_INP_ND(0x029C);
-
-	DEV_DBG("cec interrupt status is [%u]\n", cec_intr_status);
-
-	if (HDMI_MSM_CEC_FRAME_WR_SUCCESS(cec_intr_status)) {
-		DEV_DBG("CEC_IRQ_FRAME_WR_DONE\n");
-		HDMI_OUTP(0x029C, cec_intr_status |
-			HDMI_MSM_CEC_INT_FRAME_WR_DONE_ACK);
-		mutex_lock(&hdmi_msm_state_mutex);
-		hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_DONE;
-		hdmi_msm_state->first_monitor = 0;
-		del_timer(&hdmi_msm_state->cec_read_timer);
-		mutex_unlock(&hdmi_msm_state_mutex);
-		complete(&hdmi_msm_state->cec_frame_wr_done);
-		return IRQ_HANDLED;
-	}
-	if ((cec_intr_status & (1 << 2)) && (cec_intr_status & (1 << 3))) {
-		DEV_DBG("CEC_IRQ_FRAME_ERROR\n");
-#ifdef TOGGLE_CEC_HARDWARE_FSM
-		/* Toggle CEC hardware FSM */
-		HDMI_OUTP(0x028C, 0x0);
-		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-#endif
-		HDMI_OUTP(0x029C, cec_intr_status);
-		mutex_lock(&hdmi_msm_state_mutex);
-		hdmi_msm_state->first_monitor = 0;
-		del_timer(&hdmi_msm_state->cec_read_timer);
-		hdmi_msm_state->cec_frame_wr_status |= CEC_STATUS_WR_ERROR;
-		mutex_unlock(&hdmi_msm_state_mutex);
-		complete(&hdmi_msm_state->cec_frame_wr_done);
-		return IRQ_HANDLED;
-	}
-
-	if ((cec_intr_status & (1 << 4)) && (cec_intr_status & (1 << 5))) {
-		DEV_DBG("CEC_IRQ_MONITOR\n");
-		HDMI_OUTP(0x029C, cec_intr_status |
-			  HDMI_MSM_CEC_INT_MONITOR_ACK);
-
-		/*
-		 * CECT 9-5-1
-		 * On the first occassion start a timer
-		 * for few hundred ms, if it expires then
-		 * reset the CEC block else go on with
-		 * frame transactions as usual.
-		 * Below adds hdmi_msm_cec_msg_recv() as an
-		 * item into the work queue instead of running in
-		 * interrupt context
-		 */
-		mutex_lock(&hdmi_msm_state_mutex);
-		if (hdmi_msm_state->first_monitor == 0) {
-			/* This timer might have to be changed
-			 * worst case theoritical =
-			 * 16 bytes * 8 * 2.7msec = 346 msec
-			 */
-			mod_timer(&hdmi_msm_state->cec_read_timer,
-					jiffies + HZ/2);
-			hdmi_msm_state->first_monitor = 1;
-		}
-		mutex_unlock(&hdmi_msm_state_mutex);
-		return IRQ_HANDLED;
-	}
-
-	if ((cec_intr_status & (1 << 6)) && (cec_intr_status & (1 << 7))) {
-		DEV_DBG("CEC_IRQ_FRAME_RD_DONE\n");
-
-		mutex_lock(&hdmi_msm_state_mutex);
-		hdmi_msm_state->first_monitor = 0;
-		del_timer(&hdmi_msm_state->cec_read_timer);
-		mutex_unlock(&hdmi_msm_state_mutex);
-		HDMI_OUTP(0x029C, cec_intr_status |
-			HDMI_MSM_CEC_INT_FRAME_RD_DONE_ACK);
-		hdmi_msm_cec_msg_recv();
-
-#ifdef TOGGLE_CEC_HARDWARE_FSM
-		if (!msg_send_complete)
-			msg_recv_complete = FALSE;
-		else {
-			/* Toggle CEC hardware FSM */
-			HDMI_OUTP(0x028C, 0x0);
-			HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-		}
-#else
-		HDMI_OUTP(0x028C, 0x0);
-		HDMI_OUTP(0x028C, HDMI_MSM_CEC_CTRL_ENABLE);
-#endif
-
-		return IRQ_HANDLED;
-	}
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-	DEV_DBG("%s: HPD<Ctrl=%04x, State=%04x>, ddc_int_ctrl=%04x, "
-		"aud_int=%04x, cec_intr_status=%04x\n", __func__, hpd_int_ctrl,
-		hpd_int_status, ddc_int_ctrl, audio_int_val,
-		HDMI_INP_ND(0x029C));
-
-	return IRQ_HANDLED;
-}
-
-static int check_hdmi_features(void)
-{
-	/* RAW_FEAT_CONFIG_ROW0_LSB */
-	uint32 val = inpdw(QFPROM_BASE + 0x0238);
-	/* HDMI_DISABLE */
-	boolean hdmi_disabled = (val & 0x00200000) >> 21;
-	/* HDCP_DISABLE */
-	boolean hdcp_disabled = (val & 0x00400000) >> 22;
-
-	DEV_DBG("Features <val:0x%08x, HDMI:%s, HDCP:%s>\n", val,
-		hdmi_disabled ? "OFF" : "ON", hdcp_disabled ? "OFF" : "ON");
-	if (hdmi_disabled) {
-		DEV_ERR("ERROR: HDMI disabled\n");
-		return -ENODEV;
-	}
-
-	if (hdcp_disabled)
-		DEV_WARN("WARNING: HDCP disabled\n");
-
-	return 0;
-}
-
-static boolean hdmi_msm_has_hdcp(void)
-{
-	/* RAW_FEAT_CONFIG_ROW0_LSB, HDCP_DISABLE */
-	return (inpdw(QFPROM_BASE + 0x0238) & 0x00400000) ? FALSE : TRUE;
-}
-
-static boolean hdmi_msm_is_power_on(void)
-{
-	/* HDMI_CTRL, ENABLE */
-	return (HDMI_INP_ND(0x0000) & 0x00000001) ? TRUE : FALSE;
-}
-
-/* 1.2.1.2.1 DVI Operation
- * HDMI compliance requires the HDMI core to support DVI as well. The
- * HDMI core also supports DVI. In DVI operation there are no preambles
- * and guardbands transmitted. THe TMDS encoding of video data remains
- * the same as HDMI. There are no VBI or audio packets transmitted. In
- * order to enable DVI mode in HDMI core, HDMI_DVI_SEL field of
- * HDMI_CTRL register needs to be programmed to 0. */
-static boolean hdmi_msm_is_dvi_mode(void)
-{
-	/* HDMI_CTRL, HDMI_DVI_SEL */
-	return (HDMI_INP_ND(0x0000) & 0x00000002) ? FALSE : TRUE;
-}
-
-void hdmi_msm_set_mode(boolean power_on)
-{
-	uint32 reg_val = 0;
-	if (power_on) {
-		/* ENABLE */
-		reg_val |= 0x00000001; /* Enable the block */
-		if (external_common_state->hdmi_sink == 0) {
-			/* HDMI_DVI_SEL */
-			reg_val |= 0x00000002;
-			if (hdmi_msm_state->hdcp_enable)
-				/* HDMI Encryption */
-				reg_val |= 0x00000004;
-			/* HDMI_CTRL */
-			HDMI_OUTP(0x0000, reg_val);
-			/* HDMI_DVI_SEL */
-			reg_val &= ~0x00000002;
-		} else {
-			if (hdmi_msm_state->hdcp_enable)
-				/* HDMI_Encryption_ON */
-				reg_val |= 0x00000006;
-			else
-				reg_val |= 0x00000002;
-		}
-	} else
-		reg_val = 0x00000002;
-
-	/* HDMI_CTRL */
-	HDMI_OUTP(0x0000, reg_val);
-	DEV_DBG("HDMI Core: %s, HDMI_CTRL=0x%08x\n",
-			power_on ? "Enable" : "Disable", reg_val);
-}
-
-static void msm_hdmi_init_ddc(void)
-{
-	/* 0x0220 HDMI_DDC_SPEED
-	   [31:16] PRESCALE prescale = (m * xtal_frequency) /
-		(desired_i2c_speed), where m is multiply
-		factor, default: m = 1
-	   [1:0]   THRESHOLD Select threshold to use to determine whether value
-		sampled on SDA is a 1 or 0. Specified in terms of the ratio
-		between the number of sampled ones and the total number of times
-		SDA is sampled.
-		* 0x0: >0
-		* 0x1: 1/4 of total samples
-		* 0x2: 1/2 of total samples
-		* 0x3: 3/4 of total samples */
-	/* Configure the Pre-Scale multiplier
-	 * Configure the Threshold */
-	HDMI_OUTP_ND(0x0220, (10 << 16) | (2 << 0));
-
-	/*
-	 * 0x0224 HDMI_DDC_SETUP
-	 * Setting 31:24 bits : Time units to wait before timeout
-	 * when clock is being stalled by external sink device
-	 */
-	HDMI_OUTP_ND(0x0224, 0xff000000);
-
-	/* 0x027C HDMI_DDC_REF
-	   [6] REFTIMER_ENABLE	Enable the timer
-		* 0: Disable
-		* 1: Enable
-	   [15:0] REFTIMER	Value to set the register in order to generate
-		DDC strobe. This register counts on HDCP application clock */
-	/* Enable reference timer
-	 * 27 micro-seconds */
-	HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
-}
-
-static int hdmi_msm_ddc_clear_irq(const char *what)
-{
-	const uint32 time_out = 0xFFFF;
-	uint32 time_out_count, reg_val;
-
-	/* clear pending and enable interrupt */
-	time_out_count = time_out;
-	do {
-		--time_out_count;
-		/* HDMI_DDC_INT_CTRL[0x0214]
-		   [2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
-		       interrupt.
-		   [1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
-		       Write 1 to clear interrupt.
-		   [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
-		/* Clear and Enable DDC interrupt */
-		/* Write */
-		HDMI_OUTP_ND(0x0214, (1 << 2) | (1 << 1));
-		/* Read back */
-		reg_val = HDMI_INP_ND(0x0214);
-	} while ((reg_val & 0x1) && time_out_count);
-	if (!time_out_count) {
-		DEV_ERR("%s[%s]: timedout\n", __func__, what);
-		return -ETIMEDOUT;
-	}
-
-	return 0;
-}
-
-static int hdmi_msm_ddc_write(uint32 dev_addr, uint32 offset,
-	const uint8 *data_buf, uint32 data_len, const char *what)
-{
-	uint32 reg_val, ndx;
-	int status = 0, retry = 10;
-	uint32 time_out_count;
-
-	if (NULL == data_buf) {
-		status = -EINVAL;
-		DEV_ERR("%s[%s]: invalid input paramter\n", __func__, what);
-		goto error;
-	}
-
-again:
-	status = hdmi_msm_ddc_clear_irq(what);
-	if (status)
-		goto error;
-
-	/* Ensure Device Address has LSB set to 0 to indicate Slave addr read */
-	dev_addr &= 0xFE;
-
-	/* 0x0238 HDMI_DDC_DATA
-	   [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
-		1 while writing HDMI_DDC_DATA.
-	   [23:16] INDEX Use to set index into DDC buffer for next read or
-		current write, or to read index of current read or next write.
-		Writable only when INDEX_WRITE=1.
-	   [15:8] DATA Use to fill or read the DDC buffer
-	   [0] DATA_RW Select whether buffer access will be a read or write.
-		For writes, address auto-increments on write to HDMI_DDC_DATA.
-		For reads, address autoincrements on reads to HDMI_DDC_DATA.
-		* 0: Write
-		* 1: Read */
-
-	/* 1. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #1
-	 *    DATA_RW = 0x1 (write)
-	 *    DATA = linkAddress (primary link address and writing)
-	 *    INDEX = 0x0 (initial offset into buffer)
-	 *    INDEX_WRITE = 0x1 (setting initial offset) */
-	HDMI_OUTP_ND(0x0238, (0x1UL << 31) | (dev_addr << 8));
-
-	/* 2. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #2
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = offsetAddress
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	HDMI_OUTP_ND(0x0238, offset << 8);
-
-	/* 3. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #3
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = data_buf[ndx]
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	for (ndx = 0; ndx < data_len; ++ndx)
-		HDMI_OUTP_ND(0x0238, ((uint32)data_buf[ndx]) << 8);
-
-	/* Data setup is complete, now setup the transaction characteristics */
-
-	/* 0x0228 HDMI_DDC_TRANS0
-	   [23:16] CNT0 Byte count for first transaction (excluding the first
-		byte, which is usually the address).
-	   [13] STOP0 Determines whether a stop bit will be sent after the first
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	   [12] START0 Determines whether a start bit will be sent before the
-		first transaction
-		* 0: NO START
-		* 1: START
-	   [8] STOP_ON_NACK0 Determines whether the current transfer will stop
-		if a NACK is received during the first transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	   [0] RW0 Read/write indicator for first transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 4. Write to HDMI_I2C_TRANSACTION0 with the following fields set in
-	      order to handle characteristics of portion #1 and portion #2
-	 *    RW0 = 0x0 (write)
-	 *    START0 = 0x1 (insert START bit)
-	 *    STOP0 = 0x0 (do NOT insert STOP bit)
-	 *    CNT0 = 0x1 (single byte transaction excluding address) */
-	HDMI_OUTP_ND(0x0228, (1 << 12) | (1 << 16));
-
-	/* 0x022C HDMI_DDC_TRANS1
-	  [23:16] CNT1 Byte count for second transaction (excluding the first
-		byte, which is usually the address).
-	  [13] STOP1 Determines whether a stop bit will be sent after the second
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	  [12] START1 Determines whether a start bit will be sent before the
-		second transaction
-		* 0: NO START
-		* 1: START
-	  [8] STOP_ON_NACK1 Determines whether the current transfer will stop if
-		a NACK is received during the second transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	  [0] RW1 Read/write indicator for second transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
-	      order to handle characteristics of portion #3
-	 *    RW1 = 0x1 (read)
-	 *    START1 = 0x1 (insert START bit)
-	 *    STOP1 = 0x1 (insert STOP bit)
-	 *    CNT1 = data_len   (0xN (write N bytes of data))
-	 *    Byte count for second transition (excluding the first
-	 *    Byte which is usually the address) */
-	HDMI_OUTP_ND(0x022C, (1 << 13) | ((data_len-1) << 16));
-
-	/* Trigger the I2C transfer */
-	/* 0x020C HDMI_DDC_CTRL
-	   [21:20] TRANSACTION_CNT
-		Number of transactions to be done in current transfer.
-		* 0x0: transaction0 only
-		* 0x1: transaction0, transaction1
-		* 0x2: transaction0, transaction1, transaction2
-		* 0x3: transaction0, transaction1, transaction2, transaction3
-	   [3] SW_STATUS_RESET
-		Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
-		ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
-		STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
-	   [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
-		data) at start of transfer.  This sequence is sent after GO is
-		written to 1, before the first transaction only.
-	   [1] SOFT_RESET Write 1 to reset DDC controller
-	   [0] GO WRITE ONLY. Write 1 to start DDC transfer. */
-
-	/* 6. Write to HDMI_I2C_CONTROL to kick off the hardware.
-	 *    Note that NOTHING has been transmitted on the DDC lines up to this
-	 *    point.
-	 *    TRANSACTION_CNT = 0x1 (execute transaction0 followed by
-	 *    transaction1)
-	 *    GO = 0x1 (kicks off hardware) */
-	INIT_COMPLETION(hdmi_msm_state->ddc_sw_done);
-	HDMI_OUTP_ND(0x020C, (1 << 0) | (1 << 20));
-
-	time_out_count = wait_for_completion_interruptible_timeout(
-		&hdmi_msm_state->ddc_sw_done, HZ/2);
-	HDMI_OUTP_ND(0x0214, 0x2);
-	if (!time_out_count) {
-		if (retry-- > 0) {
-			DEV_INFO("%s[%s]: failed timout, retry=%d\n", __func__,
-				what, retry);
-			goto again;
-		}
-		status = -ETIMEDOUT;
-		DEV_ERR("%s[%s]: timedout, DDC SW Status=%08x, HW "
-			"Status=%08x, Int Ctrl=%08x\n", __func__, what,
-			HDMI_INP_ND(0x0218), HDMI_INP_ND(0x021C),
-			HDMI_INP_ND(0x0214));
-		goto error;
-	}
-
-	/* Read DDC status */
-	reg_val = HDMI_INP_ND(0x0218);
-	reg_val &= 0x00001000 | 0x00002000 | 0x00004000 | 0x00008000;
-
-	/* Check if any NACK occurred */
-	if (reg_val) {
-		if (retry > 1)
-			HDMI_OUTP_ND(0x020C, BIT(3)); /* SW_STATUS_RESET */
-		else
-			HDMI_OUTP_ND(0x020C, BIT(1)); /* SOFT_RESET */
-		if (retry-- > 0) {
-			DEV_DBG("%s[%s]: failed NACK=%08x, retry=%d\n",
-				__func__, what, reg_val, retry);
-			msleep(100);
-			goto again;
-		}
-		status = -EIO;
-		DEV_ERR("%s[%s]: failed NACK: %08x\n", __func__, what, reg_val);
-		goto error;
-	}
-
-	DEV_DBG("%s[%s] success\n", __func__, what);
-
-error:
-	return status;
-}
-
-static int hdmi_msm_ddc_read_retry(uint32 dev_addr, uint32 offset,
-	uint8 *data_buf, uint32 data_len, uint32 request_len, int retry,
-	const char *what)
-{
-	uint32 reg_val, ndx;
-	int status = 0;
-	uint32 time_out_count;
-	int log_retry_fail = retry != 1;
-
-	if (NULL == data_buf) {
-		status = -EINVAL;
-		DEV_ERR("%s: invalid input paramter\n", __func__);
-		goto error;
-	}
-
-again:
-	status = hdmi_msm_ddc_clear_irq(what);
-	if (status)
-		goto error;
-
-	/* Ensure Device Address has LSB set to 0 to indicate Slave addr read */
-	dev_addr &= 0xFE;
-
-	/* 0x0238 HDMI_DDC_DATA
-	   [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
-		1 while writing HDMI_DDC_DATA.
-	   [23:16] INDEX Use to set index into DDC buffer for next read or
-		current write, or to read index of current read or next write.
-		Writable only when INDEX_WRITE=1.
-	   [15:8] DATA Use to fill or read the DDC buffer
-	   [0] DATA_RW Select whether buffer access will be a read or write.
-		For writes, address auto-increments on write to HDMI_DDC_DATA.
-		For reads, address autoincrements on reads to HDMI_DDC_DATA.
-		* 0: Write
-		* 1: Read */
-
-	/* 1. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #1
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = linkAddress (primary link address and writing)
-	 *    INDEX = 0x0 (initial offset into buffer)
-	 *    INDEX_WRITE = 0x1 (setting initial offset) */
-	HDMI_OUTP_ND(0x0238, (0x1UL << 31) | (dev_addr << 8));
-
-	/* 2. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #2
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = offsetAddress
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	HDMI_OUTP_ND(0x0238, offset << 8);
-
-	/* 3. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #3
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = linkAddress + 1 (primary link address 0x74 and reading)
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	HDMI_OUTP_ND(0x0238, (dev_addr | 1) << 8);
-
-	/* Data setup is complete, now setup the transaction characteristics */
-
-	/* 0x0228 HDMI_DDC_TRANS0
-	   [23:16] CNT0 Byte count for first transaction (excluding the first
-		byte, which is usually the address).
-	   [13] STOP0 Determines whether a stop bit will be sent after the first
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	   [12] START0 Determines whether a start bit will be sent before the
-		first transaction
-		* 0: NO START
-		* 1: START
-	   [8] STOP_ON_NACK0 Determines whether the current transfer will stop
-		if a NACK is received during the first transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	   [0] RW0 Read/write indicator for first transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 4. Write to HDMI_I2C_TRANSACTION0 with the following fields set in
-	      order to handle characteristics of portion #1 and portion #2
-	 *    RW0 = 0x0 (write)
-	 *    START0 = 0x1 (insert START bit)
-	 *    STOP0 = 0x0 (do NOT insert STOP bit)
-	 *    CNT0 = 0x1 (single byte transaction excluding address) */
-	HDMI_OUTP_ND(0x0228, (1 << 12) | (1 << 16));
-
-	/* 0x022C HDMI_DDC_TRANS1
-	  [23:16] CNT1 Byte count for second transaction (excluding the first
-		byte, which is usually the address).
-	  [13] STOP1 Determines whether a stop bit will be sent after the second
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	  [12] START1 Determines whether a start bit will be sent before the
-		second transaction
-		* 0: NO START
-		* 1: START
-	  [8] STOP_ON_NACK1 Determines whether the current transfer will stop if
-		a NACK is received during the second transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	  [0] RW1 Read/write indicator for second transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
-	      order to handle characteristics of portion #3
-	 *    RW1 = 0x1 (read)
-	 *    START1 = 0x1 (insert START bit)
-	 *    STOP1 = 0x1 (insert STOP bit)
-	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read) */
-	HDMI_OUTP_ND(0x022C, 1 | (1 << 12) | (1 << 13) | (request_len << 16));
-
-	/* Trigger the I2C transfer */
-	/* 0x020C HDMI_DDC_CTRL
-	   [21:20] TRANSACTION_CNT
-		Number of transactions to be done in current transfer.
-		* 0x0: transaction0 only
-		* 0x1: transaction0, transaction1
-		* 0x2: transaction0, transaction1, transaction2
-		* 0x3: transaction0, transaction1, transaction2, transaction3
-	   [3] SW_STATUS_RESET
-		Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
-		ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
-		STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
-	   [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
-		data) at start of transfer.  This sequence is sent after GO is
-		written to 1, before the first transaction only.
-	   [1] SOFT_RESET Write 1 to reset DDC controller
-	   [0] GO WRITE ONLY. Write 1 to start DDC transfer. */
-
-	/* 6. Write to HDMI_I2C_CONTROL to kick off the hardware.
-	 *    Note that NOTHING has been transmitted on the DDC lines up to this
-	 *    point.
-	 *    TRANSACTION_CNT = 0x1 (execute transaction0 followed by
-	 *    transaction1)
-	 *    SEND_RESET = Set to 1 to send reset sequence
-	 *    GO = 0x1 (kicks off hardware) */
-	INIT_COMPLETION(hdmi_msm_state->ddc_sw_done);
-	HDMI_OUTP_ND(0x020C, (1 << 0) | (1 << 20));
-
-	time_out_count = wait_for_completion_interruptible_timeout(
-		&hdmi_msm_state->ddc_sw_done, HZ/2);
-	HDMI_OUTP_ND(0x0214, 0x2);
-	if (!time_out_count) {
-		if (retry-- > 0) {
-			DEV_INFO("%s: failed timout, retry=%d\n", __func__,
-				retry);
-			goto again;
-		}
-		status = -ETIMEDOUT;
-		DEV_ERR("%s: timedout(7), DDC SW Status=%08x, HW "
-			"Status=%08x, Int Ctrl=%08x\n", __func__,
-			HDMI_INP(0x0218), HDMI_INP(0x021C), HDMI_INP(0x0214));
-		goto error;
-	}
-
-	/* Read DDC status */
-	reg_val = HDMI_INP_ND(0x0218);
-	reg_val &= 0x00001000 | 0x00002000 | 0x00004000 | 0x00008000;
-
-	/* Check if any NACK occurred */
-	if (reg_val) {
-		HDMI_OUTP_ND(0x020C, BIT(3)); /* SW_STATUS_RESET */
-		if (retry == 1)
-			HDMI_OUTP_ND(0x020C, BIT(1)); /* SOFT_RESET */
-		if (retry-- > 0) {
-			DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d, "
-				"dev-addr=0x%02x, offset=0x%02x, "
-				"length=%d\n", __func__, what,
-				reg_val, retry, dev_addr,
-				offset, data_len);
-			goto again;
-		}
-		status = -EIO;
-		if (log_retry_fail)
-			DEV_ERR("%s(%s): failed NACK=0x%08x, dev-addr=0x%02x, "
-				"offset=0x%02x, length=%d\n", __func__, what,
-				reg_val, dev_addr, offset, data_len);
-		goto error;
-	}
-
-	/* 0x0238 HDMI_DDC_DATA
-	   [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to 1
-		while writing HDMI_DDC_DATA.
-	   [23:16] INDEX Use to set index into DDC buffer for next read or
-		current write, or to read index of current read or next write.
-		Writable only when INDEX_WRITE=1.
-	   [15:8] DATA Use to fill or read the DDC buffer
-	   [0] DATA_RW Select whether buffer access will be a read or write.
-		For writes, address auto-increments on write to HDMI_DDC_DATA.
-		For reads, address autoincrements on reads to HDMI_DDC_DATA.
-		* 0: Write
-		* 1: Read */
-
-	/* 8. ALL data is now available and waiting in the DDC buffer.
-	 *    Read HDMI_I2C_DATA with the following fields set
-	 *    RW = 0x1 (read)
-	 *    DATA = BCAPS (this is field where data is pulled from)
-	 *    INDEX = 0x3 (where the data has been placed in buffer by hardware)
-	 *    INDEX_WRITE = 0x1 (explicitly define offset) */
-	/* Write this data to DDC buffer */
-	HDMI_OUTP_ND(0x0238, 0x1 | (3 << 16) | (1 << 31));
-
-	/* Discard first byte */
-	HDMI_INP_ND(0x0238);
-	for (ndx = 0; ndx < data_len; ++ndx) {
-		reg_val = HDMI_INP_ND(0x0238);
-		data_buf[ndx] = (uint8) ((reg_val & 0x0000FF00) >> 8);
-	}
-
-	DEV_DBG("%s[%s] success\n", __func__, what);
-
-error:
-	return status;
-}
-
-static int hdmi_msm_ddc_read_edid_seg(uint32 dev_addr, uint32 offset,
-	uint8 *data_buf, uint32 data_len, uint32 request_len, int retry,
-	const char *what)
-{
-	uint32 reg_val, ndx;
-	int status = 0;
-	uint32 time_out_count;
-	int log_retry_fail = retry != 1;
-	int seg_addr = 0x60, seg_num = 0x01;
-
-	if (NULL == data_buf) {
-		status = -EINVAL;
-		DEV_ERR("%s: invalid input paramter\n", __func__);
-		goto error;
-	}
-
-again:
-	status = hdmi_msm_ddc_clear_irq(what);
-	if (status)
-		goto error;
-
-	/* Ensure Device Address has LSB set to 0 to indicate Slave addr read */
-	dev_addr &= 0xFE;
-
-	/* 0x0238 HDMI_DDC_DATA
-	   [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
-		1 while writing HDMI_DDC_DATA.
-	   [23:16] INDEX Use to set index into DDC buffer for next read or
-		current write, or to read index of current read or next write.
-		Writable only when INDEX_WRITE=1.
-	   [15:8] DATA Use to fill or read the DDC buffer
-	   [0] DATA_RW Select whether buffer access will be a read or write.
-		For writes, address auto-increments on write to HDMI_DDC_DATA.
-		For reads, address autoincrements on reads to HDMI_DDC_DATA.
-		* 0: Write
-		* 1: Read */
-
-	/* 1. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #1
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = linkAddress (primary link address and writing)
-	 *    INDEX = 0x0 (initial offset into buffer)
-	 *    INDEX_WRITE = 0x1 (setting initial offset) */
-	HDMI_OUTP_ND(0x0238, (0x1UL << 31) | (seg_addr << 8));
-
-	/* 2. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #2
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = offsetAddress
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	HDMI_OUTP_ND(0x0238, seg_num << 8);
-
-	/* 3. Write to HDMI_I2C_DATA with the following fields set in order to
-	 *    handle portion #3
-	 *    DATA_RW = 0x0 (write)
-	 *    DATA = linkAddress + 1 (primary link address 0x74 and reading)
-	 *    INDEX = 0x0
-	 *    INDEX_WRITE = 0x0 (auto-increment by hardware) */
-	HDMI_OUTP_ND(0x0238, dev_addr << 8);
-	HDMI_OUTP_ND(0x0238, offset << 8);
-	HDMI_OUTP_ND(0x0238, (dev_addr | 1) << 8);
-
-	/* Data setup is complete, now setup the transaction characteristics */
-
-	/* 0x0228 HDMI_DDC_TRANS0
-	   [23:16] CNT0 Byte count for first transaction (excluding the first
-		byte, which is usually the address).
-	   [13] STOP0 Determines whether a stop bit will be sent after the first
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	   [12] START0 Determines whether a start bit will be sent before the
-		first transaction
-		* 0: NO START
-		* 1: START
-	   [8] STOP_ON_NACK0 Determines whether the current transfer will stop
-		if a NACK is received during the first transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	   [0] RW0 Read/write indicator for first transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 4. Write to HDMI_I2C_TRANSACTION0 with the following fields set in
-	      order to handle characteristics of portion #1 and portion #2
-	 *    RW0 = 0x0 (write)
-	 *    START0 = 0x1 (insert START bit)
-	 *    STOP0 = 0x0 (do NOT insert STOP bit)
-	 *    CNT0 = 0x1 (single byte transaction excluding address) */
-	HDMI_OUTP_ND(0x0228, (1 << 12) | (1 << 16));
-
-	/* 0x022C HDMI_DDC_TRANS1
-	  [23:16] CNT1 Byte count for second transaction (excluding the first
-		byte, which is usually the address).
-	  [13] STOP1 Determines whether a stop bit will be sent after the second
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	  [12] START1 Determines whether a start bit will be sent before the
-		second transaction
-		* 0: NO START
-		* 1: START
-	  [8] STOP_ON_NACK1 Determines whether the current transfer will stop if
-		a NACK is received during the second transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	  [0] RW1 Read/write indicator for second transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
-	      order to handle characteristics of portion #3
-	 *    RW1 = 0x1 (read)
-	 *    START1 = 0x1 (insert START bit)
-	 *    STOP1 = 0x1 (insert STOP bit)
-	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read) */
-	HDMI_OUTP_ND(0x022C, (1 << 12) | (1 << 16));
-
-	/* 0x022C HDMI_DDC_TRANS2
-	  [23:16] CNT1 Byte count for second transaction (excluding the first
-		byte, which is usually the address).
-	  [13] STOP1 Determines whether a stop bit will be sent after the second
-		transaction
-		* 0: NO STOP
-		* 1: STOP
-	  [12] START1 Determines whether a start bit will be sent before the
-		second transaction
-		* 0: NO START
-		* 1: START
-	  [8] STOP_ON_NACK1 Determines whether the current transfer will stop if
-		a NACK is received during the second transaction (current
-		transaction always stops).
-		* 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
-		* 1: STOP ALL TRANSACTIONS, SEND STOP BIT
-	  [0] RW1 Read/write indicator for second transaction - set to 0 for
-		write, 1 for read. This bit only controls HDMI_DDC behaviour -
-		the R/W bit in the transaction is programmed into the DDC buffer
-		as the LSB of the address byte.
-		* 0: WRITE
-		* 1: READ */
-
-	/* 5. Write to HDMI_I2C_TRANSACTION1 with the following fields set in
-	      order to handle characteristics of portion #3
-	 *    RW1 = 0x1 (read)
-	 *    START1 = 0x1 (insert START bit)
-	 *    STOP1 = 0x1 (insert STOP bit)
-	 *    CNT1 = data_len   (it's 128 (0x80) for a blk read) */
-	HDMI_OUTP_ND(0x0230, 1 | (1 << 12) | (1 << 13) | (request_len << 16));
-
-	/* Trigger the I2C transfer */
-	/* 0x020C HDMI_DDC_CTRL
-	   [21:20] TRANSACTION_CNT
-		Number of transactions to be done in current transfer.
-		* 0x0: transaction0 only
-		* 0x1: transaction0, transaction1
-		* 0x2: transaction0, transaction1, transaction2
-		* 0x3: transaction0, transaction1, transaction2, transaction3
-	   [3] SW_STATUS_RESET
-		Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
-		ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
-		STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
-	   [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
-		data) at start of transfer.  This sequence is sent after GO is
-		written to 1, before the first transaction only.
-	   [1] SOFT_RESET Write 1 to reset DDC controller
-	   [0] GO WRITE ONLY. Write 1 to start DDC transfer. */
-
-	/* 6. Write to HDMI_I2C_CONTROL to kick off the hardware.
-	 *    Note that NOTHING has been transmitted on the DDC lines up to this
-	 *    point.
-	 *    TRANSACTION_CNT = 0x2 (execute transaction0 followed by
-	 *    transaction1)
-	 *    GO = 0x1 (kicks off hardware) */
-	INIT_COMPLETION(hdmi_msm_state->ddc_sw_done);
-	HDMI_OUTP_ND(0x020C, (1 << 0) | (2 << 20));
-
-	time_out_count = wait_for_completion_interruptible_timeout(
-		&hdmi_msm_state->ddc_sw_done, HZ/2);
-	HDMI_OUTP_ND(0x0214, 0x2);
-	if (!time_out_count) {
-		if (retry-- > 0) {
-			DEV_INFO("%s: failed timout, retry=%d\n", __func__,
-				retry);
-			goto again;
-		}
-		status = -ETIMEDOUT;
-		DEV_ERR("%s: timedout(7), DDC SW Status=%08x, HW "
-			"Status=%08x, Int Ctrl=%08x\n", __func__,
-			HDMI_INP(0x0218), HDMI_INP(0x021C), HDMI_INP(0x0214));
-		goto error;
-	}
-
-	/* Read DDC status */
-	reg_val = HDMI_INP_ND(0x0218);
-	reg_val &= 0x00001000 | 0x00002000 | 0x00004000 | 0x00008000;
-
-	/* Check if any NACK occurred */
-	if (reg_val) {
-		HDMI_OUTP_ND(0x020C, BIT(3)); /* SW_STATUS_RESET */
-		if (retry == 1)
-			HDMI_OUTP_ND(0x020C, BIT(1)); /* SOFT_RESET */
-		if (retry-- > 0) {
-			DEV_DBG("%s(%s): failed NACK=0x%08x, retry=%d, "
-				"dev-addr=0x%02x, offset=0x%02x, "
-				"length=%d\n", __func__, what,
-				reg_val, retry, dev_addr,
-				offset, data_len);
-			goto again;
-		}
-		status = -EIO;
-		if (log_retry_fail)
-			DEV_ERR("%s(%s): failed NACK=0x%08x, dev-addr=0x%02x, "
-				"offset=0x%02x, length=%d\n", __func__, what,
-				reg_val, dev_addr, offset, data_len);
-		goto error;
-	}
-
-	/* 0x0238 HDMI_DDC_DATA
-	   [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to 1
-		while writing HDMI_DDC_DATA.
-	   [23:16] INDEX Use to set index into DDC buffer for next read or
-		current write, or to read index of current read or next write.
-		Writable only when INDEX_WRITE=1.
-	   [15:8] DATA Use to fill or read the DDC buffer
-	   [0] DATA_RW Select whether buffer access will be a read or write.
-		For writes, address auto-increments on write to HDMI_DDC_DATA.
-		For reads, address autoincrements on reads to HDMI_DDC_DATA.
-		* 0: Write
-		* 1: Read */
-
-	/* 8. ALL data is now available and waiting in the DDC buffer.
-	 *    Read HDMI_I2C_DATA with the following fields set
-	 *    RW = 0x1 (read)
-	 *    DATA = BCAPS (this is field where data is pulled from)
-	 *    INDEX = 0x5 (where the data has been placed in buffer by hardware)
-	 *    INDEX_WRITE = 0x1 (explicitly define offset) */
-	/* Write this data to DDC buffer */
-	HDMI_OUTP_ND(0x0238, 0x1 | (5 << 16) | (1 << 31));
-
-	/* Discard first byte */
-	HDMI_INP_ND(0x0238);
-
-	for (ndx = 0; ndx < data_len; ++ndx) {
-		reg_val = HDMI_INP_ND(0x0238);
-		data_buf[ndx] = (uint8) ((reg_val & 0x0000FF00) >> 8);
-	}
-
-	DEV_DBG("%s[%s] success\n", __func__, what);
-
-error:
-	return status;
-}
-
-
-static int hdmi_msm_ddc_read(uint32 dev_addr, uint32 offset, uint8 *data_buf,
-	uint32 data_len, int retry, const char *what, boolean no_align)
-{
-	int ret = hdmi_msm_ddc_read_retry(dev_addr, offset, data_buf, data_len,
-		data_len, retry, what);
-	if (!ret)
-		return 0;
-	if (no_align) {
-		return hdmi_msm_ddc_read_retry(dev_addr, offset, data_buf,
-			data_len, data_len, retry, what);
-	} else {
-		return hdmi_msm_ddc_read_retry(dev_addr, offset, data_buf,
-			data_len, 32 * ((data_len + 31) / 32), retry, what);
-	}
-}
-
-
-static int hdmi_msm_read_edid_block(int block, uint8 *edid_buf)
-{
-	int i, rc = 0;
-	int block_size = 0x80;
-
-	do {
-		DEV_DBG("EDID: reading block(%d) with block-size=%d\n",
-			block, block_size);
-		for (i = 0; i < 0x80; i += block_size) {
-			/*Read EDID twice with 32bit alighnment too */
-			if (block < 2) {
-				rc = hdmi_msm_ddc_read(0xA0, block*0x80 + i,
-					edid_buf+i, block_size, 1,
-					"EDID", FALSE);
-			} else {
-				rc = hdmi_msm_ddc_read_edid_seg(0xA0,
-				block*0x80 + i, edid_buf+i, block_size,
-				block_size, 1, "EDID");
-			}
-			if (rc)
-				break;
-		}
-
-		block_size /= 2;
-	} while (rc && (block_size >= 16));
-
-	return rc;
-}
-
-static int hdmi_msm_read_edid(void)
-{
-	int status;
-
-	msm_hdmi_init_ddc();
-	/* Looks like we need to turn on HDMI engine before any
-	 * DDC transaction */
-	if (!hdmi_msm_is_power_on()) {
-		DEV_ERR("%s: failed: HDMI power is off", __func__);
-		status = -ENXIO;
-		goto error;
-	}
-
-	external_common_state->read_edid_block = hdmi_msm_read_edid_block;
-	status = hdmi_common_read_edid();
-	if (!status)
-		DEV_DBG("EDID: successfully read\n");
-
-error:
-	return status;
-}
-
-static void hdcp_auth_info(uint32 auth_info)
-{
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	switch (auth_info) {
-	case 0:
-		DEV_INFO("%s: None", __func__);
-		break;
-	case 1:
-		DEV_INFO("%s: Software Disabled Authentication", __func__);
-		break;
-	case 2:
-		DEV_INFO("%s: An Written", __func__);
-		break;
-	case 3:
-		DEV_INFO("%s: Invalid Aksv", __func__);
-		break;
-	case 4:
-		DEV_INFO("%s: Invalid Bksv", __func__);
-		break;
-	case 5:
-		DEV_INFO("%s: RI Mismatch (including RO)", __func__);
-		break;
-	case 6:
-		DEV_INFO("%s: consecutive Pj Mismatches", __func__);
-		break;
-	case 7:
-		DEV_INFO("%s: HPD Disconnect", __func__);
-		break;
-	case 8:
-	default:
-		DEV_INFO("%s: Reserved", __func__);
-		break;
-	}
-}
-
-static void hdcp_key_state(uint32 key_state)
-{
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	switch (key_state) {
-	case 0:
-		DEV_WARN("%s: No HDCP Keys", __func__);
-		break;
-	case 1:
-		DEV_WARN("%s: Not Checked", __func__);
-		break;
-	case 2:
-		DEV_DBG("%s: Checking", __func__);
-		break;
-	case 3:
-		DEV_DBG("%s: HDCP Keys Valid", __func__);
-		break;
-	case 4:
-		DEV_WARN("%s: AKSV not valid", __func__);
-		break;
-	case 5:
-		DEV_WARN("%s: Checksum Mismatch", __func__);
-		break;
-	case 6:
-		DEV_DBG("%s: Production AKSV"
-			"with ENABLE_USER_DEFINED_AN=1", __func__);
-		break;
-	case 7:
-	default:
-		DEV_INFO("%s: Reserved", __func__);
-		break;
-	}
-}
-
-static int hdmi_msm_count_one(uint8 *array, uint8 len)
-{
-	int i, j, count = 0;
-	for (i = 0; i < len; i++)
-		for (j = 0; j < 8; j++)
-			count += (((array[i] >> j) & 0x1) ? 1 : 0);
-	return count;
-}
-
-static void hdcp_deauthenticate(void)
-{
-	int hdcp_link_status = HDMI_INP(0x011C);
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	/* Disable HDCP interrupts */
-	HDMI_OUTP(0x0118, 0x0);
-
-	mutex_lock(&hdcp_auth_state_mutex);
-	external_common_state->hdcp_active = FALSE;
-	mutex_unlock(&hdcp_auth_state_mutex);
-	/* 0x0130 HDCP_RESET
-	  [0] LINK0_DEAUTHENTICATE */
-	HDMI_OUTP(0x0130, 0x1);
-
-	/* 0x0110 HDCP_CTRL
-	  [8] ENCRYPTION_ENABLE
-	  [0] ENABLE */
-	/* encryption_enable = 0 | hdcp block enable = 1 */
-	HDMI_OUTP(0x0110, 0x0);
-
-	if (hdcp_link_status & 0x00000004)
-		hdcp_auth_info((hdcp_link_status & 0x000000F0) >> 4);
-}
-
-static void check_and_clear_HDCP_DDC_Failure(void)
-{
-	int hdcp_ddc_ctrl1_reg;
-	int hdcp_ddc_status;
-	int failure;
-	int nack0;
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	/*
-	 * Check for any DDC transfer failures
-	 * 0x0128 HDCP_DDC_STATUS
-	 * [16] FAILED		Indicates that the last HDCP HW DDC transer
-	 *			failed. This occurs when a transfer is
-	 *			attempted with HDCP DDC disabled
-	 *			(HDCP_DDC_DISABLE=1) or the number of retries
-	 *			match HDCP_DDC_RETRY_CNT
-	 *
-	 * [14] NACK0		Indicates that the last HDCP HW DDC transfer
-	 *			was aborted due to a NACK on the first
-	 *			transaction - cleared by writing 0 to GO bit
-	 */
-	hdcp_ddc_status = HDMI_INP(HDCP_DDC_STATUS);
-	failure = (hdcp_ddc_status >> 16) & 0x1;
-	nack0 = (hdcp_ddc_status >> 14) & 0x1;
-	DEV_DBG("%s: On Entry: HDCP_DDC_STATUS = 0x%x, FAILURE = %d,"
-		"NACK0 = %d\n", __func__ , hdcp_ddc_status, failure, nack0);
-
-	if (failure == 0x1) {
-		/*
-		 * Indicates that the last HDCP HW DDC transfer failed.
-		 * This occurs when a transfer is attempted with HDCP DDC
-		 * disabled (HDCP_DDC_DISABLE=1) or the number of retries
-		 * matches HDCP_DDC_RETRY_CNT.
-		 * Failure occured,  let's clear it.
-		 */
-		DEV_INFO("%s: DDC failure detected. HDCP_DDC_STATUS=0x%08x\n",
-			 __func__, hdcp_ddc_status);
-		/*
-		 * First, Disable DDC
-		 * 0x0120 HDCP_DDC_CTRL_0
-		 * [0] DDC_DISABLE	Determines whether HDCP Ri and Pj reads
-		 *			are done unassisted by hardware or by
-		 *			software via HDMI_DDC (HDCP provides
-		 *			interrupts to request software
-		 *			transfers)
-		 *     0 : Use Hardware DDC
-		 *     1 : Use Software DDC
-		 */
-		HDMI_OUTP(HDCP_DDC_CTRL_0, 0x1);
-
-		/*
-		 * ACK the Failure to Clear it
-		 * 0x0124 HDCP_DDC_CTRL_1
-		 * [0] DDC_FAILED_ACK	Write 1 to clear
-		 *			HDCP_STATUS.HDCP_DDC_FAILED
-		 */
-		hdcp_ddc_ctrl1_reg = HDMI_INP(HDCP_DDC_CTRL_1);
-		HDMI_OUTP(HDCP_DDC_CTRL_1, hdcp_ddc_ctrl1_reg | 0x1);
-
-		/* Check if the FAILURE got Cleared */
-		hdcp_ddc_status = HDMI_INP(HDCP_DDC_STATUS);
-		hdcp_ddc_status = (hdcp_ddc_status >> 16) & 0x1;
-		if (hdcp_ddc_status == 0x0) {
-			DEV_INFO("%s: HDCP DDC Failure has been cleared\n",
-				  __func__);
-		} else {
-			DEV_WARN("%s: Error: HDCP DDC Failure DID NOT get"
-				 "cleared\n", __func__);
-		}
-
-		/* Re-Enable HDCP DDC */
-		HDMI_OUTP(HDCP_DDC_CTRL_0, 0x0);
-	}
-
-	if (nack0 == 0x1) {
-		/*
-		 * 0x020C HDMI_DDC_CTRL
-		 * [3] SW_STATUS_RESET	Write 1 to reset HDMI_DDC_SW_STATUS
-		 *			flags, will reset SW_DONE, ABORTED,
-		 *			TIMEOUT, SW_INTERRUPTED,
-		 *			BUFFER_OVERFLOW, STOPPED_ON_NACK, NACK0,
-		 *			NACK1, NACK2, NACK3
-		 */
-		HDMI_OUTP_ND(HDMI_DDC_CTRL,
-			     HDMI_INP(HDMI_DDC_CTRL) | (0x1 << 3));
-		msleep(20);
-		HDMI_OUTP_ND(HDMI_DDC_CTRL,
-			     HDMI_INP(HDMI_DDC_CTRL) & ~(0x1 << 3));
-	}
-
-	hdcp_ddc_status = HDMI_INP(HDCP_DDC_STATUS);
-
-	failure = (hdcp_ddc_status >> 16) & 0x1;
-	nack0 = (hdcp_ddc_status >> 14) & 0x1;
-	DEV_DBG("%s: On Exit: HDCP_DDC_STATUS = 0x%x, FAILURE = %d,"
-		"NACK0 = %d\n", __func__ , hdcp_ddc_status, failure, nack0);
-}
-
-
-static int hdcp_authentication_part1(void)
-{
-	int ret = 0;
-	boolean is_match;
-	boolean is_part1_done = FALSE;
-	uint32 timeout_count;
-	uint8 bcaps;
-	uint8 aksv[5];
-	uint32 qfprom_aksv_0, qfprom_aksv_1, link0_aksv_0, link0_aksv_1;
-	uint8 bksv[5];
-	uint32 link0_bksv_0, link0_bksv_1;
-	uint8 an[8];
-	uint32 link0_an_0, link0_an_1;
-	uint32 hpd_int_status, hpd_int_ctrl;
-
-
-	static uint8 buf[0xFF];
-	memset(buf, 0, sizeof(buf));
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return 0;
-	}
-
-	if (!is_part1_done) {
-		is_part1_done = TRUE;
-
-		/* Fetch aksv from QFprom, this info should be public. */
-		qfprom_aksv_0 = inpdw(QFPROM_BASE + 0x000060D8);
-		qfprom_aksv_1 = inpdw(QFPROM_BASE + 0x000060DC);
-
-		/* copy an and aksv to byte arrays for transmission */
-		aksv[0] =  qfprom_aksv_0        & 0xFF;
-		aksv[1] = (qfprom_aksv_0 >> 8)  & 0xFF;
-		aksv[2] = (qfprom_aksv_0 >> 16) & 0xFF;
-		aksv[3] = (qfprom_aksv_0 >> 24) & 0xFF;
-		aksv[4] =  qfprom_aksv_1        & 0xFF;
-		/* check there are 20 ones in AKSV */
-		if (hdmi_msm_count_one(aksv, 5) != 20) {
-			DEV_ERR("HDCP: AKSV read from QFPROM doesn't have "
-				"20 1's and 20 0's, FAIL (AKSV=%02x%08x)\n",
-			qfprom_aksv_1, qfprom_aksv_0);
-			ret = -EINVAL;
-			goto error;
-		}
-		DEV_DBG("HDCP: AKSV=%02x%08x\n", qfprom_aksv_1, qfprom_aksv_0);
-
-		/* 0x0288 HDCP_SW_LOWER_AKSV
-			[31:0] LOWER_AKSV */
-		/* 0x0284 HDCP_SW_UPPER_AKSV
-			[7:0] UPPER_AKSV */
-
-		/* This is the lower 32 bits of the SW
-		 * injected AKSV value(AKSV[31:0]) read
-		 * from the EFUSE. It is needed for HDCP
-		 * authentication and must be written
-		 * before enabling HDCP. */
-		HDMI_OUTP(0x0288, qfprom_aksv_0);
-		HDMI_OUTP(0x0284, qfprom_aksv_1);
-
-		msm_hdmi_init_ddc();
-
-		/* read Bcaps at 0x40 in HDCP Port */
-		ret = hdmi_msm_ddc_read(0x74, 0x40, &bcaps, 1, 5, "Bcaps",
-			TRUE);
-		if (ret) {
-			DEV_ERR("%s(%d): Read Bcaps failed", __func__,
-			    __LINE__);
-			goto error;
-		}
-		DEV_DBG("HDCP: Bcaps=%02x\n", bcaps);
-
-		/* HDCP setup prior to HDCP enabled */
-
-		/* 0x0148 HDCP_RCVPORT_DATA4
-			[15:8] LINK0_AINFO
-			[7:0] LINK0_AKSV_1 */
-		/* LINK0_AINFO	= 0x2 FEATURE 1.1 on.
-		 *		= 0x0 FEATURE 1.1 off*/
-		HDMI_OUTP(0x0148, 0x0);
-
-		/* 0x012C HDCP_ENTROPY_CTRL0
-			[31:0] BITS_OF_INFLUENCE_0 */
-		/* 0x025C HDCP_ENTROPY_CTRL1
-			[31:0] BITS_OF_INFLUENCE_1 */
-		HDMI_OUTP(0x012C, 0xB1FFB0FF);
-		HDMI_OUTP(0x025C, 0xF00DFACE);
-
-		/* 0x0114 HDCP_DEBUG_CTRL
-			[2]	DEBUG_RNG_CIPHER
-			else default 0 */
-		HDMI_OUTP(0x0114, HDMI_INP(0x0114) & 0xFFFFFFFB);
-
-		/* 0x0110 HDCP_CTRL
-			[8] ENCRYPTION_ENABLE
-			[0] ENABLE */
-		/* Enable HDCP. Encryption should be enabled after reading R0 */
-		HDMI_OUTP(0x0110, BIT(0));
-
-		/*
-		 * Check to see if a HDCP DDC Failure is indicated in
-		 * HDCP_DDC_STATUS. If yes, clear it.
-		 */
-		check_and_clear_HDCP_DDC_Failure();
-
-		/* 0x0118 HDCP_INT_CTRL
-		 *    [2] AUTH_SUCCESS_MASK	[R/W]	Mask bit for\
-		 *					HDCP Authentication
-		 *		Success interrupt - set to 1 to enable interrupt
-		 *
-		 *    [6] AUTH_FAIL_MASK	[R/W]	Mask bit for HDCP
-		 *					Authentication
-		 *		Lost interrupt set to 1 to enable interrupt
-		 *
-		 *    [7] AUTH_FAIL_INFO_ACK	[W]	Acknwledge bit for HDCP
-		 *		Auth Failure Info field - write 1 to clear
-		 *
-		 *   [10] DDC_XFER_REQ_MASK	[R/W]	Mask bit for HDCP\
-		 *					DDC Transfer
-		 *		Request interrupt - set to 1 to enable interrupt
-		 *
-		 *   [14] DDC_XFER_DONE_MASK	[R/W]	Mask bit for HDCP\
-		 *					DDC Transfer
-		 *		done interrupt - set to 1 to enable interrupt */
-		/* enable all HDCP ints */
-		HDMI_OUTP(0x0118, (1 << 2) | (1 << 6) | (1 << 7));
-
-		/* 0x011C HDCP_LINK0_STATUS
-		[8] AN_0_READY
-		[9] AN_1_READY */
-		/* wait for an0 and an1 ready bits to be set in LINK0_STATUS */
-
-		mutex_lock(&hdcp_auth_state_mutex);
-		timeout_count = 100;
-		while (((HDMI_INP_ND(0x011C) & (0x3 << 8)) != (0x3 << 8))
-			&& timeout_count--)
-			msleep(20);
-		if (!timeout_count) {
-			ret = -ETIMEDOUT;
-			DEV_ERR("%s(%d): timedout, An0=%d, An1=%d\n",
-				__func__, __LINE__,
-			(HDMI_INP_ND(0x011C) & BIT(8)) >> 8,
-			(HDMI_INP_ND(0x011C) & BIT(9)) >> 9);
-			mutex_unlock(&hdcp_auth_state_mutex);
-			goto error;
-		}
-
-		/* 0x0168 HDCP_RCVPORT_DATA12
-		   [23:8] BSTATUS
-		   [7:0] BCAPS */
-		HDMI_OUTP(0x0168, bcaps);
-
-		/* 0x014C HDCP_RCVPORT_DATA5
-		   [31:0] LINK0_AN_0 */
-		/* read an0 calculation */
-		link0_an_0 = HDMI_INP(0x014C);
-
-		/* 0x0150 HDCP_RCVPORT_DATA6
-		   [31:0] LINK0_AN_1 */
-		/* read an1 calculation */
-		link0_an_1 = HDMI_INP(0x0150);
-		mutex_unlock(&hdcp_auth_state_mutex);
-
-		/* three bits 28..30 */
-		hdcp_key_state((HDMI_INP(0x011C) >> 28) & 0x7);
-
-		/* 0x0144 HDCP_RCVPORT_DATA3
-		[31:0] LINK0_AKSV_0 public key
-		0x0148 HDCP_RCVPORT_DATA4
-		[15:8] LINK0_AINFO
-		[7:0]  LINK0_AKSV_1 public key */
-		link0_aksv_0 = HDMI_INP(0x0144);
-		link0_aksv_1 = HDMI_INP(0x0148);
-
-		/* copy an and aksv to byte arrays for transmission */
-		aksv[0] =  link0_aksv_0        & 0xFF;
-		aksv[1] = (link0_aksv_0 >> 8)  & 0xFF;
-		aksv[2] = (link0_aksv_0 >> 16) & 0xFF;
-		aksv[3] = (link0_aksv_0 >> 24) & 0xFF;
-		aksv[4] =  link0_aksv_1        & 0xFF;
-
-		an[0] =  link0_an_0        & 0xFF;
-		an[1] = (link0_an_0 >> 8)  & 0xFF;
-		an[2] = (link0_an_0 >> 16) & 0xFF;
-		an[3] = (link0_an_0 >> 24) & 0xFF;
-		an[4] =  link0_an_1        & 0xFF;
-		an[5] = (link0_an_1 >> 8)  & 0xFF;
-		an[6] = (link0_an_1 >> 16) & 0xFF;
-		an[7] = (link0_an_1 >> 24) & 0xFF;
-
-		/* Write An 8 bytes to offset 0x18 */
-		ret = hdmi_msm_ddc_write(0x74, 0x18, an, 8, "An");
-		if (ret) {
-			DEV_ERR("%s(%d): Write An failed", __func__, __LINE__);
-			goto error;
-		}
-
-		/* Write Aksv 5 bytes to offset 0x10 */
-		ret = hdmi_msm_ddc_write(0x74, 0x10, aksv, 5, "Aksv");
-		if (ret) {
-			DEV_ERR("%s(%d): Write Aksv failed", __func__,
-			    __LINE__);
-			goto error;
-		}
-		DEV_DBG("HDCP: Link0-AKSV=%02x%08x\n",
-			link0_aksv_1 & 0xFF, link0_aksv_0);
-
-		/* Read Bksv 5 bytes at 0x00 in HDCP port */
-		ret = hdmi_msm_ddc_read(0x74, 0x00, bksv, 5, 5, "Bksv", TRUE);
-		if (ret) {
-			DEV_ERR("%s(%d): Read BKSV failed", __func__, __LINE__);
-			goto error;
-		}
-		/* check there are 20 ones in BKSV */
-		if (hdmi_msm_count_one(bksv, 5) != 20) {
-			DEV_ERR("HDCP: BKSV read from Sink doesn't have "
-				"20 1's and 20 0's, FAIL (BKSV="
-				"%02x%02x%02x%02x%02x)\n",
-				bksv[4], bksv[3], bksv[2], bksv[1], bksv[0]);
-			ret = -EINVAL;
-			goto error;
-		}
-
-		link0_bksv_0 = bksv[3];
-		link0_bksv_0 = (link0_bksv_0 << 8) | bksv[2];
-		link0_bksv_0 = (link0_bksv_0 << 8) | bksv[1];
-		link0_bksv_0 = (link0_bksv_0 << 8) | bksv[0];
-		link0_bksv_1 = bksv[4];
-		DEV_DBG("HDCP: BKSV=%02x%08x\n", link0_bksv_1, link0_bksv_0);
-
-		/* 0x0134 HDCP_RCVPORT_DATA0
-		   [31:0] LINK0_BKSV_0 */
-		HDMI_OUTP(0x0134, link0_bksv_0);
-		/* 0x0138 HDCP_RCVPORT_DATA1
-		   [31:0] LINK0_BKSV_1 */
-		HDMI_OUTP(0x0138, link0_bksv_1);
-		DEV_DBG("HDCP: Link0-BKSV=%02x%08x\n", link0_bksv_1,
-		    link0_bksv_0);
-
-		/* HDMI_HPD_INT_STATUS[0x0250] */
-		hpd_int_status = HDMI_INP_ND(0x0250);
-		/* HDMI_HPD_INT_CTRL[0x0254] */
-		hpd_int_ctrl = HDMI_INP_ND(0x0254);
-		DEV_DBG("[SR-DEUG]: HPD_INTR_CTRL=[%u] HPD_INTR_STATUS=[%u] "
-			"before reading R0'\n", hpd_int_ctrl, hpd_int_status);
-
-		/*
-		* HDCP Compliace Test case 1B-01:
-		* Wait here until all the ksv bytes have been
-		* read from the KSV FIFO register.
-		*/
-		msleep(125);
-
-		/* Reading R0' 2 bytes at offset 0x08 */
-		ret = hdmi_msm_ddc_read(0x74, 0x08, buf, 2, 5, "RO'", TRUE);
-		if (ret) {
-			DEV_ERR("%s(%d): Read RO's failed", __func__,
-			    __LINE__);
-			goto error;
-		}
-
-		DEV_DBG("HDCP: R0'=%02x%02x\n", buf[1], buf[0]);
-		INIT_COMPLETION(hdmi_msm_state->hdcp_success_done);
-		/* 0x013C HDCP_RCVPORT_DATA2_0
-		[15:0] LINK0_RI */
-		HDMI_OUTP(0x013C, (((uint32)buf[1]) << 8) | buf[0]);
-
-		timeout_count = wait_for_completion_interruptible_timeout(
-			&hdmi_msm_state->hdcp_success_done, HZ*2);
-
-		if (!timeout_count) {
-			ret = -ETIMEDOUT;
-			is_match = HDMI_INP(0x011C) & BIT(12);
-			DEV_ERR("%s(%d): timedout, Link0=<%s>\n", __func__,
-			  __LINE__,
-			  is_match ? "RI_MATCH" : "No RI Match INTR in time");
-			if (!is_match)
-				goto error;
-		}
-
-		/* 0x011C HDCP_LINK0_STATUS
-		[12] RI_MATCHES	[0] MISMATCH, [1] MATCH
-		[0] AUTH_SUCCESS */
-		/* Checking for RI, R0 Match */
-		/* RI_MATCHES */
-		if ((HDMI_INP(0x011C) & BIT(12)) != BIT(12)) {
-			ret = -EINVAL;
-			DEV_ERR("%s: HDCP_LINK0_STATUS[RI_MATCHES]: MISMATCH\n",
-			    __func__);
-			goto error;
-		}
-
-		/* Enable HDCP Encryption */
-		HDMI_OUTP(0x0110, BIT(0) | BIT(8));
-
-		DEV_INFO("HDCP: authentication part I, successful\n");
-		is_part1_done = FALSE;
-		return 0;
-error:
-		DEV_ERR("[%s]: HDCP Reauthentication\n", __func__);
-		is_part1_done = FALSE;
-		return ret;
-	} else {
-		return 1;
-	}
-}
-
-static int hdmi_msm_transfer_v_h(void)
-{
-	/* Read V'.HO 4 Byte at offset 0x20 */
-	char what[20];
-	int ret;
-	uint8 buf[4];
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return 0;
-	}
-
-	snprintf(what, sizeof(what), "V' H0");
-	ret = hdmi_msm_ddc_read(0x74, 0x20, buf, 4, 5, what, TRUE);
-	if (ret) {
-		DEV_ERR("%s: Read %s failed", __func__, what);
-		return ret;
-	}
-	DEV_DBG("buf[0]= %x , buf[1] = %x , buf[2] = %x , buf[3] = %x\n ",
-			buf[0] , buf[1] , buf[2] , buf[3]);
-
-	/* 0x0154 HDCP_RCVPORT_DATA7
-	   [31:0] V_HO */
-	HDMI_OUTP(0x0154 ,
-		(buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0]));
-
-	snprintf(what, sizeof(what), "V' H1");
-	ret = hdmi_msm_ddc_read(0x74, 0x24, buf, 4, 5, what, TRUE);
-	if (ret) {
-		DEV_ERR("%s: Read %s failed", __func__, what);
-		return ret;
-	}
-	DEV_DBG("buf[0]= %x , buf[1] = %x , buf[2] = %x , buf[3] = %x\n ",
-			buf[0] , buf[1] , buf[2] , buf[3]);
-
-	/* 0x0158 HDCP_RCVPORT_ DATA8
-	   [31:0] V_H1 */
-	HDMI_OUTP(0x0158,
-		(buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0]));
-
-
-	snprintf(what, sizeof(what), "V' H2");
-	ret = hdmi_msm_ddc_read(0x74, 0x28, buf, 4, 5, what, TRUE);
-	if (ret) {
-		DEV_ERR("%s: Read %s failed", __func__, what);
-		return ret;
-	}
-	DEV_DBG("buf[0]= %x , buf[1] = %x , buf[2] = %x , buf[3] = %x\n ",
-			buf[0] , buf[1] , buf[2] , buf[3]);
-
-	/* 0x015c HDCP_RCVPORT_DATA9
-	   [31:0] V_H2 */
-	HDMI_OUTP(0x015c ,
-		(buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0]));
-
-	snprintf(what, sizeof(what), "V' H3");
-	ret = hdmi_msm_ddc_read(0x74, 0x2c, buf, 4, 5, what, TRUE);
-	if (ret) {
-		DEV_ERR("%s: Read %s failed", __func__, what);
-		return ret;
-	}
-	DEV_DBG("buf[0]= %x , buf[1] = %x , buf[2] = %x , buf[3] = %x\n ",
-			buf[0] , buf[1] , buf[2] , buf[3]);
-
-	/* 0x0160 HDCP_RCVPORT_DATA10
-	   [31:0] V_H3 */
-	HDMI_OUTP(0x0160,
-		(buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0]));
-
-	snprintf(what, sizeof(what), "V' H4");
-	ret = hdmi_msm_ddc_read(0x74, 0x30, buf, 4, 5, what, TRUE);
-	if (ret) {
-		DEV_ERR("%s: Read %s failed", __func__, what);
-		return ret;
-	}
-	DEV_DBG("buf[0]= %x , buf[1] = %x , buf[2] = %x , buf[3] = %x\n ",
-			buf[0] , buf[1] , buf[2] , buf[3]);
-	/* 0x0164 HDCP_RCVPORT_DATA11
-	   [31:0] V_H4 */
-	HDMI_OUTP(0x0164,
-		(buf[3] << 24 | buf[2] << 16 | buf[1] << 8 | buf[0]));
-
-	return 0;
-}
-
-static int hdcp_authentication_part2(void)
-{
-	int ret = 0;
-	uint32 timeout_count;
-	int i = 0;
-	int cnt = 0;
-	uint bstatus;
-	uint8 bcaps;
-	uint32 down_stream_devices;
-	uint32 ksv_bytes;
-
-	static uint8 buf[0xFF];
-	static uint8 kvs_fifo[5 * 127];
-
-	boolean max_devs_exceeded = 0;
-	boolean max_cascade_exceeded = 0;
-
-	boolean ksv_done = FALSE;
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return 0;
-	}
-
-	memset(buf, 0, sizeof(buf));
-	memset(kvs_fifo, 0, sizeof(kvs_fifo));
-
-	/* wait until READY bit is set in bcaps */
-	timeout_count = 50;
-	do {
-		timeout_count--;
-		/* read bcaps 1 Byte at offset 0x40 */
-		ret = hdmi_msm_ddc_read(0x74, 0x40, &bcaps, 1, 1,
-		    "Bcaps", FALSE);
-		if (ret) {
-			DEV_ERR("%s(%d): Read Bcaps failed", __func__,
-			    __LINE__);
-			goto error;
-		}
-		msleep(100);
-	} while ((0 == (bcaps & 0x20)) && timeout_count); /* READY (Bit 5) */
-	if (!timeout_count) {
-		ret = -ETIMEDOUT;
-		DEV_ERR("%s:timedout(1)", __func__);
-		goto error;
-	}
-
-	/* read bstatus 2 bytes at offset 0x41 */
-
-	ret = hdmi_msm_ddc_read(0x74, 0x41, buf, 2, 5, "Bstatus", FALSE);
-	if (ret) {
-		DEV_ERR("%s(%d): Read Bstatus failed", __func__, __LINE__);
-		goto error;
-	}
-	bstatus = buf[1];
-	bstatus = (bstatus << 8) | buf[0];
-	/* 0x0168 DCP_RCVPORT_DATA12
-	[7:0] BCAPS
-	[23:8 BSTATUS */
-	HDMI_OUTP(0x0168, bcaps | (bstatus << 8));
-	/* BSTATUS [6:0] DEVICE_COUNT Number of HDMI device attached to repeater
-	* - see HDCP spec */
-	down_stream_devices = bstatus & 0x7F;
-
-	if (down_stream_devices == 0x0) {
-		/* There isn't any devices attaced to the Repeater */
-		DEV_ERR("%s: there isn't any devices attached to the "
-		    "Repeater\n", __func__);
-		ret = -EINVAL;
-		goto error;
-	}
-
-	/*
-	* HDCP Compliance 1B-05:
-	* Check if no. of devices connected to repeater
-	* exceed max_devices_connected from bit 7 of Bstatus.
-	*/
-	max_devs_exceeded = (bstatus & 0x80) >> 7;
-	if (max_devs_exceeded == 0x01) {
-		DEV_ERR("%s: Number of devs connected to repeater "
-		    "exceeds max_devs\n", __func__);
-		ret = -EINVAL;
-		goto hdcp_error;
-	}
-
-	/*
-	* HDCP Compliance 1B-06:
-	* Check if no. of cascade connected to repeater
-	* exceed max_cascade_connected from bit 11 of Bstatus.
-	*/
-	max_cascade_exceeded = (bstatus & 0x800) >> 11;
-	if (max_cascade_exceeded == 0x01) {
-		DEV_ERR("%s: Number of cascade connected to repeater "
-		    "exceeds max_cascade\n", __func__);
-		ret = -EINVAL;
-		goto hdcp_error;
-	}
-
-	/* Read KSV FIFO over DDC
-	* Key Slection vector FIFO
-	* Used to pull downstream KSVs from HDCP Repeaters.
-	* All bytes (DEVICE_COUNT * 5) must be read in a single,
-	*   auto incrementing access.
-	* All bytes read as 0x00 for HDCP Receivers that are not
-	*   HDCP Repeaters (REPEATER == 0). */
-	ksv_bytes = 5 * down_stream_devices;
-	/* Reading KSV FIFO / KSV FIFO */
-	ksv_done = FALSE;
-
-	ret = hdmi_msm_ddc_read(0x74, 0x43, kvs_fifo, ksv_bytes, 5,
-	"KSV FIFO", TRUE);
-	do {
-		if (ret) {
-			DEV_ERR("%s(%d): Read KSV FIFO failed",
-			    __func__, __LINE__);
-			/*
-			* HDCP Compliace Test case 1B-01:
-			* Wait here until all the ksv bytes have been
-			* read from the KSV FIFO register.
-			*/
-			msleep(25);
-		} else {
-			ksv_done = TRUE;
-		}
-		cnt++;
-	} while (!ksv_done && cnt != 20);
-
-	if (ksv_done == FALSE)
-		goto error;
-
-	ret = hdmi_msm_transfer_v_h();
-	if (ret)
-		goto error;
-
-	/* Next: Write KSV FIFO to HDCP_SHA_DATA.
-	* This is done 1 byte at time starting with the LSB.
-	* On the very last byte write,
-	* the HDCP_SHA_DATA_DONE bit[0]
-	*/
-
-	/* 0x023C HDCP_SHA_CTRL
-	[0] RESET	[0] Enable, [1] Reset
-	[4] SELECT	[0] DIGA_HDCP, [1] DIGB_HDCP */
-	/* reset SHA engine */
-	HDMI_OUTP(0x023C, 1);
-	/* enable SHA engine, SEL=DIGA_HDCP */
-	HDMI_OUTP(0x023C, 0);
-
-	for (i = 0; i < ksv_bytes - 1; i++) {
-		/* Write KSV byte and do not set DONE bit[0] */
-		HDMI_OUTP_ND(0x0244, kvs_fifo[i] << 16);
-
-		/* Once 64 bytes have been written, we need to poll for
-		 * HDCP_SHA_BLOCK_DONE before writing any further
-		 */
-		if (i && !((i+1)%64)) {
-			timeout_count = 100;
-			while (!(HDMI_INP_ND(0x0240) & 0x1)
-					&& (--timeout_count)) {
-				DEV_DBG("HDCP Auth Part II: Waiting for the "
-					"computation of the current 64 byte to "
-					"complete. HDCP_SHA_STATUS=%08x. "
-					"timeout_count=%d\n",
-					 HDMI_INP_ND(0x0240), timeout_count);
-				msleep(20);
-			}
-			if (!timeout_count) {
-				ret = -ETIMEDOUT;
-				DEV_ERR("%s(%d): timedout", __func__, __LINE__);
-				goto error;
-			}
-		}
-
-	}
-
-	/* Write l to DONE bit[0] */
-	HDMI_OUTP_ND(0x0244, (kvs_fifo[ksv_bytes - 1] << 16) | 0x1);
-
-	/* 0x0240 HDCP_SHA_STATUS
-	[4] COMP_DONE */
-	/* Now wait for HDCP_SHA_COMP_DONE */
-	timeout_count = 100;
-	while ((0x10 != (HDMI_INP_ND(0x0240) & 0xFFFFFF10)) && --timeout_count)
-		msleep(20);
-
-	if (!timeout_count) {
-		ret = -ETIMEDOUT;
-		DEV_ERR("%s(%d): timedout", __func__, __LINE__);
-		goto error;
-	}
-
-	/* 0x011C HDCP_LINK0_STATUS
-	[20] V_MATCHES */
-	timeout_count = 100;
-	while (((HDMI_INP_ND(0x011C) & (1 << 20)) != (1 << 20))
-	    && --timeout_count) {
-		msleep(20);
-	}
-
-	if (!timeout_count) {
-		ret = -ETIMEDOUT;
-		DEV_ERR("%s(%d): timedout", __func__, __LINE__);
-		goto error;
-	}
-
-	DEV_INFO("HDCP: authentication part II, successful\n");
-
-hdcp_error:
-error:
-	return ret;
-}
-
-static int hdcp_authentication_part3(uint32 found_repeater)
-{
-	int ret = 0;
-	int poll = 3000;
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return 0;
-	}
-
-	while (poll) {
-		/* 0x011C HDCP_LINK0_STATUS
-		    [30:28]  KEYS_STATE = 3 = "Valid"
-		    [24] RO_COMPUTATION_DONE	[0] Not Done, [1] Done
-		    [20] V_MATCHES		[0] Mismtach, [1] Match
-		    [12] RI_MATCHES		[0] Mismatch, [1] Match
-		    [0] AUTH_SUCCESS */
-		if (HDMI_INP_ND(0x011C) != (0x31001001 |
-		    (found_repeater << 20))) {
-			DEV_ERR("HDCP: autentication part III, FAILED, "
-			    "Link Status=%08x\n", HDMI_INP(0x011C));
-			ret = -EINVAL;
-			goto error;
-		}
-		poll--;
-	}
-
-	DEV_INFO("HDCP: authentication part III, successful\n");
-
-error:
-	return ret;
-}
-
-static void hdmi_msm_hdcp_enable(void)
-{
-	int ret = 0;
-	uint8 bcaps;
-	uint32 found_repeater = 0x0;
-	char *envp[2];
-
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_INFO("%s: HDCP NOT ENABLED\n", __func__);
-		return;
-	}
-
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->hdcp_activating = TRUE;
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	mutex_lock(&hdcp_auth_state_mutex);
-	/* This flag prevents other threads from re-authenticating
-	* after we've just authenticated (i.e., finished part3)
-	* We probably need to protect this in a mutex lock */
-	hdmi_msm_state->full_auth_done = FALSE;
-	mutex_unlock(&hdcp_auth_state_mutex);
-
-	/* Disable HDCP before we start part1 */
-	HDMI_OUTP(0x0110, 0x0);
-
-	/* PART I Authentication*/
-	ret = hdcp_authentication_part1();
-	if (ret)
-		goto error;
-
-	/* PART II Authentication*/
-	/* read Bcaps at 0x40 in HDCP Port */
-	ret = hdmi_msm_ddc_read(0x74, 0x40, &bcaps, 1, 5, "Bcaps", FALSE);
-	if (ret) {
-		DEV_ERR("%s(%d): Read Bcaps failed\n", __func__, __LINE__);
-		goto error;
-	}
-	DEV_DBG("HDCP: Bcaps=0x%02x (%s)\n", bcaps,
-		(bcaps & BIT(6)) ? "repeater" : "no repeater");
-
-	/* if REPEATER (Bit 6), perform Part2 Authentication */
-	if (bcaps & BIT(6)) {
-		found_repeater = 0x1;
-		ret = hdcp_authentication_part2();
-		if (ret)
-			goto error;
-	} else
-		DEV_INFO("HDCP: authentication part II skipped, no repeater\n");
-
-	/* PART III Authentication*/
-	ret = hdcp_authentication_part3(found_repeater);
-	if (ret)
-		goto error;
-
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->hdcp_activating = FALSE;
-	mutex_unlock(&hdmi_msm_state_mutex);
-
-	mutex_lock(&hdcp_auth_state_mutex);
-	/*
-	 * This flag prevents other threads from re-authenticating
-	 * after we've just authenticated (i.e., finished part3)
-	 */
-	hdmi_msm_state->full_auth_done = TRUE;
-	external_common_state->hdcp_active = TRUE;
-	mutex_unlock(&hdcp_auth_state_mutex);
-
-	if (!hdmi_msm_is_dvi_mode()) {
-		DEV_INFO("HDMI HPD: sense : send HDCP_PASS\n");
-		envp[0] = "HDCP_STATE=PASS";
-		envp[1] = NULL;
-		kobject_uevent_env(external_common_state->uevent_kobj,
-		    KOBJ_CHANGE, envp);
-
-		SWITCH_SET_HDMI_AUDIO(1, 0);
-	}
-
-	return;
-
-error:
-	if (hdmi_msm_state->hpd_during_auth) {
-		DEV_WARN("Calling Deauthentication: HPD occured during "
-			 "authentication  from [%s]\n", __func__);
-		hdcp_deauthenticate();
-		mutex_lock(&hdcp_auth_state_mutex);
-		hdmi_msm_state->hpd_during_auth = FALSE;
-		mutex_unlock(&hdcp_auth_state_mutex);
-	} else {
-		DEV_WARN("[DEV_DBG]: Calling reauth from [%s]\n", __func__);
-		if (hdmi_msm_state->panel_power_on)
-			queue_work(hdmi_work_queue,
-			    &hdmi_msm_state->hdcp_reauth_work);
-	}
-	mutex_lock(&hdmi_msm_state_mutex);
-	hdmi_msm_state->hdcp_activating = FALSE;
-	mutex_unlock(&hdmi_msm_state_mutex);
-}
-
-static void hdmi_msm_video_setup(int video_format)
-{
-	uint32 total_v   = 0;
-	uint32 total_h   = 0;
-	uint32 start_h   = 0;
-	uint32 end_h     = 0;
-	uint32 start_v   = 0;
-	uint32 end_v     = 0;
-	const struct hdmi_disp_mode_timing_type *timing =
-		hdmi_common_get_supported_mode(video_format);
-
-	/* timing register setup */
-	if (timing == NULL) {
-		DEV_ERR("video format not supported: %d\n", video_format);
-		return;
-	}
-
-	/* Hsync Total and Vsync Total */
-	total_h = timing->active_h + timing->front_porch_h
-		+ timing->back_porch_h + timing->pulse_width_h - 1;
-	total_v = timing->active_v + timing->front_porch_v
-		+ timing->back_porch_v + timing->pulse_width_v - 1;
-	/* 0x02C0 HDMI_TOTAL
-	   [27:16] V_TOTAL Vertical Total
-	   [11:0]  H_TOTAL Horizontal Total */
-	HDMI_OUTP(0x02C0, ((total_v << 16) & 0x0FFF0000)
-		| ((total_h << 0) & 0x00000FFF));
-
-	/* Hsync Start and Hsync End */
-	start_h = timing->back_porch_h + timing->pulse_width_h;
-	end_h   = (total_h + 1) - timing->front_porch_h;
-	/* 0x02B4 HDMI_ACTIVE_H
-	   [27:16] END Horizontal end
-	   [11:0]  START Horizontal start */
-	HDMI_OUTP(0x02B4, ((end_h << 16) & 0x0FFF0000)
-		| ((start_h << 0) & 0x00000FFF));
-
-	start_v = timing->back_porch_v + timing->pulse_width_v - 1;
-	end_v   = total_v - timing->front_porch_v;
-	/* 0x02B8 HDMI_ACTIVE_V
-	   [27:16] END Vertical end
-	   [11:0]  START Vertical start */
-	HDMI_OUTP(0x02B8, ((end_v << 16) & 0x0FFF0000)
-		| ((start_v << 0) & 0x00000FFF));
-
-	if (timing->interlaced) {
-		/* 0x02C4 HDMI_V_TOTAL_F2
-		   [11:0] V_TOTAL_F2 Vertical total for field2 */
-		HDMI_OUTP(0x02C4, ((total_v + 1) << 0) & 0x00000FFF);
-
-		/* 0x02BC HDMI_ACTIVE_V_F2
-		   [27:16] END_F2 Vertical end for field2
-		   [11:0]  START_F2 Vertical start for Field2 */
-		HDMI_OUTP(0x02BC,
-			  (((start_v + 1) << 0) & 0x00000FFF)
-			| (((end_v + 1) << 16) & 0x0FFF0000));
-	} else {
-		/* HDMI_V_TOTAL_F2 */
-		HDMI_OUTP(0x02C4, 0);
-		/* HDMI_ACTIVE_V_F2 */
-		HDMI_OUTP(0x02BC, 0);
-	}
-
-	hdmi_frame_ctrl_cfg(timing);
-}
-
-struct hdmi_msm_audio_acr {
-	uint32 n;	/* N parameter for clock regeneration */
-	uint32 cts;	/* CTS parameter for clock regeneration */
-};
-
-struct hdmi_msm_audio_arcs {
-	uint32 pclk;
-	struct hdmi_msm_audio_acr lut[MSM_HDMI_SAMPLE_RATE_MAX];
-};
-
-#define HDMI_MSM_AUDIO_ARCS(pclk, ...) { pclk, __VA_ARGS__ }
-
-/* Audio constants lookup table for hdmi_msm_audio_acr_setup */
-/* Valid Pixel-Clock rates: 25.2MHz, 27MHz, 27.03MHz, 74.25MHz, 148.5MHz */
-static const struct hdmi_msm_audio_arcs hdmi_msm_audio_acr_lut[] = {
-	/*  25.200MHz  */
-	HDMI_MSM_AUDIO_ARCS(25200, {
-		{4096, 25200}, {6272, 28000}, {6144, 25200}, {12544, 28000},
-		{12288, 25200}, {25088, 28000}, {24576, 25200} }),
-	/*  27.000MHz  */
-	HDMI_MSM_AUDIO_ARCS(27000, {
-		{4096, 27000}, {6272, 30000}, {6144, 27000}, {12544, 30000},
-		{12288, 27000}, {25088, 30000}, {24576, 27000} }),
-	/*  27.027MHz */
-	HDMI_MSM_AUDIO_ARCS(27030, {
-		{4096, 27027}, {6272, 30030}, {6144, 27027}, {12544, 30030},
-		{12288, 27027}, {25088, 30030}, {24576, 27027} }),
-	/*  74.250MHz */
-	HDMI_MSM_AUDIO_ARCS(74250, {
-		{4096, 74250}, {6272, 82500}, {6144, 74250}, {12544, 82500},
-		{12288, 74250}, {25088, 82500}, {24576, 74250} }),
-	/* 148.500MHz */
-	HDMI_MSM_AUDIO_ARCS(148500, {
-		{4096, 148500}, {6272, 165000}, {6144, 148500}, {12544, 165000},
-		{12288, 148500}, {25088, 165000}, {24576, 148500} }),
-};
-
-static void hdmi_msm_audio_acr_setup(boolean enabled, int video_format,
-	int audio_sample_rate, int num_of_channels)
-{
-	/* Read first before writing */
-	/* HDMI_ACR_PKT_CTRL[0x0024] */
-	uint32 acr_pck_ctrl_reg = HDMI_INP(0x0024);
-
-	/* Clear N/CTS selection bits */
-	acr_pck_ctrl_reg &= ~(3 << 4);
-
-	if (enabled) {
-		const struct hdmi_disp_mode_timing_type *timing =
-			hdmi_common_get_supported_mode(video_format);
-		const struct hdmi_msm_audio_arcs *audio_arc =
-			&hdmi_msm_audio_acr_lut[0];
-		const int lut_size = sizeof(hdmi_msm_audio_acr_lut)
-			/sizeof(*hdmi_msm_audio_acr_lut);
-		uint32 i, n, cts, layout, multiplier, aud_pck_ctrl_2_reg;
-
-		if (timing == NULL) {
-			DEV_WARN("%s: video format %d not supported\n",
-				__func__, video_format);
-			return;
-		}
-
-		for (i = 0; i < lut_size;
-			audio_arc = &hdmi_msm_audio_acr_lut[++i]) {
-			if (audio_arc->pclk == timing->pixel_freq)
-				break;
-		}
-		if (i >= lut_size) {
-			DEV_WARN("%s: pixel clock %d not supported\n", __func__,
-				timing->pixel_freq);
-			return;
-		}
-
-		n = audio_arc->lut[audio_sample_rate].n;
-		cts = audio_arc->lut[audio_sample_rate].cts;
-		layout = (MSM_HDMI_AUDIO_CHANNEL_2 == num_of_channels) ? 0 : 1;
-
-		if ((MSM_HDMI_SAMPLE_RATE_192KHZ == audio_sample_rate) ||
-		    (MSM_HDMI_SAMPLE_RATE_176_4KHZ == audio_sample_rate)) {
-			multiplier = 4;
-			n >>= 2; /* divide N by 4 and use multiplier */
-		} else if ((MSM_HDMI_SAMPLE_RATE_96KHZ == audio_sample_rate) ||
-			  (MSM_HDMI_SAMPLE_RATE_88_2KHZ == audio_sample_rate)) {
-			multiplier = 2;
-			n >>= 1; /* divide N by 2 and use multiplier */
-		} else {
-			multiplier = 1;
-		}
-		DEV_DBG("%s: n=%u, cts=%u, layout=%u\n", __func__, n, cts,
-			layout);
-
-		/* AUDIO_PRIORITY | SOURCE */
-		acr_pck_ctrl_reg |= 0x80000100;
-		/* N_MULTIPLE(multiplier) */
-		acr_pck_ctrl_reg |= (multiplier & 7) << 16;
-
-		if ((MSM_HDMI_SAMPLE_RATE_48KHZ == audio_sample_rate) ||
-		    (MSM_HDMI_SAMPLE_RATE_96KHZ == audio_sample_rate) ||
-		    (MSM_HDMI_SAMPLE_RATE_192KHZ == audio_sample_rate)) {
-			/* SELECT(3) */
-			acr_pck_ctrl_reg |= 3 << 4;
-			/* CTS_48 */
-			cts <<= 12;
-
-			/* CTS: need to determine how many fractional bits */
-			/* HDMI_ACR_48_0 */
-			HDMI_OUTP(0x00D4, cts);
-			/* N */
-			/* HDMI_ACR_48_1 */
-			HDMI_OUTP(0x00D8, n);
-		} else if ((MSM_HDMI_SAMPLE_RATE_44_1KHZ == audio_sample_rate)
-			   || (MSM_HDMI_SAMPLE_RATE_88_2KHZ ==
-			       audio_sample_rate)
-			   || (MSM_HDMI_SAMPLE_RATE_176_4KHZ ==
-			       audio_sample_rate)) {
-			/* SELECT(2) */
-			acr_pck_ctrl_reg |= 2 << 4;
-			/* CTS_44 */
-			cts <<= 12;
-
-			/* CTS: need to determine how many fractional bits */
-			/* HDMI_ACR_44_0 */
-			HDMI_OUTP(0x00CC, cts);
-			/* N */
-			/* HDMI_ACR_44_1 */
-			HDMI_OUTP(0x00D0, n);
-		} else {	/* default to 32k */
-			/* SELECT(1) */
-			acr_pck_ctrl_reg |= 1 << 4;
-			/* CTS_32 */
-			cts <<= 12;
-
-			/* CTS: need to determine how many fractional bits */
-			/* HDMI_ACR_32_0 */
-			HDMI_OUTP(0x00C4, cts);
-			/* N */
-			/* HDMI_ACR_32_1 */
-			HDMI_OUTP(0x00C8, n);
-		}
-		/* Payload layout depends on number of audio channels */
-		/* LAYOUT_SEL(layout) */
-		aud_pck_ctrl_2_reg = 1 | (layout << 1);
-		/* override | layout */
-		/* HDMI_AUDIO_PKT_CTRL2[0x00044] */
-		HDMI_OUTP(0x00044, aud_pck_ctrl_2_reg);
-
-		/* SEND | CONT */
-		acr_pck_ctrl_reg |= 0x00000003;
-	} else {
-		/* ~(SEND | CONT) */
-		acr_pck_ctrl_reg &= ~0x00000003;
-	}
-	/* HDMI_ACR_PKT_CTRL[0x0024] */
-	HDMI_OUTP(0x0024, acr_pck_ctrl_reg);
-}
-
-static void hdmi_msm_outpdw_chk(uint32 offset, uint32 data)
-{
-	uint32 check, i = 0;
-
-#ifdef DEBUG
-	HDMI_OUTP(offset, data);
-#endif
-	do {
-		outpdw(MSM_HDMI_BASE+offset, data);
-		check = inpdw(MSM_HDMI_BASE+offset);
-	} while (check != data && i++ < 10);
-
-	if (check != data)
-		DEV_ERR("%s: failed addr=%08x, data=%x, check=%x",
-			__func__, offset, data, check);
-}
-
-static void hdmi_msm_rmw32or(uint32 offset, uint32 data)
-{
-	uint32 reg_data;
-	reg_data = inpdw(MSM_HDMI_BASE+offset);
-	reg_data = inpdw(MSM_HDMI_BASE+offset);
-	hdmi_msm_outpdw_chk(offset, reg_data | data);
-}
-
-
-#define HDMI_AUDIO_CFG				0x01D0
-#define HDMI_AUDIO_ENGINE_ENABLE		1
-#define HDMI_AUDIO_FIFO_MASK			0x000000F0
-#define HDMI_AUDIO_FIFO_WATERMARK_SHIFT		4
-#define HDMI_AUDIO_FIFO_MAX_WATER_MARK		8
-
-
-int hdmi_audio_enable(bool on , u32 fifo_water_mark)
-{
-	u32 hdmi_audio_config;
-
-	hdmi_audio_config = HDMI_INP(HDMI_AUDIO_CFG);
-
-	if (on) {
-
-		if (fifo_water_mark > HDMI_AUDIO_FIFO_MAX_WATER_MARK) {
-			pr_err("%s : HDMI audio fifo water mark can not be more"
-				" than %u\n", __func__,
-				HDMI_AUDIO_FIFO_MAX_WATER_MARK);
-			return -EINVAL;
-		}
-
-		/*
-		 *  Enable HDMI Audio engine.
-		 *  MUST be enabled after Audio DMA is enabled.
-		*/
-		hdmi_audio_config &= ~(HDMI_AUDIO_FIFO_MASK);
-
-		hdmi_audio_config |= (HDMI_AUDIO_ENGINE_ENABLE |
-			 (fifo_water_mark << HDMI_AUDIO_FIFO_WATERMARK_SHIFT));
-
-	} else
-		 hdmi_audio_config &= ~(HDMI_AUDIO_ENGINE_ENABLE);
-
-	HDMI_OUTP(HDMI_AUDIO_CFG, hdmi_audio_config);
-
-	mb();
-	pr_info("%s :HDMI_AUDIO_CFG 0x%08x\n", __func__,
-		HDMI_INP(HDMI_AUDIO_CFG));
-
-	return 0;
-}
-EXPORT_SYMBOL(hdmi_audio_enable);
-
-#define HDMI_AUDIO_PKT_CTRL			0x0020
-#define HDMI_AUDIO_SAMPLE_SEND_ENABLE		1
-
-int hdmi_audio_packet_enable(bool on)
-{
-	u32 hdmi_audio_pkt_ctrl;
-	hdmi_audio_pkt_ctrl = HDMI_INP(HDMI_AUDIO_PKT_CTRL);
-
-	if (on)
-		hdmi_audio_pkt_ctrl |= HDMI_AUDIO_SAMPLE_SEND_ENABLE;
-	else
-		hdmi_audio_pkt_ctrl &= ~(HDMI_AUDIO_SAMPLE_SEND_ENABLE);
-
-	HDMI_OUTP(HDMI_AUDIO_PKT_CTRL, hdmi_audio_pkt_ctrl);
-
-	mb();
-	pr_info("%s : HDMI_AUDIO_PKT_CTRL 0x%08x\n", __func__,
-	HDMI_INP(HDMI_AUDIO_PKT_CTRL));
-	return 0;
-}
-EXPORT_SYMBOL(hdmi_audio_packet_enable);
-
-
-/* TO-DO: return -EINVAL when num_of_channels and channel_allocation
- *  does not match CEA 861-D spec.
-*/
-int hdmi_msm_audio_info_setup(bool enabled, u32 num_of_channels,
-	u32 channel_allocation, u32 level_shift, bool down_mix)
-{
-	uint32 channel_count = 1;	/* Default to 2 channels
-					   -> See Table 17 in CEA-D spec */
-	uint32 check_sum, audio_info_0_reg, audio_info_1_reg;
-	uint32 audio_info_ctrl_reg;
-	u32 aud_pck_ctrl_2_reg;
-	u32 layout;
-
-	layout = (MSM_HDMI_AUDIO_CHANNEL_2 == num_of_channels) ? 0 : 1;
-	aud_pck_ctrl_2_reg = 1 | (layout << 1);
-	HDMI_OUTP(0x00044, aud_pck_ctrl_2_reg);
-
-	/* Please see table 20 Audio InfoFrame in HDMI spec
-	   FL  = front left
-	   FC  = front Center
-	   FR  = front right
-	   FLC = front left center
-	   FRC = front right center
-	   RL  = rear left
-	   RC  = rear center
-	   RR  = rear right
-	   RLC = rear left center
-	   RRC = rear right center
-	   LFE = low frequency effect
-	 */
-
-	/* Read first then write because it is bundled with other controls */
-	/* HDMI_INFOFRAME_CTRL0[0x002C] */
-	audio_info_ctrl_reg = HDMI_INP(0x002C);
-
-	if (enabled) {
-		switch (num_of_channels) {
-		case MSM_HDMI_AUDIO_CHANNEL_2:
-			channel_allocation = 0;	/* Default to FR,FL */
-			break;
-		case MSM_HDMI_AUDIO_CHANNEL_4:
-			channel_count = 3;
-			/* FC,LFE,FR,FL */
-			channel_allocation = 0x3;
-			break;
-		case MSM_HDMI_AUDIO_CHANNEL_6:
-			channel_count = 5;
-			/* RR,RL,FC,LFE,FR,FL */
-			channel_allocation = 0xB;
-			break;
-		case MSM_HDMI_AUDIO_CHANNEL_8:
-			channel_count = 7;
-			/* FRC,FLC,RR,RL,FC,LFE,FR,FL */
-			channel_allocation = 0x1f;
-			break;
-		default:
-			pr_err("%s(): Unsupported num_of_channels = %u\n",
-					__func__, num_of_channels);
-			return -EINVAL;
-			break;
-		}
-
-		/* Program the Channel-Speaker allocation */
-		audio_info_1_reg = 0;
-		/* CA(channel_allocation) */
-		audio_info_1_reg |= channel_allocation & 0xff;
-		/* Program the Level shifter */
-		/* LSV(level_shift) */
-		audio_info_1_reg |= (level_shift << 11) & 0x00007800;
-		/* Program the Down-mix Inhibit Flag */
-		/* DM_INH(down_mix) */
-		audio_info_1_reg |= (down_mix << 15) & 0x00008000;
-
-		/* HDMI_AUDIO_INFO1[0x00E8] */
-		HDMI_OUTP(0x00E8, audio_info_1_reg);
-
-		/* Calculate CheckSum
-		   Sum of all the bytes in the Audio Info Packet bytes
-		   (See table 8.4 in HDMI spec) */
-		check_sum = 0;
-		/* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_TYPE[0x84] */
-		check_sum += 0x84;
-		/* HDMI_AUDIO_INFO_FRAME_PACKET_HEADER_VERSION[0x01] */
-		check_sum += 1;
-		/* HDMI_AUDIO_INFO_FRAME_PACKET_LENGTH[0x0A] */
-		check_sum += 0x0A;
-		check_sum += channel_count;
-		check_sum += channel_allocation;
-		/* See Table 8.5 in HDMI spec */
-		check_sum += (level_shift & 0xF) << 3 | (down_mix & 0x1) << 7;
-		check_sum &= 0xFF;
-		check_sum = (uint8) (256 - check_sum);
-
-		audio_info_0_reg = 0;
-		/* CHECKSUM(check_sum) */
-		audio_info_0_reg |= check_sum & 0xff;
-		/* CC(channel_count) */
-		audio_info_0_reg |= (channel_count << 8) & 0x00000700;
-
-		/* HDMI_AUDIO_INFO0[0x00E4] */
-		HDMI_OUTP(0x00E4, audio_info_0_reg);
-
-		/* Set these flags */
-		/* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
-		 | AUDIO_INFO_SEND */
-		audio_info_ctrl_reg |= 0x000000F0;
-	} else {
-		/* Clear these flags */
-		/* ~(AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
-		   | AUDIO_INFO_SEND) */
-		audio_info_ctrl_reg &= ~0x000000F0;
-	}
-	/* HDMI_INFOFRAME_CTRL0[0x002C] */
-	HDMI_OUTP(0x002C, audio_info_ctrl_reg);
-
-
-	hdmi_msm_dump_regs("HDMI-AUDIO-ON: ");
-
-	return 0;
-
-}
-EXPORT_SYMBOL(hdmi_msm_audio_info_setup);
-
-static void hdmi_msm_en_gc_packet(boolean av_mute_is_requested)
-{
-	/* HDMI_GC[0x0040] */
-	HDMI_OUTP(0x0040, av_mute_is_requested ? 1 : 0);
-
-	/* GC packet enable (every frame) */
-	/* HDMI_VBI_PKT_CTRL[0x0028] */
-	hdmi_msm_rmw32or(0x0028, 3 << 4);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_ISRC_ACP_SUPPORT
-static void hdmi_msm_en_isrc_packet(boolean isrc_is_continued)
-{
-	static const char isrc_psuedo_data[] =
-					"ISRC1:0123456789isrc2=ABCDEFGHIJ";
-	const uint32 * isrc_data = (const uint32 *) isrc_psuedo_data;
-
-	/* ISRC_STATUS =0b010 | ISRC_CONTINUE | ISRC_VALID */
-	/* HDMI_ISRC1_0[0x00048] */
-	HDMI_OUTP(0x00048, 2 | (isrc_is_continued ? 1 : 0) << 6 | 0 << 7);
-
-	/* HDMI_ISRC1_1[0x004C] */
-	HDMI_OUTP(0x004C, *isrc_data++);
-	/* HDMI_ISRC1_2[0x0050] */
-	HDMI_OUTP(0x0050, *isrc_data++);
-	/* HDMI_ISRC1_3[0x0054] */
-	HDMI_OUTP(0x0054, *isrc_data++);
-	/* HDMI_ISRC1_4[0x0058] */
-	HDMI_OUTP(0x0058, *isrc_data++);
-
-	/* HDMI_ISRC2_0[0x005C] */
-	HDMI_OUTP(0x005C, *isrc_data++);
-	/* HDMI_ISRC2_1[0x0060] */
-	HDMI_OUTP(0x0060, *isrc_data++);
-	/* HDMI_ISRC2_2[0x0064] */
-	HDMI_OUTP(0x0064, *isrc_data++);
-	/* HDMI_ISRC2_3[0x0068] */
-	HDMI_OUTP(0x0068, *isrc_data);
-
-	/* HDMI_VBI_PKT_CTRL[0x0028] */
-	/* ISRC Send + Continuous */
-	hdmi_msm_rmw32or(0x0028, 3 << 8);
-}
-#else
-static void hdmi_msm_en_isrc_packet(boolean isrc_is_continued)
-{
-	/*
-	 * Until end-to-end support for various audio packets
-	 */
-}
-#endif
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_ISRC_ACP_SUPPORT
-static void hdmi_msm_en_acp_packet(uint32 byte1)
-{
-	/* HDMI_ACP[0x003C] */
-	HDMI_OUTP(0x003C, 2 | 1 << 8 | byte1 << 16);
-
-	/* HDMI_VBI_PKT_CTRL[0x0028] */
-	/* ACP send, s/w source */
-	hdmi_msm_rmw32or(0x0028, 3 << 12);
-}
-#else
-static void hdmi_msm_en_acp_packet(uint32 byte1)
-{
-	/*
-	 * Until end-to-end support for various audio packets
-	 */
-}
-#endif
-
-int hdmi_msm_audio_get_sample_rate(void)
-{
-	return msm_hdmi_sample_rate;
-}
-EXPORT_SYMBOL(hdmi_msm_audio_get_sample_rate);
-
-void hdmi_msm_audio_sample_rate_reset(int rate)
-{
-	if (msm_hdmi_sample_rate == rate)
-		return;
-
-	msm_hdmi_sample_rate = rate;
-
-	if (hdmi_msm_state->hdcp_enable)
-		hdcp_deauthenticate();
-	else
-		hdmi_msm_turn_on();
-}
-EXPORT_SYMBOL(hdmi_msm_audio_sample_rate_reset);
-
-static void hdmi_msm_audio_setup(void)
-{
-	const int channels = MSM_HDMI_AUDIO_CHANNEL_2;
-
-	/* (0) for clr_avmute, (1) for set_avmute */
-	hdmi_msm_en_gc_packet(0);
-	/* (0) for isrc1 only, (1) for isrc1 and isrc2 */
-	hdmi_msm_en_isrc_packet(1);
-	/* arbitrary bit pattern for byte1 */
-	hdmi_msm_en_acp_packet(0x5a);
-	DEV_DBG("Not setting ACP, ISRC1, ISRC2 packets\n");
-	hdmi_msm_audio_acr_setup(TRUE,
-		external_common_state->video_resolution,
-		msm_hdmi_sample_rate, channels);
-	hdmi_msm_audio_info_setup(TRUE, channels, 0, 0, FALSE);
-
-	/* Turn on Audio FIFO and SAM DROP ISR */
-	HDMI_OUTP(0x02CC, HDMI_INP(0x02CC) | BIT(1) | BIT(3));
-	DEV_INFO("HDMI Audio: Enabled\n");
-}
-
-static int hdmi_msm_audio_off(void)
-{
-	uint32 audio_cfg;
-	int i, timeout_val = 50;
-
-	for (i = 0; (i < timeout_val) &&
-		((audio_cfg = HDMI_INP_ND(0x01D0)) & BIT(0)); i++) {
-		DEV_DBG("%s: %d times: AUDIO CFG is %08xi\n", __func__,
-				i+1, audio_cfg);
-		if (!((i+1) % 10)) {
-			DEV_ERR("%s: audio still on after %d sec. try again\n",
-				__func__, (i+1)/10);
-			SWITCH_SET_HDMI_AUDIO(0, 1);
-		}
-		msleep(100);
-	}
-
-	if (i == timeout_val)
-		DEV_ERR("%s: Error: cannot turn off audio engine\n", __func__);
-
-	hdmi_msm_audio_info_setup(FALSE, 0, 0, 0, FALSE);
-	hdmi_msm_audio_acr_setup(FALSE, 0, 0, 0);
-	DEV_INFO("HDMI Audio: Disabled\n");
-	return 0;
-}
-
-static uint8 hdmi_msm_avi_iframe_lut[][17] = {
-/*	480p60	480i60	576p50	576i50	720p60	 720p50	1080p60	1080i60	1080p50
-	1080i50	1080p24	1080p30	1080p25	640x480p 480p60_16_9 576p50_4_3 */
-	{0x10,	0x10,	0x10,	0x10,	0x10,	 0x10,	0x10,	0x10,	0x10,
-	 0x10,	0x10,	0x10,	0x10,	0x10, 0x10, 0x10, 0x10}, /*00*/
-	{0x18,	0x18,	0x28,	0x28,	0x28,	 0x28,	0x28,	0x28,	0x28,
-	 0x28,	0x28,	0x28,	0x28,	0x18, 0x28, 0x18, 0x08}, /*01*/
-	{0x00,	0x04,	0x04,	0x04,	0x04,	 0x04,	0x04,	0x04,	0x04,
-	 0x04,	0x04,	0x04,	0x04,	0x88, 0x00, 0x04, 0x04}, /*02*/
-	{0x02,	0x06,	0x11,	0x15,	0x04,	 0x13,	0x10,	0x05,	0x1F,
-	 0x14,	0x20,	0x22,	0x21,	0x01, 0x03, 0x11, 0x00}, /*03*/
-	{0x00,	0x01,	0x00,	0x01,	0x00,	 0x00,	0x00,	0x00,	0x00,
-	 0x00,	0x00,	0x00,	0x00,	0x00, 0x00, 0x00, 0x00}, /*04*/
-	{0x00,	0x00,	0x00,	0x00,	0x00,	 0x00,	0x00,	0x00,	0x00,
-	 0x00,	0x00,	0x00,	0x00,	0x00, 0x00, 0x00, 0x00}, /*05*/
-	{0x00,	0x00,	0x00,	0x00,	0x00,	 0x00,	0x00,	0x00,	0x00,
-	 0x00,	0x00,	0x00,	0x00,	0x00, 0x00, 0x00, 0x00}, /*06*/
-	{0xE1,	0xE1,	0x41,	0x41,	0xD1,	 0xd1,	0x39,	0x39,	0x39,
-	 0x39,	0x39,	0x39,	0x39,	0xe1, 0xE1, 0x41, 0x01}, /*07*/
-	{0x01,	0x01,	0x02,	0x02,	0x02,	 0x02,	0x04,	0x04,	0x04,
-	 0x04,	0x04,	0x04,	0x04,	0x01, 0x01, 0x02, 0x04}, /*08*/
-	{0x00,	0x00,	0x00,	0x00,	0x00,	 0x00,	0x00,	0x00,	0x00,
-	 0x00,	0x00,	0x00,	0x00,	0x00, 0x00, 0x00, 0x00}, /*09*/
-	{0x00,	0x00,	0x00,	0x00,	0x00,	 0x00,	0x00,	0x00,	0x00,
-	 0x00,	0x00,	0x00,	0x00,	0x00, 0x00, 0x00, 0x00}, /*10*/
-	{0xD1,	0xD1,	0xD1,	0xD1,	0x01,	 0x01,	0x81,	0x81,	0x81,
-	 0x81,	0x81,	0x81,	0x81,	0x81, 0xD1, 0xD1, 0x01}, /*11*/
-	{0x02,	0x02,	0x02,	0x02,	0x05,	 0x05,	0x07,	0x07,	0x07,
-	 0x07,	0x07,	0x07,	0x07,	0x02, 0x02, 0x02, 0x05}  /*12*/
-};
-
-static void hdmi_msm_avi_info_frame(void)
-{
-	/* two header + length + 13 data */
-	uint8 aviInfoFrame[16];
-	uint8 checksum;
-	uint32 sum;
-	uint32 regVal;
-	int i;
-	int mode = 0;
-	boolean use_ce_scan_info = TRUE;
-
-	switch (external_common_state->video_resolution) {
-	case HDMI_VFRMT_720x480p60_4_3:
-		mode = 0;
-		break;
-	case HDMI_VFRMT_720x480i60_16_9:
-		mode = 1;
-		break;
-	case HDMI_VFRMT_720x576p50_16_9:
-		mode = 2;
-		break;
-	case HDMI_VFRMT_720x576i50_16_9:
-		mode = 3;
-		break;
-	case HDMI_VFRMT_1280x720p60_16_9:
-		mode = 4;
-		break;
-	case HDMI_VFRMT_1280x720p50_16_9:
-		mode = 5;
-		break;
-	case HDMI_VFRMT_1920x1080p60_16_9:
-		mode = 6;
-		break;
-	case HDMI_VFRMT_1920x1080i60_16_9:
-		mode = 7;
-		break;
-	case HDMI_VFRMT_1920x1080p50_16_9:
-		mode = 8;
-		break;
-	case HDMI_VFRMT_1920x1080i50_16_9:
-		mode = 9;
-		break;
-	case HDMI_VFRMT_1920x1080p24_16_9:
-		mode = 10;
-		break;
-	case HDMI_VFRMT_1920x1080p30_16_9:
-		mode = 11;
-		break;
-	case HDMI_VFRMT_1920x1080p25_16_9:
-		mode = 12;
-		break;
-	case HDMI_VFRMT_640x480p60_4_3:
-		mode = 13;
-		break;
-	case HDMI_VFRMT_720x480p60_16_9:
-		mode = 14;
-		break;
-	case HDMI_VFRMT_720x576p50_4_3:
-		mode = 15;
-		break;
-	case HDMI_VFRMT_1280x1024p60_5_4:
-		mode = 16;
-		break;
-	default:
-		DEV_INFO("%s: mode %d not supported\n", __func__,
-			external_common_state->video_resolution);
-		return;
-	}
-
-	/* InfoFrame Type = 82 */
-	aviInfoFrame[0]  = 0x82;
-	/* Version = 2 */
-	aviInfoFrame[1]  = 2;
-	/* Length of AVI InfoFrame = 13 */
-	aviInfoFrame[2]  = 13;
-
-	/* Data Byte 01: 0 Y1 Y0 A0 B1 B0 S1 S0 */
-	aviInfoFrame[3]  = hdmi_msm_avi_iframe_lut[0][mode];
-
-	/*
-	 * If the sink specified support for both underscan/overscan
-	 * then, by default, set the underscan bit.
-	 * Only checking underscan support for preferred format and cea formats
-	 */
-	if ((external_common_state->video_resolution ==
-			external_common_state->preferred_video_format)) {
-		use_ce_scan_info = FALSE;
-		switch (external_common_state->pt_scan_info) {
-		case 0:
-			/*
-			 * Need to use the info specified for the corresponding
-			 * IT or CE format
-			 */
-			DEV_DBG("%s: No underscan information specified for the"
-				" preferred video format\n", __func__);
-			use_ce_scan_info = TRUE;
-			break;
-		case 3:
-			DEV_DBG("%s: Setting underscan bit for the preferred"
-				" video format\n", __func__);
-			aviInfoFrame[3] |= 0x02;
-			break;
-		default:
-			DEV_DBG("%s: Underscan information not set for the"
-				" preferred video format\n", __func__);
-			break;
-		}
-	}
-
-	if (use_ce_scan_info) {
-		if (3 == external_common_state->ce_scan_info) {
-			DEV_DBG("%s: Setting underscan bit for the CE video"
-					" format\n", __func__);
-			aviInfoFrame[3] |= 0x02;
-		} else {
-			DEV_DBG("%s: Not setting underscan bit for the CE video"
-				       " format\n", __func__);
-		}
-	}
-
-	/* Data Byte 02: C1 C0 M1 M0 R3 R2 R1 R0 */
-	aviInfoFrame[4]  = hdmi_msm_avi_iframe_lut[1][mode];
-	/* Data Byte 03: ITC EC2 EC1 EC0 Q1 Q0 SC1 SC0 */
-	aviInfoFrame[5]  = hdmi_msm_avi_iframe_lut[2][mode];
-	/* Data Byte 04: 0 VIC6 VIC5 VIC4 VIC3 VIC2 VIC1 VIC0 */
-	aviInfoFrame[6]  = hdmi_msm_avi_iframe_lut[3][mode];
-	/* Data Byte 05: 0 0 0 0 PR3 PR2 PR1 PR0 */
-	aviInfoFrame[7]  = hdmi_msm_avi_iframe_lut[4][mode];
-	/* Data Byte 06: LSB Line No of End of Top Bar */
-	aviInfoFrame[8]  = hdmi_msm_avi_iframe_lut[5][mode];
-	/* Data Byte 07: MSB Line No of End of Top Bar */
-	aviInfoFrame[9]  = hdmi_msm_avi_iframe_lut[6][mode];
-	/* Data Byte 08: LSB Line No of Start of Bottom Bar */
-	aviInfoFrame[10] = hdmi_msm_avi_iframe_lut[7][mode];
-	/* Data Byte 09: MSB Line No of Start of Bottom Bar */
-	aviInfoFrame[11] = hdmi_msm_avi_iframe_lut[8][mode];
-	/* Data Byte 10: LSB Pixel Number of End of Left Bar */
-	aviInfoFrame[12] = hdmi_msm_avi_iframe_lut[9][mode];
-	/* Data Byte 11: MSB Pixel Number of End of Left Bar */
-	aviInfoFrame[13] = hdmi_msm_avi_iframe_lut[10][mode];
-	/* Data Byte 12: LSB Pixel Number of Start of Right Bar */
-	aviInfoFrame[14] = hdmi_msm_avi_iframe_lut[11][mode];
-	/* Data Byte 13: MSB Pixel Number of Start of Right Bar */
-	aviInfoFrame[15] = hdmi_msm_avi_iframe_lut[12][mode];
-
-	sum = 0;
-	for (i = 0; i < 16; i++)
-		sum += aviInfoFrame[i];
-	sum &= 0xFF;
-	sum = 256 - sum;
-	checksum = (uint8) sum;
-
-	regVal = aviInfoFrame[5];
-	regVal = regVal << 8 | aviInfoFrame[4];
-	regVal = regVal << 8 | aviInfoFrame[3];
-	regVal = regVal << 8 | checksum;
-	HDMI_OUTP(0x006C, regVal);
-
-	regVal = aviInfoFrame[9];
-	regVal = regVal << 8 | aviInfoFrame[8];
-	regVal = regVal << 8 | aviInfoFrame[7];
-	regVal = regVal << 8 | aviInfoFrame[6];
-	HDMI_OUTP(0x0070, regVal);
-
-	regVal = aviInfoFrame[13];
-	regVal = regVal << 8 | aviInfoFrame[12];
-	regVal = regVal << 8 | aviInfoFrame[11];
-	regVal = regVal << 8 | aviInfoFrame[10];
-	HDMI_OUTP(0x0074, regVal);
-
-	regVal = aviInfoFrame[1];
-	regVal = regVal << 16 | aviInfoFrame[15];
-	regVal = regVal << 8 | aviInfoFrame[14];
-	HDMI_OUTP(0x0078, regVal);
-
-	/* INFOFRAME_CTRL0[0x002C] */
-	/* 0x3 for AVI InfFrame enable (every frame) */
-	HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_3D
-static void hdmi_msm_vendor_infoframe_packetsetup(void)
-{
-	uint32 packet_header      = 0;
-	uint32 check_sum          = 0;
-	uint32 packet_payload     = 0;
-
-	if (!external_common_state->format_3d) {
-		HDMI_OUTP(0x0034, 0);
-		return;
-	}
-
-	/* 0x0084 GENERIC0_HDR
-	 *   HB0             7:0  NUM
-	 *   HB1            15:8  NUM
-	 *   HB2           23:16  NUM */
-	/* Setup Packet header and payload */
-	/* 0x81 VS_INFO_FRAME_ID
-	   0x01 VS_INFO_FRAME_VERSION
-	   0x1B VS_INFO_FRAME_PAYLOAD_LENGTH */
-	packet_header  = 0x81 | (0x01 << 8) | (0x1B << 16);
-	HDMI_OUTP(0x0084, packet_header);
-
-	check_sum  = packet_header & 0xff;
-	check_sum += (packet_header >> 8) & 0xff;
-	check_sum += (packet_header >> 16) & 0xff;
-
-	/* 0x008C GENERIC0_1
-	 *   BYTE4           7:0  NUM
-	 *   BYTE5          15:8  NUM
-	 *   BYTE6         23:16  NUM
-	 *   BYTE7         31:24  NUM */
-	/* 0x02 VS_INFO_FRAME_3D_PRESENT */
-	packet_payload  = 0x02 << 5;
-	switch (external_common_state->format_3d) {
-	case 1:
-		/* 0b1000 VIDEO_3D_FORMAT_SIDE_BY_SIDE_HALF */
-		packet_payload |= (0x08 << 8) << 4;
-		break;
-	case 2:
-		/* 0b0110 VIDEO_3D_FORMAT_TOP_AND_BOTTOM_HALF */
-		packet_payload |= (0x06 << 8) << 4;
-		break;
-	}
-	HDMI_OUTP(0x008C, packet_payload);
-
-	check_sum += packet_payload & 0xff;
-	check_sum += (packet_payload >> 8) & 0xff;
-
-	#define IEEE_REGISTRATION_ID	0xC03
-	/* Next 3 bytes are IEEE Registration Identifcation */
-	/* 0x0088 GENERIC0_0
-	 *   BYTE0           7:0  NUM (checksum)
-	 *   BYTE1          15:8  NUM
-	 *   BYTE2         23:16  NUM
-	 *   BYTE3         31:24  NUM */
-	check_sum += IEEE_REGISTRATION_ID & 0xff;
-	check_sum += (IEEE_REGISTRATION_ID >> 8) & 0xff;
-	check_sum += (IEEE_REGISTRATION_ID >> 16) & 0xff;
-
-	HDMI_OUTP(0x0088, (0x100 - (0xff & check_sum))
-		| ((IEEE_REGISTRATION_ID & 0xff) << 8)
-		| (((IEEE_REGISTRATION_ID >> 8) & 0xff) << 16)
-		| (((IEEE_REGISTRATION_ID >> 16) & 0xff) << 24));
-
-	/* 0x0034 GEN_PKT_CTRL
-	 *   GENERIC0_SEND   0      0 = Disable Generic0 Packet Transmission
-	 *                          1 = Enable Generic0 Packet Transmission
-	 *   GENERIC0_CONT   1      0 = Send Generic0 Packet on next frame only
-	 *                          1 = Send Generic0 Packet on every frame
-	 *   GENERIC0_UPDATE 2      NUM
-	 *   GENERIC1_SEND   4      0 = Disable Generic1 Packet Transmission
-	 *                          1 = Enable Generic1 Packet Transmission
-	 *   GENERIC1_CONT   5      0 = Send Generic1 Packet on next frame only
-	 *                          1 = Send Generic1 Packet on every frame
-	 *   GENERIC0_LINE   21:16  NUM
-	 *   GENERIC1_LINE   29:24  NUM
-	 */
-	/* GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
-	 * Setup HDMI TX generic packet control
-	 * Enable this packet to transmit every frame
-	 * Enable this packet to transmit every frame
-	 * Enable HDMI TX engine to transmit Generic packet 0 */
-	HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
-}
-
-static void hdmi_msm_switch_3d(boolean on)
-{
-	mutex_lock(&external_common_state_hpd_mutex);
-	if (external_common_state->hpd_state)
-		hdmi_msm_vendor_infoframe_packetsetup();
-	mutex_unlock(&external_common_state_hpd_mutex);
-}
-#endif
-
-#define IFRAME_CHECKSUM_32(d) \
-	((d & 0xff) + ((d >> 8) & 0xff) + \
-	((d >> 16) & 0xff) + ((d >> 24) & 0xff))
-
-static void hdmi_msm_spd_infoframe_packetsetup(void)
-{
-	uint32 packet_header  = 0;
-	uint32 check_sum      = 0;
-	uint32 packet_payload = 0;
-	uint32 packet_control = 0;
-
-	uint8 *vendor_name = external_common_state->spd_vendor_name;
-	uint8 *product_description =
-		external_common_state->spd_product_description;
-
-	/* 0x00A4 GENERIC1_HDR
-	 *   HB0             7:0  NUM
-	 *   HB1            15:8  NUM
-	 *   HB2           23:16  NUM */
-	/* Setup Packet header and payload */
-	/* 0x83 InfoFrame Type Code
-	   0x01 InfoFrame Version Number
-	   0x19 Length of Source Product Description InfoFrame
-	*/
-	packet_header  = 0x83 | (0x01 << 8) | (0x19 << 16);
-	HDMI_OUTP(0x00A4, packet_header);
-	check_sum += IFRAME_CHECKSUM_32(packet_header);
-
-	/* 0x00AC GENERIC1_1
-	 *   BYTE4           7:0  VENDOR_NAME[3]
-	 *   BYTE5          15:8  VENDOR_NAME[4]
-	 *   BYTE6         23:16  VENDOR_NAME[5]
-	 *   BYTE7         31:24  VENDOR_NAME[6] */
-	packet_payload = (vendor_name[3] & 0x7f)
-		| ((vendor_name[4] & 0x7f) << 8)
-		| ((vendor_name[5] & 0x7f) << 16)
-		| ((vendor_name[6] & 0x7f) << 24);
-	HDMI_OUTP(0x00AC, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* Product Description (7-bit ASCII code) */
-	/* 0x00B0 GENERIC1_2
-	 *   BYTE8           7:0  VENDOR_NAME[7]
-	 *   BYTE9          15:8  PRODUCT_NAME[ 0]
-	 *   BYTE10        23:16  PRODUCT_NAME[ 1]
-	 *   BYTE11        31:24  PRODUCT_NAME[ 2] */
-	packet_payload = (vendor_name[7] & 0x7f)
-		| ((product_description[0] & 0x7f) << 8)
-		| ((product_description[1] & 0x7f) << 16)
-		| ((product_description[2] & 0x7f) << 24);
-	HDMI_OUTP(0x00B0, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* 0x00B4 GENERIC1_3
-	 *   BYTE12          7:0  PRODUCT_NAME[ 3]
-	 *   BYTE13         15:8  PRODUCT_NAME[ 4]
-	 *   BYTE14        23:16  PRODUCT_NAME[ 5]
-	 *   BYTE15        31:24  PRODUCT_NAME[ 6] */
-	packet_payload = (product_description[3] & 0x7f)
-		| ((product_description[4] & 0x7f) << 8)
-		| ((product_description[5] & 0x7f) << 16)
-		| ((product_description[6] & 0x7f) << 24);
-	HDMI_OUTP(0x00B4, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* 0x00B8 GENERIC1_4
-	 *   BYTE16          7:0  PRODUCT_NAME[ 7]
-	 *   BYTE17         15:8  PRODUCT_NAME[ 8]
-	 *   BYTE18        23:16  PRODUCT_NAME[ 9]
-	 *   BYTE19        31:24  PRODUCT_NAME[10] */
-	packet_payload = (product_description[7] & 0x7f)
-		| ((product_description[8] & 0x7f) << 8)
-		| ((product_description[9] & 0x7f) << 16)
-		| ((product_description[10] & 0x7f) << 24);
-	HDMI_OUTP(0x00B8, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* 0x00BC GENERIC1_5
-	 *   BYTE20          7:0  PRODUCT_NAME[11]
-	 *   BYTE21         15:8  PRODUCT_NAME[12]
-	 *   BYTE22        23:16  PRODUCT_NAME[13]
-	 *   BYTE23        31:24  PRODUCT_NAME[14] */
-	packet_payload = (product_description[11] & 0x7f)
-		| ((product_description[12] & 0x7f) << 8)
-		| ((product_description[13] & 0x7f) << 16)
-		| ((product_description[14] & 0x7f) << 24);
-	HDMI_OUTP(0x00BC, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* 0x00C0 GENERIC1_6
-	 *   BYTE24          7:0  PRODUCT_NAME[15]
-	 *   BYTE25         15:8  Source Device Information
-	 *   BYTE26        23:16  NUM
-	 *   BYTE27        31:24  NUM */
-	/* Source Device Information
-	 * 00h unknown
-	 * 01h Digital STB
-	 * 02h DVD
-	 * 03h D-VHS
-	 * 04h HDD Video
-	 * 05h DVC
-	 * 06h DSC
-	 * 07h Video CD
-	 * 08h Game
-	 * 09h PC general */
-	packet_payload = (product_description[15] & 0x7f) | 0x00 << 8;
-	HDMI_OUTP(0x00C0, packet_payload);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-
-	/* Vendor Name (7bit ASCII code) */
-	/* 0x00A8 GENERIC1_0
-	 *   BYTE0           7:0  CheckSum
-	 *   BYTE1          15:8  VENDOR_NAME[0]
-	 *   BYTE2         23:16  VENDOR_NAME[1]
-	 *   BYTE3         31:24  VENDOR_NAME[2] */
-	packet_payload = ((vendor_name[0] & 0x7f) << 8)
-		| ((vendor_name[1] & 0x7f) << 16)
-		| ((vendor_name[2] & 0x7f) << 24);
-	check_sum += IFRAME_CHECKSUM_32(packet_payload);
-	packet_payload |= ((0x100 - (0xff & check_sum)) & 0xff);
-	HDMI_OUTP(0x00A8, packet_payload);
-
-	/* GENERIC1_LINE | GENERIC1_CONT | GENERIC1_SEND
-	 * Setup HDMI TX generic packet control
-	 * Enable this packet to transmit every frame
-	 * Enable HDMI TX engine to transmit Generic packet 1 */
-	packet_control = HDMI_INP_ND(0x0034);
-	packet_control |= ((0x1 << 24) | (1 << 5) | (1 << 4));
-	HDMI_OUTP(0x0034, packet_control);
-}
-
-int hdmi_msm_clk(int on)
-{
-	int rc;
-
-	DEV_DBG("HDMI Clk: %s\n", on ? "Enable" : "Disable");
-	if (on) {
-		rc = clk_prepare_enable(hdmi_msm_state->hdmi_app_clk);
-		if (rc) {
-			DEV_ERR("'hdmi_app_clk' clock enable failed, rc=%d\n",
-				rc);
-			return rc;
-		}
-
-		rc = clk_prepare_enable(hdmi_msm_state->hdmi_m_pclk);
-		if (rc) {
-			DEV_ERR("'hdmi_m_pclk' clock enable failed, rc=%d\n",
-				rc);
-			return rc;
-		}
-
-		rc = clk_prepare_enable(hdmi_msm_state->hdmi_s_pclk);
-		if (rc) {
-			DEV_ERR("'hdmi_s_pclk' clock enable failed, rc=%d\n",
-				rc);
-			return rc;
-		}
-	} else {
-		clk_disable_unprepare(hdmi_msm_state->hdmi_app_clk);
-		clk_disable_unprepare(hdmi_msm_state->hdmi_m_pclk);
-		clk_disable_unprepare(hdmi_msm_state->hdmi_s_pclk);
-	}
-
-	return 0;
-}
-
-static void hdmi_msm_turn_on(void)
-{
-	uint32 audio_pkt_ctrl, audio_cfg;
-	/*
-	 * Number of wait iterations for QDSP to disable Audio Engine
-	 * before resetting HDMI core
-	 */
-	int i = 10;
-	audio_pkt_ctrl = HDMI_INP_ND(0x0020);
-	audio_cfg = HDMI_INP_ND(0x01D0);
-
-	/*
-	 * Checking BIT[0] of AUDIO PACKET CONTROL and
-	 * AUDIO CONFIGURATION register
-	 */
-	while (((audio_pkt_ctrl & 0x00000001) || (audio_cfg & 0x00000001))
-		&& (i--)) {
-		audio_pkt_ctrl = HDMI_INP_ND(0x0020);
-		audio_cfg = HDMI_INP_ND(0x01D0);
-		DEV_DBG("%d times :: HDMI AUDIO PACKET is %08x and "
-			"AUDIO CFG is %08x", i, audio_pkt_ctrl, audio_cfg);
-		msleep(20);
-	}
-
-	hdmi_msm_set_mode(FALSE);
-	mutex_lock(&hdcp_auth_state_mutex);
-	hdmi_msm_reset_core();
-	mutex_unlock(&hdcp_auth_state_mutex);
-
-	hdmi_msm_init_phy(external_common_state->video_resolution);
-	/* HDMI_USEC_REFTIMER[0x0208] */
-	HDMI_OUTP(0x0208, 0x0001001B);
-
-	hdmi_msm_set_mode(TRUE);
-
-	hdmi_msm_video_setup(external_common_state->video_resolution);
-	if (!hdmi_msm_is_dvi_mode()) {
-		hdmi_msm_audio_setup();
-
-		/*
-		 * Send the audio switch device notification if HDCP is
-		 * not enabled. Otherwise, the notification would be
-		 * sent after HDCP authentication is successful.
-		 */
-		if (!hdmi_msm_state->hdcp_enable)
-			SWITCH_SET_HDMI_AUDIO(1, 0);
-	}
-	hdmi_msm_avi_info_frame();
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	hdmi_msm_vendor_infoframe_packetsetup();
-#endif
-	hdmi_msm_spd_infoframe_packetsetup();
-
-	if (hdmi_msm_state->hdcp_enable && hdmi_msm_state->reauth) {
-		hdmi_msm_hdcp_enable();
-		hdmi_msm_state->reauth = FALSE ;
-	}
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	/* re-initialize CEC if enabled */
-	mutex_lock(&hdmi_msm_state_mutex);
-	if (hdmi_msm_state->cec_enabled == true) {
-		hdmi_msm_cec_init();
-		hdmi_msm_cec_write_logical_addr(
-			hdmi_msm_state->cec_logical_addr);
-	}
-	mutex_unlock(&hdmi_msm_state_mutex);
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-	DEV_INFO("HDMI Core: Initialized\n");
-}
-
-static void hdmi_msm_hdcp_timer(unsigned long data)
-{
-	if (!hdmi_msm_state->hdcp_enable) {
-		DEV_DBG("%s: HDCP not enabled\n", __func__);
-		return;
-	}
-
-	queue_work(hdmi_work_queue, &hdmi_msm_state->hdcp_work);
-}
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-static void hdmi_msm_cec_read_timer_func(unsigned long data)
-{
-	queue_work(hdmi_work_queue, &hdmi_msm_state->cec_latch_detect_work);
-}
-#endif
-
-static void hdmi_msm_hpd_polarity_setup(void)
-{
-	u32 cable_sense;
-	bool polarity = !external_common_state->hpd_state;
-	bool trigger = false;
-
-	if (polarity)
-		HDMI_OUTP(0x0254, BIT(2) | BIT(1));
-	else
-		HDMI_OUTP(0x0254, BIT(2));
-
-	cable_sense = (HDMI_INP(0x0250) & BIT(1)) >> 1;
-
-	if (cable_sense == polarity)
-		trigger = true;
-
-	DEV_DBG("%s: listen=%s, sense=%s, trigger=%s\n", __func__,
-		polarity ? "connect" : "disconnect",
-		cable_sense ? "connect" : "disconnect",
-		trigger ? "Yes" : "No");
-
-	if (trigger) {
-		u32 reg_val = HDMI_INP(0x0258);
-
-		/* Toggle HPD circuit to trigger HPD sense */
-		HDMI_OUTP(0x0258, reg_val & ~BIT(28));
-		HDMI_OUTP(0x0258, reg_val | BIT(28));
-	}
-}
-
-static void hdmi_msm_hpd_off(void)
-{
-	int rc = 0;
-
-	if (!hdmi_msm_state->hpd_initialized) {
-		DEV_DBG("%s: HPD is already OFF, returning\n", __func__);
-		return;
-	}
-
-	DEV_DBG("%s: (timer, 5V, IRQ off)\n", __func__);
-	disable_irq(hdmi_msm_state->irq);
-
-	/* Disable HPD interrupt */
-	HDMI_OUTP(0x0254, 0);
-	DEV_DBG("%s: Disabling HPD_CTRLd\n", __func__);
-
-	hdmi_msm_set_mode(FALSE);
-	hdmi_msm_state->pd->enable_5v(0);
-	hdmi_msm_clk(0);
-	rc = hdmi_msm_state->pd->gpio_config(0);
-	if (rc != 0)
-		DEV_INFO("%s: Failed to disable GPIOs. Error=%d\n",
-				__func__, rc);
-	hdmi_msm_state->hpd_initialized = FALSE;
-}
-
-static void hdmi_msm_dump_regs(const char *prefix)
-{
-#ifdef REG_DUMP
-	print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET, 32, 4,
-		(void *)MSM_HDMI_BASE, 0x0334, false);
-#endif
-}
-
-static int hdmi_msm_hpd_on(void)
-{
-	static int phy_reset_done;
-	uint32 hpd_ctrl;
-	int rc = 0;
-
-	if (hdmi_msm_state->hpd_initialized) {
-		DEV_DBG("%s: HPD is already ON\n", __func__);
-	} else {
-		rc = hdmi_msm_state->pd->gpio_config(1);
-		if (rc) {
-			DEV_ERR("%s: Failed to enable GPIOs. Error=%d\n",
-					__func__, rc);
-			goto error1;
-		}
-
-		rc = hdmi_msm_clk(1);
-		if (rc) {
-			DEV_ERR("%s: Failed to enable clocks. Error=%d\n",
-					__func__, rc);
-			goto error2;
-		}
-
-		rc = hdmi_msm_state->pd->enable_5v(1);
-		if (rc) {
-			DEV_ERR("%s: Failed to enable 5V regulator. Error=%d\n",
-					__func__, rc);
-			goto error3;
-		}
-		hdmi_msm_dump_regs("HDMI-INIT: ");
-
-		hdmi_msm_set_mode(FALSE);
-		if (!phy_reset_done) {
-			hdmi_phy_reset();
-			phy_reset_done = 1;
-		}
-		hdmi_msm_set_mode(TRUE);
-
-		/* HDMI_USEC_REFTIMER[0x0208] */
-		HDMI_OUTP(0x0208, 0x0001001B);
-
-		/* Set up HPD state variables */
-		mutex_lock(&external_common_state_hpd_mutex);
-		external_common_state->hpd_state = 0;
-		mutex_unlock(&external_common_state_hpd_mutex);
-		mutex_lock(&hdmi_msm_state_mutex);
-		mutex_unlock(&hdmi_msm_state_mutex);
-
-		enable_irq(hdmi_msm_state->irq);
-
-		hdmi_msm_state->hpd_initialized = TRUE;
-
-		/* set timeout to 4.1ms (max) for hardware debounce */
-		hpd_ctrl = HDMI_INP(0x0258) | 0x1FFF;
-
-		/* Turn on HPD HW circuit */
-		HDMI_OUTP(0x0258, hpd_ctrl | BIT(28));
-
-		/* Set HPD cable sense polarity */
-		hdmi_msm_hpd_polarity_setup();
-	}
-
-	DEV_DBG("%s: (IRQ, 5V on)\n", __func__);
-	return 0;
-
-error3:
-	hdmi_msm_clk(0);
-error2:
-	hdmi_msm_state->pd->gpio_config(0);
-error1:
-	return rc;
-}
-
-static int hdmi_msm_power_ctrl(boolean enable)
-{
-	int rc   = 0;
-	int time = 0;
-
-	if (enable) {
-		/*
-		 * Enable HPD only if the UI option is on or if
-		 * HDMI is configured as the primary display
-		 */
-		if (hdmi_prim_display ||
-			external_common_state->hpd_feature_on) {
-			DEV_DBG("%s: Turning HPD ciruitry on\n", __func__);
-
-			rc = hdmi_msm_hpd_on();
-			if (rc) {
-				DEV_ERR("%s: HPD ON FAILED\n", __func__);
-				return rc;
-			}
-
-			/* Wait for HPD initialization to complete */
-			INIT_COMPLETION(hdmi_msm_state->hpd_event_processed);
-			time = wait_for_completion_interruptible_timeout(
-				&hdmi_msm_state->hpd_event_processed, HZ);
-			if (!time && !external_common_state->hpd_state) {
-				DEV_DBG("%s: cable not detected\n", __func__);
-				queue_work(hdmi_work_queue,
-				    &hdmi_msm_state->hpd_state_work);
-			}
-		}
-	} else {
-		DEV_DBG("%s: Turning HPD ciruitry off\n", __func__);
-		hdmi_msm_hpd_off();
-	}
-
-	return rc;
-}
-
-static int hdmi_msm_power_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
-	int ret = 0;
-	bool changed;
-
-	if (!hdmi_ready()) {
-		DEV_ERR("%s: HDMI/HPD not initialized\n", __func__);
-		return ret;
-	}
-
-	if (!external_common_state->hpd_state) {
-		DEV_DBG("%s:HDMI cable not connected\n", __func__);
-		goto error;
-	}
-
-	/* Only start transmission with supported resolution */
-	changed = hdmi_common_get_video_format_from_drv_data(mfd);
-	if (changed || external_common_state->default_res_supported) {
-		mutex_lock(&external_common_state_hpd_mutex);
-		if (external_common_state->hpd_state &&
-				hdmi_msm_is_power_on()) {
-			mutex_unlock(&external_common_state_hpd_mutex);
-
-			DEV_INFO("HDMI cable connected %s(%dx%d, %d)\n",
-				__func__, mfd->var_xres, mfd->var_yres,
-				mfd->var_pixclock);
-
-			hdmi_msm_turn_on();
-			hdmi_msm_state->panel_power_on = TRUE;
-
-			if (hdmi_msm_state->hdcp_enable) {
-				/* Kick off HDCP Authentication */
-				mutex_lock(&hdcp_auth_state_mutex);
-				hdmi_msm_state->reauth = FALSE;
-				hdmi_msm_state->full_auth_done = FALSE;
-				mutex_unlock(&hdcp_auth_state_mutex);
-				mod_timer(&hdmi_msm_state->hdcp_timer,
-						jiffies + HZ/2);
-			}
-		} else {
-			mutex_unlock(&external_common_state_hpd_mutex);
-		}
-
-		hdmi_msm_dump_regs("HDMI-ON: ");
-		DEV_INFO("power=%s DVI= %s\n",
-			hdmi_msm_is_power_on() ? "ON" : "OFF" ,
-			hdmi_msm_is_dvi_mode() ? "ON" : "OFF");
-	} else {
-		DEV_ERR("%s: Video fmt %d not supp. Returning\n",
-				__func__,
-				external_common_state->video_resolution);
-	}
-
-error:
-	/* Set HPD cable sense polarity */
-	hdmi_msm_hpd_polarity_setup();
-
-	return ret;
-}
-
-void mhl_connect_api(boolean on)
-{
-	char *envp[2];
-
-	/* Simulating a HPD event based on MHL event */
-	if (on) {
-		hdmi_msm_read_edid();
-		hdmi_msm_state->reauth = FALSE ;
-		/* Build EDID table */
-		hdmi_msm_turn_on();
-		DEV_INFO("HDMI HPD: CONNECTED: send ONLINE\n");
-		kobject_uevent(external_common_state->uevent_kobj,
-			       KOBJ_ONLINE);
-		envp[0] = 0;
-		if (!hdmi_msm_state->hdcp_enable) {
-			/* Send Audio for HDMI Compliance Cases*/
-			envp[0] = "HDCP_STATE=PASS";
-			envp[1] = NULL;
-			DEV_INFO("HDMI HPD: sense : send HDCP_PASS\n");
-			kobject_uevent_env(external_common_state->uevent_kobj,
-					   KOBJ_CHANGE, envp);
-			switch_set_state(&external_common_state->sdev, 1);
-			DEV_INFO("%s: hdmi state switched to %d\n",
-				 __func__, external_common_state->sdev.state);
-		} else {
-			hdmi_msm_hdcp_enable();
-		}
-	} else {
-		DEV_INFO("HDMI HPD: DISCONNECTED: send OFFLINE\n");
-		kobject_uevent(external_common_state->uevent_kobj,
-			       KOBJ_OFFLINE);
-		switch_set_state(&external_common_state->sdev, 0);
-		DEV_INFO("%s: hdmi state switched to %d\n", __func__,
-				external_common_state->sdev.state);
-	}
-}
-EXPORT_SYMBOL(mhl_connect_api);
-
-/* Note that power-off will also be called when the cable-remove event is
- * processed on the user-space and as a result the framebuffer is powered
- * down.  However, we are still required to be able to detect a cable-insert
- * event; so for now leave the HDMI engine running; so that the HPD IRQ is
- * still being processed.
- */
-static int hdmi_msm_power_off(struct platform_device *pdev)
-{
-	int ret = 0;
-
-	if (!hdmi_ready()) {
-		DEV_ERR("%s: HDMI/HPD not initialized\n", __func__);
-		return ret;
-	}
-
-	if (!hdmi_msm_state->panel_power_on) {
-		DEV_DBG("%s: panel not ON\n", __func__);
-		goto error;
-	}
-
-	if (hdmi_msm_state->hdcp_enable) {
-		if (hdmi_msm_state->hdcp_activating) {
-			/*
-			 * Let the HDCP work know that we got an HPD
-			 * disconnect so that it can stop the
-			 * reauthentication loop.
-			 */
-			mutex_lock(&hdcp_auth_state_mutex);
-			hdmi_msm_state->hpd_during_auth = TRUE;
-			mutex_unlock(&hdcp_auth_state_mutex);
-		}
-
-		/*
-		 * Cancel any pending reauth attempts.
-		 * If one is ongoing, wait for it to finish
-		 */
-		cancel_work_sync(&hdmi_msm_state->hdcp_reauth_work);
-		cancel_work_sync(&hdmi_msm_state->hdcp_work);
-		del_timer_sync(&hdmi_msm_state->hdcp_timer);
-		hdmi_msm_state->reauth = FALSE;
-
-		hdcp_deauthenticate();
-	}
-
-	SWITCH_SET_HDMI_AUDIO(0, 0);
-
-	if (!hdmi_msm_is_dvi_mode())
-		hdmi_msm_audio_off();
-
-	hdmi_msm_powerdown_phy();
-
-	hdmi_msm_state->panel_power_on = FALSE;
-	DEV_INFO("power: OFF (audio off)\n");
-
-	if (!completion_done(&hdmi_msm_state->hpd_event_processed))
-		complete(&hdmi_msm_state->hpd_event_processed);
-error:
-	/* Set HPD cable sense polarity */
-	hdmi_msm_hpd_polarity_setup();
-
-	return ret;
-}
-
-bool mhl_is_enabled(void)
-{
-	return hdmi_msm_state->is_mhl_enabled;
-}
-
-void hdmi_msm_config_hdcp_feature(void)
-{
-	if (hdcp_feature_on && hdmi_msm_has_hdcp()) {
-		init_timer(&hdmi_msm_state->hdcp_timer);
-		hdmi_msm_state->hdcp_timer.function = hdmi_msm_hdcp_timer;
-		hdmi_msm_state->hdcp_timer.data = (uint32)NULL;
-		hdmi_msm_state->hdcp_timer.expires = 0xffffffffL;
-
-		init_completion(&hdmi_msm_state->hdcp_success_done);
-		INIT_WORK(&hdmi_msm_state->hdcp_reauth_work,
-				hdmi_msm_hdcp_reauth_work);
-		INIT_WORK(&hdmi_msm_state->hdcp_work, hdmi_msm_hdcp_work);
-		hdmi_msm_state->hdcp_enable = TRUE;
-	} else {
-		del_timer(&hdmi_msm_state->hdcp_timer);
-		hdmi_msm_state->hdcp_enable = FALSE;
-	}
-	external_common_state->present_hdcp = hdmi_msm_state->hdcp_enable;
-	DEV_INFO("%s: HDCP Feature: %s\n", __func__,
-			hdmi_msm_state->hdcp_enable ? "Enabled" : "Disabled");
-}
-
-static void hdmi_msm_update_panel_info(struct msm_fb_data_type *mfd)
-{
-	if (!mfd)
-		return;
-
-	if (hdmi_common_get_video_format_from_drv_data(mfd))
-		hdmi_common_init_panel_info(&mfd->panel_info);
-}
-
-static bool hdmi_msm_cable_connected(void)
-{
-	return hdmi_msm_state->hpd_initialized &&
-			external_common_state->hpd_state;
-}
-
-static int __devinit hdmi_msm_probe(struct platform_device *pdev)
-{
-	int rc;
-	struct platform_device *fb_dev;
-	struct msm_fb_data_type *mfd = NULL;
-
-	if (!hdmi_msm_state) {
-		pr_err("%s: hdmi_msm_state is NULL\n", __func__);
-		return -ENOMEM;
-	}
-
-	external_common_state->dev = &pdev->dev;
-	DEV_DBG("probe\n");
-	if (pdev->id == 0) {
-		struct resource *res;
-
-		#define GET_RES(name, mode) do {			\
-			res = platform_get_resource_byname(pdev, mode, name); \
-			if (!res) {					\
-				DEV_ERR("'" name "' resource not found\n"); \
-				rc = -ENODEV;				\
-				goto error;				\
-			}						\
-		} while (0)
-
-		#define IO_REMAP(var, name) do {			\
-			GET_RES(name, IORESOURCE_MEM);			\
-			var = ioremap(res->start, resource_size(res));	\
-			if (!var) {					\
-				DEV_ERR("'" name "' ioremap failed\n");	\
-				rc = -ENOMEM;				\
-				goto error;				\
-			}						\
-		} while (0)
-
-		#define GET_IRQ(var, name) do {				\
-			GET_RES(name, IORESOURCE_IRQ);			\
-			var = res->start;				\
-		} while (0)
-
-		IO_REMAP(hdmi_msm_state->qfprom_io, "hdmi_msm_qfprom_addr");
-		hdmi_msm_state->hdmi_io = MSM_HDMI_BASE;
-		GET_IRQ(hdmi_msm_state->irq, "hdmi_msm_irq");
-
-		hdmi_msm_state->pd = pdev->dev.platform_data;
-
-		#undef GET_RES
-		#undef IO_REMAP
-		#undef GET_IRQ
-		return 0;
-	}
-
-	hdmi_msm_state->hdmi_app_clk = clk_get(&pdev->dev, "core_clk");
-	if (IS_ERR(hdmi_msm_state->hdmi_app_clk)) {
-		DEV_ERR("'core_clk' clk not found\n");
-		rc = IS_ERR(hdmi_msm_state->hdmi_app_clk);
-		goto error;
-	}
-
-	hdmi_msm_state->hdmi_m_pclk = clk_get(&pdev->dev, "master_iface_clk");
-	if (IS_ERR(hdmi_msm_state->hdmi_m_pclk)) {
-		DEV_ERR("'master_iface_clk' clk not found\n");
-		rc = IS_ERR(hdmi_msm_state->hdmi_m_pclk);
-		goto error;
-	}
-
-	hdmi_msm_state->hdmi_s_pclk = clk_get(&pdev->dev, "slave_iface_clk");
-	if (IS_ERR(hdmi_msm_state->hdmi_s_pclk)) {
-		DEV_ERR("'slave_iface_clk' clk not found\n");
-		rc = IS_ERR(hdmi_msm_state->hdmi_s_pclk);
-		goto error;
-	}
-
-	hdmi_msm_state->is_mhl_enabled = hdmi_msm_state->pd->is_mhl_enabled;
-
-	rc = check_hdmi_features();
-	if (rc) {
-		DEV_ERR("Init FAILED: check_hdmi_features rc=%d\n", rc);
-		goto error;
-	}
-
-	if (!hdmi_msm_state->pd->core_power) {
-		DEV_ERR("Init FAILED: core_power function missing\n");
-		rc = -ENODEV;
-		goto error;
-	}
-	if (!hdmi_msm_state->pd->enable_5v) {
-		DEV_ERR("Init FAILED: enable_5v function missing\n");
-		rc = -ENODEV;
-		goto error;
-	}
-
-	if (!hdmi_msm_state->pd->cec_power) {
-		DEV_ERR("Init FAILED: cec_power function missing\n");
-		rc = -ENODEV;
-		goto error;
-	}
-
-	rc = request_threaded_irq(hdmi_msm_state->irq, NULL, &hdmi_msm_isr,
-		IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "hdmi_msm_isr", NULL);
-	if (rc) {
-		DEV_ERR("Init FAILED: IRQ request, rc=%d\n", rc);
-		goto error;
-	}
-	disable_irq(hdmi_msm_state->irq);
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	init_timer(&hdmi_msm_state->cec_read_timer);
-	hdmi_msm_state->cec_read_timer.function =
-		hdmi_msm_cec_read_timer_func;
-	hdmi_msm_state->cec_read_timer.data = (uint32)NULL;
-
-	hdmi_msm_state->cec_read_timer.expires = 0xffffffffL;
- #endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-	fb_dev = msm_fb_add_device(pdev);
-	if (fb_dev) {
-		rc = external_common_state_create(fb_dev);
-		if (rc) {
-			DEV_ERR("Init FAILED: hdmi_msm_state_create, rc=%d\n",
-				rc);
-			goto error;
-		}
-	} else
-		DEV_ERR("Init FAILED: failed to add fb device\n");
-
-	mfd = platform_get_drvdata(fb_dev);
-	mfd->update_panel_info = hdmi_msm_update_panel_info;
-	mfd->is_panel_ready = hdmi_msm_cable_connected;
-
-	if (hdmi_prim_display) {
-		rc = hdmi_msm_hpd_on();
-		if (rc)
-			goto error;
-	}
-
-	hdmi_msm_config_hdcp_feature();
-
-	/* Initialize hdmi node and register with switch driver */
-	if (hdmi_prim_display)
-		external_common_state->sdev.name = "hdmi_as_primary";
-	else
-		external_common_state->sdev.name = "hdmi";
-	if (switch_dev_register(&external_common_state->sdev) < 0) {
-		DEV_ERR("Hdmi switch registration failed\n");
-		rc = -ENODEV;
-		goto error;
-	}
-
-	external_common_state->audio_sdev.name = "hdmi_audio";
-	if (switch_dev_register(&external_common_state->audio_sdev) < 0) {
-		DEV_ERR("Hdmi audio switch registration failed\n");
-		switch_dev_unregister(&external_common_state->sdev);
-		rc = -ENODEV;
-		goto error;
-	}
-
-	/* Set the default video resolution for MHL-enabled display */
-	if (hdmi_msm_state->is_mhl_enabled) {
-		DEV_DBG("MHL Enabled. Restricting default video resolution\n");
-		external_common_state->video_resolution =
-			HDMI_VFRMT_1920x1080p30_16_9;
-	}
-	return 0;
-
-error:
-	if (hdmi_msm_state->qfprom_io)
-		iounmap(hdmi_msm_state->qfprom_io);
-	hdmi_msm_state->qfprom_io = NULL;
-
-	if (hdmi_msm_state->hdmi_io)
-		iounmap(hdmi_msm_state->hdmi_io);
-	hdmi_msm_state->hdmi_io = NULL;
-
-	external_common_state_remove();
-
-	if (hdmi_msm_state->hdmi_app_clk)
-		clk_put(hdmi_msm_state->hdmi_app_clk);
-	if (hdmi_msm_state->hdmi_m_pclk)
-		clk_put(hdmi_msm_state->hdmi_m_pclk);
-	if (hdmi_msm_state->hdmi_s_pclk)
-		clk_put(hdmi_msm_state->hdmi_s_pclk);
-
-	hdmi_msm_state->hdmi_app_clk = NULL;
-	hdmi_msm_state->hdmi_m_pclk = NULL;
-	hdmi_msm_state->hdmi_s_pclk = NULL;
-
-	return rc;
-}
-
-static int __devexit hdmi_msm_remove(struct platform_device *pdev)
-{
-	DEV_INFO("HDMI device: remove\n");
-
-	DEV_INFO("HDMI HPD: OFF\n");
-
-	/* Unregister hdmi node from switch driver */
-	switch_dev_unregister(&external_common_state->sdev);
-	switch_dev_unregister(&external_common_state->audio_sdev);
-
-	hdmi_msm_hpd_off();
-	free_irq(hdmi_msm_state->irq, NULL);
-
-	if (hdmi_msm_state->qfprom_io)
-		iounmap(hdmi_msm_state->qfprom_io);
-	hdmi_msm_state->qfprom_io = NULL;
-
-	if (hdmi_msm_state->hdmi_io)
-		iounmap(hdmi_msm_state->hdmi_io);
-	hdmi_msm_state->hdmi_io = NULL;
-
-	external_common_state_remove();
-
-	if (hdmi_msm_state->hdmi_app_clk)
-		clk_put(hdmi_msm_state->hdmi_app_clk);
-	if (hdmi_msm_state->hdmi_m_pclk)
-		clk_put(hdmi_msm_state->hdmi_m_pclk);
-	if (hdmi_msm_state->hdmi_s_pclk)
-		clk_put(hdmi_msm_state->hdmi_s_pclk);
-
-	hdmi_msm_state->hdmi_app_clk = NULL;
-	hdmi_msm_state->hdmi_m_pclk = NULL;
-	hdmi_msm_state->hdmi_s_pclk = NULL;
-
-	kfree(hdmi_msm_state);
-	hdmi_msm_state = NULL;
-
-	return 0;
-}
-
-static int hdmi_msm_hpd_feature(int on)
-{
-	int rc = 0;
-
-	DEV_INFO("%s: %d\n", __func__, on);
-	if (on) {
-		rc = hdmi_msm_hpd_on();
-	} else {
-		if (external_common_state->hpd_state) {
-			external_common_state->hpd_state = 0;
-
-			/* Send offline event to switch OFF HDMI and HAL FD */
-			hdmi_msm_send_event(HPD_EVENT_OFFLINE);
-
-			/* Wait for HDMI and FD to close */
-			INIT_COMPLETION(hdmi_msm_state->hpd_event_processed);
-			wait_for_completion_interruptible_timeout(
-				&hdmi_msm_state->hpd_event_processed, HZ);
-		}
-
-		hdmi_msm_hpd_off();
-
-		/* Set HDMI switch node to 0 on HPD feature disable */
-		switch_set_state(&external_common_state->sdev, 0);
-		DEV_INFO("%s: hdmi state switched to %d\n", __func__,
-				external_common_state->sdev.state);
-	}
-
-	return rc;
-}
-
-static struct platform_driver this_driver = {
-	.probe = hdmi_msm_probe,
-	.remove = hdmi_msm_remove,
-	.driver.name = "hdmi_msm",
-};
-
-static struct msm_fb_panel_data hdmi_msm_panel_data = {
-	.on = hdmi_msm_power_on,
-	.off = hdmi_msm_power_off,
-	.power_ctrl = hdmi_msm_power_ctrl,
-};
-
-static struct platform_device this_device = {
-	.name = "hdmi_msm",
-	.id = 1,
-	.dev.platform_data = &hdmi_msm_panel_data,
-};
-
-static int __init hdmi_msm_init(void)
-{
-	int rc;
-
-	if (msm_fb_detect_client("hdmi_msm"))
-		return 0;
-
-#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
-	hdmi_prim_display = 1;
-#endif
-
-	hdmi_msm_setup_video_mode_lut();
-	hdmi_msm_state = kzalloc(sizeof(*hdmi_msm_state), GFP_KERNEL);
-	if (!hdmi_msm_state) {
-		pr_err("hdmi_msm_init FAILED: out of memory\n");
-		rc = -ENOMEM;
-		goto init_exit;
-	}
-
-	external_common_state = &hdmi_msm_state->common;
-
-	if (hdmi_prim_display && hdmi_prim_resolution)
-		external_common_state->video_resolution =
-			hdmi_prim_resolution - 1;
-	else
-		external_common_state->video_resolution =
-			HDMI_VFRMT_1920x1080p60_16_9;
-
-#ifdef CONFIG_FB_MSM_HDMI_3D
-	external_common_state->switch_3d = hdmi_msm_switch_3d;
-#endif
-	memset(external_common_state->spd_vendor_name, 0,
-			sizeof(external_common_state->spd_vendor_name));
-	memset(external_common_state->spd_product_description, 0,
-			sizeof(external_common_state->spd_product_description));
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	hdmi_msm_state->cec_queue_start =
-		kzalloc(sizeof(struct hdmi_msm_cec_msg)*CEC_QUEUE_SIZE,
-			GFP_KERNEL);
-	if (!hdmi_msm_state->cec_queue_start) {
-		pr_err("hdmi_msm_init FAILED: CEC queue out of memory\n");
-		rc = -ENOMEM;
-		goto init_exit;
-	}
-
-	hdmi_msm_state->cec_queue_wr = hdmi_msm_state->cec_queue_start;
-	hdmi_msm_state->cec_queue_rd = hdmi_msm_state->cec_queue_start;
-	hdmi_msm_state->cec_queue_full = false;
-#endif
-
-	/*
-	 * Create your work queue
-	 * allocs and returns ptr
-	*/
-	hdmi_work_queue = create_workqueue("hdmi_hdcp");
-	external_common_state->hpd_feature = hdmi_msm_hpd_feature;
-
-	rc = platform_driver_register(&this_driver);
-	if (rc) {
-		pr_err("hdmi_msm_init FAILED: platform_driver_register rc=%d\n",
-		       rc);
-		goto init_exit;
-	}
-
-	hdmi_common_init_panel_info(&hdmi_msm_panel_data.panel_info);
-	init_completion(&hdmi_msm_state->ddc_sw_done);
-	init_completion(&hdmi_msm_state->hpd_event_processed);
-	INIT_WORK(&hdmi_msm_state->hpd_state_work, hdmi_msm_hpd_state_work);
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	INIT_WORK(&hdmi_msm_state->cec_latch_detect_work,
-		  hdmi_msm_cec_latch_work);
-	init_completion(&hdmi_msm_state->cec_frame_wr_done);
-	init_completion(&hdmi_msm_state->cec_line_latch_wait);
-#endif
-
-	rc = platform_device_register(&this_device);
-	if (rc) {
-		pr_err("hdmi_msm_init FAILED: platform_device_register rc=%d\n",
-		       rc);
-		platform_driver_unregister(&this_driver);
-		goto init_exit;
-	}
-
-	pr_debug("%s: success:"
-#ifdef DEBUG
-		" DEBUG"
-#else
-		" RELEASE"
-#endif
-		" AUDIO EDID HPD HDCP"
-		" DVI"
-#ifndef CONFIG_FB_MSM_HDMI_MSM_PANEL_DVI_SUPPORT
-		":0"
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_DVI_SUPPORT */
-		"\n", __func__);
-
-	return 0;
-
-init_exit:
-	kfree(hdmi_msm_state);
-	hdmi_msm_state = NULL;
-
-	return rc;
-}
-
-static void __exit hdmi_msm_exit(void)
-{
-	platform_device_unregister(&this_device);
-	platform_driver_unregister(&this_driver);
-}
-
-static int set_hdcp_feature_on(const char *val, const struct kernel_param *kp)
-{
-	int rv = param_set_bool(val, kp);
-
-	if (rv)
-		return rv;
-
-	pr_debug("%s: HDCP feature = %d\n", __func__, hdcp_feature_on);
-	if (hdmi_msm_state) {
-		if ((HDMI_INP(0x0250) & 0x2)) {
-			pr_err("%s: Unable to set HDCP feature", __func__);
-			pr_err("%s: HDMI panel is currently turned on",
-					__func__);
-		} else if (hdcp_feature_on != hdmi_msm_state->hdcp_enable) {
-			hdmi_msm_config_hdcp_feature();
-		}
-	}
-
-	return 0;
-}
-
-static struct kernel_param_ops hdcp_feature_on_param_ops = {
-	.set = set_hdcp_feature_on,
-	.get = param_get_bool,
-};
-
-module_param_cb(hdcp, &hdcp_feature_on_param_ops, &hdcp_feature_on,
-			S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(hdcp, "Enable or Disable HDCP");
-
-module_init(hdmi_msm_init);
-module_exit(hdmi_msm_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_VERSION("0.3");
-MODULE_AUTHOR("Qualcomm Innovation Center, Inc.");
-MODULE_DESCRIPTION("HDMI MSM TX driver");
diff --git a/drivers/video/msm/hdmi_msm.h b/drivers/video/msm/hdmi_msm.h
deleted file mode 100644
index ce01830..0000000
--- a/drivers/video/msm/hdmi_msm.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __HDMI_MSM_H__
-#define __HDMI_MSM_H__
-
-#include <mach/msm_iomap.h>
-#include "external_common.h"
-/* #define PORT_DEBUG */
-
-#ifdef PORT_DEBUG
-const char *hdmi_msm_name(uint32 offset);
-void hdmi_outp(uint32 offset, uint32 value);
-uint32 hdmi_inp(uint32 offset);
-
-#define HDMI_OUTP_ND(offset, value)	outpdw(MSM_HDMI_BASE+(offset), (value))
-#define HDMI_OUTP(offset, value)	hdmi_outp((offset), (value))
-#define HDMI_INP_ND(offset)		inpdw(MSM_HDMI_BASE+(offset))
-#define HDMI_INP(offset)		hdmi_inp((offset))
-#else
-#define HDMI_OUTP_ND(offset, value)	outpdw(MSM_HDMI_BASE+(offset), (value))
-#define HDMI_OUTP(offset, value)	outpdw(MSM_HDMI_BASE+(offset), (value))
-#define HDMI_INP_ND(offset)		inpdw(MSM_HDMI_BASE+(offset))
-#define HDMI_INP(offset)		inpdw(MSM_HDMI_BASE+(offset))
-#endif
-
-
-/*
- * Ref. HDMI 1.4a
- * Supplement-1 CEC Section 6, 7
- */
-struct hdmi_msm_cec_msg {
-	uint8 sender_id;
-	uint8 recvr_id;
-	uint8 opcode;
-	uint8 operand[15];
-	uint8 frame_size;
-	uint8 retransmit;
-};
-
-#define QFPROM_BASE		((uint32)hdmi_msm_state->qfprom_io)
-#define HDMI_BASE		((uint32)hdmi_msm_state->hdmi_io)
-
-struct hdmi_msm_state_type {
-	boolean panel_power_on;
-	boolean hpd_initialized;
-#ifdef CONFIG_SUSPEND
-	boolean pm_suspended;
-#endif
-	boolean full_auth_done;
-	boolean hpd_during_auth;
-	struct work_struct hpd_state_work;
-	struct completion ddc_sw_done;
-
-	bool hdcp_enable;
-	boolean hdcp_activating;
-	boolean reauth ;
-	struct work_struct hdcp_reauth_work, hdcp_work;
-	struct completion hdcp_success_done;
-	struct timer_list hdcp_timer;
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-	boolean cec_enabled;
-	unsigned int first_monitor;
-	int cec_logical_addr;
-	struct completion cec_frame_wr_done;
-	struct timer_list cec_read_timer;
-#define CEC_STATUS_WR_ERROR	0x0001
-#define CEC_STATUS_WR_DONE	0x0002
-#define CEC_STATUS_WR_TMOUT	0x0004
-	uint32 cec_frame_wr_status;
-
-	struct hdmi_msm_cec_msg *cec_queue_start;
-	struct hdmi_msm_cec_msg *cec_queue_wr;
-	struct hdmi_msm_cec_msg *cec_queue_rd;
-	boolean cec_queue_full;
-	boolean fsm_reset_done;
-
-	/*
-	 * CECT 9-5-1
-	 */
-	struct completion cec_line_latch_wait;
-	struct work_struct cec_latch_detect_work;
-
-#define CEC_QUEUE_SIZE		16
-#define CEC_QUEUE_END	 (hdmi_msm_state->cec_queue_start + CEC_QUEUE_SIZE)
-#define RETRANSMIT_MAX_NUM	5
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-
-	int irq;
-	struct msm_hdmi_platform_data *pd;
-	struct clk *hdmi_app_clk;
-	struct clk *hdmi_m_pclk;
-	struct clk *hdmi_s_pclk;
-	void __iomem *qfprom_io;
-	void __iomem *hdmi_io;
-
-	struct external_common_state_type common;
-	boolean is_mhl_enabled;
-	struct completion hpd_event_processed;
-};
-
-extern struct hdmi_msm_state_type *hdmi_msm_state;
-
-uint32 hdmi_msm_get_io_base(void);
-
-#ifdef CONFIG_FB_MSM_HDMI_COMMON
-void hdmi_msm_set_mode(boolean power_on);
-int hdmi_msm_clk(int on);
-void hdmi_phy_reset(void);
-void hdmi_msm_reset_core(void);
-void hdmi_msm_init_phy(int video_format);
-void hdmi_msm_powerdown_phy(void);
-void hdmi_frame_ctrl_cfg(const struct hdmi_disp_mode_timing_type *timing);
-void hdmi_msm_phy_status_poll(void);
-#endif
-
-#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT
-void hdmi_msm_cec_init(void);
-void hdmi_msm_cec_write_logical_addr(int addr);
-void hdmi_msm_cec_msg_recv(void);
-void hdmi_msm_cec_one_touch_play(void);
-void hdmi_msm_cec_msg_send(struct hdmi_msm_cec_msg *msg);
-#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL_CEC_SUPPORT */
-void mhl_connect_api(boolean on);
-#endif /* __HDMI_MSM_H__ */
diff --git a/drivers/video/msm/hdmi_sii9022.c b/drivers/video/msm/hdmi_sii9022.c
deleted file mode 100644
index c1b5e03..0000000
--- a/drivers/video/msm/hdmi_sii9022.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/i2c.h>
-#include <linux/delay.h>
-#include "msm_fb.h"
-
-#define DEVICE_NAME "sii9022"
-#define SII9022_DEVICE_ID   0xB0
-
-struct sii9022_i2c_addr_data{
-	u8 addr;
-	u8 data;
-};
-
-/* video mode data */
-static u8 video_mode_data[] = {
-	0x00,
-	0xF9, 0x1C, 0x70, 0x17, 0x72, 0x06, 0xEE, 0x02,
-};
-
-static u8 avi_io_format[] = {
-	0x09,
-	0x00, 0x00,
-};
-
-/* power state */
-static struct sii9022_i2c_addr_data regset0[] = {
-	{ 0x60, 0x04 },
-	{ 0x63, 0x00 },
-	{ 0x1E, 0x00 },
-};
-
-static u8 video_infoframe[] = {
-	0x0C,
-	0xF0, 0x00, 0x68, 0x00, 0x04, 0x00, 0x19, 0x00,
-	0xE9, 0x02, 0x04, 0x01, 0x04, 0x06,
-};
-
-/* configure audio */
-static struct sii9022_i2c_addr_data regset1[] = {
-	{ 0x26, 0x90 },
-	{ 0x20, 0x90 },
-	{ 0x1F, 0x80 },
-	{ 0x26, 0x80 },
-	{ 0x24, 0x02 },
-	{ 0x25, 0x0B },
-	{ 0xBC, 0x02 },
-	{ 0xBD, 0x24 },
-	{ 0xBE, 0x02 },
-};
-
-/* enable audio */
-static u8 misc_infoframe[] = {
-	0xBF,
-	0xC2, 0x84, 0x01, 0x0A, 0x6F, 0x02, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-/* set HDMI, active */
-static struct sii9022_i2c_addr_data regset2[] = {
-	{ 0x1A, 0x01 },
-	{ 0x3D, 0x00 },
-};
-
-static int send_i2c_data(struct i2c_client *client,
-			 struct sii9022_i2c_addr_data *regset,
-			 int size)
-{
-	int i;
-	int rc = 0;
-
-	for (i = 0; i < size; i++) {
-		rc = i2c_smbus_write_byte_data(
-			client,
-			regset[i].addr, regset[i].data);
-		if (rc)
-			break;
-	}
-	return rc;
-}
-
-static int hdmi_sii_enable(struct i2c_client *client)
-{
-	int rc;
-	int retries = 10;
-	int count;
-
-	rc = i2c_smbus_write_byte_data(client, 0xC7, 0x00);
-	if (rc)
-		goto enable_exit;
-
-	do {
-		msleep(1);
-		rc = i2c_smbus_read_byte_data(client, 0x1B);
-	} while ((rc != SII9022_DEVICE_ID) && retries--);
-
-	if (rc != SII9022_DEVICE_ID)
-		return -ENODEV;
-
-	rc = i2c_smbus_write_byte_data(client, 0x1A, 0x11);
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(video_mode_data);
-	rc = i2c_master_send(client, video_mode_data, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = i2c_smbus_write_byte_data(client, 0x08, 0x20);
-	if (rc)
-		goto enable_exit;
-	count = ARRAY_SIZE(avi_io_format);
-	rc = i2c_master_send(client, avi_io_format, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset0, ARRAY_SIZE(regset0));
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(video_infoframe);
-	rc = i2c_master_send(client, video_infoframe, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset1, ARRAY_SIZE(regset1));
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(misc_infoframe);
-	rc = i2c_master_send(client, misc_infoframe, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset2, ARRAY_SIZE(regset2));
-	if (rc)
-		goto enable_exit;
-
-	return 0;
-enable_exit:
-	printk(KERN_ERR "%s: exited rc=%d\n", __func__, rc);
-	return rc;
-}
-
-static const struct i2c_device_id hmdi_sii_id[] = {
-	{ DEVICE_NAME, 0 },
-	{ }
-};
-
-static int hdmi_sii_probe(struct i2c_client *client,
-			const struct i2c_device_id *id)
-{
-	int rc;
-
-	if (!i2c_check_functionality(client->adapter,
-				     I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
-		return -ENODEV;
-	rc = hdmi_sii_enable(client);
-	return rc;
-}
-
-
-static struct i2c_driver hdmi_sii_i2c_driver = {
-	.driver = {
-		.name = DEVICE_NAME,
-		.owner = THIS_MODULE,
-	},
-	.probe = hdmi_sii_probe,
-	.remove =  __exit_p(hdmi_sii_remove),
-	.id_table = hmdi_sii_id,
-};
-
-static int __init hdmi_sii_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-
-	if (msm_fb_detect_client("hdmi_sii9022"))
-		return 0;
-
-	pinfo.xres = 1280;
-	pinfo.yres = 720;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = HDMI_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 18;
-	pinfo.fb_num = 2;
-	pinfo.clk_rate = 74250000;
-
-	pinfo.lcdc.h_back_porch = 124;
-	pinfo.lcdc.h_front_porch = 110;
-	pinfo.lcdc.h_pulse_width = 136;
-	pinfo.lcdc.v_back_porch = 19;
-	pinfo.lcdc.v_front_porch = 5;
-	pinfo.lcdc.v_pulse_width = 6;
-	pinfo.lcdc.border_clr = 0;
-	pinfo.lcdc.underflow_clr = 0xff;
-	pinfo.lcdc.hsync_skew = 0;
-
-	ret = lcdc_device_register(&pinfo);
-	if (ret) {
-		printk(KERN_ERR "%s: failed to register device\n", __func__);
-		goto init_exit;
-	}
-
-	ret = i2c_add_driver(&hdmi_sii_i2c_driver);
-	if (ret)
-		printk(KERN_ERR "%s: failed to add i2c driver\n", __func__);
-
-init_exit:
-	return ret;
-}
-
-static void __exit hdmi_sii_exit(void)
-{
-	i2c_del_driver(&hdmi_sii_i2c_driver);
-}
-
-module_init(hdmi_sii_init);
-module_exit(hdmi_sii_exit);
-MODULE_LICENSE("GPL v2");
-MODULE_VERSION("0.1");
-MODULE_AUTHOR("Qualcomm Innovation Center, Inc.");
-MODULE_DESCRIPTION("SiI9022 HDMI driver");
-MODULE_ALIAS("platform:hdmi-sii9022");
diff --git a/drivers/video/msm/lcdc.c b/drivers/video/msm/lcdc.c
deleted file mode 100644
index 24c4ec9..0000000
--- a/drivers/video/msm/lcdc.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/* Copyright (c) 2008-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-
-#include "msm_fb.h"
-
-static int lcdc_probe(struct platform_device *pdev);
-static int lcdc_remove(struct platform_device *pdev);
-
-static int lcdc_off(struct platform_device *pdev);
-static int lcdc_on(struct platform_device *pdev);
-static void cont_splash_clk_ctrl(int enable);
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-
-static struct clk *pixel_mdp_clk; /* drives the lcdc block in mdp */
-static struct clk *pixel_lcdc_clk; /* drives the lcdc interface */
-
-static struct platform_driver lcdc_driver = {
-	.probe = lcdc_probe,
-	.remove = lcdc_remove,
-	.suspend = NULL,
-	.resume = NULL,
-	.shutdown = NULL,
-	.driver = {
-		   .name = "lcdc",
-		   },
-};
-
-static struct lcdc_platform_data *lcdc_pdata;
-
-static int lcdc_off(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-	ret = panel_next_off(pdev);
-
-	clk_disable_unprepare(pixel_mdp_clk);
-	clk_disable_unprepare(pixel_lcdc_clk);
-
-	if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
-		lcdc_pdata->lcdc_power_save(0);
-
-	if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
-		ret = lcdc_pdata->lcdc_gpio_config(0);
-
-#ifndef CONFIG_MSM_BUS_SCALING
-	if (mfd->ebi1_clk) {
-		if (mdp_rev == MDP_REV_303) {
-			if (clk_set_rate(mfd->ebi1_clk, 0))
-				pr_err("%s: ebi1_lcdc_clk set rate failed\n",
-					__func__);
-		}
-		clk_disable_unprepare(mfd->ebi1_clk);
-	}
-#endif
-
-	return ret;
-}
-
-static int lcdc_on(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd;
-	unsigned long panel_pixclock_freq = 0;
-#ifndef CONFIG_MSM_BUS_SCALING
-	unsigned long pm_qos_rate;
-#endif
-	mfd = platform_get_drvdata(pdev);
-
-	cont_splash_clk_ctrl(0);
-
-	if (lcdc_pdata && lcdc_pdata->lcdc_get_clk)
-		panel_pixclock_freq = lcdc_pdata->lcdc_get_clk();
-
-	if (!panel_pixclock_freq)
-		panel_pixclock_freq = mfd->fbi->var.pixclock;
-#ifndef CONFIG_MSM_BUS_SCALING
-	if (panel_pixclock_freq > 65000000)
-		/* pm_qos_rate should be in Khz */
-		pm_qos_rate = panel_pixclock_freq / 1000 ;
-	else
-		pm_qos_rate = 65000;
-
-	if (mfd->ebi1_clk) {
-		if (mdp_rev == MDP_REV_303) {
-			if (clk_set_rate(mfd->ebi1_clk, 65000000))
-				pr_err("%s: ebi1_lcdc_clk set rate failed\n",
-					__func__);
-		} else {
-			clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000);
-		}
-		clk_prepare_enable(mfd->ebi1_clk);
-	}
-
-#endif
-	mfd = platform_get_drvdata(pdev);
-
-	mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk,
-					mfd->fbi->var.pixclock);
-	ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock);
-	if (ret) {
-		pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n",
-			__func__, mfd->fbi->var.pixclock);
-		goto out;
-	}
-
-	clk_prepare_enable(pixel_mdp_clk);
-	clk_prepare_enable(pixel_lcdc_clk);
-
-	if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
-		lcdc_pdata->lcdc_power_save(1);
-	if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
-		ret = lcdc_pdata->lcdc_gpio_config(1);
-
-	ret = panel_next_on(pdev);
-
-out:
-	return ret;
-}
-
-static void cont_splash_clk_ctrl(int enable)
-{
-	static int cont_splash_clks_enabled;
-	if (enable && !cont_splash_clks_enabled) {
-		clk_prepare_enable(pixel_mdp_clk);
-		clk_prepare_enable(pixel_lcdc_clk);
-		cont_splash_clks_enabled = 1;
-	} else if (!enable && cont_splash_clks_enabled) {
-		clk_disable_unprepare(pixel_mdp_clk);
-		clk_disable_unprepare(pixel_lcdc_clk);
-		cont_splash_clks_enabled = 0;
-	}
-}
-
-static int lcdc_probe(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	struct fb_info *fbi;
-	struct platform_device *mdp_dev = NULL;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-	struct clk *ebi1_clk = NULL;
-
-	if (pdev->id == 0) {
-		lcdc_pdata = pdev->dev.platform_data;
-		pixel_mdp_clk = clk_get(&pdev->dev, "mdp_clk");
-		if (IS_ERR(pixel_mdp_clk)) {
-			pr_err("Couldnt find pixel_mdp_clk\n");
-			return -EINVAL;
-		}
-
-		pixel_lcdc_clk = clk_get(&pdev->dev, "lcdc_clk");
-		if (IS_ERR(pixel_lcdc_clk)) {
-			pr_err("Couldnt find pixel_lcdc_clk\n");
-			return -EINVAL;
-		}
-
-#ifndef CONFIG_MSM_BUS_SCALING
-		ebi1_clk = clk_get(&pdev->dev, "mem_clk");
-		if (IS_ERR(ebi1_clk))
-			return PTR_ERR(ebi1_clk);
-#endif
-
-		return 0;
-	}
-
-	mfd = platform_get_drvdata(pdev);
-	mfd->ebi1_clk = ebi1_clk;
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	mdp_dev = platform_device_alloc("mdp", pdev->id);
-	if (!mdp_dev)
-		return -ENOMEM;
-
-	cont_splash_clk_ctrl(1);
-
-	/*
-	 * link to the latest pdev
-	 */
-	mfd->pdev = mdp_dev;
-	mfd->dest = DISPLAY_LCDC;
-
-	/*
-	 * alloc panel device data
-	 */
-	if (platform_device_add_data
-	    (mdp_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		pr_err("lcdc_probe: platform_device_add_data failed!\n");
-		platform_device_put(mdp_dev);
-		return -ENOMEM;
-	}
-	/*
-	 * data chain
-	 */
-	pdata = (struct msm_fb_panel_data *)mdp_dev->dev.platform_data;
-	pdata->on = lcdc_on;
-	pdata->off = lcdc_off;
-	pdata->next = pdev;
-
-	/*
-	 * get/set panel specific fb info
-	 */
-	mfd->panel_info = pdata->panel_info;
-
-	if (mfd->index == 0)
-		mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
-	else
-		mfd->fb_imgType = MDP_RGB_565;
-
-	fbi = mfd->fbi;
-	fbi->var.pixclock = clk_round_rate(pixel_mdp_clk,
-					mfd->panel_info.clk_rate);
-	fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
-	fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch;
-	fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch;
-	fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch;
-	fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width;
-	fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width;
-
-	/*
-	 * set driver data
-	 */
-	platform_set_drvdata(mdp_dev, mfd);
-	/*
-	 * register in mdp driver
-	 */
-	rc = platform_device_add(mdp_dev);
-	if (rc)
-		goto lcdc_probe_err;
-
-	pdev_list[pdev_list_cnt++] = pdev;
-
-	return 0;
-
-lcdc_probe_err:
-	platform_device_put(mdp_dev);
-	return rc;
-}
-
-static int lcdc_remove(struct platform_device *pdev)
-{
-#ifndef CONFIG_MSM_BUS_SCALING
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-
-	clk_put(mfd->ebi1_clk);
-#endif
-	return 0;
-}
-
-static int lcdc_register_driver(void)
-{
-	return platform_driver_register(&lcdc_driver);
-}
-
-static int __init lcdc_driver_init(void)
-{
-
-	return lcdc_register_driver();
-}
-
-module_init(lcdc_driver_init);
diff --git a/drivers/video/msm/lcdc_auo_wvga.c b/drivers/video/msm/lcdc_auo_wvga.c
deleted file mode 100644
index 70a28d2..0000000
--- a/drivers/video/msm/lcdc_auo_wvga.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#ifdef CONFIG_SPI_QUP
-#include <linux/spi/spi.h>
-#else
-#include <mach/gpio.h>
-#endif
-#include "msm_fb.h"
-
-#define MAX_BACKLIGHT_LEVEL			15
-#define PANEL_CMD_BACKLIGHT_LEVEL	0x6A18
-#define PANEL_CMD_FORMAT			0x3A00
-#define PANEL_CMD_RGBCTRL			0x3B00
-#define PANEL_CMD_BCTRL				0x5300
-#define PANEL_CMD_PWM_EN			0x6A17
-
-#define PANEL_CMD_SLEEP_OUT			0x1100
-#define PANEL_CMD_DISP_ON			0x2900
-#define PANEL_CMD_DISP_OFF			0x2800
-#define PANEL_CMD_SLEEP_IN			0x1000
-
-#define LCDC_AUO_PANEL_NAME			"lcdc_auo_wvga"
-
-#ifdef CONFIG_SPI_QUP
-#define LCDC_AUO_SPI_DEVICE_NAME	"lcdc_auo_nt35582"
-static struct spi_device *lcdc_spi_client;
-#else
-static int spi_cs;
-static int spi_sclk;
-static int spi_mosi;
-#endif
-
-struct auo_state_type {
-	boolean display_on;
-	int bl_level;
-};
-
-
-static struct auo_state_type auo_state = { .bl_level = 10 };
-static struct msm_panel_common_pdata *lcdc_auo_pdata;
-
-#ifndef CONFIG_SPI_QUP
-static void auo_spi_write_byte(u8 data)
-{
-	uint32 bit;
-	int bnum;
-
-	bnum = 8;			/* 8 data bits */
-	bit = 0x80;
-	while (bnum--) {
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		gpio_set_value(spi_mosi, (data & bit) ? 1 : 0);
-		udelay(1);
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		udelay(1);
-		bit >>= 1;
-	}
-	gpio_set_value(spi_mosi, 0);
-}
-
-static void auo_spi_read_byte(u16 cmd_16, u8 *data)
-{
-	int bnum;
-	u8 cmd_hi = (u8)(cmd_16 >> 8);
-	u8 cmd_low = (u8)(cmd_16);
-
-	/* Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(2);
-
-	/* command byte first */
-	auo_spi_write_byte(0x20);
-	udelay(2);
-	auo_spi_write_byte(cmd_hi);
-	udelay(2);
-	auo_spi_write_byte(0x00);
-	udelay(2);
-	auo_spi_write_byte(cmd_low);
-	udelay(2);
-	auo_spi_write_byte(0xc0);
-	udelay(2);
-
-	gpio_direction_input(spi_mosi);
-
-	/* followed by data bytes */
-	bnum = 1 * 8;	/* number of bits */
-	*data = 0;
-	while (bnum) {
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		udelay(1);
-		*data <<= 1;
-		*data |= gpio_get_value(spi_mosi) ? 1 : 0;
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		udelay(1);
-		--bnum;
-		if ((bnum % 8) == 0)
-			++data;
-	}
-
-	gpio_direction_output(spi_mosi, 0);
-
-	/* Chip Select - high */
-	udelay(2);
-	gpio_set_value(spi_cs, 1);
-}
-#endif
-
-static int auo_serigo(u8 *input_data, int input_len)
-{
-#ifdef CONFIG_SPI_QUP
-	int                 rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	if (!lcdc_spi_client) {
-		pr_err("%s lcdc_spi_client is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-
-	t.tx_buf = input_data;
-	t.len = input_len;
-	t.bits_per_word = 16;
-
-	spi_setup(lcdc_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	rc = spi_sync(lcdc_spi_client, &m);
-
-	return rc;
-#else
-	int i;
-
-	/* Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(2);
-
-	for (i = 0; i < input_len; ++i) {
-		auo_spi_write_byte(input_data[i]);
-		udelay(2);
-	}
-
-	/* Chip Select - high */
-	gpio_set_value(spi_cs, 1);
-
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SPI_QUP
-static void auo_spi_init(void)
-{
-	spi_sclk = *(lcdc_auo_pdata->gpio_num);
-	spi_cs   = *(lcdc_auo_pdata->gpio_num + 1);
-	spi_mosi = *(lcdc_auo_pdata->gpio_num + 2);
-
-	/* Set the output so that we don't disturb the slave device */
-	gpio_set_value(spi_sclk, 1);
-	gpio_set_value(spi_mosi, 0);
-
-	/* Set the Chip Select deasserted (active low) */
-	gpio_set_value(spi_cs, 1);
-}
-#endif
-
-static struct work_struct disp_on_delayed_work;
-static void auo_write_cmd(u16  cmd)
-{
-	u8  local_data[4];
-
-	local_data[0] = 0x20;
-	local_data[1] = (u8)(cmd >> 8);
-	local_data[2] = 0;
-	local_data[3] = (u8)cmd;
-	auo_serigo(local_data, 4);
-}
-static void auo_write_cmd_1param(u16  cmd, u8  para1)
-{
-	u8  local_data[6];
-
-	local_data[0] = 0x20;
-	local_data[1] = (u8)(cmd >> 8);
-	local_data[2] = 0;
-	local_data[3] = (u8)cmd;
-	local_data[4] = 0x40;
-	local_data[5] = para1;
-	auo_serigo(local_data, 6);
-}
-static void lcdc_auo_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int bl_level;
-
-	bl_level = mfd->bl_level;
-	if (auo_state.display_on) {
-		auo_write_cmd_1param(PANEL_CMD_BACKLIGHT_LEVEL,
-			bl_level * 255 / MAX_BACKLIGHT_LEVEL);
-		auo_state.bl_level = bl_level;
-	}
-
-}
-static void auo_disp_on_delayed_work(struct work_struct *work_ptr)
-{
-	/* 0x1100: Sleep Out */
-	auo_write_cmd(PANEL_CMD_SLEEP_OUT);
-
-	msleep(180);
-
-	/* SET_PIXEL_FORMAT: Set how many bits per pixel are used (3A00h)*/
-	auo_write_cmd_1param(PANEL_CMD_FORMAT, 0x66); /* 18 bits */
-
-	/* RGBCTRL: RGB Interface Signal Control (3B00h) */
-	auo_write_cmd_1param(PANEL_CMD_RGBCTRL, 0x2B);
-
-	/* Display ON command */
-	auo_write_cmd(PANEL_CMD_DISP_ON);
-	msleep(20);
-
-	/*Backlight on */
-	auo_write_cmd_1param(PANEL_CMD_BCTRL, 0x24); /*BCTRL, BL */
-	auo_write_cmd_1param(PANEL_CMD_PWM_EN, 0x01); /*Enable PWM Level */
-
-	msleep(20);
-}
-
-static void auo_disp_on(void)
-{
-	if (!auo_state.display_on) {
-		INIT_WORK(&disp_on_delayed_work, auo_disp_on_delayed_work);
-#ifdef CONFIG_SPI_QUP
-		if (lcdc_spi_client)
-#endif
-			schedule_work(&disp_on_delayed_work);
-		auo_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_auo_panel_on(struct platform_device *pdev)
-{
-	pr_info("%s\n", __func__);
-	if (!auo_state.display_on) {
-#ifndef CONFIG_SPI_QUP
-		lcdc_auo_pdata->panel_config_gpio(1);
-		auo_spi_init();
-#endif
-		auo_disp_on();
-	}
-	return 0;
-}
-
-static int lcdc_auo_panel_off(struct platform_device *pdev)
-{
-	pr_info("%s\n", __func__);
-	if (auo_state.display_on) {
-		/* 0x2800: Display Off */
-		auo_write_cmd(PANEL_CMD_DISP_OFF);
-		msleep(120);
-		/* 0x1000: Sleep In */
-		auo_write_cmd(PANEL_CMD_SLEEP_IN);
-		msleep(120);
-
-		auo_state.display_on = FALSE;
-	}
-	return 0;
-}
-
-static int auo_probe(struct platform_device *pdev)
-{
-	pr_info("%s: id=%d\n", __func__, pdev->id);
-	if (pdev->id == 0) {
-		lcdc_auo_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPI_QUP
-static int __devinit lcdc_auo_spi_probe(struct spi_device *spi)
-{
-	pr_info("%s\n", __func__);
-	lcdc_spi_client = spi;
-	lcdc_spi_client->bits_per_word = 32;
-	if (auo_state.display_on)
-		schedule_work(&disp_on_delayed_work);
-	return 0;
-}
-static int __devexit lcdc_auo_spi_remove(struct spi_device *spi)
-{
-	lcdc_spi_client = NULL;
-	return 0;
-}
-static struct spi_driver lcdc_auo_spi_driver = {
-	.driver.name   = LCDC_AUO_SPI_DEVICE_NAME,
-	.driver.owner  = THIS_MODULE,
-	.probe         = lcdc_auo_spi_probe,
-	.remove        = __devexit_p(lcdc_auo_spi_remove),
-};
-#endif
-
-static struct platform_driver this_driver = {
-	.probe		= auo_probe,
-	.driver.name	= LCDC_AUO_PANEL_NAME,
-};
-
-static struct msm_fb_panel_data auo_panel_data = {
-	.on = lcdc_auo_panel_on,
-	.off = lcdc_auo_panel_off,
-	.set_backlight = lcdc_auo_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name	= LCDC_AUO_PANEL_NAME,
-	.id	= 1,
-	.dev.platform_data = &auo_panel_data,
-};
-
-static int __init lcdc_auo_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client(LCDC_AUO_PANEL_NAME)) {
-		pr_err("%s: detect failed\n", __func__);
-		return 0;
-	}
-
-	ret = platform_driver_register(&this_driver);
-	if (ret) {
-		pr_err("%s: driver register failed, rc=%d\n", __func__, ret);
-		return ret;
-	}
-
-	pinfo = &auo_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 800;
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 25600000;
-	pinfo->bl_max = MAX_BACKLIGHT_LEVEL;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 16-2;	/* HBP-HLW */
-	pinfo->lcdc.h_front_porch = 16;
-	pinfo->lcdc.h_pulse_width = 2;
-
-	pinfo->lcdc.v_back_porch = 3-2;		/* VBP-VLW */
-	pinfo->lcdc.v_front_porch = 28;
-	pinfo->lcdc.v_pulse_width = 2;
-
-	pinfo->lcdc.border_clr = 0;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		pr_err("%s: device register failed, rc=%d\n", __func__, ret);
-		goto fail_driver;
-	}
-#ifdef CONFIG_SPI_QUP
-	ret = spi_register_driver(&lcdc_auo_spi_driver);
-
-	if (ret) {
-		pr_err("%s: spi register failed: rc=%d\n", __func__, ret);
-		goto fail_device;
-	}
-	pr_info("%s: SUCCESS (SPI)\n", __func__);
-#else
-	pr_info("%s: SUCCESS (BitBang)\n", __func__);
-#endif
-	return ret;
-
-#ifdef CONFIG_SPI_QUP
-fail_device:
-	platform_device_unregister(&this_device);
-#endif
-fail_driver:
-	platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lcdc_auo_panel_init);
-static void __exit lcdc_auo_panel_exit(void)
-{
-	pr_info("%s\n", __func__);
-	platform_device_unregister(&this_device);
-	platform_driver_unregister(&this_driver);
-#ifdef CONFIG_SPI_QUP
-	spi_unregister_driver(&lcdc_auo_spi_driver);
-#endif
-}
-module_exit(lcdc_auo_panel_exit);
diff --git a/drivers/video/msm/lcdc_chimei_wxga.c b/drivers/video/msm/lcdc_chimei_wxga.c
deleted file mode 100644
index cab7bb3..0000000
--- a/drivers/video/msm/lcdc_chimei_wxga.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#ifdef CONFIG_PMIC8058_PWM
-#include <linux/mfd/pmic8058.h>
-#include <linux/pmic8058-pwm.h>
-#endif
-#include <mach/gpio.h>
-#include "msm_fb.h"
-
-
-
-
-static struct pwm_device *bl_pwm;
-
-#define PWM_FREQ_HZ 210
-#define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ)
-#define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL)
-#define PWM_LEVEL 15
-
-static struct msm_panel_common_pdata *cm_pdata;
-static struct platform_device *cm_fbpdev;
-static int led_pwm;		/* pm8058 gpio 24, channel 0 */
-static int led_en;		/* pm8058 gpio 1 */
-static int lvds_pwr_down;	/* msm gpio 30 */
-static int chimei_bl_level = 1;
-
-
-static void lcdc_chimei_set_backlight(int level)
-{
-	int ret;
-
-	if (bl_pwm) {
-		ret = pwm_config(bl_pwm, PWM_DUTY_LEVEL * level,
-			PWM_PERIOD_USEC);
-		if (ret) {
-			pr_err("%s: pwm_config on pwm failed %d\n",
-					__func__, ret);
-			return;
-		}
-
-		ret = pwm_enable(bl_pwm);
-		if (ret) {
-			pr_err("%s: pwm_enable on pwm failed %d\n",
-					__func__, ret);
-			return;
-		}
-	}
-
-	chimei_bl_level = level;
-}
-
-static int lcdc_chimei_panel_on(struct platform_device *pdev)
-{
-	int ret;
-
-	/* panel powered on here */
-
-	ret = gpio_request(lvds_pwr_down, "lvds_pwr_down");
-	if (ret == 0) {
-		/* output, pull high to enable */
-		gpio_direction_output(lvds_pwr_down, 1);
-	} else {
-		pr_err("%s: lvds_pwr_down=%d, gpio_request failed\n",
-			__func__, lvds_pwr_down);
-	}
-
-	msleep(200);
-	/* power on led pwm power >= 200 ms */
-
-	if (chimei_bl_level == 0)
-		chimei_bl_level = 1;
-	lcdc_chimei_set_backlight(chimei_bl_level);
-
-	msleep(10);
-
-	ret = gpio_request(led_en, "led_en");
-	if (ret == 0) {
-		/* output, pull high */
-		gpio_direction_output(led_en, 1);
-	} else {
-		pr_err("%s: led_en=%d, gpio_request failed\n",
-			__func__, led_en);
-	}
-	return ret;
-}
-
-static int lcdc_chimei_panel_off(struct platform_device *pdev)
-{
-	/* pull low to disable */
-	gpio_set_value_cansleep(led_en, 0);
-	gpio_free(led_en);
-
-	msleep(10);
-
-	lcdc_chimei_set_backlight(0);
-
-	msleep(200);
-	/* power off led pwm power >= 200 ms */
-
-	/* pull low to shut down lvds */
-	gpio_set_value_cansleep(lvds_pwr_down, 0);
-	gpio_free(lvds_pwr_down);
-
-	/* panel power off here */
-
-	return 0;
-}
-
-static void lcdc_chimei_panel_backlight(struct msm_fb_data_type *mfd)
-{
-	lcdc_chimei_set_backlight(mfd->bl_level);
-}
-
-static int __devinit chimei_probe(struct platform_device *pdev)
-{
-	int rc = 0;
-
-	if (pdev->id == 0) {
-		cm_pdata = pdev->dev.platform_data;
-		if (cm_pdata == NULL) {
-			pr_err("%s: no PWM gpio specified\n", __func__);
-			return 0;
-		}
-		led_pwm = cm_pdata->gpio_num[0];
-		led_en = cm_pdata->gpio_num[1];
-		lvds_pwr_down = cm_pdata->gpio_num[2];
-		pr_info("%s: led_pwm=%d led_en=%d lvds_pwr_down=%d\n",
-			__func__, led_pwm, led_en, lvds_pwr_down);
-		return 0;
-	}
-
-	if (cm_pdata == NULL)
-		return -ENODEV;
-
-	bl_pwm = pwm_request(led_pwm, "backlight");
-	if (bl_pwm == NULL || IS_ERR(bl_pwm)) {
-		pr_err("%s pwm_request() failed\n", __func__);
-		bl_pwm = NULL;
-	}
-
-	cm_fbpdev = msm_fb_add_device(pdev);
-	if (!cm_fbpdev) {
-		dev_err(&pdev->dev, "failed to add msm_fb device\n");
-		rc = -ENODEV;
-		goto probe_exit;
-	}
-
-probe_exit:
-	return rc;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = chimei_probe,
-	.driver = {
-		.name   = "lcdc_chimei_lvds_wxga",
-	},
-};
-
-static struct msm_fb_panel_data chimei_panel_data = {
-	.on = lcdc_chimei_panel_on,
-	.off = lcdc_chimei_panel_off,
-	.set_backlight = lcdc_chimei_panel_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_chimei_lvds_wxga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &chimei_panel_data,
-	}
-};
-
-static int __init lcdc_chimei_lvds_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client("lcdc_chimei_wxga"))
-		return 0;
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &chimei_panel_data.panel_info;
-	pinfo->xres = 1366;
-	pinfo->yres = 768;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 69300000;
-	pinfo->bl_max = PWM_LEVEL;
-	pinfo->bl_min = 1;
-
-	/*
-	 * this panel is operated by de,
-	 * vsycn and hsync are ignored
-	 */
-	pinfo->lcdc.h_back_porch = 108;
-	pinfo->lcdc.h_front_porch = 0;
-	pinfo->lcdc.h_pulse_width = 1;
-	pinfo->lcdc.v_back_porch = 0;
-	pinfo->lcdc.v_front_porch = 16;
-	pinfo->lcdc.v_pulse_width = 1;
-	pinfo->lcdc.border_clr = 0;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret)
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lcdc_chimei_lvds_panel_init);
diff --git a/drivers/video/msm/lcdc_external.c b/drivers/video/msm/lcdc_external.c
deleted file mode 100644
index b699610..0000000
--- a/drivers/video/msm/lcdc_external.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-static int __init lcdc_external_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-
-	if (msm_fb_detect_client("lcdc_external"))
-		return 0;
-
-	pinfo.xres = 1280;
-	pinfo.yres = 720;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = LCDC_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 24;
-	pinfo.fb_num = 2;
-	pinfo.clk_rate = 74250000;
-
-	pinfo.lcdc.h_back_porch = 124;
-	pinfo.lcdc.h_front_porch = 110;
-	pinfo.lcdc.h_pulse_width = 136;
-	pinfo.lcdc.v_back_porch = 19;
-	pinfo.lcdc.v_front_porch = 5;
-	pinfo.lcdc.v_pulse_width = 6;
-	pinfo.lcdc.border_clr = 0;	/* blk */
-	pinfo.lcdc.underflow_clr = 0xff;	/* blue */
-	pinfo.lcdc.hsync_skew = 0;
-
-	ret = lcdc_device_register(&pinfo);
-	if (ret)
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-
-	return ret;
-}
-
-module_init(lcdc_external_init);
diff --git a/drivers/video/msm/lcdc_gordon.c b/drivers/video/msm/lcdc_gordon.c
deleted file mode 100644
index ecb23f0..0000000
--- a/drivers/video/msm/lcdc_gordon.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright (c) 2009-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include "msm_fb.h"
-
-/* registers */
-#define GORDON_REG_NOP          0x00
-#define GORDON_REG_IMGCTL1      0x10
-#define GORDON_REG_IMGCTL2      0x11
-#define GORDON_REG_IMGSET1      0x12
-#define GORDON_REG_IMGSET2      0x13
-#define GORDON_REG_IVBP1        0x14
-#define GORDON_REG_IHBP1        0x15
-#define GORDON_REG_IVNUM1       0x16
-#define GORDON_REG_IHNUM1       0x17
-#define GORDON_REG_IVBP2        0x18
-#define GORDON_REG_IHBP2        0x19
-#define GORDON_REG_IVNUM2       0x1A
-#define GORDON_REG_IHNUM2       0x1B
-#define GORDON_REG_LCDIFCTL1    0x30
-#define GORDON_REG_VALTRAN      0x31
-#define GORDON_REG_AVCTL        0x33
-#define GORDON_REG_LCDIFCTL2    0x34
-#define GORDON_REG_LCDIFCTL3    0x35
-#define GORDON_REG_LCDIFSET1    0x36
-#define GORDON_REG_PCCTL        0x3C
-#define GORDON_REG_TPARAM1      0x40
-#define GORDON_REG_TLCDIF1      0x41
-#define GORDON_REG_TSSPB_ST1    0x42
-#define GORDON_REG_TSSPB_ED1    0x43
-#define GORDON_REG_TSCK_ST1     0x44
-#define GORDON_REG_TSCK_WD1     0x45
-#define GORDON_REG_TGSPB_VST1   0x46
-#define GORDON_REG_TGSPB_VED1   0x47
-#define GORDON_REG_TGSPB_CH1    0x48
-#define GORDON_REG_TGCK_ST1     0x49
-#define GORDON_REG_TGCK_ED1     0x4A
-#define GORDON_REG_TPCTL_ST1    0x4B
-#define GORDON_REG_TPCTL_ED1    0x4C
-#define GORDON_REG_TPCHG_ED1    0x4D
-#define GORDON_REG_TCOM_CH1     0x4E
-#define GORDON_REG_THBP1        0x4F
-#define GORDON_REG_TPHCTL1      0x50
-#define GORDON_REG_EVPH1        0x51
-#define GORDON_REG_EVPL1        0x52
-#define GORDON_REG_EVNH1        0x53
-#define GORDON_REG_EVNL1        0x54
-#define GORDON_REG_TBIAS1       0x55
-#define GORDON_REG_TPARAM2      0x56
-#define GORDON_REG_TLCDIF2      0x57
-#define GORDON_REG_TSSPB_ST2    0x58
-#define GORDON_REG_TSSPB_ED2    0x59
-#define GORDON_REG_TSCK_ST2     0x5A
-#define GORDON_REG_TSCK_WD2     0x5B
-#define GORDON_REG_TGSPB_VST2   0x5C
-#define GORDON_REG_TGSPB_VED2   0x5D
-#define GORDON_REG_TGSPB_CH2    0x5E
-#define GORDON_REG_TGCK_ST2     0x5F
-#define GORDON_REG_TGCK_ED2     0x60
-#define GORDON_REG_TPCTL_ST2    0x61
-#define GORDON_REG_TPCTL_ED2    0x62
-#define GORDON_REG_TPCHG_ED2    0x63
-#define GORDON_REG_TCOM_CH2     0x64
-#define GORDON_REG_THBP2        0x65
-#define GORDON_REG_TPHCTL2      0x66
-#define GORDON_REG_POWCTL       0x80
-
-static int lcdc_gordon_panel_off(struct platform_device *pdev);
-
-static int spi_cs;
-static int spi_sclk;
-static int spi_sdo;
-static int spi_sdi;
-static int spi_dac;
-static int bl_level;
-static unsigned char bit_shift[8] = { (1 << 7),	/* MSB */
-	(1 << 6),
-	(1 << 5),
-	(1 << 4),
-	(1 << 3),
-	(1 << 2),
-	(1 << 1),
-	(1 << 0)		               /* LSB */
-};
-
-struct gordon_state_type{
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-};
-
-static struct gordon_state_type gordon_state = { 0 };
-static struct msm_panel_common_pdata *lcdc_gordon_pdata;
-
-static void serigo(uint16 reg, uint8 data)
-{
-	unsigned int tx_val = ((0x00FF & reg) << 8) | data;
-	unsigned char i, val = 0;
-
-	/* Enable the Chip Select */
-	gpio_set_value(spi_cs, 1);
-	udelay(33);
-
-	/* Transmit it in two parts, Higher Byte first, then Lower Byte */
-	val = (unsigned char)((tx_val & 0xFF00) >> 8);
-
-	/* Clock should be Low before entering ! */
-	for (i = 0; i < 8; i++) {
-		/* #1: Drive the Data (High or Low) */
-		if (val & bit_shift[i])
-			gpio_set_value(spi_sdi, 1);
-		else
-			gpio_set_value(spi_sdi, 0);
-
-		/* #2: Drive the Clk High and then Low */
-		udelay(33);
-		gpio_set_value(spi_sclk, 1);
-		udelay(33);
-		gpio_set_value(spi_sclk, 0);
-	}
-
-	/* Idle state of SDO (MOSI) is Low */
-	gpio_set_value(spi_sdi, 0);
-	/* ..then Lower Byte */
-	val = (uint8) (tx_val & 0x00FF);
-	/* Before we enter here the Clock should be Low ! */
-
-	for (i = 0; i < 8; i++) {
-		/* #1: Drive the Data (High or Low) */
-		if (val & bit_shift[i])
-			gpio_set_value(spi_sdi, 1);
-		else
-			gpio_set_value(spi_sdi, 0);
-
-		/* #2: Drive the Clk High and then Low */
-		udelay(33);
-
-		gpio_set_value(spi_sclk, 1);
-		udelay(33);
-		gpio_set_value(spi_sclk, 0);
-	}
-
-	/* Idle state of SDO (MOSI) is Low */
-	gpio_set_value(spi_sdi, 0);
-
-	/* Now Disable the Chip Select */
-	udelay(33);
-	gpio_set_value(spi_cs, 0);
-}
-
-static void spi_init(void)
-{
-	/* Setting the Default GPIO's */
-	spi_sclk = *(lcdc_gordon_pdata->gpio_num);
-	spi_cs   = *(lcdc_gordon_pdata->gpio_num + 1);
-	spi_sdi  = *(lcdc_gordon_pdata->gpio_num + 2);
-	spi_sdo  = *(lcdc_gordon_pdata->gpio_num + 3);
-
-	/* Set the output so that we dont disturb the slave device */
-	gpio_set_value(spi_sclk, 0);
-	gpio_set_value(spi_sdi, 0);
-
-	/* Set the Chip Select De-asserted */
-	gpio_set_value(spi_cs, 0);
-
-}
-
-static void gordon_disp_powerup(void)
-{
-	if (!gordon_state.disp_powered_up && !gordon_state.display_on) {
-		/* Reset the hardware first */
-		/* Include DAC power up implementation here */
-	      gordon_state.disp_powered_up = TRUE;
-	}
-}
-
-static void gordon_init(void)
-{
-	/* Image interface settings */
-	serigo(GORDON_REG_IMGCTL2, 0x00);
-	serigo(GORDON_REG_IMGSET1, 0x00);
-
-	/* Exchange the RGB signal for J510(Softbank mobile) */
-	serigo(GORDON_REG_IMGSET2, 0x12);
-	serigo(GORDON_REG_LCDIFSET1, 0x00);
-
-	/* Pre-charge settings */
-	serigo(GORDON_REG_PCCTL, 0x09);
-	serigo(GORDON_REG_LCDIFCTL2, 0x7B);
-
-	mdelay(1);
-}
-
-static void gordon_disp_on(void)
-{
-	if (gordon_state.disp_powered_up && !gordon_state.display_on) {
-		gordon_init();
-		mdelay(20);
-		/* gordon_dispmode setting */
-		serigo(GORDON_REG_TPARAM1, 0x30);
-		serigo(GORDON_REG_TLCDIF1, 0x00);
-		serigo(GORDON_REG_TSSPB_ST1, 0x8B);
-		serigo(GORDON_REG_TSSPB_ED1, 0x93);
-		serigo(GORDON_REG_TSCK_ST1, 0x88);
-		serigo(GORDON_REG_TSCK_WD1, 0x00);
-		serigo(GORDON_REG_TGSPB_VST1, 0x01);
-		serigo(GORDON_REG_TGSPB_VED1, 0x02);
-		serigo(GORDON_REG_TGSPB_CH1, 0x5E);
-		serigo(GORDON_REG_TGCK_ST1, 0x80);
-		serigo(GORDON_REG_TGCK_ED1, 0x3C);
-		serigo(GORDON_REG_TPCTL_ST1, 0x50);
-		serigo(GORDON_REG_TPCTL_ED1, 0x74);
-		serigo(GORDON_REG_TPCHG_ED1, 0x78);
-		serigo(GORDON_REG_TCOM_CH1, 0x50);
-		serigo(GORDON_REG_THBP1, 0x84);
-		serigo(GORDON_REG_TPHCTL1, 0x00);
-		serigo(GORDON_REG_EVPH1, 0x70);
-		serigo(GORDON_REG_EVPL1, 0x64);
-		serigo(GORDON_REG_EVNH1, 0x56);
-		serigo(GORDON_REG_EVNL1, 0x48);
-		serigo(GORDON_REG_TBIAS1, 0x88);
-
-		/* QVGA settings */
-		serigo(GORDON_REG_TPARAM2, 0x28);
-		serigo(GORDON_REG_TLCDIF2, 0x14);
-		serigo(GORDON_REG_TSSPB_ST2, 0x49);
-		serigo(GORDON_REG_TSSPB_ED2, 0x4B);
-		serigo(GORDON_REG_TSCK_ST2, 0x4A);
-		serigo(GORDON_REG_TSCK_WD2, 0x02);
-		serigo(GORDON_REG_TGSPB_VST2, 0x02);
-		serigo(GORDON_REG_TGSPB_VED2, 0x03);
-		serigo(GORDON_REG_TGSPB_CH2, 0x2F);
-		serigo(GORDON_REG_TGCK_ST2, 0x40);
-		serigo(GORDON_REG_TGCK_ED2, 0x1E);
-		serigo(GORDON_REG_TPCTL_ST2, 0x2C);
-		serigo(GORDON_REG_TPCTL_ED2, 0x3A);
-		serigo(GORDON_REG_TPCHG_ED2, 0x3C);
-		serigo(GORDON_REG_TCOM_CH2, 0x28);
-		serigo(GORDON_REG_THBP2, 0x4D);
-		serigo(GORDON_REG_TPHCTL2, 0x1A);
-
-		/* VGA settings */
-		serigo(GORDON_REG_IVBP1, 0x02);
-		serigo(GORDON_REG_IHBP1, 0x90);
-		serigo(GORDON_REG_IVNUM1, 0xA0);
-		serigo(GORDON_REG_IHNUM1, 0x78);
-
-		/* QVGA settings */
-		serigo(GORDON_REG_IVBP2, 0x02);
-		serigo(GORDON_REG_IHBP2, 0x48);
-		serigo(GORDON_REG_IVNUM2, 0x50);
-		serigo(GORDON_REG_IHNUM2, 0x3C);
-
-		/* Gordon Charge pump settings and ON */
-		serigo(GORDON_REG_POWCTL, 0x03);
-		mdelay(15);
-		serigo(GORDON_REG_POWCTL, 0x07);
-		mdelay(15);
-
-		serigo(GORDON_REG_POWCTL, 0x0F);
-		mdelay(15);
-
-		serigo(GORDON_REG_AVCTL, 0x03);
-		mdelay(15);
-
-		serigo(GORDON_REG_POWCTL, 0x1F);
-		mdelay(15);
-
-		serigo(GORDON_REG_POWCTL, 0x5F);
-		mdelay(15);
-
-		serigo(GORDON_REG_POWCTL, 0x7F);
-		mdelay(15);
-
-		serigo(GORDON_REG_LCDIFCTL1, 0x02);
-		mdelay(15);
-
-		serigo(GORDON_REG_IMGCTL1, 0x00);
-		mdelay(15);
-
-		serigo(GORDON_REG_LCDIFCTL3, 0x00);
-		mdelay(15);
-
-		serigo(GORDON_REG_VALTRAN, 0x01);
-		mdelay(15);
-
-		serigo(GORDON_REG_LCDIFCTL1, 0x03);
-		mdelay(1);
-		gordon_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_gordon_panel_on(struct platform_device *pdev)
-{
-	if (!gordon_state.disp_initialized) {
-		/* Configure reset GPIO that drives DAC */
-		lcdc_gordon_pdata->panel_config_gpio(1);
-		spi_dac = *(lcdc_gordon_pdata->gpio_num + 4);
-		gpio_set_value(spi_dac, 0);
-		udelay(15);
-		gpio_set_value(spi_dac, 1);
-		spi_init();	/* LCD needs SPI */
-		gordon_disp_powerup();
-		gordon_disp_on();
-		if (bl_level <= 1) {
-			/* keep back light OFF */
-			serigo(GORDON_REG_LCDIFCTL2, 0x0B);
-			udelay(15);
-			serigo(GORDON_REG_VALTRAN, 0x01);
-		} else {
-			/* keep back light ON */
-			serigo(GORDON_REG_LCDIFCTL2, 0x7B);
-			udelay(15);
-			serigo(GORDON_REG_VALTRAN, 0x01);
-		}
-		gordon_state.disp_initialized = TRUE;
-	}
-	return 0;
-}
-
-static int lcdc_gordon_panel_off(struct platform_device *pdev)
-{
-	if (gordon_state.disp_powered_up && gordon_state.display_on) {
-		serigo(GORDON_REG_LCDIFCTL2, 0x7B);
-		serigo(GORDON_REG_VALTRAN, 0x01);
-		serigo(GORDON_REG_LCDIFCTL1, 0x02);
-		serigo(GORDON_REG_LCDIFCTL3, 0x01);
-		mdelay(20);
-		serigo(GORDON_REG_VALTRAN, 0x01);
-		serigo(GORDON_REG_IMGCTL1, 0x01);
-		serigo(GORDON_REG_LCDIFCTL1, 0x00);
-		mdelay(20);
-
-		serigo(GORDON_REG_POWCTL, 0x1F);
-		mdelay(40);
-
-		serigo(GORDON_REG_POWCTL, 0x07);
-		mdelay(40);
-
-		serigo(GORDON_REG_POWCTL, 0x03);
-		mdelay(40);
-
-		serigo(GORDON_REG_POWCTL, 0x00);
-		mdelay(40);
-		lcdc_gordon_pdata->panel_config_gpio(0);
-		gordon_state.display_on = FALSE;
-		gordon_state.disp_initialized = FALSE;
-	}
-	return 0;
-}
-
-static void lcdc_gordon_set_backlight(struct msm_fb_data_type *mfd)
-{
-		bl_level = mfd->bl_level;
-
-		if (gordon_state.disp_initialized) {
-			if (bl_level <= 1) {
-				/* keep back light OFF */
-				serigo(GORDON_REG_LCDIFCTL2, 0x0B);
-				udelay(15);
-				serigo(GORDON_REG_VALTRAN, 0x01);
-			} else {
-				/* keep back light ON */
-				serigo(GORDON_REG_LCDIFCTL2, 0x7B);
-				udelay(15);
-				serigo(GORDON_REG_VALTRAN, 0x01);
-			}
-		}
-}
-
-static int __devinit gordon_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		lcdc_gordon_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = gordon_probe,
-	.driver = {
-		.name   = "lcdc_gordon_vga",
-	},
-};
-
-static struct msm_fb_panel_data gordon_panel_data = {
-	.on = lcdc_gordon_panel_on,
-	.off = lcdc_gordon_panel_off,
-	.set_backlight = lcdc_gordon_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_gordon_vga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &gordon_panel_data,
-	}
-};
-
-static int __init lcdc_gordon_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-	if (msm_fb_detect_client("lcdc_gordon_vga"))
-		return 0;
-#endif
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &gordon_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 640;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 24500000;
-	pinfo->bl_max = 4;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 84;
-	pinfo->lcdc.h_front_porch = 33;
-	pinfo->lcdc.h_pulse_width = 60;
-	pinfo->lcdc.v_back_porch = 0;
-	pinfo->lcdc.v_front_porch = 2;
-	pinfo->lcdc.v_pulse_width = 2;
-	pinfo->lcdc.border_clr = 0;     /* blk */
-	pinfo->lcdc.underflow_clr = 0xff;       /* blue */
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret)
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lcdc_gordon_panel_init);
diff --git a/drivers/video/msm/lcdc_nt35582_wvga.c b/drivers/video/msm/lcdc_nt35582_wvga.c
deleted file mode 100644
index 2152b1a..0000000
--- a/drivers/video/msm/lcdc_nt35582_wvga.c
+++ /dev/null
@@ -1,472 +0,0 @@
-/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#ifdef CONFIG_SPI_QUP
-#include <linux/spi/spi.h>
-#endif
-#include <mach/gpio.h>
-#include <mach/pmic.h>
-#include "msm_fb.h"
-
-#define LCDC_NT35582_PANEL_NAME		"lcdc_nt35582_wvga"
-
-#define WRITE_FIRST_TRANS	0x20
-#define WRITE_SECOND_TRANS	0x00
-#define WRITE_THIRD_TRANS	0x40
-#define READ_FIRST_TRANS	0x20
-#define READ_SECOND_TRANS	0x00
-#define READ_THIRD_TRANS	0xC0
-
-#ifdef CONFIG_SPI_QUP
-#define LCDC_NT35582_SPI_DEVICE_NAME		"lcdc_nt35582_spi"
-static struct spi_device *spi_client;
-#endif
-
-struct nt35582_state_type {
-	boolean display_on;
-	int bl_level;
-};
-
-static struct nt35582_state_type nt35582_state = { 0 };
-static int gpio_backlight_en;
-static struct msm_panel_common_pdata *lcdc_nt35582_pdata;
-
-static int spi_write_2bytes(struct spi_device *spi,
-	unsigned char reg_high_addr, unsigned char reg_low_addr)
-{
-	char tx_buf[4];
-	int rc;
-	struct spi_message m;
-	struct spi_transfer t;
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-
-	spi_setup(spi);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	tx_buf[0] = WRITE_FIRST_TRANS;
-	tx_buf[1] = reg_high_addr;
-	tx_buf[2] = WRITE_SECOND_TRANS;
-	tx_buf[3] = reg_low_addr;
-	t.rx_buf = NULL;
-	t.len = 4;
-	t.bits_per_word = 16;
-	rc = spi_sync(spi, &m);
-	if (rc)
-		pr_err("write spi command failed!\n");
-
-	return rc;
-}
-
-static int spi_write_3bytes(struct spi_device *spi, unsigned char reg_high_addr,
-	unsigned char reg_low_addr, unsigned char write_data)
-{
-	char tx_buf[6];
-	int rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-
-	spi_setup(spi);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	tx_buf[0] = WRITE_FIRST_TRANS;
-	tx_buf[1] = reg_high_addr;
-	tx_buf[2] = WRITE_SECOND_TRANS;
-	tx_buf[3] = reg_low_addr;
-	tx_buf[4] = WRITE_THIRD_TRANS;
-	tx_buf[5] = write_data;
-	t.rx_buf = NULL;
-	t.len = 6;
-	t.bits_per_word = 16;
-	rc = spi_sync(spi, &m);
-
-	if (rc)
-		pr_err("write spi command failed!\n");
-
-	return rc;
-}
-
-static int spi_read_bytes(struct spi_device *spi, unsigned char reg_high_addr,
-	unsigned char reg_low_addr, unsigned char *read_value)
-{
-	char tx_buf[6];
-	char rx_buf[6];
-	int rc;
-	struct spi_message m;
-	struct spi_transfer t;
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-
-	spi_setup(spi);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	tx_buf[0] = READ_FIRST_TRANS;
-	tx_buf[1] = reg_high_addr;
-	tx_buf[2] = READ_SECOND_TRANS;
-	tx_buf[3] = reg_low_addr;
-	tx_buf[4] = READ_THIRD_TRANS;
-	tx_buf[5] = 0x00;
-
-	t.rx_buf = rx_buf;
-	t.len = 6;
-	t.bits_per_word = 16;
-	rc = spi_sync(spi, &m);
-
-	if (rc)
-		pr_err("write spi command failed!\n");
-	else
-		*read_value = rx_buf[5];
-
-	return rc;
-}
-
-static void nt35582_disp_on(void)
-{
-	uint32 panel_id1 = 0, panel_id2 = 0;
-
-	if (!nt35582_state.display_on) {
-
-		/* GVDD setting */
-		spi_write_3bytes(spi_client, 0xC0, 0x00, 0xC0);
-		spi_write_3bytes(spi_client, 0xC0, 0x01, 0x00);
-		spi_write_3bytes(spi_client, 0xC0, 0x02, 0xC0);
-		spi_write_3bytes(spi_client, 0xC0, 0x03, 0x00);
-		/* Power setting */
-		spi_write_3bytes(spi_client, 0xC1, 0x00, 0x40);
-		spi_write_3bytes(spi_client, 0xC2, 0x00, 0x21);
-		spi_write_3bytes(spi_client, 0xC2, 0x02, 0x02);
-
-		/* Gamma setting */
-		spi_write_3bytes(spi_client, 0xE0, 0x00, 0x0E);
-		spi_write_3bytes(spi_client, 0xE0, 0x01, 0x54);
-		spi_write_3bytes(spi_client, 0xE0, 0x02, 0x63);
-		spi_write_3bytes(spi_client, 0xE0, 0x03, 0x76);
-		spi_write_3bytes(spi_client, 0xE0, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE0, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE0, 0x06, 0x62);
-		spi_write_3bytes(spi_client, 0xE0, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE0, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE0, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE0, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE0, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE0, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE0, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE0, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE0, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE0, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE0, 0x11, 0x57);
-
-		spi_write_3bytes(spi_client, 0xE1, 0x00, 0x0E);
-		spi_write_3bytes(spi_client, 0xE1, 0x01, 0x54);
-		spi_write_3bytes(spi_client, 0xE1, 0x02, 0x63);
-		spi_write_3bytes(spi_client, 0xE1, 0x03, 0x76);
-		spi_write_3bytes(spi_client, 0xE1, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE1, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE1, 0x06, 0X62);
-		spi_write_3bytes(spi_client, 0xE1, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE1, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE1, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE1, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE1, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE1, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE1, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE1, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE1, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE1, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE1, 0x11, 0x57);
-
-		spi_write_3bytes(spi_client, 0xE2, 0x00, 0x0E);
-		spi_write_3bytes(spi_client, 0xE2, 0x01, 0x54);
-		spi_write_3bytes(spi_client, 0xE2, 0x02, 0x63);
-		spi_write_3bytes(spi_client, 0xE2, 0x03, 0x76);
-		spi_write_3bytes(spi_client, 0xE2, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE2, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE2, 0x06, 0x62);
-		spi_write_3bytes(spi_client, 0xE2, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE2, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE2, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE2, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE2, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE2, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE2, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE2, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE2, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE2, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE2, 0x11, 0x57);
-
-		spi_write_3bytes(spi_client, 0xE3, 0x00, 0x0E);
-		spi_write_3bytes(spi_client, 0xE3, 0x01, 0x54);
-		spi_write_3bytes(spi_client, 0xE3, 0x02, 0x63);
-		spi_write_3bytes(spi_client, 0xE3, 0x03, 0x76);
-		spi_write_3bytes(spi_client, 0xE3, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE3, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE3, 0x06, 0x62);
-		spi_write_3bytes(spi_client, 0xE3, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE3, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE3, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE3, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE3, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE3, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE3, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE3, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE3, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE3, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE3, 0x11, 0x57);
-
-		spi_write_3bytes(spi_client, 0xE4, 0x00, 0x48);
-		spi_write_3bytes(spi_client, 0xE4, 0x01, 0x6B);
-		spi_write_3bytes(spi_client, 0xE4, 0x02, 0x84);
-		spi_write_3bytes(spi_client, 0xE4, 0x03, 0x9B);
-		spi_write_3bytes(spi_client, 0xE4, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE4, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE4, 0x06, 0x62);
-		spi_write_3bytes(spi_client, 0xE4, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE4, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE4, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE4, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE4, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE4, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE4, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE4, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE4, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE4, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE4, 0x11, 0x57);
-
-		spi_write_3bytes(spi_client, 0xE5, 0x00, 0x48);
-		spi_write_3bytes(spi_client, 0xE5, 0x01, 0x6B);
-		spi_write_3bytes(spi_client, 0xE5, 0x02, 0x84);
-		spi_write_3bytes(spi_client, 0xE5, 0x03, 0x9B);
-		spi_write_3bytes(spi_client, 0xE5, 0x04, 0x1F);
-		spi_write_3bytes(spi_client, 0xE5, 0x05, 0x31);
-		spi_write_3bytes(spi_client, 0xE5, 0x06, 0x62);
-		spi_write_3bytes(spi_client, 0xE5, 0x07, 0x78);
-		spi_write_3bytes(spi_client, 0xE5, 0x08, 0x1F);
-		spi_write_3bytes(spi_client, 0xE5, 0x09, 0x25);
-		spi_write_3bytes(spi_client, 0xE5, 0x0A, 0xB3);
-		spi_write_3bytes(spi_client, 0xE5, 0x0B, 0x17);
-		spi_write_3bytes(spi_client, 0xE5, 0x0C, 0x38);
-		spi_write_3bytes(spi_client, 0xE5, 0x0D, 0x5A);
-		spi_write_3bytes(spi_client, 0xE5, 0x0E, 0xA2);
-		spi_write_3bytes(spi_client, 0xE5, 0x0F, 0xA2);
-		spi_write_3bytes(spi_client, 0xE5, 0x10, 0x24);
-		spi_write_3bytes(spi_client, 0xE5, 0x11, 0x57);
-
-		/* Data format setting */
-		spi_write_3bytes(spi_client, 0x3A, 0x00, 0x70);
-
-		/* Reverse PCLK signal of LCM to meet Qualcomm's platform */
-		spi_write_3bytes(spi_client, 0x3B, 0x00, 0x2B);
-
-		/* Scan direstion setting */
-		spi_write_3bytes(spi_client, 0x36, 0x00, 0x00);
-
-		/* Sleep out */
-		spi_write_2bytes(spi_client, 0x11, 0x00);
-
-		msleep(120);
-
-		/* Display on */
-		spi_write_2bytes(spi_client, 0x29, 0x00);
-
-		pr_info("%s: LCM SPI display on CMD finished...\n", __func__);
-
-		msleep(200);
-
-		nt35582_state.display_on = TRUE;
-	}
-
-	/* Test to read RDDID. It should be 0x0055h and 0x0082h */
-	spi_read_bytes(spi_client, 0x10, 0x80, (unsigned char *)&panel_id1);
-	spi_read_bytes(spi_client, 0x11, 0x80, (unsigned char *)&panel_id2);
-
-	pr_info(KERN_INFO "nt35582_disp_on: LCM_ID=[0x%x, 0x%x]\n",
-		panel_id1, panel_id2);
-}
-
-static int lcdc_nt35582_panel_on(struct platform_device *pdev)
-{
-	nt35582_disp_on();
-	return 0;
-}
-
-static int lcdc_nt35582_panel_off(struct platform_device *pdev)
-{
-	nt35582_state.display_on = FALSE;
-	return 0;
-}
-
-static void lcdc_nt35582_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int bl_level;
-	int i = 0, step = 0;
-
-	bl_level = mfd->bl_level;
-	if (bl_level == nt35582_state.bl_level)
-		return;
-	else
-		nt35582_state.bl_level = bl_level;
-
-	if (bl_level == 0) {
-		gpio_set_value_cansleep(gpio_backlight_en, 0);
-		return;
-	}
-
-	/* Level:0~31 mapping to step 32~1 */
-	step = 32 - bl_level;
-	for (i = 0; i < step; i++) {
-		gpio_set_value_cansleep(gpio_backlight_en, 0);
-		ndelay(5);
-		gpio_set_value_cansleep(gpio_backlight_en, 1);
-		ndelay(5);
-	}
-}
-
-static int __devinit nt35582_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		lcdc_nt35582_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-	gpio_backlight_en = *(lcdc_nt35582_pdata->gpio_num);
-
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-#ifdef CONFIG_SPI_QUP
-static int __devinit lcdc_nt35582_spi_probe(struct spi_device *spi)
-{
-	spi_client = spi;
-	spi_client->bits_per_word = 16;
-	spi_client->chip_select = 0;
-	spi_client->max_speed_hz = 1100000;
-	spi_client->mode = SPI_MODE_0;
-	spi_setup(spi_client);
-
-	return 0;
-}
-
-static int __devexit lcdc_nt35582_spi_remove(struct spi_device *spi)
-{
-	spi_client = NULL;
-	return 0;
-}
-
-static struct spi_driver lcdc_nt35582_spi_driver = {
-	.driver = {
-		.name = LCDC_NT35582_SPI_DEVICE_NAME,
-		.owner = THIS_MODULE,
-	},
-	.probe = lcdc_nt35582_spi_probe,
-	.remove = __devexit_p(lcdc_nt35582_spi_remove),
-};
-#endif
-static struct platform_driver this_driver = {
-	.probe = nt35582_probe,
-	.driver = {
-		.name = LCDC_NT35582_PANEL_NAME,
-	},
-};
-
-static struct msm_fb_panel_data nt35582_panel_data = {
-	.on = lcdc_nt35582_panel_on,
-	.off = lcdc_nt35582_panel_off,
-	.set_backlight = lcdc_nt35582_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name = LCDC_NT35582_PANEL_NAME,
-	.id = 1,
-	.dev = {
-		.platform_data = &nt35582_panel_data,
-	}
-};
-
-static int __init lcdc_nt35582_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_LCDC_AUTO_DETECT
-	if (msm_fb_detect_client(LCDC_NT35582_PANEL_NAME)) {
-		pr_err("detect failed\n");
-		return 0;
-	}
-#endif
-	ret = platform_driver_register(&this_driver);
-	if (ret) {
-		pr_err("Fails to platform_driver_register...\n");
-		return ret;
-	}
-
-	pinfo = &nt35582_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 800;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 25600000;
-	pinfo->bl_max = 31;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 10;	/* hsw = 8 + hbp=184 */
-	pinfo->lcdc.h_front_porch = 10;
-	pinfo->lcdc.h_pulse_width = 2;
-	pinfo->lcdc.v_back_porch = 4;	/* vsw=1 + vbp = 2 */
-	pinfo->lcdc.v_front_porch = 10;
-	pinfo->lcdc.v_pulse_width = 2;
-	pinfo->lcdc.border_clr = 0;	/* blk */
-	pinfo->lcdc.underflow_clr = 0xff;	/* blue */
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		pr_err("not able to register the device\n");
-		goto fail_driver;
-	}
-#ifdef CONFIG_SPI_QUP
-	ret = spi_register_driver(&lcdc_nt35582_spi_driver);
-
-	if (ret) {
-		pr_err("not able to register spi\n");
-		goto fail_device;
-	}
-#endif
-	return ret;
-
-#ifdef CONFIG_SPI_QUP
-fail_device:
-	platform_device_unregister(&this_device);
-#endif
-fail_driver:
-	platform_driver_unregister(&this_driver);
-	return ret;
-}
-
-device_initcall(lcdc_nt35582_panel_init);
diff --git a/drivers/video/msm/lcdc_panel.c b/drivers/video/msm/lcdc_panel.c
deleted file mode 100644
index 5de2557..0000000
--- a/drivers/video/msm/lcdc_panel.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-static int lcdc_panel_on(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int lcdc_panel_off(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int __devinit lcdc_panel_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = lcdc_panel_probe,
-	.driver = {
-		.name   = "lcdc_panel",
-	},
-};
-
-static struct msm_fb_panel_data lcdc_panel_data = {
-	.on = lcdc_panel_on,
-	.off = lcdc_panel_off,
-};
-
-static int lcdc_dev_id;
-
-int lcdc_device_register(struct msm_panel_info *pinfo)
-{
-	struct platform_device *pdev = NULL;
-	int ret;
-
-	pdev = platform_device_alloc("lcdc_panel", ++lcdc_dev_id);
-	if (!pdev)
-		return -ENOMEM;
-
-	lcdc_panel_data.panel_info = *pinfo;
-	ret = platform_device_add_data(pdev, &lcdc_panel_data,
-		sizeof(lcdc_panel_data));
-	if (ret) {
-		printk(KERN_ERR
-		  "%s: platform_device_add_data failed!\n", __func__);
-		goto err_device_put;
-	}
-
-	ret = platform_device_add(pdev);
-	if (ret) {
-		printk(KERN_ERR
-		  "%s: platform_device_register failed!\n", __func__);
-		goto err_device_put;
-	}
-
-	return 0;
-
-err_device_put:
-	platform_device_put(pdev);
-	return ret;
-}
-
-static int __init lcdc_panel_init(void)
-{
-	return platform_driver_register(&this_driver);
-}
-
-module_init(lcdc_panel_init);
diff --git a/drivers/video/msm/lcdc_prism.c b/drivers/video/msm/lcdc_prism.c
deleted file mode 100644
index fb040ca..0000000
--- a/drivers/video/msm/lcdc_prism.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-#ifdef CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-#include "mddihosti.h"
-#endif
-
-static int __init lcdc_prism_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-
-#ifdef CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-	ret = msm_fb_detect_client("lcdc_prism_wvga");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret && (mddi_get_client_id() != 0))
-		return 0;
-#endif
-
-	pinfo.xres = 800;
-	pinfo.yres = 480;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = LCDC_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 24;
-	pinfo.fb_num = 2;
-	pinfo.clk_rate = 30720000;
-
-	pinfo.lcdc.h_back_porch = 21;
-	pinfo.lcdc.h_front_porch = 81;
-	pinfo.lcdc.h_pulse_width = 60;
-	pinfo.lcdc.v_back_porch = 18;
-	pinfo.lcdc.v_front_porch = 27;
-	pinfo.lcdc.v_pulse_width = 2;
-	pinfo.lcdc.border_clr = 0;	/* blk */
-	pinfo.lcdc.underflow_clr = 0xff;	/* blue */
-	pinfo.lcdc.hsync_skew = 0;
-
-	ret = lcdc_device_register(&pinfo);
-	if (ret)
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-
-	return ret;
-}
-
-module_init(lcdc_prism_init);
diff --git a/drivers/video/msm/lcdc_samsung_oled_pt.c b/drivers/video/msm/lcdc_samsung_oled_pt.c
deleted file mode 100644
index 409496e..0000000
--- a/drivers/video/msm/lcdc_samsung_oled_pt.c
+++ /dev/null
@@ -1,588 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#ifdef CONFIG_SPI_QUP
-#include <linux/spi/spi.h>
-#else
-#include <mach/gpio.h>
-#endif
-#include "msm_fb.h"
-
-#define DEBUG
-/* #define SYSFS_DEBUG_CMD */
-
-#ifdef CONFIG_SPI_QUP
-#define LCDC_SAMSUNG_SPI_DEVICE_NAME	"lcdc_samsung_ams367pe02"
-static struct spi_device *lcdc_spi_client;
-#else
-static int spi_cs;
-static int spi_sclk;
-static int spi_mosi;
-#endif
-
-struct samsung_state_type {
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-	int brightness;
-};
-
-struct samsung_spi_data {
-	u8 addr;
-	u8 len;
-	u8 data[22];
-};
-
-static struct samsung_spi_data panel_sequence[] = {
-	{ .addr = 0xf8, .len = 14, .data = { 0x01, 0x27, 0x27, 0x07, 0x07,
-	 0x54, 0x9f, 0x63, 0x86, 0x1a, 0x33, 0x0d, 0x00, 0x00 } },
-};
-static struct samsung_spi_data display_sequence[] = {
-	{ .addr = 0xf2, .len = 5, .data = { 0x02, 0x03, 0x1c, 0x10, 0x10 } },
-	{ .addr = 0xf7, .len = 3, .data = { 0x00, 0x00, 0x30 } },
-};
-
-/* lum=300 cd/m2 */
-static struct samsung_spi_data gamma_sequence_300[] = {
-	{ .addr = 0xfa, .len = 22, .data = { 0x02, 0x18, 0x08, 0x24, 0x7d, 0x77,
-	 0x5b, 0xbe, 0xc1, 0xb1, 0xb3, 0xb7, 0xa6, 0xc3, 0xc5, 0xb9, 0x00, 0xb3,
-	 0x00, 0xaf, 0x00, 0xe8 } },
-	{ .addr = 0xFA, .len = 1, .data = { 0x03 } },
-};
-/* lum = 180 cd/m2*/
-static struct samsung_spi_data gamma_sequence_180[] = {
-	{ .addr = 0xfa, .len = 22, .data = { 0x02, 0x18, 0x08, 0x24, 0x83, 0x78,
-	 0x60, 0xc5, 0xc6, 0xb8, 0xba, 0xbe, 0xad, 0xcb, 0xcd, 0xc2, 0x00, 0x92,
-	 0x00, 0x8e, 0x00, 0xbc } },
-	{ .addr = 0xFA, .len = 1, .data = { 0x03 } },
-};
-/* lum = 80 cd/m2*/
-static struct samsung_spi_data gamma_sequence_80[] = {
-	{ .addr = 0xfa, .len = 22, .data = { 0x02, 0x18, 0x08, 0x24, 0x94, 0x73,
-	 0x6c, 0xcb, 0xca, 0xbe, 0xc4, 0xc7, 0xb8, 0xd3, 0xd5, 0xcb, 0x00, 0x6d,
-	 0x00, 0x69, 0x00, 0x8b } },
-	{ .addr = 0xFA, .len = 1, .data = { 0x03 } },
-};
-
-static struct samsung_spi_data etc_sequence[] = {
-	{ .addr = 0xF6, .len = 3, .data = { 0x00, 0x8e, 0x07 } },
-	{ .addr = 0xB3, .len = 1, .data = { 0x0C } },
-};
-
-static struct samsung_state_type samsung_state = { .brightness = 180 };
-static struct msm_panel_common_pdata *lcdc_samsung_pdata;
-
-#ifndef CONFIG_SPI_QUP
-static void samsung_spi_write_byte(boolean dc, u8 data)
-{
-	uint32 bit;
-	int bnum;
-
-	gpio_set_value(spi_sclk, 0);
-	gpio_set_value(spi_mosi, dc ? 1 : 0);
-	udelay(1);			/* at least 20 ns */
-	gpio_set_value(spi_sclk, 1);	/* clk high */
-	udelay(1);			/* at least 20 ns */
-
-	bnum = 8;			/* 8 data bits */
-	bit = 0x80;
-	while (bnum--) {
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		gpio_set_value(spi_mosi, (data & bit) ? 1 : 0);
-		udelay(1);
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		udelay(1);
-		bit >>= 1;
-	}
-	gpio_set_value(spi_mosi, 0);
-
-}
-
-static void samsung_spi_read_bytes(u8 cmd, u8 *data, int num)
-{
-	int bnum;
-
-	/* Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(2);
-
-	/* command byte first */
-	samsung_spi_write_byte(0, cmd);
-	udelay(2);
-
-	gpio_direction_input(spi_mosi);
-
-	if (num > 1) {
-		/* extra dummy clock */
-		gpio_set_value(spi_sclk, 0);
-		udelay(1);
-		gpio_set_value(spi_sclk, 1);
-		udelay(1);
-	}
-
-	/* followed by data bytes */
-	bnum = num * 8;	/* number of bits */
-	*data = 0;
-	while (bnum) {
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		udelay(1);
-		*data <<= 1;
-		*data |= gpio_get_value(spi_mosi) ? 1 : 0;
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		udelay(1);
-		--bnum;
-		if ((bnum % 8) == 0)
-			++data;
-	}
-
-	gpio_direction_output(spi_mosi, 0);
-
-	/* Chip Select - high */
-	udelay(2);
-	gpio_set_value(spi_cs, 1);
-}
-#endif
-
-#ifdef DEBUG
-static const char *byte_to_binary(const u8 *buf, int len)
-{
-	static char b[32*8+1];
-	char *p = b;
-	int i, z;
-
-	for (i = 0; i < len; ++i) {
-		u8 val = *buf++;
-		for (z = 1 << 7; z > 0; z >>= 1)
-			*p++ = (val & z) ? '1' : '0';
-	}
-	*p = 0;
-
-	return b;
-}
-#endif
-
-#define BIT_OFFSET	(bit_size % 8)
-#define ADD_BIT(val) do { \
-		tx_buf[bit_size / 8] |= \
-			(u8)((val ? 1 : 0) << (7 - BIT_OFFSET)); \
-		++bit_size; \
-	} while (0)
-
-#define ADD_BYTE(data) do { \
-		tx_buf[bit_size / 8] |= (u8)(data >> BIT_OFFSET); \
-		bit_size += 8; \
-		if (BIT_OFFSET != 0) \
-			tx_buf[bit_size / 8] |= (u8)(data << (8 - BIT_OFFSET));\
-	} while (0)
-
-static int samsung_serigo(struct samsung_spi_data data)
-{
-#ifdef CONFIG_SPI_QUP
-	char                tx_buf[32];
-	int                 bit_size = 0, i, rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	if (!lcdc_spi_client) {
-		pr_err("%s lcdc_spi_client is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-	memset(tx_buf, 0, sizeof tx_buf);
-	t.tx_buf = tx_buf;
-	spi_setup(lcdc_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ADD_BIT(FALSE);
-	ADD_BYTE(data.addr);
-	for (i = 0; i < data.len; ++i) {
-		ADD_BIT(TRUE);
-		ADD_BYTE(data.data[i]);
-	}
-
-	/* add padding bits so we round to next byte */
-	t.len = (bit_size+7) / 8;
-	if (t.len <= 4)
-		t.bits_per_word = bit_size;
-
-	rc = spi_sync(lcdc_spi_client, &m);
-#ifdef DEBUG
-	pr_info("%s: addr=0x%02x, #args=%d[%d] [%s], rc=%d\n",
-		__func__, data.addr, t.len, t.bits_per_word,
-		byte_to_binary(tx_buf, t.len), rc);
-#endif
-	return rc;
-#else
-	int i;
-
-	/* Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(2);
-
-	samsung_spi_write_byte(FALSE, data.addr);
-	udelay(2);
-
-	for (i = 0; i < data.len; ++i) {
-		samsung_spi_write_byte(TRUE, data.data[i]);
-		udelay(2);
-	}
-
-	/* Chip Select - high */
-	gpio_set_value(spi_cs, 1);
-#ifdef DEBUG
-	pr_info("%s: cmd=0x%02x, #args=%d\n", __func__, data.addr, data.len);
-#endif
-	return 0;
-#endif
-}
-
-static int samsung_write_cmd(u8 cmd)
-{
-#ifdef CONFIG_SPI_QUP
-	char                tx_buf[2];
-	int                 bit_size = 0, rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	if (!lcdc_spi_client) {
-		pr_err("%s lcdc_spi_client is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-	memset(tx_buf, 0, sizeof tx_buf);
-	t.tx_buf = tx_buf;
-	spi_setup(lcdc_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	ADD_BIT(FALSE);
-	ADD_BYTE(cmd);
-
-	t.len = 2;
-	t.bits_per_word = 9;
-
-	rc = spi_sync(lcdc_spi_client, &m);
-#ifdef DEBUG
-	pr_info("%s: addr=0x%02x, #args=%d[%d] [%s], rc=%d\n",
-		__func__, cmd, t.len, t.bits_per_word,
-		byte_to_binary(tx_buf, t.len), rc);
-#endif
-	return rc;
-#else
-	/* Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(2);
-
-	samsung_spi_write_byte(FALSE, cmd);
-
-	/* Chip Select - high */
-	udelay(2);
-	gpio_set_value(spi_cs, 1);
-#ifdef DEBUG
-	pr_info("%s: cmd=0x%02x\n", __func__, cmd);
-#endif
-	return 0;
-#endif
-}
-
-static int samsung_serigo_list(struct samsung_spi_data *data, int count)
-{
-	int i, rc;
-	for (i = 0; i < count; ++i, ++data) {
-		rc = samsung_serigo(*data);
-		if (rc)
-			return rc;
-		msleep(10);
-	}
-	return 0;
-}
-
-#ifndef CONFIG_SPI_QUP
-static void samsung_spi_init(void)
-{
-	spi_sclk = *(lcdc_samsung_pdata->gpio_num);
-	spi_cs   = *(lcdc_samsung_pdata->gpio_num + 1);
-	spi_mosi = *(lcdc_samsung_pdata->gpio_num + 2);
-
-	/* Set the output so that we don't disturb the slave device */
-	gpio_set_value(spi_sclk, 1);
-	gpio_set_value(spi_mosi, 0);
-
-	/* Set the Chip Select deasserted (active low) */
-	gpio_set_value(spi_cs, 1);
-}
-#endif
-
-static void samsung_disp_powerup(void)
-{
-	if (!samsung_state.disp_powered_up && !samsung_state.display_on)
-		samsung_state.disp_powered_up = TRUE;
-}
-
-static struct work_struct disp_on_delayed_work;
-static void samsung_disp_on_delayed_work(struct work_struct *work_ptr)
-{
-	/* 0x01: Software Reset */
-	samsung_write_cmd(0x01);
-	msleep(120);
-
-	msleep(300);
-	samsung_serigo_list(panel_sequence,
-		sizeof(panel_sequence)/sizeof(*panel_sequence));
-	samsung_serigo_list(display_sequence,
-		sizeof(display_sequence)/sizeof(*display_sequence));
-
-	switch (samsung_state.brightness) {
-	case 300:
-		samsung_serigo_list(gamma_sequence_300,
-			sizeof(gamma_sequence_300)/sizeof(*gamma_sequence_300));
-		break;
-	case 180:
-	default:
-		samsung_serigo_list(gamma_sequence_180,
-			sizeof(gamma_sequence_180)/sizeof(*gamma_sequence_180));
-		break;
-	case 80:
-		samsung_serigo_list(gamma_sequence_80,
-			sizeof(gamma_sequence_80)/sizeof(*gamma_sequence_80));
-		break;
-	}
-
-	samsung_serigo_list(etc_sequence,
-		sizeof(etc_sequence)/sizeof(*etc_sequence));
-
-	/* 0x11: Sleep Out */
-	samsung_write_cmd(0x11);
-	msleep(120);
-	/* 0x13: Normal Mode On */
-	samsung_write_cmd(0x13);
-
-#ifndef CONFIG_SPI_QUP
-	{
-		u8 data;
-
-		msleep(120);
-		/* 0x0A: Read Display Power Mode */
-		samsung_spi_read_bytes(0x0A, &data, 1);
-		pr_info("%s: power=[%s]\n", __func__,
-			byte_to_binary(&data, 1));
-
-		msleep(120);
-		/* 0x0C: Read Display Pixel Format */
-		samsung_spi_read_bytes(0x0C, &data, 1);
-		pr_info("%s: pixel-format=[%s]\n", __func__,
-			byte_to_binary(&data, 1));
-	}
-#endif
-	msleep(120);
-	/* 0x29: Display On */
-	samsung_write_cmd(0x29);
-}
-
-static void samsung_disp_on(void)
-{
-	if (samsung_state.disp_powered_up && !samsung_state.display_on) {
-		INIT_WORK(&disp_on_delayed_work, samsung_disp_on_delayed_work);
-		schedule_work(&disp_on_delayed_work);
-
-		samsung_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_samsung_panel_on(struct platform_device *pdev)
-{
-	pr_info("%s\n", __func__);
-	if (!samsung_state.disp_initialized) {
-#ifndef CONFIG_SPI_QUP
-		lcdc_samsung_pdata->panel_config_gpio(1);
-		samsung_spi_init();
-#endif
-		samsung_disp_powerup();
-		samsung_disp_on();
-		samsung_state.disp_initialized = TRUE;
-	}
-	return 0;
-}
-
-static int lcdc_samsung_panel_off(struct platform_device *pdev)
-{
-	pr_info("%s\n", __func__);
-	if (samsung_state.disp_powered_up && samsung_state.display_on) {
-		/* 0x10: Sleep In */
-		samsung_write_cmd(0x10);
-		msleep(120);
-
-		samsung_state.display_on = FALSE;
-		samsung_state.disp_initialized = FALSE;
-	}
-	return 0;
-}
-
-#ifdef SYSFS_DEBUG_CMD
-static ssize_t samsung_rda_cmd(struct device *dev,
-	struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = snprintf(buf, PAGE_SIZE, "n/a\n");
-	pr_info("%s: 'n/a'\n", __func__);
-	return ret;
-}
-
-static ssize_t samsung_wta_cmd(struct device *dev,
-	struct device_attribute *attr, const char *buf, size_t count)
-{
-	ssize_t ret = strnlen(buf, PAGE_SIZE);
-	uint32 cmd;
-
-	sscanf(buf, "%x", &cmd);
-	samsung_write_cmd((u8)cmd);
-
-	return ret;
-}
-
-static DEVICE_ATTR(cmd, S_IRUGO | S_IWUGO, samsung_rda_cmd, samsung_wta_cmd);
-static struct attribute *fs_attrs[] = {
-	&dev_attr_cmd.attr,
-	NULL,
-};
-static struct attribute_group fs_attr_group = {
-	.attrs = fs_attrs,
-};
-#endif
-
-static struct msm_fb_panel_data samsung_panel_data = {
-	.on = lcdc_samsung_panel_on,
-	.off = lcdc_samsung_panel_off,
-};
-
-static int __devinit samsung_probe(struct platform_device *pdev)
-{
-	struct msm_panel_info *pinfo;
-#ifdef SYSFS_DEBUG_CMD
-	struct platform_device *fb_dev;
-	struct msm_fb_data_type *mfd;
-	int rc;
-#endif
-
-	pr_info("%s: id=%d\n", __func__, pdev->id);
-	lcdc_samsung_pdata = pdev->dev.platform_data;
-
-	pinfo = &samsung_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 800;
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 25600000; /* Max 27.77MHz */
-	pinfo->bl_max = 15;
-	pinfo->bl_min = 1;
-
-	/* AMS367PE02 Operation Manual, Page 7 */
-	pinfo->lcdc.h_back_porch = 16-2;	/* HBP-HLW */
-	pinfo->lcdc.h_front_porch = 16;
-	pinfo->lcdc.h_pulse_width = 2;
-	/* AMS367PE02 Operation Manual, Page 6 */
-	pinfo->lcdc.v_back_porch = 3-2;		/* VBP-VLW */
-	pinfo->lcdc.v_front_porch = 28;
-	pinfo->lcdc.v_pulse_width = 2;
-
-	pinfo->lcdc.border_clr = 0;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-	pdev->dev.platform_data = &samsung_panel_data;
-
-#ifndef SYSFS_DEBUG_CMD
-	msm_fb_add_device(pdev);
-#else
-	fb_dev = msm_fb_add_device(pdev);
-	mfd = platform_get_drvdata(fb_dev);
-	rc = sysfs_create_group(&mfd->fbi->dev->kobj, &fs_attr_group);
-	if (rc) {
-		pr_err("%s: sysfs group creation failed, rc=%d\n", __func__,
-			rc);
-		return rc;
-	}
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_SPI_QUP
-static int __devinit lcdc_samsung_spi_probe(struct spi_device *spi)
-{
-	pr_info("%s\n", __func__);
-	lcdc_spi_client = spi;
-	lcdc_spi_client->bits_per_word = 32;
-	return 0;
-}
-static int __devexit lcdc_samsung_spi_remove(struct spi_device *spi)
-{
-	lcdc_spi_client = NULL;
-	return 0;
-}
-static struct spi_driver lcdc_samsung_spi_driver = {
-	.driver.name   = LCDC_SAMSUNG_SPI_DEVICE_NAME,
-	.driver.owner  = THIS_MODULE,
-	.probe         = lcdc_samsung_spi_probe,
-	.remove        = __devexit_p(lcdc_samsung_spi_remove),
-};
-#endif
-
-static struct platform_driver this_driver = {
-	.probe		= samsung_probe,
-	.driver.name	= "lcdc_samsung_oled",
-};
-
-static int __init lcdc_samsung_panel_init(void)
-{
-	int ret;
-
-	if (msm_fb_detect_client("lcdc_samsung_oled")) {
-		pr_err("%s: detect failed\n", __func__);
-		return 0;
-	}
-
-	ret = platform_driver_register(&this_driver);
-	if (ret) {
-		pr_err("%s: driver register failed, rc=%d\n", __func__, ret);
-		return ret;
-	}
-
-#ifdef CONFIG_SPI_QUP
-	ret = spi_register_driver(&lcdc_samsung_spi_driver);
-
-	if (ret) {
-		pr_err("%s: spi register failed: rc=%d\n", __func__, ret);
-		platform_driver_unregister(&this_driver);
-	} else
-		pr_info("%s: SUCCESS (SPI)\n", __func__);
-#else
-	pr_info("%s: SUCCESS (BitBang)\n", __func__);
-#endif
-	return ret;
-}
-
-module_init(lcdc_samsung_panel_init);
-static void __exit lcdc_samsung_panel_exit(void)
-{
-	pr_info("%s\n", __func__);
-#ifdef CONFIG_SPI_QUP
-	spi_unregister_driver(&lcdc_samsung_spi_driver);
-#endif
-	platform_driver_unregister(&this_driver);
-}
-module_exit(lcdc_samsung_panel_exit);
diff --git a/drivers/video/msm/lcdc_samsung_wsvga.c b/drivers/video/msm/lcdc_samsung_wsvga.c
deleted file mode 100644
index ced8344..0000000
--- a/drivers/video/msm/lcdc_samsung_wsvga.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#ifdef CONFIG_PMIC8058_PWM
-#include <linux/mfd/pmic8058.h>
-#include <linux/pmic8058-pwm.h>
-#endif
-#include <mach/gpio.h>
-#include "msm_fb.h"
-
-
-
-#ifdef CONFIG_PMIC8058_PWM
-static struct pwm_device *bl_pwm0;
-static struct pwm_device *bl_pwm1;
-
-/* for samsung panel 300hz was the minimum freq where flickering wasnt
- * observed as the screen was dimmed
- */
-
-#define PWM_FREQ_HZ 300
-#define PWM_PERIOD_USEC (USEC_PER_SEC / PWM_FREQ_HZ)
-#define PWM_LEVEL 100
-#define PWM_DUTY_LEVEL (PWM_PERIOD_USEC / PWM_LEVEL)
-#endif
-
-struct lcdc_samsung_data {
-	struct msm_panel_common_pdata *pdata;
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-	int vga_enabled;
-#endif
-	struct platform_device *fbpdev;
-};
-
-static struct lcdc_samsung_data *dd;
-
-
-static void lcdc_samsung_panel_set_backlight(struct msm_fb_data_type *mfd)
-{
-#ifdef CONFIG_PMIC8058_PWM
-	int bl_level;
-	int ret;
-
-	bl_level = mfd->bl_level;
-
-	if (bl_pwm0) {
-		ret = pwm_config(bl_pwm0, PWM_DUTY_LEVEL * bl_level,
-			PWM_PERIOD_USEC);
-		if (ret)
-			printk(KERN_ERR "pwm_config on pwm 0 failed %d\n", ret);
-	}
-
-	if (bl_pwm1) {
-		ret = pwm_config(bl_pwm1,
-			PWM_PERIOD_USEC - (PWM_DUTY_LEVEL * bl_level),
-			PWM_PERIOD_USEC);
-		if (ret)
-			printk(KERN_ERR "pwm_config on pwm 1 failed %d\n", ret);
-	}
-
-	if (bl_pwm0) {
-		ret = pwm_enable(bl_pwm0);
-		if (ret)
-			printk(KERN_ERR "pwm_enable on pwm 0 failed %d\n", ret);
-	}
-
-	if (bl_pwm1) {
-		ret = pwm_enable(bl_pwm1);
-		if (ret)
-			printk(KERN_ERR "pwm_enable on pwm 1 failed %d\n", ret);
-	}
-#endif
-
-}
-
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-static ssize_t show_vga_enable(struct device *device,
-			       struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%d\n", dd->vga_enabled);
-}
-
-static ssize_t store_vga_enable(struct device *dev,
-				struct device_attribute *attr,
-				const char *buf, size_t count)
-{
-	unsigned long enable;
-	int rc;
-
-	rc = strict_strtoul(buf, 10, &enable);
-	if (rc)
-		return -EINVAL;
-
-	if (dd->pdata && dd->pdata->vga_switch)
-		rc = dd->pdata->vga_switch(enable);
-	else
-		rc = -ENODEV;
-	if (!rc) {
-		dd->vga_enabled = enable;
-		rc = count;
-	}
-	return rc;
-}
-
-static DEVICE_ATTR(vga_enable, S_IRUGO|S_IWUSR, show_vga_enable,
-		   store_vga_enable);
-static struct attribute *attrs[] = {
-	&dev_attr_vga_enable.attr,
-	NULL,
-};
-static struct attribute_group attr_group = {
-	.attrs = attrs,
-};
-#endif
-
-static int __devinit samsung_probe(struct platform_device *pdev)
-{
-	int rc = 0;
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-	struct msm_fb_data_type *mfd;
-#endif
-
-	if (pdev->id == 0) {
-		dd = kzalloc(sizeof *dd, GFP_KERNEL);
-		if (!dd)
-			return -ENOMEM;
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-		dd->vga_enabled = 0;
-#endif
-		dd->pdata = pdev->dev.platform_data;
-		return 0;
-	} else if (!dd)
-		return -ENODEV;
-
-#ifdef CONFIG_PMIC8058_PWM
-	bl_pwm0 = pwm_request(dd->pdata->gpio_num[0], "backlight1");
-	if (bl_pwm0 == NULL || IS_ERR(bl_pwm0)) {
-		pr_err("%s pwm_request() failed\n", __func__);
-		bl_pwm0 = NULL;
-	}
-
-	bl_pwm1 = pwm_request(dd->pdata->gpio_num[1], "backlight2");
-	if (bl_pwm1 == NULL || IS_ERR(bl_pwm1)) {
-		pr_err("%s pwm_request() failed\n", __func__);
-		bl_pwm1 = NULL;
-	}
-
-	pr_debug("samsung_probe: bl_pwm0=%p LPG_chan0=%d "
-			"bl_pwm1=%p LPG_chan1=%d\n",
-			bl_pwm0, (int)dd->pdata->gpio_num[0],
-			bl_pwm1, (int)dd->pdata->gpio_num[1]
-			);
-#endif
-
-
-	dd->fbpdev = msm_fb_add_device(pdev);
-	if (!dd->fbpdev) {
-		dev_err(&pdev->dev, "failed to add msm_fb device\n");
-		rc = -ENODEV;
-		goto probe_exit;
-	}
-
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-	mfd = platform_get_drvdata(dd->fbpdev);
-	if (mfd && mfd->fbi && mfd->fbi->dev) {
-		rc = sysfs_create_group(&mfd->fbi->dev->kobj, &attr_group);
-		if (rc)
-			dev_err(&pdev->dev, "failed to create sysfs group\n");
-	} else {
-		dev_err(&pdev->dev, "no dev to create sysfs group\n");
-		rc = -ENODEV;
-	}
-#endif
-
-probe_exit:
-	return rc;
-}
-
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-static int __devexit samsung_remove(struct platform_device *pdev)
-{
-	sysfs_remove_group(&dd->fbpdev->dev.kobj, &attr_group);
-	return 0;
-}
-#endif
-
-static struct platform_driver this_driver = {
-	.probe  = samsung_probe,
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-	.remove = samsung_remove,
-#endif
-	.driver = {
-		.name   = "lcdc_samsung_wsvga",
-	},
-};
-
-static struct msm_fb_panel_data samsung_panel_data = {
-	.set_backlight = lcdc_samsung_panel_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_samsung_wsvga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &samsung_panel_data,
-	}
-};
-
-static int __init lcdc_samsung_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client("lcdc_samsung_wsvga"))
-		return 0;
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &samsung_panel_data.panel_info;
-	pinfo->xres = 1024;
-	pinfo->yres = 600;
-#ifdef CONFIG_FB_MSM_LCDC_DSUB
-	/* DSUB (VGA) is on the same bus, this allows us to allocate for the
-	 * max resolution of the DSUB display */
-	pinfo->mode2_xres = 1440;
-	pinfo->mode2_yres = 900;
-	pinfo->mode2_bpp = 16;
-#else
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-#endif
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 43192000;
-	pinfo->bl_max = PWM_LEVEL;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 80;
-	pinfo->lcdc.h_front_porch = 48;
-	pinfo->lcdc.h_pulse_width = 32;
-	pinfo->lcdc.v_back_porch = 4;
-	pinfo->lcdc.v_front_porch = 3;
-	pinfo->lcdc.v_pulse_width = 1;
-	pinfo->lcdc.border_clr = 0;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret)
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lcdc_samsung_panel_init);
diff --git a/drivers/video/msm/lcdc_sharp_wvga_pt.c b/drivers/video/msm/lcdc_sharp_wvga_pt.c
deleted file mode 100644
index ee125e2..0000000
--- a/drivers/video/msm/lcdc_sharp_wvga_pt.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/pwm.h>
-#ifdef CONFIG_PMIC8058_PWM
-#include <linux/mfd/pmic8058.h>
-#include <linux/pmic8058-pwm.h>
-#endif
-#ifdef CONFIG_SPI_QSD
-#include <linux/spi/spi.h>
-#endif
-#include <mach/gpio.h>
-#include "msm_fb.h"
-
-#ifdef CONFIG_SPI_QSD
-#define LCDC_SHARP_SPI_DEVICE_NAME	"lcdc_sharp_ls038y7dx01"
-static struct spi_device *lcdc_spi_client;
-#endif
-static int lcdc_sharp_panel_off(struct platform_device *pdev);
-
-#define BL_MAX		16
-
-#ifdef CONFIG_PMIC8058_PWM
-static struct pwm_device *bl_pwm;
-
-#define PWM_PERIOD	1000	/* us, period of 1Khz */
-#define DUTY_LEVEL	(PWM_PERIOD / BL_MAX)
-#endif
-
-#ifndef CONFIG_SPI_QSD
-static int spi_cs;
-static int spi_sclk;
-static int spi_mosi;
-static int spi_miso;
-static unsigned char bit_shift[8] = { (1 << 7),	/* MSB */
-	(1 << 6),
-	(1 << 5),
-	(1 << 4),
-	(1 << 3),
-	(1 << 2),
-	(1 << 1),
-	(1 << 0)		               /* LSB */
-};
-#endif
-
-struct sharp_state_type {
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-};
-
-struct sharp_spi_data {
-	u8 addr;
-	u8 data;
-};
-
-static struct sharp_spi_data init_sequence[] = {
-	{  15, 0x01 },
-	{   5, 0x01 },
-	{   7, 0x10 },
-	{   9, 0x1E },
-	{  10, 0x04 },
-	{  17, 0xFF },
-	{  21, 0x8A },
-	{  22, 0x00 },
-	{  23, 0x82 },
-	{  24, 0x24 },
-	{  25, 0x22 },
-	{  26, 0x6D },
-	{  27, 0xEB },
-	{  28, 0xB9 },
-	{  29, 0x3A },
-	{  49, 0x1A },
-	{  50, 0x16 },
-	{  51, 0x05 },
-	{  55, 0x7F },
-	{  56, 0x15 },
-	{  57, 0x7B },
-	{  60, 0x05 },
-	{  61, 0x0C },
-	{  62, 0x80 },
-	{  63, 0x00 },
-	{  92, 0x90 },
-	{  97, 0x01 },
-	{  98, 0xFF },
-	{ 113, 0x11 },
-	{ 114, 0x02 },
-	{ 115, 0x08 },
-	{ 123, 0xAB },
-	{ 124, 0x04 },
-	{   6, 0x02 },
-	{ 133, 0x00 },
-	{ 134, 0xFE },
-	{ 135, 0x22 },
-	{ 136, 0x0B },
-	{ 137, 0xFF },
-	{ 138, 0x0F },
-	{ 139, 0x00 },
-	{ 140, 0xFE },
-	{ 141, 0x22 },
-	{ 142, 0x0B },
-	{ 143, 0xFF },
-	{ 144, 0x0F },
-	{ 145, 0x00 },
-	{ 146, 0xFE },
-	{ 147, 0x22 },
-	{ 148, 0x0B },
-	{ 149, 0xFF },
-	{ 150, 0x0F },
-	{ 202, 0x30 },
-	{  30, 0x01 },
-	{   4, 0x01 },
-	{  31, 0x41 },
-};
-
-static struct sharp_state_type sharp_state = { 0 };
-static struct msm_panel_common_pdata *lcdc_sharp_pdata;
-
-#ifndef CONFIG_SPI_QSD
-static void sharp_spi_write_byte(u8 val)
-{
-	int i;
-
-	/* Clock should be Low before entering */
-	for (i = 0; i < 8; i++) {
-		/* #1: Drive the Data (High or Low) */
-		if (val & bit_shift[i])
-			gpio_set_value(spi_mosi, 1);
-		else
-			gpio_set_value(spi_mosi, 0);
-
-		/* #2: Drive the Clk High and then Low */
-		gpio_set_value(spi_sclk, 1);
-		gpio_set_value(spi_sclk, 0);
-	}
-}
-#endif
-
-static int serigo(u8 reg, u8 data)
-{
-#ifdef CONFIG_SPI_QSD
-	char                tx_buf[2];
-	int                 rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	if (!lcdc_spi_client) {
-		printk(KERN_ERR "%s lcdc_spi_client is NULL\n", __func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-	spi_setup(lcdc_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	tx_buf[0] = reg;
-	tx_buf[1] = data;
-	t.rx_buf = NULL;
-	t.len = 2;
-	rc = spi_sync(lcdc_spi_client, &m);
-	return rc;
-#else
-	/* Enable the Chip Select - low */
-	gpio_set_value(spi_cs, 0);
-	udelay(1);
-
-	/* Transmit register address first, then data */
-	sharp_spi_write_byte(reg);
-
-	/* Idle state of MOSI is Low */
-	gpio_set_value(spi_mosi, 0);
-	udelay(1);
-	sharp_spi_write_byte(data);
-
-	gpio_set_value(spi_mosi, 0);
-	gpio_set_value(spi_cs, 1);
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SPI_QSD
-static void sharp_spi_init(void)
-{
-	spi_sclk = *(lcdc_sharp_pdata->gpio_num);
-	spi_cs   = *(lcdc_sharp_pdata->gpio_num + 1);
-	spi_mosi = *(lcdc_sharp_pdata->gpio_num + 2);
-	spi_miso = *(lcdc_sharp_pdata->gpio_num + 3);
-
-	/* Set the output so that we don't disturb the slave device */
-	gpio_set_value(spi_sclk, 0);
-	gpio_set_value(spi_mosi, 0);
-
-	/* Set the Chip Select deasserted (active low) */
-	gpio_set_value(spi_cs, 1);
-}
-#endif
-
-static void sharp_disp_powerup(void)
-{
-	if (!sharp_state.disp_powered_up && !sharp_state.display_on)
-		sharp_state.disp_powered_up = TRUE;
-}
-
-static void sharp_disp_on(void)
-{
-	int i;
-
-	if (sharp_state.disp_powered_up && !sharp_state.display_on) {
-		for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
-			serigo(init_sequence[i].addr,
-			       init_sequence[i].data);
-		}
-		mdelay(10);
-		serigo(31, 0xC1);
-		mdelay(10);
-		serigo(31, 0xD9);
-		serigo(31, 0xDF);
-
-		sharp_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_sharp_panel_on(struct platform_device *pdev)
-{
-	if (!sharp_state.disp_initialized) {
-#ifndef CONFIG_SPI_QSD
-		lcdc_sharp_pdata->panel_config_gpio(1);
-		sharp_spi_init();
-#endif
-		sharp_disp_powerup();
-		sharp_disp_on();
-		sharp_state.disp_initialized = TRUE;
-	}
-	return 0;
-}
-
-static int lcdc_sharp_panel_off(struct platform_device *pdev)
-{
-	if (sharp_state.disp_powered_up && sharp_state.display_on) {
-		serigo(4, 0x00);
-		mdelay(40);
-		serigo(31, 0xC1);
-		mdelay(40);
-		serigo(31, 0x00);
-		msleep(16);
-		sharp_state.display_on = FALSE;
-		sharp_state.disp_initialized = FALSE;
-	}
-	return 0;
-}
-
-static void lcdc_sharp_panel_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int bl_level;
-
-	bl_level = mfd->bl_level;
-
-#ifdef CONFIG_PMIC8058_PWM
-	if (bl_pwm) {
-		pwm_config(bl_pwm, DUTY_LEVEL * bl_level, PWM_PERIOD);
-		pwm_enable(bl_pwm);
-	}
-#endif
-}
-
-static int __devinit sharp_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		lcdc_sharp_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-#ifdef CONFIG_PMIC8058_PWM
-	bl_pwm = pwm_request(lcdc_sharp_pdata->gpio, "backlight");
-	if (bl_pwm == NULL || IS_ERR(bl_pwm)) {
-		pr_err("%s pwm_request() failed\n", __func__);
-		bl_pwm = NULL;
-	}
-
-	printk(KERN_INFO "sharp_probe: bl_pwm=%x LPG_chan=%d\n",
-			(int) bl_pwm, (int)lcdc_sharp_pdata->gpio);
-#endif
-
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPI_QSD
-static int __devinit lcdc_sharp_spi_probe(struct spi_device *spi)
-{
-	lcdc_spi_client = spi;
-	lcdc_spi_client->bits_per_word = 32;
-	return 0;
-}
-static int __devexit lcdc_sharp_spi_remove(struct spi_device *spi)
-{
-	lcdc_spi_client = NULL;
-	return 0;
-}
-static struct spi_driver lcdc_sharp_spi_driver = {
-	.driver = {
-		.name  = LCDC_SHARP_SPI_DEVICE_NAME,
-		.owner = THIS_MODULE,
-	},
-	.probe         = lcdc_sharp_spi_probe,
-	.remove        = __devexit_p(lcdc_sharp_spi_remove),
-};
-#endif
-static struct platform_driver this_driver = {
-	.probe  = sharp_probe,
-	.driver = {
-		.name   = "lcdc_sharp_wvga",
-	},
-};
-
-static struct msm_fb_panel_data sharp_panel_data = {
-	.on = lcdc_sharp_panel_on,
-	.off = lcdc_sharp_panel_off,
-	.set_backlight = lcdc_sharp_panel_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_sharp_wvga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &sharp_panel_data,
-	}
-};
-
-static int __init lcdc_sharp_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	if (msm_fb_detect_client("lcdc_sharp_wvga_pt"))
-		return 0;
-#endif
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &sharp_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 800;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 24500000;
-	pinfo->bl_max = BL_MAX;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 20;
-	pinfo->lcdc.h_front_porch = 10;
-	pinfo->lcdc.h_pulse_width = 10;
-	pinfo->lcdc.v_back_porch = 2;
-	pinfo->lcdc.v_front_porch = 2;
-	pinfo->lcdc.v_pulse_width = 2;
-	pinfo->lcdc.border_clr = 0;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		printk(KERN_ERR "%s not able to register the device\n",
-			__func__);
-		goto fail_driver;
-	}
-#ifdef CONFIG_SPI_QSD
-	ret = spi_register_driver(&lcdc_sharp_spi_driver);
-
-	if (ret) {
-		printk(KERN_ERR "%s not able to register spi\n", __func__);
-		goto fail_device;
-	}
-#endif
-	return ret;
-#ifdef CONFIG_SPI_QSD
-fail_device:
-	platform_device_unregister(&this_device);
-#endif
-fail_driver:
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lcdc_sharp_panel_init);
-#ifdef CONFIG_SPI_QSD
-static void __exit lcdc_sharp_panel_exit(void)
-{
-	spi_unregister_driver(&lcdc_sharp_spi_driver);
-}
-module_exit(lcdc_sharp_panel_exit);
-#endif
-
diff --git a/drivers/video/msm/lcdc_st15.c b/drivers/video/msm/lcdc_st15.c
deleted file mode 100644
index 3effac9..0000000
--- a/drivers/video/msm/lcdc_st15.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/* Copyright (c) 2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/i2c.h>
-#include <linux/delay.h>
-#include "msm_fb.h"
-
-#define DEVICE_NAME "sii9022"
-#define SII9022_DEVICE_ID   0xB0
-#define SII9022_ISR                   0x3D
-#define SII9022_ISR_RXS_STATUS        0x08
-
-static int lcdc_sii9022_panel_on(struct platform_device *pdev);
-static int lcdc_sii9022_panel_off(struct platform_device *pdev);
-
-static struct i2c_client *sii9022_i2c_client;
-
-struct sii9022_data {
-	struct msm_hdmi_platform_data *pd;
-	struct platform_device *pdev;
-	struct work_struct work;
-	int x_res;
-	int y_res;
-	int sysfs_entry_created;
-	int hdmi_attached;
-};
-static struct sii9022_data *dd;
-
-struct sii9022_i2c_addr_data{
-	u8 addr;
-	u8 data;
-};
-
-/* video mode data */
-static u8 video_mode_data[] = {
-	0x00,
-	0xF9, 0x1C, 0x70, 0x17, 0x72, 0x06, 0xEE, 0x02,
-};
-
-static u8 avi_io_format[] = {
-	0x09,
-	0x00, 0x00,
-};
-
-/* power state */
-static struct sii9022_i2c_addr_data regset0[] = {
-	{ 0x60, 0x04 },
-	{ 0x63, 0x00 },
-	{ 0x1E, 0x00 },
-};
-
-static u8 video_infoframe[] = {
-	0x0C,
-	0xF0, 0x00, 0x68, 0x00, 0x04, 0x00, 0x19, 0x00,
-	0xE9, 0x02, 0x04, 0x01, 0x04, 0x06,
-};
-
-/* configure audio */
-static struct sii9022_i2c_addr_data regset1[] = {
-	{ 0x26, 0x90 },
-	{ 0x20, 0x90 },
-	{ 0x1F, 0x80 },
-	{ 0x26, 0x80 },
-	{ 0x24, 0x02 },
-	{ 0x25, 0x0B },
-	{ 0xBC, 0x02 },
-	{ 0xBD, 0x24 },
-	{ 0xBE, 0x02 },
-};
-
-/* enable audio */
-static u8 misc_infoframe[] = {
-	0xBF,
-	0xC2, 0x84, 0x01, 0x0A, 0x6F, 0x02, 0x00, 0x00,
-	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-/* set HDMI, active */
-static struct sii9022_i2c_addr_data regset2[] = {
-	{ 0x1A, 0x01 },
-	{ 0x3D, 0x00 },
-	{ 0x3C, 0x02 },
-};
-
-static struct msm_fb_panel_data sii9022_panel_data = {
-	.on = lcdc_sii9022_panel_on,
-	.off = lcdc_sii9022_panel_off,
-};
-
-static struct platform_device sii9022_device = {
-	.name   = DEVICE_NAME,
-	.id	= 1,
-	.dev	= {
-		.platform_data = &sii9022_panel_data,
-	}
-};
-
-static int send_i2c_data(struct i2c_client *client,
-			 struct sii9022_i2c_addr_data *regset,
-			 int size)
-{
-	int i;
-	int rc = 0;
-
-	for (i = 0; i < size; i++) {
-		rc = i2c_smbus_write_byte_data(
-			client,
-			regset[i].addr, regset[i].data);
-		if (rc)
-			break;
-	}
-	return rc;
-}
-
-static void sii9022_work_f(struct work_struct *work)
-{
-	int isr;
-
-	isr = i2c_smbus_read_byte_data(sii9022_i2c_client, SII9022_ISR);
-	if (isr < 0) {
-		dev_err(&sii9022_i2c_client->dev,
-			"i2c read of isr failed rc = 0x%x\n", isr);
-		return;
-	}
-	if (isr == 0)
-		return;
-
-	/* reset any set bits */
-	i2c_smbus_write_byte_data(sii9022_i2c_client, SII9022_ISR, isr);
-	dd->hdmi_attached = isr & SII9022_ISR_RXS_STATUS;
-	if (dd->pd->cable_detect)
-		dd->pd->cable_detect(dd->hdmi_attached);
-	if (dd->hdmi_attached) {
-		dd->x_res = 1280;
-		dd->y_res = 720;
-	} else {
-		dd->x_res = sii9022_panel_data.panel_info.xres;
-		dd->y_res = sii9022_panel_data.panel_info.yres;
-	}
-}
-
-static irqreturn_t sii9022_interrupt(int irq, void *dev_id)
-{
-	struct sii9022_data *dd = dev_id;
-
-	schedule_work(&dd->work);
-	return IRQ_HANDLED;
-}
-
-static int hdmi_sii_enable(struct i2c_client *client)
-{
-	int rc;
-	int retries = 10;
-	int count;
-
-	rc = i2c_smbus_write_byte_data(client, 0xC7, 0x00);
-	if (rc)
-		goto enable_exit;
-
-	do {
-		msleep(1);
-		rc = i2c_smbus_read_byte_data(client, 0x1B);
-	} while ((rc != SII9022_DEVICE_ID) && retries--);
-
-	if (rc != SII9022_DEVICE_ID)
-		return -ENODEV;
-
-	rc = i2c_smbus_write_byte_data(client, 0x1A, 0x11);
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(video_mode_data);
-	rc = i2c_master_send(client, video_mode_data, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = i2c_smbus_write_byte_data(client, 0x08, 0x20);
-	if (rc)
-		goto enable_exit;
-	count = ARRAY_SIZE(avi_io_format);
-	rc = i2c_master_send(client, avi_io_format, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset0, ARRAY_SIZE(regset0));
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(video_infoframe);
-	rc = i2c_master_send(client, video_infoframe, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset1, ARRAY_SIZE(regset1));
-	if (rc)
-		goto enable_exit;
-
-	count = ARRAY_SIZE(misc_infoframe);
-	rc = i2c_master_send(client, misc_infoframe, count);
-	if (rc != count) {
-		rc = -EIO;
-		goto enable_exit;
-	}
-
-	rc = send_i2c_data(client, regset2, ARRAY_SIZE(regset2));
-	if (rc)
-		goto enable_exit;
-
-	return 0;
-enable_exit:
-	printk(KERN_ERR "%s: exited rc=%d\n", __func__, rc);
-	return rc;
-}
-
-static ssize_t show_res(struct device *device,
-			 struct device_attribute *attr, char *buf)
-{
-	return snprintf(buf, PAGE_SIZE, "%dx%d\n", dd->x_res, dd->y_res);
-}
-
-static struct device_attribute device_attrs[] = {
-	__ATTR(screen_resolution, S_IRUGO|S_IWUSR, show_res, NULL),
-};
-
-static int lcdc_sii9022_panel_on(struct platform_device *pdev)
-{
-	int rc;
-	if (!dd->sysfs_entry_created) {
-		dd->pdev = pdev;
-		rc = device_create_file(&pdev->dev, &device_attrs[0]);
-		if (!rc)
-			dd->sysfs_entry_created = 1;
-	}
-
-	rc = hdmi_sii_enable(sii9022_i2c_client);
-	if (rc) {
-		dd->hdmi_attached = 0;
-		dd->x_res = sii9022_panel_data.panel_info.xres;
-		dd->y_res = sii9022_panel_data.panel_info.yres;
-	}
-	if (dd->pd->irq)
-		enable_irq(dd->pd->irq);
-	/* Don't return the value from hdmi_sii_enable().
-	 * It may fail on some ST1.5s, but we must return 0 from this
-	 * function in order for the on-board display to turn on.
-	 */
-	return 0;
-}
-
-static int lcdc_sii9022_panel_off(struct platform_device *pdev)
-{
-	if (dd->pd->irq)
-		disable_irq(dd->pd->irq);
-	return 0;
-}
-
-static const struct i2c_device_id hmdi_sii_id[] = {
-	{ DEVICE_NAME, 0 },
-	{ }
-};
-
-static int hdmi_sii_probe(struct i2c_client *client,
-			const struct i2c_device_id *id)
-{
-	int rc;
-
-	if (!i2c_check_functionality(client->adapter,
-				     I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
-		return -ENODEV;
-
-	dd = kzalloc(sizeof *dd, GFP_KERNEL);
-	if (!dd) {
-		rc = -ENOMEM;
-		goto probe_exit;
-	}
-	sii9022_i2c_client = client;
-	i2c_set_clientdata(client, dd);
-	dd->pd = client->dev.platform_data;
-	if (!dd->pd) {
-		rc = -ENODEV;
-		goto probe_free;
-	}
-	if (dd->pd->irq) {
-		INIT_WORK(&dd->work, sii9022_work_f);
-		rc = request_irq(dd->pd->irq,
-				 &sii9022_interrupt,
-				 IRQF_TRIGGER_FALLING,
-				 "sii9022_cable", dd);
-		if (rc)
-			goto probe_free;
-		disable_irq(dd->pd->irq);
-	}
-	msm_fb_add_device(&sii9022_device);
-	dd->x_res = sii9022_panel_data.panel_info.xres;
-	dd->y_res = sii9022_panel_data.panel_info.yres;
-
-	return 0;
-
-probe_free:
-	i2c_set_clientdata(client, NULL);
-	kfree(dd);
-probe_exit:
-	return rc;
-}
-
-static int __devexit hdmi_sii_remove(struct i2c_client *client)
-{
-	int err = 0 ;
-	struct msm_hdmi_platform_data *pd;
-
-	if (dd->sysfs_entry_created)
-		device_remove_file(&dd->pdev->dev, &device_attrs[0]);
-	pd = client->dev.platform_data;
-	if (pd && pd->irq)
-		free_irq(pd->irq, dd);
-	i2c_set_clientdata(client, NULL);
-	kfree(dd);
-
-	return err ;
-}
-
-#ifdef CONFIG_PM
-static int sii9022_suspend(struct device *dev)
-{
-	if (dd && dd->pd && dd->pd->irq)
-		disable_irq(dd->pd->irq);
-	return 0;
-}
-
-static int sii9022_resume(struct device *dev)
-{
-	if (dd && dd->pd && dd->pd->irq)
-		enable_irq(dd->pd->irq);
-	return 0;
-}
-
-static struct dev_pm_ops sii9022_pm_ops = {
-	.suspend = sii9022_suspend,
-	.resume = sii9022_resume,
-};
-#endif
-
-static struct i2c_driver hdmi_sii_i2c_driver = {
-	.driver = {
-		.name = DEVICE_NAME,
-		.owner = THIS_MODULE,
-#ifdef CONFIG_PM
-		.pm     = &sii9022_pm_ops,
-#endif
-	},
-	.probe = hdmi_sii_probe,
-	.remove =  __exit_p(hdmi_sii_remove),
-	.id_table = hmdi_sii_id,
-};
-
-static int __init lcdc_st15_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client("lcdc_st15"))
-		return 0;
-
-	pinfo = &sii9022_panel_data.panel_info;
-	pinfo->xres = 1366;
-	pinfo->yres = 768;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 74250000;
-
-	pinfo->lcdc.h_back_porch = 120;
-	pinfo->lcdc.h_front_porch = 20;
-	pinfo->lcdc.h_pulse_width = 40;
-	pinfo->lcdc.v_back_porch = 25;
-	pinfo->lcdc.v_front_porch = 1;
-	pinfo->lcdc.v_pulse_width = 7;
-	pinfo->lcdc.border_clr = 0;      /* blk */
-	pinfo->lcdc.underflow_clr = 0xff;        /* blue */
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = i2c_add_driver(&hdmi_sii_i2c_driver);
-	if (ret)
-		printk(KERN_ERR "%s: failed to add i2c driver\n", __func__);
-
-	return ret;
-}
-
-static void __exit hdmi_sii_exit(void)
-{
-	i2c_del_driver(&hdmi_sii_i2c_driver);
-}
-
-module_init(lcdc_st15_init);
-module_exit(hdmi_sii_exit);
diff --git a/drivers/video/msm/lcdc_toshiba_fwvga_pt.c b/drivers/video/msm/lcdc_toshiba_fwvga_pt.c
deleted file mode 100644
index 65c6415..0000000
--- a/drivers/video/msm/lcdc_toshiba_fwvga_pt.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <mach/gpio.h>
-#include <mach/pmic.h>
-#include <mach/socinfo.h>
-#include "msm_fb.h"
-
-static int spi_cs0_N;
-static int spi_sclk;
-static int spi_mosi;
-static int spi_miso;
-
-struct toshiba_state_type {
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-};
-
-static struct toshiba_state_type toshiba_state = { 0 };
-static struct msm_panel_common_pdata *lcdc_toshiba_pdata;
-
-static int toshiba_spi_write(char data1, char data2, int rs)
-{
-	uint32 bitdata = 0, bnum = 24, bmask = 0x800000;
-
-	gpio_set_value_cansleep(spi_cs0_N, 0);	/* cs* low */
-	udelay(1);
-
-	if (rs)
-		bitdata = (0x72 << 16);
-	else
-		bitdata = (0x70 << 16);
-
-	bitdata |= ((data1 << 8) | data2);
-
-	while (bnum) {
-		gpio_set_value_cansleep(spi_sclk, 0); /* clk low */
-		udelay(1);
-
-		if (bitdata & bmask)
-			gpio_set_value_cansleep(spi_mosi, 1);
-		else
-			gpio_set_value_cansleep(spi_mosi, 0);
-
-		udelay(1);
-		gpio_set_value_cansleep(spi_sclk, 1); /* clk high */
-		udelay(1);
-		bmask >>= 1;
-		bnum--;
-	}
-
-	gpio_set_value_cansleep(spi_cs0_N, 1);	/* cs* high */
-	udelay(1);
-	return 0;
-}
-
-static void spi_pin_assign(void)
-{
-	/* Setting the Default GPIO's */
-	spi_mosi  = *(lcdc_toshiba_pdata->gpio_num);
-	spi_miso  = *(lcdc_toshiba_pdata->gpio_num + 1);
-	spi_sclk  = *(lcdc_toshiba_pdata->gpio_num + 2);
-	spi_cs0_N = *(lcdc_toshiba_pdata->gpio_num + 3);
-}
-
-static void toshiba_disp_powerup(void)
-{
-	if (!toshiba_state.disp_powered_up && !toshiba_state.display_on) {
-		/* Reset the hardware first */
-		/* Include DAC power up implementation here */
-	      toshiba_state.disp_powered_up = TRUE;
-	}
-}
-
-static void toshiba_disp_on(void)
-{
-	if (toshiba_state.disp_powered_up && !toshiba_state.display_on) {
-		toshiba_spi_write(0x01, 0x00, 0);
-		toshiba_spi_write(0x30, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x01, 0);
-		toshiba_spi_write(0x40, 0x10, 1);
-
-#ifdef TOSHIBA_FWVGA_FULL_INIT
-		udelay(500);
-		toshiba_spi_write(0x01, 0x06, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-		msleep(20);
-
-		toshiba_spi_write(0x00, 0x01, 0);
-		toshiba_spi_write(0x03, 0x10, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x02, 0);
-		toshiba_spi_write(0x01, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x03, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x07, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x08, 0);
-		toshiba_spi_write(0x00, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x09, 0);
-		toshiba_spi_write(0x00, 0x0c, 1);
-#endif
-		udelay(500);
-		toshiba_spi_write(0x00, 0x0c, 0);
-		toshiba_spi_write(0x40, 0x10, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x0e, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x20, 0);
-		toshiba_spi_write(0x01, 0x3f, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x22, 0);
-		toshiba_spi_write(0x76, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x23, 0);
-		toshiba_spi_write(0x1c, 0x0a, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x24, 0);
-		toshiba_spi_write(0x1c, 0x2c, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x25, 0);
-		toshiba_spi_write(0x1c, 0x4e, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x27, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x28, 0);
-		toshiba_spi_write(0x76, 0x0c, 1);
-
-#ifdef TOSHIBA_FWVGA_FULL_INIT
-		udelay(500);
-		toshiba_spi_write(0x03, 0x00, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x01, 0);
-		toshiba_spi_write(0x05, 0x02, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x02, 0);
-		toshiba_spi_write(0x07, 0x05, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x03, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x04, 0);
-		toshiba_spi_write(0x02, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x05, 0);
-		toshiba_spi_write(0x07, 0x07, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x06, 0);
-		toshiba_spi_write(0x10, 0x10, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x07, 0);
-		toshiba_spi_write(0x02, 0x02, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x08, 0);
-		toshiba_spi_write(0x07, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x09, 0);
-		toshiba_spi_write(0x07, 0x07, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x0a, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x0b, 0);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x0c, 0);
-		toshiba_spi_write(0x07, 0x07, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x0d, 0);
-		toshiba_spi_write(0x10, 0x10, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x10, 0);
-		toshiba_spi_write(0x01, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x11, 0);
-		toshiba_spi_write(0x05, 0x03, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x12, 0);
-		toshiba_spi_write(0x03, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x15, 0);
-		toshiba_spi_write(0x03, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x16, 0);
-		toshiba_spi_write(0x03, 0x1c, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x17, 0);
-		toshiba_spi_write(0x02, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x18, 0);
-		toshiba_spi_write(0x04, 0x02, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x19, 0);
-		toshiba_spi_write(0x03, 0x05, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x1c, 0);
-		toshiba_spi_write(0x07, 0x07, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x1d, 0);
-		toshiba_spi_write(0x02, 0x1f, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x20, 0);
-		toshiba_spi_write(0x05, 0x07, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x21, 0);
-		toshiba_spi_write(0x06, 0x04, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x22, 0);
-		toshiba_spi_write(0x04, 0x05, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x27, 0);
-		toshiba_spi_write(0x02, 0x03, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x28, 0);
-		toshiba_spi_write(0x03, 0x00, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x03, 0x29, 0);
-		toshiba_spi_write(0x00, 0x02, 1);
-
-#endif
-		udelay(500);
-		toshiba_spi_write(0x01, 0x00, 0);
-		toshiba_spi_write(0x36, 0x3c, 1);
-		udelay(500);
-
-		toshiba_spi_write(0x01, 0x01, 0);
-		toshiba_spi_write(0x40, 0x03, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x02, 0);
-		toshiba_spi_write(0x00, 0x01, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x03, 0);
-		toshiba_spi_write(0x3c, 0x58, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x0c, 0);
-		toshiba_spi_write(0x01, 0x35, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x06, 0);
-		toshiba_spi_write(0x00, 0x02, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x00, 0x29, 0);
-		toshiba_spi_write(0x03, 0xbf, 1);
-
-		udelay(500);
-		toshiba_spi_write(0x01, 0x06, 0);
-		toshiba_spi_write(0x00, 0x03, 1);
-		msleep(32);
-
-		toshiba_spi_write(0x01, 0x01, 0);
-		toshiba_spi_write(0x40, 0x10, 1);
-		msleep(80);
-
-		toshiba_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_toshiba_panel_on(struct platform_device *pdev)
-{
-	if (!toshiba_state.disp_initialized) {
-		/* Configure reset GPIO that drives DAC */
-		if (lcdc_toshiba_pdata->panel_config_gpio)
-			lcdc_toshiba_pdata->panel_config_gpio(1);
-		toshiba_disp_powerup();
-		toshiba_disp_on();
-		toshiba_state.disp_initialized = TRUE;
-	}
-	return 0;
-}
-
-static int lcdc_toshiba_panel_off(struct platform_device *pdev)
-{
-	if (toshiba_state.disp_powered_up && toshiba_state.display_on) {
-		toshiba_spi_write(0x01, 0x06, 1);
-		toshiba_spi_write(0x00, 0x02, 1);
-		msleep(80);
-
-		toshiba_spi_write(0x01, 0x06, 1);
-		toshiba_spi_write(0x00, 0x00, 1);
-
-		toshiba_spi_write(0x00, 0x29, 1);
-		toshiba_spi_write(0x00, 0x02, 1);
-
-		toshiba_spi_write(0x01, 0x00, 1);
-		toshiba_spi_write(0x30, 0x00, 1);
-
-		if (lcdc_toshiba_pdata->panel_config_gpio)
-			lcdc_toshiba_pdata->panel_config_gpio(0);
-		toshiba_state.display_on = FALSE;
-		toshiba_state.disp_initialized = FALSE;
-	}
-
-	return 0;
-}
-
-static void lcdc_toshiba_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int ret;
-	int bl_level;
-
-	bl_level = mfd->bl_level;
-
-	if (lcdc_toshiba_pdata && lcdc_toshiba_pdata->pmic_backlight)
-		ret = lcdc_toshiba_pdata->pmic_backlight(bl_level);
-	else
-		pr_err("%s(): Backlight level set failed", __func__);
-
-	return;
-}
-
-static int __devinit toshiba_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		lcdc_toshiba_pdata = pdev->dev.platform_data;
-		spi_pin_assign();
-		return 0;
-	}
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = toshiba_probe,
-	.driver = {
-		.name   = "lcdc_toshiba_fwvga_pt",
-	},
-};
-
-static struct msm_fb_panel_data toshiba_panel_data = {
-	.on = lcdc_toshiba_panel_on,
-	.off = lcdc_toshiba_panel_off,
-	.set_backlight = lcdc_toshiba_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_toshiba_fwvga_pt",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &toshiba_panel_data,
-	}
-};
-
-static int __init lcdc_toshiba_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = msm_fb_detect_client("lcdc_toshiba_fwvga_pt");
-	if (ret)
-		return 0;
-
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &toshiba_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 864;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	/* 30Mhz mdp_lcdc_pclk and mdp_lcdc_pad_pcl */
-	pinfo->clk_rate = 30720000;
-	pinfo->bl_max = 100;
-	pinfo->bl_min = 1;
-
-	if (cpu_is_msm7x25a() || cpu_is_msm7x25aa() || cpu_is_msm7x25ab()) {
-		pinfo->yres = 320;
-		pinfo->lcdc.h_back_porch = 10;
-		pinfo->lcdc.h_front_porch = 21;
-		pinfo->lcdc.h_pulse_width = 5;
-		pinfo->lcdc.v_back_porch = 8;
-		pinfo->lcdc.v_front_porch = 540;
-		pinfo->lcdc.v_pulse_width = 42;
-		pinfo->lcdc.border_clr = 0;     /* blk */
-		pinfo->lcdc.underflow_clr = 0xff;       /* blue */
-		pinfo->lcdc.hsync_skew = 0;
-	} else {
-		pinfo->lcdc.h_back_porch = 8;
-		pinfo->lcdc.h_front_porch = 16;
-		pinfo->lcdc.h_pulse_width = 8;
-		pinfo->lcdc.v_back_porch = 2;
-		pinfo->lcdc.v_front_porch = 2;
-		pinfo->lcdc.v_pulse_width = 2;
-		pinfo->lcdc.border_clr = 0;     /* blk */
-		pinfo->lcdc.underflow_clr = 0xff;       /* blue */
-		pinfo->lcdc.hsync_skew = 0;
-	}
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		printk(KERN_ERR "%s not able to register the device\n",
-			 __func__);
-		platform_driver_unregister(&this_driver);
-	}
-	return ret;
-}
-
-device_initcall(lcdc_toshiba_panel_init);
diff --git a/drivers/video/msm/lcdc_toshiba_wvga_pt.c b/drivers/video/msm/lcdc_toshiba_wvga_pt.c
deleted file mode 100644
index 30248ff..0000000
--- a/drivers/video/msm/lcdc_toshiba_wvga_pt.c
+++ /dev/null
@@ -1,519 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#ifdef CONFIG_SPI_QSD
-#include <linux/spi/spi.h>
-#endif
-#include <mach/gpio.h>
-#include <mach/pmic.h>
-#include "msm_fb.h"
-
-#ifdef CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-#include "mddihosti.h"
-#endif
-
-#ifdef CONFIG_SPI_QSD
-#define LCDC_TOSHIBA_SPI_DEVICE_NAME "lcdc_toshiba_ltm030dd40"
-static struct spi_device *lcdc_toshiba_spi_client;
-#else
-static int spi_cs;
-static int spi_sclk;
-static int spi_mosi;
-static int spi_miso;
-#endif
-struct toshiba_state_type{
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-};
-
-static struct toshiba_state_type toshiba_state = { 0 };
-static struct msm_panel_common_pdata *lcdc_toshiba_pdata;
-
-#ifndef CONFIG_SPI_QSD
-static void toshiba_spi_write_byte(char dc, uint8 data)
-{
-	uint32 bit;
-	int bnum;
-
-	gpio_set_value(spi_sclk, 0); /* clk low */
-	/* dc: 0 for command, 1 for parameter */
-	gpio_set_value(spi_mosi, dc);
-	udelay(1);	/* at least 20 ns */
-	gpio_set_value(spi_sclk, 1); /* clk high */
-	udelay(1);	/* at least 20 ns */
-	bnum = 8;	/* 8 data bits */
-	bit = 0x80;
-	while (bnum) {
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		if (data & bit)
-			gpio_set_value(spi_mosi, 1);
-		else
-			gpio_set_value(spi_mosi, 0);
-		udelay(1);
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		udelay(1);
-		bit >>= 1;
-		bnum--;
-	}
-}
-#endif
-
-static int toshiba_spi_write(char cmd, uint32 data, int num)
-{
-	char *bp;
-#ifdef CONFIG_SPI_QSD
-	char                tx_buf[4];
-	int                 rc, i;
-	struct spi_message  m;
-	struct spi_transfer t;
-	uint32 final_data = 0;
-
-	if (!lcdc_toshiba_spi_client) {
-		printk(KERN_ERR "%s lcdc_toshiba_spi_client is NULL\n",
-			__func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-	spi_setup(lcdc_toshiba_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	/* command byte first */
-	final_data |= cmd << 23;
-	t.len = num + 2;
-	if (t.len < 4)
-		t.bits_per_word = 8 * t.len;
-	/* followed by parameter bytes */
-	if (num) {
-		bp = (char *)&data;;
-		bp += (num - 1);
-		i = 1;
-		while (num) {
-			final_data |= 1 << (((4 - i) << 3) - i - 1);
-			final_data |= *bp << (((4 - i - 1) << 3) - i - 1);
-			num--;
-			bp--;
-			i++;
-		}
-	}
-
-	bp = (char *)&final_data;
-	for (i = 0; i < t.len; i++)
-		tx_buf[i] = bp[3 - i];
-	t.rx_buf = NULL;
-	rc = spi_sync(lcdc_toshiba_spi_client, &m);
-	if (rc)
-		printk(KERN_ERR "spi_sync _write failed %d\n", rc);
-	return rc;
-#else
-	gpio_set_value(spi_cs, 1);	/* cs high */
-
-	/* command byte first */
-	toshiba_spi_write_byte(0, cmd);
-
-	/* followed by parameter bytes */
-	if (num) {
-		bp = (char *)&data;;
-		bp += (num - 1);
-		while (num) {
-			toshiba_spi_write_byte(1, *bp);
-			num--;
-			bp--;
-		}
-	}
-
-	gpio_set_value(spi_cs, 0);	/* cs low */
-	udelay(1);
-	return 0;
-#endif
-}
-
-static int toshiba_spi_read_bytes(char cmd, uint32 *data, int num)
-{
-#ifdef CONFIG_SPI_QSD
-	char            tx_buf[5];
-	char		    rx_buf[5];
-	int                 rc;
-	struct spi_message  m;
-	struct spi_transfer t;
-
-	if (!lcdc_toshiba_spi_client) {
-		printk(KERN_ERR "%s lcdc_toshiba_spi_client is NULL\n",
-			 __func__);
-		return -EINVAL;
-	}
-
-	memset(&t, 0, sizeof t);
-	t.tx_buf = tx_buf;
-	t.rx_buf = rx_buf;
-	spi_setup(lcdc_toshiba_spi_client);
-	spi_message_init(&m);
-	spi_message_add_tail(&t, &m);
-
-	/* command byte first */
-	tx_buf[0] = 0 | ((cmd >> 1) & 0x7f);
-	tx_buf[1] = (cmd & 0x01) << 7;
-	tx_buf[2] = 0;
-	tx_buf[3] = 0;
-	tx_buf[4] = 0;
-
-	t.len = 5;
-
-	rc = spi_sync(lcdc_toshiba_spi_client, &m);
-	*data = 0;
-	*data = ((rx_buf[1] & 0x1f) << 19) | (rx_buf[2] << 11) |
-		(rx_buf[3] << 3) | ((rx_buf[4] & 0xe0) >> 5);
-	if (rc)
-		printk(KERN_ERR "spi_sync _read failed %d\n", rc);
-	return rc;
-#else
-	uint32 dbit, bits;
-	int bnum;
-
-	gpio_set_value(spi_cs, 1);	/* cs high */
-
-	/* command byte first */
-	toshiba_spi_write_byte(0, cmd);
-
-	if (num > 1) {
-		/* extra dc bit */
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		udelay(1);
-		dbit = gpio_get_value(spi_miso);/* dc bit */
-		udelay(1);
-		gpio_set_value(spi_sclk, 1); /* clk high */
-	}
-
-	/* followed by data bytes */
-	bnum = num * 8;	/* number of bits */
-	bits = 0;
-	while (bnum) {
-		bits <<= 1;
-		gpio_set_value(spi_sclk, 0); /* clk low */
-		udelay(1);
-		dbit = gpio_get_value(spi_miso);
-		udelay(1);
-		gpio_set_value(spi_sclk, 1); /* clk high */
-		bits |= dbit;
-		bnum--;
-	}
-
-	*data = bits;
-
-	udelay(1);
-	gpio_set_value(spi_cs, 0);	/* cs low */
-	udelay(1);
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SPI_QSD
-static void spi_pin_assign(void)
-{
-	/* Setting the Default GPIO's */
-	spi_sclk = *(lcdc_toshiba_pdata->gpio_num);
-	spi_cs   = *(lcdc_toshiba_pdata->gpio_num + 1);
-	spi_mosi  = *(lcdc_toshiba_pdata->gpio_num + 2);
-	spi_miso  = *(lcdc_toshiba_pdata->gpio_num + 3);
-}
-#endif
-
-static void toshiba_disp_powerup(void)
-{
-	if (!toshiba_state.disp_powered_up && !toshiba_state.display_on) {
-		/* Reset the hardware first */
-		/* Include DAC power up implementation here */
-	      toshiba_state.disp_powered_up = TRUE;
-	}
-}
-
-static void toshiba_disp_on(void)
-{
-	uint32	data;
-
-#ifndef CONFIG_SPI_QSD
-	gpio_set_value(spi_cs, 0);	/* low */
-	gpio_set_value(spi_sclk, 1);	/* high */
-	gpio_set_value(spi_mosi, 0);
-	gpio_set_value(spi_miso, 0);
-#endif
-
-	if (toshiba_state.disp_powered_up && !toshiba_state.display_on) {
-		toshiba_spi_write(0, 0, 0);
-		mdelay(7);
-		toshiba_spi_write(0, 0, 0);
-		mdelay(7);
-		toshiba_spi_write(0, 0, 0);
-		mdelay(7);
-		toshiba_spi_write(0xba, 0x11, 1);
-		toshiba_spi_write(0x36, 0x00, 1);
-		mdelay(1);
-		toshiba_spi_write(0x3a, 0x60, 1);
-		toshiba_spi_write(0xb1, 0x5d, 1);
-		mdelay(1);
-		toshiba_spi_write(0xb2, 0x33, 1);
-		toshiba_spi_write(0xb3, 0x22, 1);
-		mdelay(1);
-		toshiba_spi_write(0xb4, 0x02, 1);
-		toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
-		mdelay(1);
-		toshiba_spi_write(0xb6, 0x27, 1);
-		toshiba_spi_write(0xb7, 0x03, 1);
-		mdelay(1);
-		toshiba_spi_write(0xb9, 0x24, 1);
-		toshiba_spi_write(0xbd, 0xa1, 1);
-		mdelay(1);
-		toshiba_spi_write(0xbb, 0x00, 1);
-		toshiba_spi_write(0xbf, 0x01, 1);
-		mdelay(1);
-		toshiba_spi_write(0xbe, 0x00, 1);
-		toshiba_spi_write(0xc0, 0x11, 1);
-		mdelay(1);
-		toshiba_spi_write(0xc1, 0x11, 1);
-		toshiba_spi_write(0xc2, 0x11, 1);
-		mdelay(1);
-		toshiba_spi_write(0xc3, 0x3232, 2);
-		mdelay(1);
-		toshiba_spi_write(0xc4, 0x3232, 2);
-		mdelay(1);
-		toshiba_spi_write(0xc5, 0x3232, 2);
-		mdelay(1);
-		toshiba_spi_write(0xc6, 0x3232, 2);
-		mdelay(1);
-		toshiba_spi_write(0xc7, 0x6445, 2);
-		mdelay(1);
-		toshiba_spi_write(0xc8, 0x44, 1);
-		toshiba_spi_write(0xc9, 0x52, 1);
-		mdelay(1);
-		toshiba_spi_write(0xca, 0x00, 1);
-		mdelay(1);
-		toshiba_spi_write(0xec, 0x02a4, 2);	/* 0x02a4 */
-		mdelay(1);
-		toshiba_spi_write(0xcf, 0x01, 1);
-		mdelay(1);
-		toshiba_spi_write(0xd0, 0xc003, 2);	/* c003 */
-		mdelay(1);
-		toshiba_spi_write(0xd1, 0x01, 1);
-		mdelay(1);
-		toshiba_spi_write(0xd2, 0x0028, 2);
-		mdelay(1);
-		toshiba_spi_write(0xd3, 0x0028, 2);
-		mdelay(1);
-		toshiba_spi_write(0xd4, 0x26a4, 2);
-		mdelay(1);
-		toshiba_spi_write(0xd5, 0x20, 1);
-		mdelay(1);
-		toshiba_spi_write(0xef, 0x3200, 2);
-		mdelay(32);
-		toshiba_spi_write(0xbc, 0x80, 1);	/* wvga pass through */
-		toshiba_spi_write(0x3b, 0x00, 1);
-		mdelay(1);
-		toshiba_spi_write(0xb0, 0x16, 1);
-		mdelay(1);
-		toshiba_spi_write(0xb8, 0xfff5, 2);
-		mdelay(1);
-		toshiba_spi_write(0x11, 0, 0);
-		mdelay(5);
-		toshiba_spi_write(0x29, 0, 0);
-		mdelay(5);
-		toshiba_state.display_on = TRUE;
-	}
-
-	data = 0;
-	toshiba_spi_read_bytes(0x04, &data, 3);
-	printk(KERN_INFO "toshiba_disp_on: id=%x\n", data);
-
-}
-
-static int lcdc_toshiba_panel_on(struct platform_device *pdev)
-{
-	if (!toshiba_state.disp_initialized) {
-		/* Configure reset GPIO that drives DAC */
-		if (lcdc_toshiba_pdata->panel_config_gpio)
-			lcdc_toshiba_pdata->panel_config_gpio(1);
-		toshiba_disp_powerup();
-		toshiba_disp_on();
-		toshiba_state.disp_initialized = TRUE;
-	}
-	return 0;
-}
-
-static int lcdc_toshiba_panel_off(struct platform_device *pdev)
-{
-	if (toshiba_state.disp_powered_up && toshiba_state.display_on) {
-		/* Main panel power off (Deep standby in) */
-
-		toshiba_spi_write(0x28, 0, 0);	/* display off */
-		mdelay(1);
-		toshiba_spi_write(0xb8, 0x8002, 2);	/* output control */
-		mdelay(1);
-		toshiba_spi_write(0x10, 0x00, 1);	/* sleep mode in */
-		mdelay(85);		/* wait 85 msec */
-		toshiba_spi_write(0xb0, 0x00, 1);	/* deep standby in */
-		mdelay(1);
-		if (lcdc_toshiba_pdata->panel_config_gpio)
-			lcdc_toshiba_pdata->panel_config_gpio(0);
-		toshiba_state.display_on = FALSE;
-		toshiba_state.disp_initialized = FALSE;
-	}
-	return 0;
-}
-
-static void lcdc_toshiba_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int bl_level;
-	int ret = -EPERM;
-	int i = 0;
-
-	bl_level = mfd->bl_level;
-
-	while (i++ < 3) {
-		ret = pmic_set_led_intensity(LED_LCD, bl_level);
-		if (ret == 0)
-			return;
-		msleep(10);
-	}
-
-	printk(KERN_WARNING "%s: can't set lcd backlight!\n",
-				__func__);
-}
-
-static int __devinit toshiba_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		lcdc_toshiba_pdata = pdev->dev.platform_data;
-#ifndef CONFIG_SPI_QSD
-		spi_pin_assign();
-#endif
-		return 0;
-	}
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-#ifdef CONFIG_SPI_QSD
-static int __devinit lcdc_toshiba_spi_probe(struct spi_device *spi)
-{
-	lcdc_toshiba_spi_client = spi;
-	lcdc_toshiba_spi_client->bits_per_word = 32;
-	return 0;
-}
-static int __devexit lcdc_toshiba_spi_remove(struct spi_device *spi)
-{
-	lcdc_toshiba_spi_client = NULL;
-	return 0;
-}
-
-static struct spi_driver lcdc_toshiba_spi_driver = {
-	.driver = {
-		.name  = LCDC_TOSHIBA_SPI_DEVICE_NAME,
-		.owner = THIS_MODULE,
-	},
-	.probe         = lcdc_toshiba_spi_probe,
-	.remove        = __devexit_p(lcdc_toshiba_spi_remove),
-};
-#endif
-static struct platform_driver this_driver = {
-	.probe  = toshiba_probe,
-	.driver = {
-		.name   = "lcdc_toshiba_wvga",
-	},
-};
-
-static struct msm_fb_panel_data toshiba_panel_data = {
-	.on = lcdc_toshiba_panel_on,
-	.off = lcdc_toshiba_panel_off,
-	.set_backlight = lcdc_toshiba_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_toshiba_wvga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &toshiba_panel_data,
-	}
-};
-
-static int __init lcdc_toshiba_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-#ifdef CONFIG_FB_MSM_TRY_MDDI_CATCH_LCDC_PRISM
-	if (mddi_get_client_id() != 0)
-		return 0;
-
-	ret = msm_fb_detect_client("lcdc_toshiba_wvga_pt");
-	if (ret)
-		return 0;
-
-#endif
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &toshiba_panel_data.panel_info;
-	pinfo->xres = 480;
-	pinfo->yres = 800;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	/* 30Mhz mdp_lcdc_pclk and mdp_lcdc_pad_pcl */
-	pinfo->clk_rate = 30720000;
-	pinfo->bl_max = 15;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 184;	/* hsw = 8 + hbp=184 */
-	pinfo->lcdc.h_front_porch = 4;
-	pinfo->lcdc.h_pulse_width = 8;
-	pinfo->lcdc.v_back_porch = 2;	/* vsw=1 + vbp = 2 */
-	pinfo->lcdc.v_front_porch = 3;
-	pinfo->lcdc.v_pulse_width = 1;
-	pinfo->lcdc.border_clr = 0;     /* blk */
-	pinfo->lcdc.underflow_clr = 0xff;       /* blue */
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		printk(KERN_ERR "%s not able to register the device\n",
-			 __func__);
-		goto fail_driver;
-	}
-#ifdef CONFIG_SPI_QSD
-	ret = spi_register_driver(&lcdc_toshiba_spi_driver);
-
-	if (ret) {
-		printk(KERN_ERR "%s not able to register spi\n", __func__);
-		goto fail_device;
-	}
-#endif
-	return ret;
-
-#ifdef CONFIG_SPI_QSD
-fail_device:
-	platform_device_unregister(&this_device);
-#endif
-fail_driver:
-	platform_driver_unregister(&this_driver);
-	return ret;
-}
-
-device_initcall(lcdc_toshiba_panel_init);
diff --git a/drivers/video/msm/lcdc_truly_ips3p2335.c b/drivers/video/msm/lcdc_truly_ips3p2335.c
deleted file mode 100644
index 89ede49..0000000
--- a/drivers/video/msm/lcdc_truly_ips3p2335.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/gpio.h>
-#include <mach/pmic.h>
-#include "msm_fb.h"
-
-static int prev_bl = 17;
-
-static int spi_cs;
-static int spi_sclk;
-static int spi_mosi;
-static int gpio_backlight_en;
-static int gpio_display_reset;
-
-struct truly_state_type {
-	boolean disp_initialized;
-	boolean display_on;
-	boolean disp_powered_up;
-};
-
-static struct truly_state_type truly_state = { 0 };
-static struct msm_panel_common_pdata *lcdc_truly_pdata;
-
-static char init_item_v1[] = { 0xff, 0x83, 0x57, };
-static char init_item_v2[] = { 0x03, };
-static char init_item_v3[] = { 0x00, 0x13, 0x1C, 0x1C, 0x83, 0x48, };
-static char init_item_v4[] = { 0x43, 0x06, 0x06, 0x06, };
-static char init_item_v5[] = { 0x53, };
-static char init_item_v6[] = { 0x02, 0x40, 0x00, 0x2a, 0x2a, 0x0d, 0x3f, };
-static char init_item_v7[] = { 0x70, 0x50, 0x01, 0x3c, 0xe8, 0x08, };
-static char init_item_v8[] = { 0x17, 0x0f, };
-static char init_item_v9[] = { 0x60};
-static char init_item_v10[] = { 0x00, 0x13, 0x1a, 0x29, 0x2d, 0x41, 0x49,
-				0x52, 0x48, 0x41, 0x3c, 0x33, 0x30, 0x1c,
-				0x19, 0x03, 0x00, 0x13, 0x1a, 0x29, 0x2d,
-				0x41, 0x49, 0x52, 0x48, 0x41, 0x3c, 0x33,
-				0x31, 0x1c, 0x19, 0x03, 0x00, 0x01,
-				};
-static char init_item_v11[] = { 0x40, };
-
-static inline void truly_spi_write_byte(char dc, uint8 data)
-{
-	uint32 bit;
-	int bnum;
-
-	gpio_set_value_cansleep(spi_sclk, 0); /* clk low */
-	/* dc: 0 for command, 1 for parameter */
-	gpio_set_value_cansleep(spi_mosi, dc);
-	udelay(1);	/* at least 20 ns */
-	gpio_set_value_cansleep(spi_sclk, 1); /* clk high */
-	udelay(1);	/* at least 20 ns */
-	bnum = 8;	/* 8 data bits */
-	bit = 0x80;
-	while (bnum) {
-		gpio_set_value_cansleep(spi_sclk, 0); /* clk low */
-		if (data & bit)
-			gpio_set_value_cansleep(spi_mosi, 1);
-		else
-			gpio_set_value_cansleep(spi_mosi, 0);
-		udelay(1);
-		gpio_set_value_cansleep(spi_sclk, 1); /* clk high */
-		udelay(1);
-		bit >>= 1;
-		bnum--;
-	}
-}
-
-static inline int truly_spi_write(char cmd, char *data, int num)
-{
-	int i;
-
-	gpio_set_value_cansleep(spi_cs, 0);	/* cs low */
-	/* command byte first */
-	truly_spi_write_byte(0, cmd);
-	/* followed by parameter bytes */
-	for (i = 0; i < num; i++) {
-		if (data)
-			truly_spi_write_byte(1, data[i]);
-	}
-	gpio_set_value_cansleep(spi_mosi, 1);	/* mosi high */
-	gpio_set_value_cansleep(spi_cs, 1);	/* cs high */
-	udelay(10);
-	return 0;
-}
-
-static void spi_pin_assign(void)
-{
-	/* Setting the Default GPIO's */
-	spi_mosi	= *(lcdc_truly_pdata->gpio_num);
-	spi_sclk	= *(lcdc_truly_pdata->gpio_num + 1);
-	spi_cs		= *(lcdc_truly_pdata->gpio_num + 2);
-	gpio_backlight_en = *(lcdc_truly_pdata->gpio_num + 3);
-	gpio_display_reset = *(lcdc_truly_pdata->gpio_num + 4);
-	pr_debug("spi_mosi:%d spi_sclk:%d spi_cs:%d backlight:%d reset:%d\n",
-		spi_mosi, spi_sclk, spi_cs, gpio_backlight_en,
-		gpio_display_reset);
-
-}
-
-static void truly_disp_powerup(void)
-{
-	/* Reset the hardware first */
-	/* Include DAC power up implementation here */
-	if (!truly_state.disp_powered_up && !truly_state.display_on)
-		truly_state.disp_powered_up = TRUE;
-}
-
-static void truly_disp_reginit(void)
-{
-	pr_debug("%s disp_powered_up:%d display_on:%d\n", __func__,
-			truly_state.disp_powered_up, truly_state.display_on);
-	if (truly_state.disp_powered_up && !truly_state.display_on) {
-		gpio_set_value_cansleep(spi_cs, 1);	/* cs high */
-
-		truly_spi_write(0xb9, init_item_v1, sizeof(init_item_v1));
-		msleep(20);
-		truly_spi_write(0xcc, init_item_v2, sizeof(init_item_v2));
-		truly_spi_write(0xb1, init_item_v3, sizeof(init_item_v3));
-		truly_spi_write(0xb3, init_item_v4, sizeof(init_item_v4));
-		truly_spi_write(0xb6, init_item_v5, sizeof(init_item_v5));
-		truly_spi_write(0xb4, init_item_v6, sizeof(init_item_v6));
-		truly_spi_write(0xc0, init_item_v7, sizeof(init_item_v7));
-		truly_spi_write(0xe3, init_item_v8, sizeof(init_item_v8));
-		truly_spi_write(0x3a, init_item_v9, sizeof(init_item_v9));
-		truly_spi_write(0xe0, init_item_v10, sizeof(init_item_v10));
-		truly_spi_write(0x36, init_item_v11, sizeof(init_item_v11));
-		truly_spi_write(0x11, NULL, 0);
-		msleep(150);
-		truly_spi_write(0x29, NULL, 0);
-		msleep(25);
-
-		truly_state.display_on = TRUE;
-	}
-}
-
-static int lcdc_truly_panel_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
-
-	if (!mfd->cont_splash_done) {
-		mfd->cont_splash_done = 1;
-		return 0;
-	}
-
-	/* Configure reset GPIO that drives DAC */
-	if (lcdc_truly_pdata->panel_config_gpio)
-		lcdc_truly_pdata->panel_config_gpio(1);
-	gpio_set_value_cansleep(gpio_display_reset, 1);
-	truly_disp_powerup();
-	truly_disp_reginit();
-	truly_state.disp_initialized = TRUE;
-	return 0;
-}
-
-static int lcdc_truly_panel_off(struct platform_device *pdev)
-{
-	if (truly_state.disp_powered_up && truly_state.display_on) {
-		/* Main panel power off (Pull down reset) */
-		gpio_set_value_cansleep(gpio_display_reset, 0);
-		truly_state.display_on = FALSE;
-		truly_state.disp_initialized = FALSE;
-	}
-	return 0;
-}
-
-static void lcdc_truly_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int step = 0, i = 0;
-	unsigned long flags;
-	int bl_level = mfd->bl_level;
-
-	/* real backlight level, 1 - max, 16 - min, 17 - off */
-	bl_level = 17 - bl_level;
-
-	if (bl_level > prev_bl) {
-		step = bl_level - prev_bl;
-		if (bl_level == 17)
-			step--;
-	} else if (bl_level < prev_bl) {
-		step = bl_level + 16 - prev_bl;
-	} else {
-		pr_info("%s: no change\n", __func__);
-		return;
-	}
-
-	if (bl_level == 17) {
-		/* turn off backlight */
-		gpio_set_value(gpio_backlight_en, 0);
-	} else {
-		local_irq_save(flags);
-
-		if (prev_bl == 17) {
-			/* turn on backlight */
-			gpio_set_value(gpio_backlight_en, 1);
-			udelay(30);
-		}
-
-		/* adjust backlight level */
-		for (i = 0; i < step; i++) {
-			gpio_set_value(gpio_backlight_en, 0);
-			udelay(1);
-			gpio_set_value(gpio_backlight_en, 1);
-			udelay(1);
-		}
-
-		local_irq_restore(flags);
-	}
-	msleep(20);
-	prev_bl = bl_level;
-
-	return;
-}
-
-static int __devinit truly_probe(struct platform_device *pdev)
-{
-
-	if (pdev->id == 0) {
-		lcdc_truly_pdata = pdev->dev.platform_data;
-
-		if (!lcdc_truly_pdata)
-			pr_err("%s pdata is null\n", __func__);
-
-		spi_pin_assign();
-		return 0;
-	}
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = truly_probe,
-	.driver = {
-		.name   = "lcdc_truly_hvga_ips3p2335_pt",
-	},
-};
-
-static struct msm_fb_panel_data truly_panel_data = {
-	.on = lcdc_truly_panel_on,
-	.off = lcdc_truly_panel_off,
-	.set_backlight = lcdc_truly_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lcdc_truly_hvga_ips3p2335_pt",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &truly_panel_data,
-	}
-};
-
-static int __init lcdc_truly_panel_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = msm_fb_detect_client("lcdc_truly_hvga_ips3p2335_pt");
-	if (ret)
-		return 0;
-
-	ret = platform_driver_register(&this_driver);
-	if (ret) {
-		pr_err("%s() driver registration failed", __func__);
-		return ret;
-	}
-
-	pinfo = &truly_panel_data.panel_info;
-	pinfo->xres = 320;
-	pinfo->yres = 480;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LCDC_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 18;
-	pinfo->fb_num = 2;
-	/* 10Mhz mdp_lcdc_pclk and mdp_lcdc_pad_pcl */
-	pinfo->clk_rate = 10240000;
-	pinfo->bl_max = 16;
-	pinfo->bl_min = 1;
-
-	pinfo->lcdc.h_back_porch = 16;		/* hsw = 8 + hbp=16 */
-	pinfo->lcdc.h_front_porch = 4;
-	pinfo->lcdc.h_pulse_width = 8;
-	pinfo->lcdc.v_back_porch = 7;		/* vsw=1 + vbp = 7 */
-	pinfo->lcdc.v_front_porch = 3;
-	pinfo->lcdc.v_pulse_width = 1;
-	pinfo->lcdc.border_clr = 0;		/* blk */
-	pinfo->lcdc.underflow_clr = 0xff;	/* blue */
-	pinfo->lcdc.hsync_skew = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret) {
-		pr_err("%s not able to register the device\n", __func__);
-		platform_driver_unregister(&this_driver);
-	}
-	return ret;
-}
-
-device_initcall(lcdc_truly_panel_init);
diff --git a/drivers/video/msm/lcdc_wxga.c b/drivers/video/msm/lcdc_wxga.c
deleted file mode 100644
index dca57de..0000000
--- a/drivers/video/msm/lcdc_wxga.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-
-static int __init lcdc_wxga_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	if (msm_fb_detect_client("lcdc_wxga"))
-		return 0;
-#endif
-
-	pinfo.xres = 1280;
-	pinfo.yres = 720;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = LCDC_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 24;
-	pinfo.fb_num = 2;
-	pinfo.clk_rate = 74250000;
-
-	pinfo.lcdc.h_back_porch = 124;
-	pinfo.lcdc.h_front_porch = 110;
-	pinfo.lcdc.h_pulse_width = 136;
-	pinfo.lcdc.v_back_porch = 19;
-	pinfo.lcdc.v_front_porch = 5;
-	pinfo.lcdc.v_pulse_width = 6;
-	pinfo.lcdc.border_clr = 0;	/* blk */
-	pinfo.lcdc.underflow_clr = 0xff;	/* blue */
-	pinfo.lcdc.hsync_skew = 0;
-
-	ret = lcdc_device_register(&pinfo);
-	if (ret)
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-
-	return ret;
-}
-
-module_init(lcdc_wxga_init);
diff --git a/drivers/video/msm/logo.c b/drivers/video/msm/logo.c
deleted file mode 100644
index 57d754e..0000000
--- a/drivers/video/msm/logo.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* drivers/video/msm/logo.c
- *
- * Show Logo in RLE 565 format
- *
- * Copyright (C) 2008 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/fb.h>
-#include <linux/vt_kern.h>
-#include <linux/unistd.h>
-#include <linux/syscalls.h>
-
-#include <linux/irq.h>
-#include <asm/system.h>
-
-#define fb_width(fb)	((fb)->var.xres)
-#define fb_height(fb)	((fb)->var.yres)
-#define fb_size(fb)	((fb)->var.xres * (fb)->var.yres * 2)
-
-static void memset16(void *_ptr, unsigned short val, unsigned count)
-{
-	unsigned short *ptr = _ptr;
-	count >>= 1;
-	while (count--)
-		*ptr++ = val;
-}
-
-/* 565RLE image format: [count(2 bytes), rle(2 bytes)] */
-int load_565rle_image(char *filename, bool bf_supported)
-{
-	struct fb_info *info;
-	int fd, count, err = 0;
-	unsigned max;
-	unsigned short *data, *bits, *ptr;
-
-	info = registered_fb[0];
-	if (!info) {
-		printk(KERN_WARNING "%s: Can not access framebuffer\n",
-			__func__);
-		return -ENODEV;
-	}
-
-	fd = sys_open(filename, O_RDONLY, 0);
-	if (fd < 0) {
-		printk(KERN_WARNING "%s: Can not open %s\n",
-			__func__, filename);
-		return -ENOENT;
-	}
-	count = sys_lseek(fd, (off_t)0, 2);
-	if (count <= 0) {
-		err = -EIO;
-		goto err_logo_close_file;
-	}
-	sys_lseek(fd, (off_t)0, 0);
-	data = kmalloc(count, GFP_KERNEL);
-	if (!data) {
-		printk(KERN_WARNING "%s: Can not alloc data\n", __func__);
-		err = -ENOMEM;
-		goto err_logo_close_file;
-	}
-	if (sys_read(fd, (char *)data, count) != count) {
-		err = -EIO;
-		goto err_logo_free_data;
-	}
-
-	max = fb_width(info) * fb_height(info);
-	ptr = data;
-	if (bf_supported && (info->node == 1 || info->node == 2)) {
-		err = -EPERM;
-		pr_err("%s:%d no info->creen_base on fb%d!\n",
-		       __func__, __LINE__, info->node);
-		goto err_logo_free_data;
-	}
-	bits = (unsigned short *)(info->screen_base);
-	while (count > 3) {
-		unsigned n = ptr[0];
-		if (n > max)
-			break;
-		memset16(bits, ptr[1], n << 1);
-		bits += n;
-		max -= n;
-		ptr += 2;
-		count -= 4;
-	}
-
-err_logo_free_data:
-	kfree(data);
-err_logo_close_file:
-	sys_close(fd);
-	return err;
-}
-EXPORT_SYMBOL(load_565rle_image);
diff --git a/drivers/video/msm/lvds.c b/drivers/video/msm/lvds.c
deleted file mode 100644
index 4e31d6a..0000000
--- a/drivers/video/msm/lvds.c
+++ /dev/null
@@ -1,414 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/msm_iomap.h>
-#include <mach/clk.h>
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/consumer.h>
-
-#include "msm_fb.h"
-#include "mdp4.h"
-
-#define LVDS_PIXEL_MAP_PATTERN_2	2
-
-static int lvds_probe(struct platform_device *pdev);
-static int lvds_remove(struct platform_device *pdev);
-
-static int lvds_off(struct platform_device *pdev);
-static int lvds_on(struct platform_device *pdev);
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-
-static struct clk *lvds_clk;
-
-static struct platform_driver lvds_driver = {
-	.probe = lvds_probe,
-	.remove = lvds_remove,
-	.suspend = NULL,
-	.resume = NULL,
-	.shutdown = NULL,
-	.driver = {
-		   .name = "lvds",
-		   },
-};
-
-static struct lcdc_platform_data *lvds_pdata;
-
-static void lvds_init(struct msm_fb_data_type *mfd)
-{
-	unsigned int lvds_intf = 0, lvds_phy_cfg0 = 0;
-
-	MDP_OUTP(MDP_BASE + 0xc2034, 0x33);
-	usleep(1000);
-
-	/* LVDS PHY PLL configuration */
-	if (mfd->panel_info.clk_rate == 74250000) {
-		MDP_OUTP(MDP_BASE + 0xc3000, 0x08);
-		MDP_OUTP(MDP_BASE + 0xc3004, 0x4c);
-		MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
-		MDP_OUTP(MDP_BASE + 0xc300c, 0xc3);
-		MDP_OUTP(MDP_BASE + 0xc3014, 0x10);
-		MDP_OUTP(MDP_BASE + 0xc3018, 0x04);
-		MDP_OUTP(MDP_BASE + 0xc301c, 0x62);
-		MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
-		MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
-		MDP_OUTP(MDP_BASE + 0xc3028, 0x07);
-		MDP_OUTP(MDP_BASE + 0xc302c, 0x00);
-		MDP_OUTP(MDP_BASE + 0xc3030, 0x1c);
-		MDP_OUTP(MDP_BASE + 0xc3034, 0x01);
-		MDP_OUTP(MDP_BASE + 0xc3038, 0x00);
-		MDP_OUTP(MDP_BASE + 0xc3040, 0xC0);
-		MDP_OUTP(MDP_BASE + 0xc3044, 0x00);
-		MDP_OUTP(MDP_BASE + 0xc3048, 0x30);
-		MDP_OUTP(MDP_BASE + 0xc304c, 0x00);
-
-		MDP_OUTP(MDP_BASE + 0xc3000, 0x11);
-		MDP_OUTP(MDP_BASE + 0xc3064, 0x05);
-		MDP_OUTP(MDP_BASE + 0xc3050, 0x20);
-	} else {
-		MDP_OUTP(MDP_BASE + 0xc3004, 0x8f);
-		MDP_OUTP(MDP_BASE + 0xc3008, 0x30);
-		MDP_OUTP(MDP_BASE + 0xc300c, 0xc6);
-		MDP_OUTP(MDP_BASE + 0xc3014, 0x10);
-		MDP_OUTP(MDP_BASE + 0xc3018, 0x07);
-		MDP_OUTP(MDP_BASE + 0xc301c, 0x62);
-		MDP_OUTP(MDP_BASE + 0xc3020, 0x41);
-		MDP_OUTP(MDP_BASE + 0xc3024, 0x0d);
-	}
-
-	MDP_OUTP(MDP_BASE + 0xc3000, 0x01);
-	/* Wait until LVDS PLL is locked and ready */
-	while (!readl_relaxed(MDP_BASE + 0xc3080))
-		cpu_relax();
-
-	writel_relaxed(0x00, mmss_cc_base + 0x0264);
-	writel_relaxed(0x00, mmss_cc_base + 0x0094);
-
-	writel_relaxed(0x02, mmss_cc_base + 0x00E4);
-
-	writel_relaxed((0x80 | readl_relaxed(mmss_cc_base + 0x00E4)),
-	       mmss_cc_base + 0x00E4);
-	usleep(1000);
-	writel_relaxed((~0x80 & readl_relaxed(mmss_cc_base + 0x00E4)),
-	       mmss_cc_base + 0x00E4);
-
-	writel_relaxed(0x05, mmss_cc_base + 0x0094);
-	writel_relaxed(0x02, mmss_cc_base + 0x0264);
-	/* Wait until LVDS pixel clock output is enabled */
-	mb();
-
-	if (mfd->panel_info.bpp == 24) {
-		if (lvds_pdata &&
-		    lvds_pdata->lvds_pixel_remap &&
-		    lvds_pdata->lvds_pixel_remap()) {
-			if (lvds_pdata->lvds_pixel_remap() ==
-				LVDS_PIXEL_MAP_PATTERN_2) {
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc2014, 0x070A1B1B);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2018, 0x00040506);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc201c, 0x12131B1B);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2020, 0x000B0C0D);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc2024, 0x191A1B1B);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2028, 0x00141518);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc202c, 0x171B1B1B);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2030, 0x000e0f16);
-			} else {
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc2014, 0x05080001);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2018, 0x00020304);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc201c, 0x1011090a);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2020, 0x000b0c0d);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc2024, 0x191a1213);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2028, 0x00141518);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
-				MDP_OUTP(MDP_BASE +  0xc202c, 0x171b0607);
-				/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
-				MDP_OUTP(MDP_BASE +  0xc2030, 0x000e0f16);
-			}
-		} else {
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
-			MDP_OUTP(MDP_BASE +  0xc2014, 0x03040508);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
-			MDP_OUTP(MDP_BASE +  0xc2018, 0x00000102);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
-			MDP_OUTP(MDP_BASE +  0xc201c, 0x0c0d1011);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
-			MDP_OUTP(MDP_BASE +  0xc2020, 0x00090a0b);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
-			MDP_OUTP(MDP_BASE +  0xc2024, 0x1518191a);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
-			MDP_OUTP(MDP_BASE +  0xc2028, 0x00121314);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_3_TO_0 */
-			MDP_OUTP(MDP_BASE +  0xc202c, 0x0f16171b);
-			/* MDP_LCDC_LVDS_MUX_CTL_FOR_D3_6_TO_4 */
-			MDP_OUTP(MDP_BASE +  0xc2030, 0x0006070e);
-		}
-		if (mfd->panel_info.lvds.channel_mode ==
-			LVDS_DUAL_CHANNEL_MODE) {
-			lvds_intf = 0x0003ff80;
-			lvds_phy_cfg0 = BIT(6) | BIT(7);
-			if (mfd->panel_info.lvds.channel_swap)
-				lvds_intf |= BIT(4);
-		} else {
-			lvds_intf = 0x00010f84;
-			lvds_phy_cfg0 = BIT(6);
-		}
-	} else if (mfd->panel_info.bpp == 18) {
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_3_TO_0 */
-		MDP_OUTP(MDP_BASE +  0xc2014, 0x03040508);
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D0_6_TO_4 */
-		MDP_OUTP(MDP_BASE +  0xc2018, 0x00000102);
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_3_TO_0 */
-		MDP_OUTP(MDP_BASE +  0xc201c, 0x0c0d1011);
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D1_6_TO_4 */
-		MDP_OUTP(MDP_BASE +  0xc2020, 0x00090a0b);
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_3_TO_0 */
-		MDP_OUTP(MDP_BASE +  0xc2024, 0x1518191a);
-		/* MDP_LCDC_LVDS_MUX_CTL_FOR_D2_6_TO_4 */
-		MDP_OUTP(MDP_BASE +  0xc2028, 0x00121314);
-
-		if (mfd->panel_info.lvds.channel_mode ==
-			LVDS_DUAL_CHANNEL_MODE) {
-			lvds_intf = 0x00037788;
-			lvds_phy_cfg0 = BIT(6) | BIT(7);
-			if (mfd->panel_info.lvds.channel_swap)
-				lvds_intf |= BIT(4);
-		} else {
-			lvds_intf = 0x0001078c;
-			lvds_phy_cfg0 = BIT(6);
-		}
-	} else {
-		BUG();
-	}
-
-	/* MDP_LVDSPHY_CFG0 */
-	MDP_OUTP(MDP_BASE +  0xc3100, lvds_phy_cfg0);
-	/* MDP_LCDC_LVDS_INTF_CTL */
-	MDP_OUTP(MDP_BASE +  0xc2000, lvds_intf);
-	MDP_OUTP(MDP_BASE +  0xc3108, 0x30);
-	lvds_phy_cfg0 |= BIT(4);
-
-	/* Wait until LVDS PHY registers are configured */
-	mb();
-	usleep(1);
-	/* MDP_LVDSPHY_CFG0, enable serialization */
-	MDP_OUTP(MDP_BASE +  0xc3100, lvds_phy_cfg0);
-}
-
-static int lvds_off(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-	ret = panel_next_off(pdev);
-
-	if (lvds_clk)
-		clk_disable_unprepare(lvds_clk);
-
-	MDP_OUTP(MDP_BASE +  0xc3100, 0x0);
-	MDP_OUTP(MDP_BASE + 0xc3000, 0x0);
-	usleep(10);
-
-	if (lvds_pdata && lvds_pdata->lcdc_power_save)
-		lvds_pdata->lcdc_power_save(0);
-
-	if (lvds_pdata && lvds_pdata->lcdc_gpio_config)
-		ret = lvds_pdata->lcdc_gpio_config(0);
-
-	return ret;
-}
-
-static int lvds_on(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd;
-	unsigned long panel_pixclock_freq = 0;
-	mfd = platform_get_drvdata(pdev);
-
-	if (lvds_pdata && lvds_pdata->lcdc_get_clk)
-		panel_pixclock_freq = lvds_pdata->lcdc_get_clk();
-
-	if (!panel_pixclock_freq)
-		panel_pixclock_freq = mfd->fbi->var.pixclock;
-	mfd = platform_get_drvdata(pdev);
-
-	if (lvds_clk) {
-		mfd->fbi->var.pixclock = clk_round_rate(lvds_clk,
-			mfd->fbi->var.pixclock);
-		ret = clk_set_rate(lvds_clk, mfd->fbi->var.pixclock);
-		if (ret) {
-			pr_err("%s: Can't set lvds clock to rate %u\n",
-				__func__, mfd->fbi->var.pixclock);
-			goto out;
-		}
-		clk_prepare_enable(lvds_clk);
-	}
-
-	if (lvds_pdata && lvds_pdata->lcdc_power_save)
-		lvds_pdata->lcdc_power_save(1);
-	if (lvds_pdata && lvds_pdata->lcdc_gpio_config)
-		ret = lvds_pdata->lcdc_gpio_config(1);
-
-	lvds_init(mfd);
-	ret = panel_next_on(pdev);
-
-out:
-	return ret;
-}
-
-static int lvds_probe(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	struct fb_info *fbi;
-	struct platform_device *mdp_dev = NULL;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-
-	if (pdev->id == 0) {
-		lvds_pdata = pdev->dev.platform_data;
-
-		lvds_clk = clk_get(&pdev->dev, "lvds_clk");
-		if (IS_ERR_OR_NULL(lvds_clk)) {
-			pr_err("Couldnt find lvds_clk\n");
-			lvds_clk = NULL;
-		}
-		return 0;
-	}
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	mdp_dev = platform_device_alloc("mdp", pdev->id);
-	if (!mdp_dev)
-		return -ENOMEM;
-
-	/*
-	 * link to the latest pdev
-	 */
-	mfd->pdev = mdp_dev;
-	mfd->dest = DISPLAY_LCDC;
-
-	/*
-	 * alloc panel device data
-	 */
-	if (platform_device_add_data
-	    (mdp_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		pr_err("lvds_probe: platform_device_add_data failed!\n");
-		platform_device_put(mdp_dev);
-		return -ENOMEM;
-	}
-	/*
-	 * data chain
-	 */
-	pdata = (struct msm_fb_panel_data *)mdp_dev->dev.platform_data;
-	pdata->on = lvds_on;
-	pdata->off = lvds_off;
-	pdata->next = pdev;
-
-	/*
-	 * get/set panel specific fb info
-	 */
-	mfd->panel_info = pdata->panel_info;
-
-	if (mfd->index == 0)
-		mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
-	else
-		mfd->fb_imgType = MDP_RGB_565;
-
-	fbi = mfd->fbi;
-	if (lvds_clk) {
-		fbi->var.pixclock = clk_round_rate(lvds_clk,
-			mfd->panel_info.clk_rate);
-	}
-
-	fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch;
-	fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch;
-	fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch;
-	fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch;
-	fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width;
-	fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width;
-
-	/*
-	 * set driver data
-	 */
-	platform_set_drvdata(mdp_dev, mfd);
-	/*
-	 * register in mdp driver
-	 */
-	rc = platform_device_add(mdp_dev);
-	if (rc)
-		goto lvds_probe_err;
-
-	pdev_list[pdev_list_cnt++] = pdev;
-
-	return 0;
-
-lvds_probe_err:
-	platform_device_put(mdp_dev);
-	return rc;
-}
-
-static int lvds_remove(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int lvds_register_driver(void)
-{
-	return platform_driver_register(&lvds_driver);
-}
-
-static int __init lvds_driver_init(void)
-{
-	return lvds_register_driver();
-}
-
-module_init(lvds_driver_init);
diff --git a/drivers/video/msm/lvds_chimei_wxga.c b/drivers/video/msm/lvds_chimei_wxga.c
deleted file mode 100644
index 181ec6a..0000000
--- a/drivers/video/msm/lvds_chimei_wxga.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "msm_fb.h"
-#include <linux/pwm.h>
-#include <linux/mfd/pm8xxx/pm8921.h>
-
-#define LVDS_CHIMEI_PWM_FREQ_HZ 300
-#define LVDS_CHIMEI_PWM_PERIOD_USEC (USEC_PER_SEC / LVDS_CHIMEI_PWM_FREQ_HZ)
-#define LVDS_CHIMEI_PWM_LEVEL 255
-#define LVDS_CHIMEI_PWM_DUTY_LEVEL \
-	(LVDS_CHIMEI_PWM_PERIOD_USEC / LVDS_CHIMEI_PWM_LEVEL)
-
-
-static struct lvds_panel_platform_data *cm_pdata;
-static struct platform_device *cm_fbpdev;
-static struct pwm_device *bl_lpm;
-
-static int lvds_chimei_panel_on(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int lvds_chimei_panel_off(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static void lvds_chimei_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int ret;
-
-	pr_debug("%s: back light level %d\n", __func__, mfd->bl_level);
-
-	if (bl_lpm) {
-		ret = pwm_config(bl_lpm, LVDS_CHIMEI_PWM_DUTY_LEVEL *
-			mfd->bl_level, LVDS_CHIMEI_PWM_PERIOD_USEC);
-		if (ret) {
-			pr_err("pwm_config on lpm failed %d\n", ret);
-			return;
-		}
-		if (mfd->bl_level) {
-			ret = pwm_enable(bl_lpm);
-			if (ret)
-				pr_err("pwm enable/disable on lpm failed"
-					"for bl %d\n",	mfd->bl_level);
-		} else {
-			pwm_disable(bl_lpm);
-		}
-	}
-}
-
-static int __devinit lvds_chimei_probe(struct platform_device *pdev)
-{
-	int rc = 0;
-
-	if (pdev->id == 0) {
-		cm_pdata = pdev->dev.platform_data;
-		if (cm_pdata == NULL)
-			pr_err("%s: no PWM gpio specified\n", __func__);
-		return 0;
-	}
-
-	if (cm_pdata != NULL)
-		bl_lpm = pwm_request(cm_pdata->gpio[0],
-			"backlight");
-
-	if (bl_lpm == NULL || IS_ERR(bl_lpm)) {
-		pr_err("%s pwm_request() failed\n", __func__);
-		bl_lpm = NULL;
-	}
-	pr_debug("bl_lpm = %p lpm = %d\n", bl_lpm,
-		cm_pdata->gpio[0]);
-
-	cm_fbpdev = msm_fb_add_device(pdev);
-	if (!cm_fbpdev) {
-		dev_err(&pdev->dev, "failed to add msm_fb device\n");
-		rc = -ENODEV;
-		goto probe_exit;
-	}
-
-probe_exit:
-	return rc;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = lvds_chimei_probe,
-	.driver = {
-		.name   = "lvds_chimei_wxga",
-	},
-};
-
-static struct msm_fb_panel_data lvds_chimei_panel_data = {
-	.on = lvds_chimei_panel_on,
-	.off = lvds_chimei_panel_off,
-	.set_backlight = lvds_chimei_set_backlight,
-};
-
-static struct platform_device this_device = {
-	.name   = "lvds_chimei_wxga",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &lvds_chimei_panel_data,
-	}
-};
-
-static int __init lvds_chimei_wxga_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client("lvds_chimei_wxga"))
-		return 0;
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &lvds_chimei_panel_data.panel_info;
-	pinfo->xres = 1366;
-	pinfo->yres = 768;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LVDS_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 79400000;
-	pinfo->bl_max = 255;
-	pinfo->bl_min = 1;
-
-	/*
-	 * this panel is operated by de,
-	 * vsycn and hsync are ignored
-	 */
-	pinfo->lcdc.h_back_porch = 0;
-	pinfo->lcdc.h_front_porch = 194;
-	pinfo->lcdc.h_pulse_width = 40;
-	pinfo->lcdc.v_back_porch = 0;
-	pinfo->lcdc.v_front_porch = 38;
-	pinfo->lcdc.v_pulse_width = 20;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-	pinfo->lvds.channel_mode = LVDS_SINGLE_CHANNEL_MODE;
-
-	/* Set border color, padding only for reducing active display region */
-	pinfo->lcdc.border_clr = 0x0;
-	pinfo->lcdc.xres_pad = 0;
-	pinfo->lcdc.yres_pad = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret)
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lvds_chimei_wxga_init);
diff --git a/drivers/video/msm/lvds_frc_fhd.c b/drivers/video/msm/lvds_frc_fhd.c
deleted file mode 100644
index 36d26c5..0000000
--- a/drivers/video/msm/lvds_frc_fhd.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <mach/gpio.h>
-#include "msm_fb.h"
-
-static struct lvds_panel_platform_data *frc_pdata;
-static struct platform_device *frc_fbpdev;
-static int gpio_update;		/* 268 */
-static int gpio_reset;	/* 269 */
-static int gpio_pwr;		/* 270 */
-
-static int lvds_frc_panel_on(struct platform_device *pdev)
-{
-	int ret;
-
-	ret = gpio_request(gpio_pwr, "frc_pwr");
-	if (ret) {
-		pr_err("%s: gpio_pwr=%d, gpio_request failed\n",
-			__func__, gpio_pwr);
-		goto panel_on_exit;
-	}
-	ret = gpio_request(gpio_update, "frc_update");
-	if (ret) {
-		pr_err("%s: gpio_update=%d, gpio_request failed\n",
-			__func__, gpio_update);
-		goto panel_on_exit1;
-	}
-	ret = gpio_request(gpio_reset, "frc_reset");
-	if (ret) {
-		pr_err("%s: gpio_reset=%d, gpio_request failed\n",
-			__func__, gpio_reset);
-		goto panel_on_exit2;
-	}
-
-	gpio_direction_output(gpio_reset, 1);
-	gpio_direction_output(gpio_pwr, 0);
-	gpio_direction_output(gpio_update, 0);
-	usleep(1000);
-	gpio_direction_output(gpio_reset, 0);
-	usleep(1000);
-	gpio_direction_output(gpio_pwr, 1);
-	usleep(1000);
-	gpio_direction_output(gpio_update, 1);
-	usleep(1000);
-	gpio_direction_output(gpio_reset, 1);
-	usleep(1000);
-	gpio_free(gpio_reset);
-panel_on_exit2:
-	gpio_free(gpio_update);
-panel_on_exit1:
-	gpio_free(gpio_pwr);
-panel_on_exit:
-	return ret;
-}
-
-static int lvds_frc_panel_off(struct platform_device *pdev)
-{
-	int ret;
-
-	ret = gpio_request(gpio_pwr, "frc_pwr");
-	if (ret) {
-		pr_err("%s: gpio_pwr=%d, gpio_request failed\n",
-			__func__, gpio_pwr);
-		goto panel_off_exit;
-	}
-	ret = gpio_request(gpio_update, "frc_update");
-	if (ret) {
-		pr_err("%s: gpio_update=%d, gpio_request failed\n",
-			__func__, gpio_update);
-		goto panel_off_exit1;
-	}
-	ret = gpio_request(gpio_reset, "frc_reset");
-	if (ret) {
-		pr_err("%s: gpio_reset=%d, gpio_request failed\n",
-			__func__, gpio_reset);
-		goto panel_off_exit2;
-	}
-	gpio_direction_output(gpio_reset, 0);
-	usleep(1000);
-	gpio_direction_output(gpio_update, 0);
-	usleep(1000);
-	gpio_direction_output(gpio_pwr, 0);
-	usleep(1000);
-	gpio_free(gpio_reset);
-panel_off_exit2:
-	gpio_free(gpio_update);
-panel_off_exit1:
-	gpio_free(gpio_pwr);
-panel_off_exit:
-	return ret;
-}
-
-static int __devinit lvds_frc_probe(struct platform_device *pdev)
-{
-	int rc = 0;
-
-	if (pdev->id == 0) {
-		frc_pdata = pdev->dev.platform_data;
-		if (frc_pdata != NULL) {
-			gpio_update = frc_pdata->gpio[0];
-			gpio_reset = frc_pdata->gpio[1];
-			gpio_pwr = frc_pdata->gpio[2];
-			pr_info("%s: power=%d update=%d reset=%d\n",
-				__func__, gpio_pwr, gpio_update, gpio_reset);
-		}
-		return 0;
-	}
-
-	frc_fbpdev = msm_fb_add_device(pdev);
-	if (!frc_fbpdev) {
-		dev_err(&pdev->dev, "failed to add msm_fb device\n");
-		rc = -ENODEV;
-		goto probe_exit;
-	}
-
-probe_exit:
-	return rc;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = lvds_frc_probe,
-	.driver = {
-		.name   = "lvds_frc_fhd",
-	},
-};
-
-static struct msm_fb_panel_data lvds_frc_panel_data = {
-	.on = lvds_frc_panel_on,
-	.off = lvds_frc_panel_off,
-};
-
-static struct platform_device this_device = {
-	.name   = "lvds_frc_fhd",
-	.id	= 1,
-	.dev	= {
-		.platform_data = &lvds_frc_panel_data,
-	}
-};
-
-static int __init lvds_frc_fhd_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	if (msm_fb_detect_client("lvds_frc_fhd"))
-		return 0;
-
-	ret = platform_driver_register(&this_driver);
-	if (ret)
-		return ret;
-
-	pinfo = &lvds_frc_panel_data.panel_info;
-	pinfo->xres = 1920;
-	pinfo->yres = 1080;
-	MSM_FB_SINGLE_MODE_PANEL(pinfo);
-	pinfo->type = LVDS_PANEL;
-	pinfo->pdest = DISPLAY_1;
-	pinfo->wait_cycle = 0;
-	pinfo->bpp = 24;
-	pinfo->fb_num = 2;
-	pinfo->clk_rate = 74250000;
-	pinfo->bl_max = 255;
-	pinfo->bl_min = 1;
-
-	/*
-	 * use hdmi 1080p60 setting, for dual channel mode,
-	 * horizontal length is half.
-	 */
-	pinfo->lcdc.h_back_porch = 148/2;
-	pinfo->lcdc.h_front_porch = 88/2;
-	pinfo->lcdc.h_pulse_width = 44/2;
-	pinfo->lcdc.v_back_porch = 36;
-	pinfo->lcdc.v_front_porch = 4;
-	pinfo->lcdc.v_pulse_width = 5;
-	pinfo->lcdc.underflow_clr = 0xff;
-	pinfo->lcdc.hsync_skew = 0;
-	pinfo->lvds.channel_mode = LVDS_DUAL_CHANNEL_MODE;
-	pinfo->lcdc.is_sync_active_high = TRUE;
-
-	/* Set border color, padding only for reducing active display region */
-	pinfo->lcdc.border_clr = 0x0;
-	pinfo->lcdc.xres_pad = 0;
-	pinfo->lcdc.yres_pad = 0;
-
-	ret = platform_device_register(&this_device);
-	if (ret)
-		platform_driver_unregister(&this_driver);
-
-	return ret;
-}
-
-module_init(lvds_frc_fhd_init);
diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c
deleted file mode 100644
index 796f67f..0000000
--- a/drivers/video/msm/mddi.c
+++ /dev/null
@@ -1,586 +0,0 @@
-/*
- * MSM MDDI Transport
- *
- * Copyright (C) 2007 Google Incorporated
- * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include "msm_fb.h"
-#include "mddihosti.h"
-#include "mddihost.h"
-#include <mach/gpio.h>
-#include <mach/clk.h>
-
-static int mddi_probe(struct platform_device *pdev);
-static int mddi_remove(struct platform_device *pdev);
-
-static int mddi_off(struct platform_device *pdev);
-static int mddi_on(struct platform_device *pdev);
-
-#ifdef CONFIG_PM
-static int mddi_suspend(struct platform_device *pdev, pm_message_t state);
-static int mddi_resume(struct platform_device *pdev);
-#endif
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void mddi_early_suspend(struct early_suspend *h);
-static void mddi_early_resume(struct early_suspend *h);
-#endif
-
-static void pmdh_clk_disable(void);
-static void pmdh_clk_enable(void);
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-static struct clk *mddi_clk;
-static struct clk *mddi_pclk;
-static struct mddi_platform_data *mddi_pdata;
-
-DEFINE_MUTEX(mddi_timer_lock);
-
-static int mddi_runtime_suspend(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: suspending...\n");
-	return 0;
-}
-
-static int mddi_runtime_resume(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: resuming...\n");
-	return 0;
-}
-
-static int mddi_runtime_idle(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: idling...\n");
-	return 0;
-}
-
-static struct dev_pm_ops mddi_dev_pm_ops = {
-	.runtime_suspend = mddi_runtime_suspend,
-	.runtime_resume = mddi_runtime_resume,
-	.runtime_idle = mddi_runtime_idle,
-};
-
-static int pmdh_clk_status;
-int irq_enabled;
-unsigned char mddi_timer_shutdown_flag;
-
-static struct platform_driver mddi_driver = {
-	.probe = mddi_probe,
-	.remove = mddi_remove,
-#ifndef CONFIG_HAS_EARLYSUSPEND
-#ifdef CONFIG_PM
-	.suspend = mddi_suspend,
-	.resume = mddi_resume,
-#endif
-#endif
-	.shutdown = NULL,
-	.driver = {
-		.name = "mddi",
-		.pm = &mddi_dev_pm_ops,
-		   },
-};
-
-extern int int_mddi_pri_flag;
-DEFINE_MUTEX(pmdh_clk_lock);
-
-int pmdh_clk_func(int value)
-{
-	int ret = 0;
-
-	switch (value) {
-	case 0:
-		pmdh_clk_disable();
-		break;
-	case 1:
-		pmdh_clk_enable();
-		break;
-	case 2:
-	default:
-		mutex_lock(&pmdh_clk_lock);
-		ret = pmdh_clk_status;
-		mutex_unlock(&pmdh_clk_lock);
-		break;
-	}
-	return ret;
-}
-
-static void pmdh_clk_disable()
-{
-	mutex_lock(&pmdh_clk_lock);
-	if (pmdh_clk_status == 0) {
-		mutex_unlock(&pmdh_clk_lock);
-		return;
-	}
-
-	if (mddi_host_timer.function) {
-		mutex_lock(&mddi_timer_lock);
-		mddi_timer_shutdown_flag = 1;
-		mutex_unlock(&mddi_timer_lock);
-		del_timer_sync(&mddi_host_timer);
-		mutex_lock(&mddi_timer_lock);
-		mddi_timer_shutdown_flag = 0;
-		mutex_unlock(&mddi_timer_lock);
-	}
-	if (int_mddi_pri_flag && irq_enabled) {
-		disable_irq(INT_MDDI_PRI);
-		irq_enabled = 0;
-	}
-
-	if (mddi_clk) {
-		clk_disable_unprepare(mddi_clk);
-		pmdh_clk_status = 0;
-	}
-	if (mddi_pclk)
-		clk_disable_unprepare(mddi_pclk);
-	mutex_unlock(&pmdh_clk_lock);
-}
-
-static void pmdh_clk_enable()
-{
-	mutex_lock(&pmdh_clk_lock);
-	if (pmdh_clk_status == 1) {
-		mutex_unlock(&pmdh_clk_lock);
-		return;
-	}
-
-	if (mddi_clk) {
-		clk_prepare_enable(mddi_clk);
-		pmdh_clk_status = 1;
-	}
-	if (mddi_pclk)
-		clk_prepare_enable(mddi_pclk);
-
-	if (int_mddi_pri_flag && !irq_enabled) {
-		enable_irq(INT_MDDI_PRI);
-		irq_enabled = 1;
-	}
-
-	if (mddi_host_timer.function)
-		mddi_host_timer_service(0);
-
-	mutex_unlock(&pmdh_clk_lock);
-}
-
-static int mddi_off(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	boolean dma_pending, dma_update_flag;
-	int ret, i;
-
-	mfd = platform_get_drvdata(pdev);
-
-	for (i = 0; i < 6; i++) {
-		dma_update_flag = mfd->dma_update_flag;
-		dma_pending = mfd->dma->busy;
-		if (dma_update_flag && !dma_pending)
-			break;
-		msleep(5);
-	}
-
-	pmdh_clk_enable();
-	ret = panel_next_off(pdev);
-	pmdh_clk_disable();
-
-	if (mddi_pdata && mddi_pdata->mddi_power_save)
-		mddi_pdata->mddi_power_save(0);
-#ifndef CONFIG_MSM_BUS_SCALING
-	if (mfd->ebi1_clk)
-		clk_disable_unprepare(mfd->ebi1_clk);
-#endif
-	pm_runtime_put(&pdev->dev);
-	return ret;
-}
-
-static int mddi_on(struct platform_device *pdev)
-{
-	int ret = 0;
-	u32 clk_rate;
-	struct msm_fb_data_type *mfd;
-#ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	u32 stat_reg;
-#endif
-
-	mfd = platform_get_drvdata(pdev);
-	pm_runtime_get(&pdev->dev);
-	if (mddi_pdata && mddi_pdata->mddi_power_save)
-		mddi_pdata->mddi_power_save(1);
-
-	pmdh_clk_enable();
-#ifdef ENABLE_FWD_LINK_SKEW_CALIBRATION
-	if (mddi_client_type < 2) {
-		/* For skew calibration, clock should be less than 50MHz */
-		clk_rate = clk_round_rate(mddi_clk, 49000000);
-		if (!clk_set_rate(mddi_clk, clk_rate)) {
-			stat_reg = mddi_host_reg_in(STAT);
-			printk(KERN_DEBUG "\n stat_reg = 0x%x", stat_reg);
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
-			if (stat_reg & (0x1 << 4))
-				mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-
-			mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD);
-			mddi_send_fw_link_skew_cal(host_idx);
-			mddi_host_reg_out(CMD, MDDI_CMD_SEND_RTD);
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
-		} else {
-			printk(KERN_ERR "%s: clk_set_rate failed\n",
-				__func__);
-		}
-	}
-#endif
-
-	clk_rate = mfd->fbi->var.pixclock;
-	clk_rate = min(clk_rate, mfd->panel_info.clk_max);
-
-	if (mddi_pdata &&
-	    mddi_pdata->mddi_sel_clk &&
-	    mddi_pdata->mddi_sel_clk(&clk_rate))
-			printk(KERN_ERR
-			  "%s: can't select mddi io clk targate rate = %d\n",
-			  __func__, clk_rate);
-
-	clk_rate = clk_round_rate(mddi_clk, clk_rate);
-	if (clk_set_rate(mddi_clk, clk_rate) < 0)
-		printk(KERN_ERR "%s: clk_set_rate failed\n",
-			__func__);
-
-#ifndef CONFIG_MSM_BUS_SCALING
-	if (mfd->ebi1_clk)
-		clk_prepare_enable(mfd->ebi1_clk);
-#endif
-	ret = panel_next_on(pdev);
-
-	return ret;
-}
-
-static int mddi_resource_initialized;
-
-static int mddi_probe(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	struct platform_device *mdp_dev = NULL;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-	resource_size_t size ;
-	u32 clk_rate;
-	unsigned long rate;
-	int ret;
-	struct clk *ebi1_clk = NULL;
-
-	if ((pdev->id == 0) && (pdev->num_resources >= 0)) {
-		mddi_pdata = pdev->dev.platform_data;
-		pmdh_clk_status = 0;
-
-		mddi_clk = clk_get(&pdev->dev, "core_clk");
-		if (IS_ERR(mddi_clk)) {
-			pr_err("can't find mddi_clk\n");
-			return PTR_ERR(mddi_clk);
-		}
-		rate = clk_round_rate(mddi_clk, 49000000);
-		ret = clk_set_rate(mddi_clk, rate);
-		if (ret)
-			pr_err("Can't set mddi_clk min rate to %lu\n",
-									rate);
-
-		pr_info("mddi_clk init rate is %lu\n",
-			clk_get_rate(mddi_clk));
-		mddi_pclk = clk_get(&pdev->dev, "iface_clk");
-		if (IS_ERR(mddi_pclk))
-			mddi_pclk = NULL;
-		pmdh_clk_enable();
-
-#ifndef CONFIG_MSM_BUS_SCALING
-		ebi1_clk = clk_get(&pdev->dev, "mem_clk");
-		if (IS_ERR(ebi1_clk))
-			return PTR_ERR(ebi1_clk);
-		clk_set_rate(ebi1_clk, 65000000);
-#endif
-
-		size =  resource_size(&pdev->resource[0]);
-		msm_pmdh_base =  ioremap(pdev->resource[0].start, size);
-
-		MSM_FB_INFO("primary mddi base phy_addr = 0x%x virt = 0x%x\n",
-				pdev->resource[0].start, (int) msm_pmdh_base);
-
-		if (unlikely(!msm_pmdh_base))
-			return -ENOMEM;
-
-		if (mddi_pdata && mddi_pdata->mddi_power_save)
-			mddi_pdata->mddi_power_save(1);
-
-		mddi_resource_initialized = 1;
-		return 0;
-	}
-
-	if (!mddi_resource_initialized)
-		return -EPERM;
-
-	mfd = platform_get_drvdata(pdev);
-	mfd->ebi1_clk = ebi1_clk;
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	mdp_dev = platform_device_alloc("mdp", pdev->id);
-	if (!mdp_dev)
-		return -ENOMEM;
-
-	/*
-	 * link to the latest pdev
-	 */
-	mfd->pdev = mdp_dev;
-	mfd->dest = DISPLAY_LCD;
-
-	/*
-	 * alloc panel device data
-	 */
-	if (platform_device_add_data
-	    (mdp_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		printk(KERN_ERR "mddi_probe: platform_device_add_data failed!\n");
-		platform_device_put(mdp_dev);
-		return -ENOMEM;
-	}
-	/*
-	 * data chain
-	 */
-	pdata = mdp_dev->dev.platform_data;
-	pdata->on = mddi_on;
-	pdata->off = mddi_off;
-	pdata->next = pdev;
-	pdata->clk_func = pmdh_clk_func;
-	/*
-	 * get/set panel specific fb info
-	 */
-	mfd->panel_info = pdata->panel_info;
-
-	if (mfd->index == 0)
-		mfd->fb_imgType = MSMFB_DEFAULT_TYPE;
-	else
-		mfd->fb_imgType = MDP_RGB_565;
-
-	clk_rate = mfd->panel_info.clk_max;
-	if (mddi_pdata &&
-	    mddi_pdata->mddi_sel_clk &&
-	    mddi_pdata->mddi_sel_clk(&clk_rate))
-			printk(KERN_ERR
-			  "%s: can't select mddi io clk targate rate = %d\n",
-			  __func__, clk_rate);
-
-	if (clk_set_max_rate(mddi_clk, clk_rate) < 0)
-		printk(KERN_ERR "%s: clk_set_max_rate failed\n", __func__);
-	mfd->panel_info.clk_rate = mfd->panel_info.clk_min;
-
-	if (!mddi_client_type)
-		mddi_client_type = mfd->panel_info.lcd.rev;
-	else if (!mfd->panel_info.lcd.rev)
-		printk(KERN_ERR
-		"%s: mddi client is trying to revert back to type 1	!!!\n",
-		__func__);
-
-	/*
-	 * set driver data
-	 */
-	platform_set_drvdata(mdp_dev, mfd);
-	rc = pm_runtime_set_active(&pdev->dev);
-	if (rc < 0)
-		printk(KERN_ERR "pm_runtime: fail to set active\n");
-
-	rc = 0;
-	pm_runtime_enable(&pdev->dev);
-	/*
-	 * register in mdp driver
-	 */
-	rc = platform_device_add(mdp_dev);
-	if (rc)
-		goto mddi_probe_err;
-
-	pdev_list[pdev_list_cnt++] = pdev;
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-	mfd->mddi_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
-	mfd->mddi_early_suspend.suspend = mddi_early_suspend;
-	mfd->mddi_early_suspend.resume = mddi_early_resume;
-	register_early_suspend(&mfd->mddi_early_suspend);
-#endif
-
-	return 0;
-
-mddi_probe_err:
-	platform_device_put(mdp_dev);
-	return rc;
-}
-
-static int mddi_pad_ctrl;
-static int mddi_power_locked;
-
-int mddi_client_power(unsigned int client_id)
-{
-	int ret = 0;
-	if (mddi_pdata && mddi_pdata->mddi_client_power)
-		ret = mddi_pdata->mddi_client_power(client_id);
-	return ret;
-}
-
-void mddi_disable(int lock)
-{
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-
-	if (mddi_power_locked)
-		return;
-
-	if (lock)
-		mddi_power_locked = 1;
-	pmdh_clk_enable();
-
-	mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
-	mddi_host_reg_out(PAD_CTL, 0x0);
-
-	pmdh_clk_disable();
-
-	if (mddi_pdata && mddi_pdata->mddi_power_save)
-		mddi_pdata->mddi_power_save(0);
-}
-
-#ifdef CONFIG_PM
-static int mddi_is_in_suspend;
-
-static int mddi_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	if (mddi_is_in_suspend)
-		return 0;
-
-	mddi_is_in_suspend = 1;
-
-	if (mddi_power_locked)
-		return 0;
-
-	pmdh_clk_enable();
-
-	mddi_pad_ctrl = mddi_host_reg_in(PAD_CTL);
-	mddi_host_reg_out(PAD_CTL, 0x0);
-
-	pmdh_clk_disable();
-
-	return 0;
-}
-
-static int mddi_resume(struct platform_device *pdev)
-{
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-
-	if (!mddi_is_in_suspend)
-		return 0;
-
-	mddi_is_in_suspend = 0;
-
-	if (mddi_power_locked)
-		return 0;
-
-	pmdh_clk_enable();
-
-	mddi_host_reg_out(PAD_CTL, mddi_pad_ctrl);
-
-
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void mddi_early_suspend(struct early_suspend *h)
-{
-	pm_message_t state;
-	struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
-							mddi_early_suspend);
-
-	state.event = PM_EVENT_SUSPEND;
-	mddi_suspend(mfd->pdev, state);
-}
-
-static void mddi_early_resume(struct early_suspend *h)
-{
-	struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
-							mddi_early_suspend);
-	mddi_resume(mfd->pdev);
-}
-#endif
-
-static int mddi_remove(struct platform_device *pdev)
-{
-	pm_runtime_disable(&pdev->dev);
-	if (mddi_host_timer.function) {
-		mutex_lock(&mddi_timer_lock);
-		mddi_timer_shutdown_flag = 1;
-		mutex_unlock(&mddi_timer_lock);
-		del_timer_sync(&mddi_host_timer);
-		mutex_lock(&mddi_timer_lock);
-		mddi_timer_shutdown_flag = 0;
-		mutex_unlock(&mddi_timer_lock);
-	}
-
-	iounmap(msm_pmdh_base);
-
-	return 0;
-}
-
-static int mddi_register_driver(void)
-{
-	return platform_driver_register(&mddi_driver);
-}
-
-static int __init mddi_driver_init(void)
-{
-	int ret;
-
-	ret = mddi_register_driver();
-	if (ret) {
-		pmdh_clk_disable();
-		clk_put(mddi_clk);
-		if (mddi_pclk)
-			clk_put(mddi_pclk);
-		printk(KERN_ERR "mddi_register_driver() failed!\n");
-		return ret;
-	}
-
-	mddi_init();
-
-	return ret;
-}
-
-module_init(mddi_driver_init);
diff --git a/drivers/video/msm/mddi_client_dummy.c b/drivers/video/msm/mddi_client_dummy.c
deleted file mode 100644
index ebbae87..0000000
--- a/drivers/video/msm/mddi_client_dummy.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* drivers/video/msm_fb/mddi_client_dummy.c
- *
- * Support for "dummy" mddi client devices which require no
- * special initialization code.
- *
- * Copyright (C) 2007 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-
-#include <mach/msm_fb.h>
-
-struct panel_info {
-	struct platform_device pdev;
-	struct msm_panel_data panel_data;
-};
-
-static int mddi_dummy_suspend(struct msm_panel_data *panel_data)
-{
-	return 0;
-}
-
-static int mddi_dummy_resume(struct msm_panel_data *panel_data)
-{
-	return 0;
-}
-
-static int mddi_dummy_blank(struct msm_panel_data *panel_data)
-{
-	return 0;
-}
-
-static int mddi_dummy_unblank(struct msm_panel_data *panel_data)
-{
-	return 0;
-}
-
-static int mddi_dummy_probe(struct platform_device *pdev)
-{
-	struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
-	struct panel_info *panel =
-		kzalloc(sizeof(struct panel_info), GFP_KERNEL);
-	int ret;
-	if (!panel)
-		return -ENOMEM;
-	platform_set_drvdata(pdev, panel);
-	panel->panel_data.suspend = mddi_dummy_suspend;
-	panel->panel_data.resume = mddi_dummy_resume;
-	panel->panel_data.blank = mddi_dummy_blank;
-	panel->panel_data.unblank = mddi_dummy_unblank;
-	panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES;
-	panel->pdev.name = "msm_panel";
-	panel->pdev.id = pdev->id;
-	platform_device_add_resources(&panel->pdev,
-				      client_data->fb_resource, 1);
-	panel->panel_data.fb_data = client_data->private_client_data;
-	panel->pdev.dev.platform_data = &panel->panel_data;
-	ret = platform_device_register(&panel->pdev);
-	if (ret) {
-		kfree(panel);
-		return ret;
-	}
-	return 0;
-}
-
-static int mddi_dummy_remove(struct platform_device *pdev)
-{
-	struct panel_info *panel = platform_get_drvdata(pdev);
-	kfree(panel);
-	return 0;
-}
-
-static struct platform_driver mddi_client_dummy = {
-	.probe = mddi_dummy_probe,
-	.remove = mddi_dummy_remove,
-	.driver = { .name = "mddi_c_dummy" },
-};
-
-static int __init mddi_client_dummy_init(void)
-{
-	platform_driver_register(&mddi_client_dummy);
-	return 0;
-}
-
-module_init(mddi_client_dummy_init);
-
diff --git a/drivers/video/msm/mddi_client_nt35399.c b/drivers/video/msm/mddi_client_nt35399.c
deleted file mode 100644
index eb8c701..0000000
--- a/drivers/video/msm/mddi_client_nt35399.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/* drivers/video/msm_fb/mddi_client_nt35399.c
- *
- * Support for Novatek NT35399 MDDI client of Sapphire
- *
- * Copyright (C) 2008 HTC Incorporated
- * Author: Solomon Chiu ([email protected])
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/gpio.h>
-#include <mach/msm_fb.h>
-
-static DECLARE_WAIT_QUEUE_HEAD(nt35399_vsync_wait);
-
-struct panel_info {
-	struct msm_mddi_client_data *client_data;
-	struct platform_device pdev;
-	struct msm_panel_data panel_data;
-	struct msmfb_callback *fb_callback;
-	struct work_struct panel_work;
-	struct workqueue_struct *fb_wq;
-	int nt35399_got_int;
-};
-
-static void
-nt35399_request_vsync(struct msm_panel_data *panel_data,
-		      struct msmfb_callback *callback)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	panel->fb_callback = callback;
-	if (panel->nt35399_got_int) {
-		panel->nt35399_got_int = 0;
-		client_data->activate_link(client_data); /* clears interrupt */
-	}
-}
-
-static void nt35399_wait_vsync(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	if (panel->nt35399_got_int) {
-		panel->nt35399_got_int = 0;
-		client_data->activate_link(client_data); /* clears interrupt */
-	}
-
-	if (wait_event_timeout(nt35399_vsync_wait, panel->nt35399_got_int,
-				HZ/2) == 0)
-		printk(KERN_ERR "timeout waiting for VSYNC\n");
-
-	panel->nt35399_got_int = 0;
-	/* interrupt clears when screen dma starts */
-}
-
-static int nt35399_suspend(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-	int ret;
-
-	ret = bridge_data->uninit(bridge_data, client_data);
-	if (ret) {
-		printk(KERN_INFO "mddi nt35399 client: non zero return from "
-			"uninit\n");
-		return ret;
-	}
-	client_data->suspend(client_data);
-	return 0;
-}
-
-static int nt35399_resume(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-	int ret;
-
-	client_data->resume(client_data);
-	ret = bridge_data->init(bridge_data, client_data);
-	if (ret)
-		return ret;
-	return 0;
-}
-
-static int nt35399_blank(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-
-	return bridge_data->blank(bridge_data, client_data);
-}
-
-static int nt35399_unblank(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-
-	return bridge_data->unblank(bridge_data, client_data);
-}
-
-irqreturn_t nt35399_vsync_interrupt(int irq, void *data)
-{
-	struct panel_info *panel = data;
-
-	panel->nt35399_got_int = 1;
-
-	if (panel->fb_callback) {
-		panel->fb_callback->func(panel->fb_callback);
-		panel->fb_callback = NULL;
-	}
-
-	wake_up(&nt35399_vsync_wait);
-
-	return IRQ_HANDLED;
-}
-
-static int setup_vsync(struct panel_info *panel, int init)
-{
-	int ret;
-	int gpio = 97;
-	unsigned int irq;
-
-	if (!init) {
-		ret = 0;
-		goto uninit;
-	}
-	ret = gpio_request_one(gpio, GPIOF_IN, "vsync");
-	if (ret)
-		goto err_request_gpio_failed;
-
-	ret = irq = gpio_to_irq(gpio);
-	if (ret < 0)
-		goto err_get_irq_num_failed;
-
-	ret = request_irq(irq, nt35399_vsync_interrupt, IRQF_TRIGGER_RISING,
-			  "vsync", panel);
-	if (ret)
-		goto err_request_irq_failed;
-
-	printk(KERN_INFO "vsync on gpio %d now %d\n",
-	       gpio, gpio_get_value(gpio));
-	return 0;
-
-uninit:
-	free_irq(gpio_to_irq(gpio), panel->client_data);
-err_request_irq_failed:
-err_get_irq_num_failed:
-	gpio_free(gpio);
-err_request_gpio_failed:
-	return ret;
-}
-
-static int mddi_nt35399_probe(struct platform_device *pdev)
-{
-	struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-
-	int ret;
-
-	struct panel_info *panel = kzalloc(sizeof(struct panel_info),
-					   GFP_KERNEL);
-
-	printk(KERN_DEBUG "%s: enter.\n", __func__);
-
-	if (!panel)
-		return -ENOMEM;
-	platform_set_drvdata(pdev, panel);
-
-	ret = setup_vsync(panel, 1);
-	if (ret) {
-		dev_err(&pdev->dev, "mddi_nt35399_setup_vsync failed\n");
-		return ret;
-	}
-
-	panel->client_data = client_data;
-	panel->panel_data.suspend = nt35399_suspend;
-	panel->panel_data.resume = nt35399_resume;
-	panel->panel_data.wait_vsync = nt35399_wait_vsync;
-	panel->panel_data.request_vsync = nt35399_request_vsync;
-	panel->panel_data.blank = nt35399_blank;
-	panel->panel_data.unblank = nt35399_unblank;
-	panel->panel_data.fb_data = &bridge_data->fb_data;
-	panel->panel_data.caps = 0;
-
-	panel->pdev.name = "msm_panel";
-	panel->pdev.id = pdev->id;
-	panel->pdev.resource = client_data->fb_resource;
-	panel->pdev.num_resources = 1;
-	panel->pdev.dev.platform_data = &panel->panel_data;
-
-	if (bridge_data->init)
-		bridge_data->init(bridge_data, client_data);
-
-	platform_device_register(&panel->pdev);
-
-	return 0;
-}
-
-static int mddi_nt35399_remove(struct platform_device *pdev)
-{
-	struct panel_info *panel = platform_get_drvdata(pdev);
-
-	setup_vsync(panel, 0);
-	kfree(panel);
-	return 0;
-}
-
-static struct platform_driver mddi_client_0bda_8a47 = {
-	.probe = mddi_nt35399_probe,
-	.remove = mddi_nt35399_remove,
-	.driver = { .name = "mddi_c_0bda_8a47" },
-};
-
-static int __init mddi_client_nt35399_init(void)
-{
-	return platform_driver_register(&mddi_client_0bda_8a47);
-}
-
-module_init(mddi_client_nt35399_init);
-
diff --git a/drivers/video/msm/mddi_client_toshiba.c b/drivers/video/msm/mddi_client_toshiba.c
deleted file mode 100644
index 8868781..0000000
--- a/drivers/video/msm/mddi_client_toshiba.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/* drivers/video/msm_fb/mddi_client_toshiba.c
- *
- * Support for Toshiba TC358720XBG mddi client devices which require no
- * special initialization code.
- *
- * Copyright (C) 2007 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/sched.h>
-#include <mach/msm_fb.h>
-
-
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define CMN         (LCD_CONTROL_BLOCK_BASE|0x10)
-#define INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
-#define HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define VPOS        (LCD_CONTROL_BLOCK_BASE|0xC0)
-#define MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
-#define WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
-#define WSYN_DLY    (LCD_CONTROL_BLOCK_BASE|0x58)
-#define REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
-
-#define BASE5 0x150000
-#define BASE6 0x160000
-#define BASE7 0x170000
-
-#define GPIOIEV     (BASE5 + 0x10)
-#define GPIOIE      (BASE5 + 0x14)
-#define GPIORIS     (BASE5 + 0x18)
-#define GPIOMIS     (BASE5 + 0x1C)
-#define GPIOIC      (BASE5 + 0x20)
-
-#define INTMASK     (BASE6 + 0x0C)
-#define INTMASK_VWAKEOUT (1U << 0)
-#define INTMASK_VWAKEOUT_ACTIVE_LOW (1U << 8)
-#define GPIOSEL     (BASE7 + 0x00)
-#define GPIOSEL_VWAKEINT (1U << 0)
-
-static DECLARE_WAIT_QUEUE_HEAD(toshiba_vsync_wait);
-
-struct panel_info {
-	struct msm_mddi_client_data *client_data;
-	struct platform_device pdev;
-	struct msm_panel_data panel_data;
-	struct msmfb_callback *toshiba_callback;
-	int toshiba_got_int;
-	int irq;
-};
-
-
-static void toshiba_request_vsync(struct msm_panel_data *panel_data,
-				  struct msmfb_callback *callback)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	panel->toshiba_callback = callback;
-	if (panel->toshiba_got_int) {
-		panel->toshiba_got_int = 0;
-		client_data->activate_link(client_data);
-	}
-}
-
-static void toshiba_clear_vsync(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	client_data->activate_link(client_data);
-}
-
-static void toshiba_wait_vsync(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	if (panel->toshiba_got_int) {
-		panel->toshiba_got_int = 0;
-		client_data->activate_link(client_data); /* clears interrupt */
-	}
-	if (wait_event_timeout(toshiba_vsync_wait, panel->toshiba_got_int,
-				HZ/2) == 0)
-		printk(KERN_ERR "timeout waiting for VSYNC\n");
-	panel->toshiba_got_int = 0;
-	/* interrupt clears when screen dma starts */
-}
-
-static int toshiba_suspend(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-	int ret;
-
-	ret = bridge_data->uninit(bridge_data, client_data);
-	if (ret) {
-		printk(KERN_INFO "mddi toshiba client: non zero return from "
-			"uninit\n");
-		return ret;
-	}
-	client_data->suspend(client_data);
-	return 0;
-}
-
-static int toshiba_resume(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-	int ret;
-
-	client_data->resume(client_data);
-	ret = bridge_data->init(bridge_data, client_data);
-	if (ret)
-		return ret;
-	return 0;
-}
-
-static int toshiba_blank(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-
-	return bridge_data->blank(bridge_data, client_data);
-}
-
-static int toshiba_unblank(struct msm_panel_data *panel_data)
-{
-	struct panel_info *panel = container_of(panel_data, struct panel_info,
-						panel_data);
-	struct msm_mddi_client_data *client_data = panel->client_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-
-	return bridge_data->unblank(bridge_data, client_data);
-}
-
-irqreturn_t toshiba_vsync_interrupt(int irq, void *data)
-{
-	struct panel_info *panel = data;
-
-	panel->toshiba_got_int = 1;
-	if (panel->toshiba_callback) {
-		panel->toshiba_callback->func(panel->toshiba_callback);
-		panel->toshiba_callback = 0;
-	}
-	wake_up(&toshiba_vsync_wait);
-	return IRQ_HANDLED;
-}
-
-static int mddi_toshiba_probe(struct platform_device *pdev)
-{
-	int ret;
-	struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
-	struct msm_mddi_bridge_platform_data *bridge_data =
-		client_data->private_client_data;
-	struct panel_info *panel =
-		kzalloc(sizeof(struct panel_info), GFP_KERNEL);
-	if (!panel)
-		return -ENOMEM;
-	platform_set_drvdata(pdev, panel);
-
-	/* mddi_remote_write(mddi, 0, WAKEUP); */
-	client_data->remote_write(client_data, GPIOSEL_VWAKEINT, GPIOSEL);
-	client_data->remote_write(client_data, INTMASK_VWAKEOUT, INTMASK);
-
-	ret = platform_get_irq_byname(pdev, "vsync");
-	if (ret < 0)
-		goto err_plat_get_irq;
-
-	panel->irq = ret;
-	ret = request_irq(panel->irq, toshiba_vsync_interrupt,
-			  IRQF_TRIGGER_RISING, "vsync", panel);
-	if (ret) {
-		dev_err(&pdev->dev, "mddi_bridge_setup_vsync failed\n");
-		goto err_req_irq;
-	}
-
-	panel->client_data = client_data;
-	panel->panel_data.suspend = toshiba_suspend;
-	panel->panel_data.resume = toshiba_resume;
-	panel->panel_data.wait_vsync = toshiba_wait_vsync;
-	panel->panel_data.request_vsync = toshiba_request_vsync;
-	panel->panel_data.clear_vsync = toshiba_clear_vsync;
-	panel->panel_data.blank = toshiba_blank;
-	panel->panel_data.unblank = toshiba_unblank;
-	panel->panel_data.fb_data =  &bridge_data->fb_data;
-	panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES;
-
-	panel->pdev.name = "msm_panel";
-	panel->pdev.id = pdev->id;
-	panel->pdev.resource = client_data->fb_resource;
-	panel->pdev.num_resources = 1;
-	panel->pdev.dev.platform_data = &panel->panel_data;
-	bridge_data->init(bridge_data, client_data);
-	platform_device_register(&panel->pdev);
-
-	return 0;
-
-err_req_irq:
-err_plat_get_irq:
-	kfree(panel);
-	return ret;
-}
-
-static int mddi_toshiba_remove(struct platform_device *pdev)
-{
-	struct panel_info *panel = platform_get_drvdata(pdev);
-
-	platform_set_drvdata(pdev, NULL);
-	free_irq(panel->irq, panel);
-	kfree(panel);
-	return 0;
-}
-
-static struct platform_driver mddi_client_d263_0000 = {
-	.probe = mddi_toshiba_probe,
-	.remove = mddi_toshiba_remove,
-	.driver = { .name = "mddi_c_d263_0000" },
-};
-
-static int __init mddi_client_toshiba_init(void)
-{
-	platform_driver_register(&mddi_client_d263_0000);
-	return 0;
-}
-
-module_init(mddi_client_toshiba_init);
-
diff --git a/drivers/video/msm/mddi_ext.c b/drivers/video/msm/mddi_ext.c
deleted file mode 100644
index 83831b0..0000000
--- a/drivers/video/msm/mddi_ext.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <linux/clk.h>
-#include <mach/clk.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-
-#include "msm_fb.h"
-#include "mddihosti.h"
-
-static int mddi_ext_probe(struct platform_device *pdev);
-static int mddi_ext_remove(struct platform_device *pdev);
-
-static int mddi_ext_off(struct platform_device *pdev);
-static int mddi_ext_on(struct platform_device *pdev);
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-
-static int mddi_ext_suspend(struct platform_device *pdev, pm_message_t state);
-static int mddi_ext_resume(struct platform_device *pdev);
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void mddi_ext_early_suspend(struct early_suspend *h);
-static void mddi_ext_early_resume(struct early_suspend *h);
-#endif
-
-static int mddi_ext_runtime_suspend(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: suspending...\n");
-	return 0;
-}
-
-static int mddi_ext_runtime_resume(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: resuming...\n");
-	return 0;
-}
-
-static int mddi_ext_runtime_idle(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: idling...\n");
-	return 0;
-}
-static struct dev_pm_ops mddi_ext_dev_pm_ops = {
-	.runtime_suspend = mddi_ext_runtime_suspend,
-	.runtime_resume = mddi_ext_runtime_resume,
-	.runtime_idle = mddi_ext_runtime_idle,
-};
-
-static struct platform_driver mddi_ext_driver = {
-	.probe = mddi_ext_probe,
-	.remove = mddi_ext_remove,
-#ifndef CONFIG_HAS_EARLYSUSPEND
-#ifdef CONFIG_PM
-	.suspend = mddi_ext_suspend,
-	.resume = mddi_ext_resume,
-#endif
-#endif
-	.resume_early = NULL,
-	.resume = NULL,
-	.shutdown = NULL,
-	.driver = {
-		.name = "mddi_ext",
-		.pm = &mddi_ext_dev_pm_ops,
-		   },
-};
-
-static struct clk *mddi_ext_clk;
-static struct clk *mddi_ext_pclk;
-static struct mddi_platform_data *mddi_ext_pdata;
-
-extern int int_mddi_ext_flag;
-
-static int mddi_ext_off(struct platform_device *pdev)
-{
-	int ret = 0;
-
-	ret = panel_next_off(pdev);
-	mddi_host_stop_ext_display();
-	pm_runtime_put(&pdev->dev);
-	return ret;
-}
-
-static int mddi_ext_on(struct platform_device *pdev)
-{
-	int ret = 0;
-	u32 clk_rate;
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-	pm_runtime_get(&pdev->dev);
-	clk_rate = mfd->fbi->var.pixclock;
-	clk_rate = min(clk_rate, mfd->panel_info.clk_max);
-
-	if (mddi_ext_pdata &&
-	    mddi_ext_pdata->mddi_sel_clk &&
-	    mddi_ext_pdata->mddi_sel_clk(&clk_rate))
-		printk(KERN_ERR
-			  "%s: can't select mddi io clk targate rate = %d\n",
-			  __func__, clk_rate);
-
-	clk_rate = clk_round_rate(mddi_ext_clk, clk_rate);
-	if (clk_set_rate(mddi_ext_clk, clk_rate) < 0)
-		printk(KERN_ERR "%s: clk_set_rate failed\n",
-			__func__);
-
-	mddi_host_start_ext_display();
-	ret = panel_next_on(pdev);
-
-	return ret;
-}
-
-static int mddi_ext_resource_initialized;
-
-static int mddi_ext_probe(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	struct platform_device *mdp_dev = NULL;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-	resource_size_t size ;
-	u32 clk_rate;
-
-	if ((pdev->id == 0) && (pdev->num_resources >= 0)) {
-		mddi_ext_pdata = pdev->dev.platform_data;
-		mddi_ext_clk = clk_get(&pdev->dev, "core_clk");
-		if (IS_ERR(mddi_ext_clk)) {
-			pr_err("can't find emdh_clk\n");
-			return PTR_ERR(mddi_ext_clk);
-		}
-		clk_prepare_enable(mddi_ext_clk);
-
-		mddi_ext_pclk = clk_get(&pdev->dev, "iface_clk");
-		if (IS_ERR(mddi_ext_pclk))
-			mddi_ext_pclk = NULL;
-		else
-			clk_prepare_enable(mddi_ext_pclk);
-
-		size =  resource_size(&pdev->resource[0]);
-		msm_emdh_base = ioremap(pdev->resource[0].start, size);
-
-		MSM_FB_INFO("external mddi base address = 0x%x\n",
-				pdev->resource[0].start);
-
-		if (unlikely(!msm_emdh_base))
-			return -ENOMEM;
-
-		mddi_ext_resource_initialized = 1;
-		return 0;
-	}
-
-	if (!mddi_ext_resource_initialized)
-		return -EPERM;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	mdp_dev = platform_device_alloc("mdp", pdev->id);
-	if (!mdp_dev)
-		return -ENOMEM;
-
-	/*
-	 * link to the latest pdev
-	 */
-	mfd->pdev = mdp_dev;
-	mfd->dest = DISPLAY_EXT_MDDI;
-
-	/*
-	 * alloc panel device data
-	 */
-	if (platform_device_add_data
-	    (mdp_dev, pdev->dev.platform_data,
-	     sizeof(struct msm_fb_panel_data))) {
-		printk(KERN_ERR "mddi_ext_probe: platform_device_add_data failed!\n");
-		platform_device_put(mdp_dev);
-		return -ENOMEM;
-	}
-	/*
-	 * data chain
-	 */
-	pdata = mdp_dev->dev.platform_data;
-	pdata->on = mddi_ext_on;
-	pdata->off = mddi_ext_off;
-	pdata->next = pdev;
-
-	/*
-	 * get/set panel specific fb info
-	 */
-	mfd->panel_info = pdata->panel_info;
-	mfd->fb_imgType = MDP_RGB_565;
-
-	clk_rate = mfd->panel_info.clk_max;
-	if (mddi_ext_pdata &&
-	    mddi_ext_pdata->mddi_sel_clk &&
-	    mddi_ext_pdata->mddi_sel_clk(&clk_rate))
-			printk(KERN_ERR
-			  "%s: can't select mddi io clk targate rate = %d\n",
-			  __func__, clk_rate);
-
-	if (clk_set_max_rate(mddi_ext_clk, clk_rate) < 0)
-		printk(KERN_ERR "%s: clk_set_max_rate failed\n", __func__);
-	mfd->panel_info.clk_rate = mfd->panel_info.clk_min;
-
-	/*
-	 * set driver data
-	 */
-	platform_set_drvdata(mdp_dev, mfd);
-	rc = pm_runtime_set_active(&pdev->dev);
-	if (rc < 0)
-		printk(KERN_ERR "pm_runtime: fail to set active\n");
-
-	rc = 0;
-	pm_runtime_enable(&pdev->dev);
-	/*
-	 * register in mdp driver
-	 */
-	rc = platform_device_add(mdp_dev);
-	if (rc)
-		goto mddi_ext_probe_err;
-
-	pdev_list[pdev_list_cnt++] = pdev;
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-	mfd->mddi_ext_early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
-	mfd->mddi_ext_early_suspend.suspend = mddi_ext_early_suspend;
-	mfd->mddi_ext_early_suspend.resume = mddi_ext_early_resume;
-	register_early_suspend(&mfd->mddi_ext_early_suspend);
-#endif
-
-	return 0;
-
-mddi_ext_probe_err:
-	platform_device_put(mdp_dev);
-	return rc;
-}
-
-static int mddi_ext_is_in_suspend;
-
-static int mddi_ext_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	if (mddi_ext_is_in_suspend)
-		return 0;
-
-	mddi_ext_is_in_suspend = 1;
-
-	clk_disable_unprepare(mddi_ext_clk);
-	if (mddi_ext_pclk)
-		clk_disable_unprepare(mddi_ext_pclk);
-
-	disable_irq(INT_MDDI_EXT);
-
-	return 0;
-}
-
-static int mddi_ext_resume(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mddi_ext_is_in_suspend)
-		return 0;
-
-	mddi_ext_is_in_suspend = 0;
-	enable_irq(INT_MDDI_EXT);
-
-	clk_prepare_enable(mddi_ext_clk);
-	if (mddi_ext_pclk)
-		clk_prepare_enable(mddi_ext_pclk);
-
-	return 0;
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void mddi_ext_early_suspend(struct early_suspend *h)
-{
-	pm_message_t state;
-	struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
-							mddi_ext_early_suspend);
-
-	state.event = PM_EVENT_SUSPEND;
-	mddi_ext_suspend(mfd->pdev, state);
-}
-
-static void mddi_ext_early_resume(struct early_suspend *h)
-{
-	struct msm_fb_data_type *mfd = container_of(h, struct msm_fb_data_type,
-							mddi_ext_early_suspend);
-	mddi_ext_resume(mfd->pdev);
-}
-#endif
-
-static int mddi_ext_remove(struct platform_device *pdev)
-{
-	pm_runtim_disable(&pdev->dev);
-	iounmap(msm_emdh_base);
-	return 0;
-}
-
-static int mddi_ext_register_driver(void)
-{
-	return platform_driver_register(&mddi_ext_driver);
-}
-
-static int __init mddi_ext_driver_init(void)
-{
-	int ret;
-
-	ret = mddi_ext_register_driver();
-	if (ret) {
-		printk(KERN_ERR "mddi_ext_register_driver() failed!\n");
-		return ret;
-	}
-	mddi_init();
-
-	return ret;
-}
-
-module_init(mddi_ext_driver_init);
diff --git a/drivers/video/msm/mddi_ext_lcd.c b/drivers/video/msm/mddi_ext_lcd.c
deleted file mode 100644
index aa4d484..0000000
--- a/drivers/video/msm/mddi_ext_lcd.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-static int mddi_ext_lcd_on(struct platform_device *pdev);
-static int mddi_ext_lcd_off(struct platform_device *pdev);
-
-static int mddi_ext_lcd_on(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int mddi_ext_lcd_off(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int __init mddi_ext_lcd_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = mddi_ext_lcd_probe,
-	.driver = {
-		.name   = "extmddi_svga",
-	},
-};
-
-static struct msm_fb_panel_data mddi_ext_lcd_panel_data = {
-	.panel_info.xres = 800,
-	.panel_info.yres = 600,
-	.panel_info.mode2_xres = 0;
-	.panel_info.mode2_yres = 0;
-	.panel_info.mode2_bpp = 0;
-	.panel_info.type = EXT_MDDI_PANEL,
-	.panel_info.pdest = DISPLAY_1,
-	.panel_info.wait_cycle = 0,
-	.panel_info.bpp = 18,
-	.panel_info.fb_num = 2,
-	.panel_info.clk_rate = 122880000,
-	.panel_info.clk_min  = 120000000,
-	.panel_info.clk_max  = 125000000,
-	.on = mddi_ext_lcd_on,
-	.off = mddi_ext_lcd_off,
-};
-
-static struct platform_device this_device = {
-	.name   = "extmddi_svga",
-	.id	= 0,
-	.dev	= {
-		.platform_data = &mddi_ext_lcd_panel_data,
-	}
-};
-
-static int __init mddi_ext_lcd_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &mddi_ext_lcd_panel_data.panel_info;
-		pinfo->lcd.vsync_enable = FALSE;
-		pinfo->mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-
-	return ret;
-}
-
-module_init(mddi_ext_lcd_init);
diff --git a/drivers/video/msm/mddi_hw.h b/drivers/video/msm/mddi_hw.h
deleted file mode 100644
index 47bb449..0000000
--- a/drivers/video/msm/mddi_hw.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* drivers/video/msm_fb/mddi_hw.h
- *
- * MSM MDDI Hardware Registers and Structures
- *
- * Copyright (C) 2007 QUALCOMM Incorporated
- * Copyright (C) 2007 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MDDI_HW_H_
-#define _MDDI_HW_H_
-
-#include <linux/types.h>
-
-#define MDDI_CMD                0x0000
-#define MDDI_VERSION            0x0004
-#define MDDI_PRI_PTR            0x0008
-#define MDDI_SEC_PTR            0x000c
-#define MDDI_BPS                0x0010
-#define MDDI_SPM                0x0014
-#define MDDI_INT                0x0018
-#define MDDI_INTEN              0x001c
-#define MDDI_REV_PTR            0x0020
-#define MDDI_REV_SIZE           0x0024
-#define MDDI_STAT               0x0028
-#define MDDI_REV_RATE_DIV       0x002c
-#define MDDI_REV_CRC_ERR        0x0030
-#define MDDI_TA1_LEN            0x0034
-#define MDDI_TA2_LEN            0x0038
-#define MDDI_TEST_BUS           0x003c
-#define MDDI_TEST               0x0040
-#define MDDI_REV_PKT_CNT        0x0044
-#define MDDI_DRIVE_HI           0x0048
-#define MDDI_DRIVE_LO           0x004c
-#define MDDI_DISP_WAKE          0x0050
-#define MDDI_REV_ENCAP_SZ       0x0054
-#define MDDI_RTD_VAL            0x0058
-#define MDDI_PAD_CTL            0x0068
-#define MDDI_DRIVER_START_CNT   0x006c
-#define MDDI_NEXT_PRI_PTR       0x0070
-#define MDDI_NEXT_SEC_PTR       0x0074
-#define MDDI_MISR_CTL           0x0078
-#define MDDI_MISR_DATA          0x007c
-#define MDDI_SF_CNT             0x0080
-#define MDDI_MF_CNT             0x0084
-#define MDDI_CURR_REV_PTR       0x0088
-#define MDDI_CORE_VER           0x008c
-#define MDDI_FIFO_ALLOC         0x0090
-#define MDDI_PAD_IO_CTL         0x00a0
-#define MDDI_PAD_CAL            0x00a4
-
-#define MDDI_INT_PRI_PTR_READ       0x0001
-#define MDDI_INT_SEC_PTR_READ       0x0002
-#define MDDI_INT_REV_DATA_AVAIL     0x0004
-#define MDDI_INT_DISP_REQ           0x0008
-#define MDDI_INT_PRI_UNDERFLOW      0x0010
-#define MDDI_INT_SEC_UNDERFLOW      0x0020
-#define MDDI_INT_REV_OVERFLOW       0x0040
-#define MDDI_INT_CRC_ERROR          0x0080
-#define MDDI_INT_MDDI_IN            0x0100
-#define MDDI_INT_PRI_OVERWRITE      0x0200
-#define MDDI_INT_SEC_OVERWRITE      0x0400
-#define MDDI_INT_REV_OVERWRITE      0x0800
-#define MDDI_INT_DMA_FAILURE        0x1000
-#define MDDI_INT_LINK_ACTIVE        0x2000
-#define MDDI_INT_IN_HIBERNATION     0x4000
-#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
-#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
-#define MDDI_INT_NO_CMD_PKTS_PEND   0x20000
-#define MDDI_INT_RTD_FAILURE        0x40000
-#define MDDI_INT_REV_PKT_RECEIVED   0x80000
-#define MDDI_INT_REV_PKTS_AVAIL     0x100000
-
-#define MDDI_INT_NEED_CLEAR ( \
-	MDDI_INT_REV_DATA_AVAIL | \
-	MDDI_INT_PRI_UNDERFLOW | \
-	MDDI_INT_SEC_UNDERFLOW | \
-	MDDI_INT_REV_OVERFLOW | \
-	MDDI_INT_CRC_ERROR | \
-	MDDI_INT_REV_PKT_RECEIVED)
-
-
-#define MDDI_STAT_LINK_ACTIVE        0x0001
-#define MDDI_STAT_NEW_REV_PTR        0x0002
-#define MDDI_STAT_NEW_PRI_PTR        0x0004
-#define MDDI_STAT_NEW_SEC_PTR        0x0008
-#define MDDI_STAT_IN_HIBERNATION     0x0010
-#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
-#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
-#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
-#define MDDI_STAT_PENDING_REV_ENCAP  0x0100
-#define MDDI_STAT_PENDING_POWERDOWN  0x0200
-#define MDDI_STAT_RTD_MEAS_FAIL      0x0800
-#define MDDI_STAT_CLIENT_WAKEUP_REQ  0x1000
-
-
-#define MDDI_CMD_POWERDOWN           0x0100
-#define MDDI_CMD_POWERUP             0x0200
-#define MDDI_CMD_HIBERNATE           0x0300
-#define MDDI_CMD_RESET               0x0400
-#define MDDI_CMD_DISP_IGNORE         0x0501
-#define MDDI_CMD_DISP_LISTEN         0x0500
-#define MDDI_CMD_SEND_REV_ENCAP      0x0600
-#define MDDI_CMD_GET_CLIENT_CAP      0x0601
-#define MDDI_CMD_GET_CLIENT_STATUS   0x0602
-#define MDDI_CMD_SEND_RTD            0x0700
-#define MDDI_CMD_LINK_ACTIVE         0x0900
-#define MDDI_CMD_PERIODIC_REV_ENCAP  0x0A00
-#define MDDI_CMD_FORCE_NEW_REV_PTR   0x0C00
-
-
-
-#define MDDI_VIDEO_REV_PKT_SIZE              0x40
-#define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE  0x60
-#define MDDI_MAX_REV_PKT_SIZE                0x60
-
-/* #define MDDI_REV_BUFFER_SIZE 128 */
-#define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
-
-/* MDP sends 256 pixel packets, so lower value hibernates more without
- * significantly increasing latency of waiting for next subframe */
-#define MDDI_HOST_BYTES_PER_SUBFRAME  0x3C00
-
-#if defined(CONFIG_MSM_MDP31) || defined(CONFIG_MSM_MDP40)
-#define MDDI_HOST_TA2_LEN       0x001a
-#define MDDI_HOST_REV_RATE_DIV  0x0004
-#else
-#define MDDI_HOST_TA2_LEN       0x000c
-#define MDDI_HOST_REV_RATE_DIV  0x0002
-#endif
-
-
-struct __attribute__((packed)) mddi_rev_packet {
-	uint16_t length;
-	uint16_t type;
-	uint16_t client_id;
-};
-
-struct __attribute__((packed)) mddi_client_status {
-	uint16_t length;
-	uint16_t type;
-	uint16_t client_id;
-	uint16_t reverse_link_request;  /* bytes needed in rev encap message */
-	uint8_t  crc_error_count;
-	uint8_t  capability_change;
-	uint16_t graphics_busy_flags;
-	uint16_t crc16;
-};
-
-struct __attribute__((packed)) mddi_client_caps {
-	uint16_t length; /* length, exclusive of this field */
-	uint16_t type; /* 66 */
-	uint16_t client_id;
-
-	uint16_t Protocol_Version;
-	uint16_t Minimum_Protocol_Version;
-	uint16_t Data_Rate_Capability;
-	uint8_t  Interface_Type_Capability;
-	uint8_t  Number_of_Alt_Displays;
-	uint16_t PostCal_Data_Rate;
-	uint16_t Bitmap_Width;
-	uint16_t Bitmap_Height;
-	uint16_t Display_Window_Width;
-	uint16_t Display_Window_Height;
-	uint32_t Color_Map_Size;
-	uint16_t Color_Map_RGB_Width;
-	uint16_t RGB_Capability;
-	uint8_t  Monochrome_Capability;
-	uint8_t  Reserved_1;
-	uint16_t Y_Cb_Cr_Capability;
-	uint16_t Bayer_Capability;
-	uint16_t Alpha_Cursor_Image_Planes;
-	uint32_t Client_Feature_Capability_Indicators;
-	uint8_t  Maximum_Video_Frame_Rate_Capability;
-	uint8_t  Minimum_Video_Frame_Rate_Capability;
-	uint16_t Minimum_Sub_frame_Rate;
-	uint16_t Audio_Buffer_Depth;
-	uint16_t Audio_Channel_Capability;
-	uint16_t Audio_Sample_Rate_Capability;
-	uint8_t  Audio_Sample_Resolution;
-	uint8_t  Mic_Audio_Sample_Resolution;
-	uint16_t Mic_Sample_Rate_Capability;
-	uint8_t  Keyboard_Data_Format;
-	uint8_t  pointing_device_data_format;
-	uint16_t content_protection_type;
-	uint16_t Mfr_Name;
-	uint16_t Product_Code;
-	uint16_t Reserved_3;
-	uint32_t Serial_Number;
-	uint8_t  Week_of_Manufacture;
-	uint8_t  Year_of_Manufacture;
-
-	uint16_t crc16;
-} mddi_client_capability_type;
-
-
-struct __attribute__((packed)) mddi_video_stream {
-	uint16_t length;
-	uint16_t type; /* 16 */
-	uint16_t client_id; /* 0 */
-
-	uint16_t video_data_format_descriptor;
-/* format of each pixel in the Pixel Data in the present stream in the
- * present packet.
- * If bits [15:13] = 000 monochrome
- * If bits [15:13] = 001 color pixels (palette).
- * If bits [15:13] = 010 color pixels in raw RGB
- * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
- * If bits [15:13] = 100 Bayer pixels
- */
-
-	uint16_t pixel_data_attributes;
-/* interpreted as follows:
- * Bits [1:0] = 11  pixel data is displayed to both eyes
- * Bits [1:0] = 10  pixel data is routed to the left eye only.
- * Bits [1:0] = 01  pixel data is routed to the right eye only.
- * Bits [1:0] = 00  pixel data is routed to the alternate display.
- * Bit 2 is 0  Pixel Data is in the standard progressive format.
- * Bit 2 is 1  Pixel Data is in interlace format.
- * Bit 3 is 0  Pixel Data is in the standard progressive format.
- * Bit 3 is 1  Pixel Data is in alternate pixel format.
- * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
- * Bit 4 is 1  Pixel Data is to or from the camera.
- * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
- * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
- *             X Start, and Y Start parameters are not defined and
- *             shall be ignored by the client.
- * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
- * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
- * Bits [7:6] = 11  Pixel data is written to all image buffers.
- * Bits [7:6] = 10  Invalid. Reserved for future use.
- * Bits 8 through 11 alternate display number.
- * Bits 12 through 14 are reserved for future use and shall be set to zero.
- * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
- */
-
-	uint16_t x_left_edge;
-	uint16_t y_top_edge;
-	/* X,Y coordinate of the top left edge of the screen window */
-
-	uint16_t x_right_edge;
-	uint16_t y_bottom_edge;
-	/* X,Y coordinate of the bottom right edge of the window being
-	 * updated. */
-
-	uint16_t x_start;
-	uint16_t y_start;
-	/* (X Start, Y Start) is the first pixel in the Pixel Data field
-	 * below. */
-
-	uint16_t pixel_count;
-	/* number of pixels in the Pixel Data field below. */
-
-	uint16_t parameter_CRC;
-	/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
-
-	uint16_t reserved;
-	/* 16-bit variable to make structure align on 4 byte boundary */
-};
-
-#define TYPE_VIDEO_STREAM      16
-#define TYPE_CLIENT_CAPS       66
-#define TYPE_REGISTER_ACCESS   146
-#define TYPE_CLIENT_STATUS     70
-
-struct __attribute__((packed)) mddi_register_access {
-	uint16_t length;
-	uint16_t type; /* 146 */
-	uint16_t client_id;
-
-	uint16_t read_write_info;
-	/* Bits 13:0  a 14-bit unsigned integer that specifies the number of
-	 *            32-bit Register Data List items to be transferred in the
-	 *            Register Data List field.
-	 * Bits[15:14] = 00  Write to register(s);
-	 * Bits[15:14] = 10  Read from register(s);
-	 * Bits[15:14] = 11  Response to a Read.
-	 * Bits[15:14] = 01  this value is reserved for future use. */
-#define MDDI_WRITE     (0 << 14)
-#define MDDI_READ      (2 << 14)
-#define MDDI_READ_RESP (3 << 14)
-
-	uint32_t register_address;
-	/* the register address that is to be written to or read from. */
-
-	uint16_t crc16;
-
-	uint32_t register_data_list;
-	/* list of 4-byte register data values for/from client registers */
-};
-
-struct __attribute__((packed)) mddi_llentry {
-	uint16_t flags;
-	uint16_t header_count;
-	uint16_t data_count;
-	dma_addr_t data; /* 32 bit */
-	struct mddi_llentry *next;
-	uint16_t reserved;
-	union {
-		struct mddi_video_stream v;
-		struct mddi_register_access r;
-		uint32_t _[12];
-	} u;
-};
-
-#endif
diff --git a/drivers/video/msm/mddi_orise.c b/drivers/video/msm/mddi_orise.c
deleted file mode 100644
index bf9f1fa..0000000
--- a/drivers/video/msm/mddi_orise.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* Copyright (c) 2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-#define MDDI_ORISE_1_2 1
-#define write_client_reg(__X, __Y, __Z) {\
-	mddi_queue_register_write(__X, __Y, TRUE, 0);\
-}
-
-static int mddi_orise_lcd_on(struct platform_device *pdev);
-static int mddi_orise_lcd_off(struct platform_device *pdev);
-static int __init mddi_orise_probe(struct platform_device *pdev);
-static int __init mddi_orise_init(void);
-
-/* function used to turn on the display */
-static void mddi_orise_prim_lcd_init(void)
-{
-	write_client_reg(0x00110000, 0, TRUE);
-	mddi_wait(150);
-	write_client_reg(0x00290000, 0, TRUE);
-}
-
-static struct platform_driver this_driver = {
-	.driver = {
-		.name   = "mddi_orise",
-	},
-};
-
-static struct msm_fb_panel_data mddi_orise_panel_data = {
-	.on = mddi_orise_lcd_on,
-	.off = mddi_orise_lcd_off,
-};
-
-static struct platform_device this_device = {
-	.name	= "mddi_orise",
-	.id	= MDDI_ORISE_1_2,
-	.dev	= {
-		.platform_data = &mddi_orise_panel_data,
-	}
-};
-
-static int mddi_orise_lcd_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	mfd = platform_get_drvdata(pdev);
-	if (!mfd)
-		return -ENODEV;
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	mddi_orise_prim_lcd_init();
-
-	return 0;
-}
-
-static int mddi_orise_lcd_off(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int __init mddi_orise_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-static int __init mddi_orise_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	u32 id;
-	ret = msm_fb_detect_client("mddi_orise");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret) {
-		id = mddi_get_client_id();
-		if (((id >> 16) != 0xbe8d) || ((id & 0xffff) != 0x8031))
-			return 0;
-	}
-#endif
-	ret = platform_driver_probe(&this_driver, mddi_orise_probe);
-	if (!ret) {
-		pinfo = &mddi_orise_panel_data.panel_info;
-		pinfo->xres = 480;
-		pinfo->yres = 800;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = MDDI_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->mddi.is_type1 = TRUE;
-		pinfo->mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-		pinfo->wait_cycle = 0;
-		pinfo->bpp = 18;
-		pinfo->fb_num = 2;
-		pinfo->clk_rate = 192000000;
-		pinfo->clk_min = 192000000;
-		pinfo->clk_max = 192000000;
-		pinfo->lcd.rev = 2;
-		pinfo->lcd.vsync_enable = FALSE;
-		pinfo->lcd.refx100 = 6050;
-		pinfo->lcd.v_back_porch = 2;
-		pinfo->lcd.v_front_porch = 2;
-		pinfo->lcd.v_pulse_width = 105;
-		pinfo->lcd.hw_vsync_mode = TRUE;
-		pinfo->lcd.vsync_notifier_period = 0;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-	return ret;
-}
-module_init(mddi_orise_init);
diff --git a/drivers/video/msm/mddi_prism.c b/drivers/video/msm/mddi_prism.c
deleted file mode 100644
index c2fa8b9..0000000
--- a/drivers/video/msm/mddi_prism.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright (c) 2008-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-static int prism_lcd_on(struct platform_device *pdev);
-static int prism_lcd_off(struct platform_device *pdev);
-
-static int prism_lcd_on(struct platform_device *pdev)
-{
-	/* Set the MDP pixel data attributes for Primary Display */
-	mddi_host_write_pix_attr_reg(0x00C3);
-
-	return 0;
-}
-
-static int prism_lcd_off(struct platform_device *pdev)
-{
-	return 0;
-}
-
-static int __devinit prism_probe(struct platform_device *pdev)
-{
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = prism_probe,
-	.driver = {
-		.name   = "mddi_prism_wvga",
-	},
-};
-
-static struct msm_fb_panel_data prism_panel_data = {
-	.on = prism_lcd_on,
-	.off = prism_lcd_off,
-};
-
-static struct platform_device this_device = {
-	.name   = "mddi_prism_wvga",
-	.id	= 0,
-	.dev	= {
-		.platform_data = &prism_panel_data,
-	}
-};
-
-static int __init prism_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	u32 id;
-
-	ret = msm_fb_detect_client("mddi_prism_wvga");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret) {
-		id = mddi_get_client_id();
-
-		if (((id >> 16) != 0x4474) || ((id & 0xffff) == 0x8960))
-			return 0;
-	}
-#endif
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &prism_panel_data.panel_info;
-		pinfo->xres = 800;
-		pinfo->yres = 480;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = MDDI_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-		pinfo->wait_cycle = 0;
-		pinfo->mddi.is_type1 = TRUE;
-		pinfo->bpp = 18;
-		pinfo->fb_num = 2;
-		pinfo->clk_rate = 153600000;
-		pinfo->clk_min = 140000000;
-		pinfo->clk_max = 160000000;
-		pinfo->lcd.vsync_enable = TRUE;
-		pinfo->lcd.refx100 = 6050;
-		pinfo->lcd.v_back_porch = 23;
-		pinfo->lcd.v_front_porch = 20;
-		pinfo->lcd.v_pulse_width = 105;
-		pinfo->lcd.hw_vsync_mode = TRUE;
-		pinfo->lcd.vsync_notifier_period = 0;
-
-		ret = platform_device_register(&this_device);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-	}
-
-	return ret;
-}
-
-module_init(prism_init);
diff --git a/drivers/video/msm/mddi_quickvx.c b/drivers/video/msm/mddi_quickvx.c
deleted file mode 100644
index a5d9ea3..0000000
--- a/drivers/video/msm/mddi_quickvx.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/* Copyright (c) 2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <mach/pmic.h>
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-/* WVGA Primary Display */
-#define MDDI_QUICKVX_1_2		1
-/* MDDI Manufacturer Code */
-#define QUICKVX_MDDI_MFR_CODE	0xc583
-/* MDDI Product Code */
-#define QUICKVX_MDDI_PRD_CODE	0x5800
-
-/* Register Address Maps */
-/* MDDI Address Anti-fuse values for bits [31:22] */
-#define QUICKVX_ADDR_31_22_AF	(0X000 << 22)
-
-/* MDDI Address Maps */
-/* VEE Block Address Base */
-#define QUICKVX_VEE_BASE		(QUICKVX_ADDR_31_22_AF | 0x00000000)
-/* SPI Block Address Base */
-#define QUICKVX_SPI_BASE		(QUICKVX_ADDR_31_22_AF | 0x00010000)
-/* Clock and Reset (CAR) Address Base */
-#define QUICKVX_CAR_BASE		(QUICKVX_ADDR_31_22_AF | 0x00020000)
-/* Register Control Block (RCB) Address Base */
-#define QUICKVX_RCB_BASE		(QUICKVX_ADDR_31_22_AF | 0x00030000)
-/* Cellular RAM Address Base */
-#define QUICKVX_CELLRAM_BASE	(QUICKVX_ADDR_31_22_AF | 0x00100000)
-/* FB through A2F Address Base */
-#define QUICKVX_FB_A2F_BASE		(QUICKVX_ADDR_31_22_AF | 0x00200000)
-
-
-/***************************************************
- * Common Registers in Register Control Block (RCB) Registers
- ***************************************************/
- /* CellRAM Configuration RCR Register */
-#define QUICKVX_RCB_RCR_REG			(QUICKVX_RCB_BASE | 0x00000000)
-/* Image Effect Register */
-#define QUICKVX_RCB_IER_REG			(QUICKVX_RCB_BASE | 0x00000004)
-/* Row Number Register */
-#define QUICKVX_RCB_ROWNUM_REG		(QUICKVX_RCB_BASE | 0x00000008)
-/* TCON Timing0 Register */
-#define QUICKVX_RCB_TCON0_REG		(QUICKVX_RCB_BASE | 0x0000000C)
-/* TCON Timing1 Register */
-#define QUICKVX_RCB_TCON1_REG		(QUICKVX_RCB_BASE | 0x00000010)
-/* TCON Timing2 Register */
-#define QUICKVX_RCB_TCON2_REG		(QUICKVX_RCB_BASE | 0x00000014)
-/* PWM Control Register */
-#define QUICKVX_RCB_PWMC_REG		(QUICKVX_RCB_BASE | 0x00000018)
-/* PWM Width Register */
-#define QUICKVX_RCB_PWMW_REG		(QUICKVX_RCB_BASE | 0x0000001C)
-/* VEE Configuration Register */
-#define QUICKVX_RCB_VEECONF_REG		(QUICKVX_RCB_BASE | 0x00000020)
-/* CellRAM Configuration BCR Register */
-#define QUICKVX_RCB_CELLBCR_REG		(QUICKVX_RCB_BASE | 0x00000024)
-/* CellRAM Configuration Control Register */
-#define QUICKVX_RCB_CELLCC_REG		(QUICKVX_RCB_BASE | 0x00000028)
-/* Use Case Register */
-#define QUICKVX_RCB_USECASE_REG		(QUICKVX_RCB_BASE | 0x00000100)
-/* Video Parameter Register */
-#define QUICKVX_RCB_VPARM_REG		(QUICKVX_RCB_BASE | 0x00000104)
-/* MDDI Client Wake-up Register */
-#define QUICKVX_RCB_MCW_REG			(QUICKVX_RCB_BASE | 0x00000108)
-/* Burst Length Register */
-#define QUICKVX_RCB_BURSTLN_REG		(QUICKVX_RCB_BASE | 0x0000010C)
-/* Display Attributes Register */
-#define QUICKVX_RCB_DISPATTR_REG	(QUICKVX_RCB_BASE | 0x00000110)
-/* Error Status Register */
-#define QUICKVX_RCB_ERRSTAT_REG		(QUICKVX_RCB_BASE | 0x00000114)
-/* Error Mask Register */
-#define QUICKVX_RCB_ERRMSK_REG		(QUICKVX_RCB_BASE | 0x00000118)
-/* MDDI ASSP FIFO Overflow Address Register */
-#define QUICKVX_RCB_ASSPFOA_REG		(QUICKVX_RCB_BASE | 0x0000011C)
-/* MDDI Fabric FIFO Overflow Address Register */
-#define QUICKVX_RCB_FABFOA_REG		(QUICKVX_RCB_BASE | 0x00000120)
-/* Incoming RGB FIFO Overflow Address Register */
-#define QUICKVX_RCB_IRFOA_REG		(QUICKVX_RCB_BASE | 0x00000124)
-/* SPI Overflow Address Register */
-#define QUICKVX_RCB_SPIOA_REG		(QUICKVX_RCB_BASE | 0x00000128)
-/* Ping Buffer Address Register */
-#define QUICKVX_RCB_PINGBA_REG		(QUICKVX_RCB_BASE | 0x0000012C)
-/* Pong Buffer Address Register */
-#define QUICKVX_RCB_PONGBA_REG		(QUICKVX_RCB_BASE | 0x00000130)
-/* Configuration Done Register */
-#define QUICKVX_RCB_CONFDONE_REG	(QUICKVX_RCB_BASE | 0x00000134)
-/* FIFO Flush Register */
-#define QUICKVX_RCB_FFLUSH_REG		(QUICKVX_RCB_BASE | 0x00000138)
-
-
-/***************************************************
- * SPI Block Registers
- ***************************************************/
-/* SPI Rx0 Register */
-#define QUICKVX_SPI_RX0_REG			(QUICKVX_SPI_BASE | 0x00000000)
-/* SPI Rx1 Register */
-#define QUICKVX_SPI_RX1_REG			(QUICKVX_SPI_BASE | 0x00000004)
-/* SPI Rx2 Register */
-#define QUICKVX_SPI_RX2_REG			(QUICKVX_SPI_BASE | 0x00000008)
-/* SPI Rx3 Register */
-#define QUICKVX_SPI_RX3_REG			(QUICKVX_SPI_BASE | 0x0000000C)
-/* SPI Rx4 Register */
-#define QUICKVX_SPI_RX4_REG			(QUICKVX_SPI_BASE | 0x00000010)
-/* SPI Rx5 Register */
-#define QUICKVX_SPI_RX5_REG			(QUICKVX_SPI_BASE | 0x00000014)
-/* SPI Rx6 Register */
-#define QUICKVX_SPI_RX6_REG			(QUICKVX_SPI_BASE | 0x00000018)
-/* SPI Rx7 Register */
-#define QUICKVX_SPI_RX7_REG			(QUICKVX_SPI_BASE | 0x0000001C)
-/* SPI Tx0 Register */
-#define QUICKVX_SPI_TX0_REG			(QUICKVX_SPI_BASE | 0x00000020)
-/* SPI Tx1 Register */
-#define QUICKVX_SPI_TX1_REG			(QUICKVX_SPI_BASE | 0x00000024)
-/* SPI Tx2 Register */
-#define QUICKVX_SPI_TX2_REG			(QUICKVX_SPI_BASE | 0x00000028)
-/* SPI Tx3 Register */
-#define QUICKVX_SPI_TX3_REG			(QUICKVX_SPI_BASE | 0x0000002C)
-/* SPI Tx4 Register */
-#define QUICKVX_SPI_TX4_REG			(QUICKVX_SPI_BASE | 0x00000030)
-/* SPI Tx5 Register */
-#define QUICKVX_SPI_TX5_REG			(QUICKVX_SPI_BASE | 0x00000034)
-/* SPI Tx6 Register */
-#define QUICKVX_SPI_TX6_REG			(QUICKVX_SPI_BASE | 0x00000038)
-/* SPI Tx7 Register */
-#define QUICKVX_SPI_TX7_REG			(QUICKVX_SPI_BASE | 0x0000003C)
-/* SPI Control Register */
-#define QUICKVX_SPI_CTRL_REG		(QUICKVX_SPI_BASE | 0x00000040)
-/* SPI Transfer Length Register */
-#define QUICKVX_SPI_TLEN_REG		(QUICKVX_SPI_BASE | 0x00000044)
-
-
-/***************************************************
- * Clock and Reset (CAR) Block Registers
- ***************************************************/
-/* ASSP Global Clock Enable Register */
-#define QUICKVX_CAR_ASSP_GCE_REG	(QUICKVX_CAR_BASE | 0x00000000)
-/* VLP Control1 Register */
-#define QUICKVX_CAR_VLPCTRL1_REG	(QUICKVX_CAR_BASE | 0x00000004)
-/* VLP Control2 Register */
-#define QUICKVX_CAR_VLPCTRL2_REG	(QUICKVX_CAR_BASE | 0x00000008)
-/* Clock Selection Register */
-#define QUICKVX_CAR_CLKSEL_REG		(QUICKVX_CAR_BASE | 0x0000000C)
-/* PLL Control Register */
-#define QUICKVX_CAR_PLLCTRL_REG		(QUICKVX_CAR_BASE | 0x00000010)
-/* PLL Clock Ratio Register */
-#define QUICKVX_CAR_PLLCLKRATIO_REG	(QUICKVX_CAR_BASE | 0x00000014)
-
-
-/***************************************************
- * VEE Block Registers
- ***************************************************/
-/* VEE Control Register */
-#define QUICKVX_VEE_VEECTRL_REG		(QUICKVX_VEE_BASE | 0x00000000)
-/* Strength Register */
-#define QUICKVX_VEE_STRENGTH_REG	(QUICKVX_VEE_BASE | 0x0000000C)
-/* Variance Register */
-#define QUICKVX_VEE_VARIANCE_REG	(QUICKVX_VEE_BASE | 0x00000010)
-/* Slope Register */
-#define QUICKVX_VEE_SLOPE_REG		(QUICKVX_VEE_BASE | 0x00000014)
-/* Sharpen Control0 Register */
-#define QUICKVX_VEE_SHRPCTRL0_REG	(QUICKVX_VEE_BASE | 0x0000001C)
-/* Sharpen Control1 Register */
-#define QUICKVX_VEE_SHRPCTRL1_REG	(QUICKVX_VEE_BASE | 0x00000020)
-/* Upper Horizontal Positon Register */
-#define QUICKVX_VEE_UHPOS_REG		(QUICKVX_VEE_BASE | 0x00000024)
-/* Lower Horizontal Positon Register */
-#define QUICKVX_VEE_LHPOS_REG		(QUICKVX_VEE_BASE | 0x00000028)
-/* Upper Vertical Positon Register */
-#define QUICKVX_VEE_UVPOS_REG		(QUICKVX_VEE_BASE | 0x0000002C)
-/* Lower Vertical Positon Register */
-#define QUICKVX_VEE_LVPOS_REG		(QUICKVX_VEE_BASE | 0x00000030)
-/* Upper Frame Width Register */
-#define QUICKVX_VEE_UFWDTH_REG		(QUICKVX_VEE_BASE | 0x00000034)
-/* Lower Frame Width Register */
-#define QUICKVX_VEE_LFWDTH_REG		(QUICKVX_VEE_BASE | 0x00000038)
-/* Upper Frame Height Register */
-#define QUICKVX_VEE_UFHGHT_REG		(QUICKVX_VEE_BASE | 0x0000003C)
-/* Lower Frame Height Register */
-#define QUICKVX_VEE_LFHGHT_REG		(QUICKVX_VEE_BASE | 0x00000040)
-/* Control0 Register */
-#define QUICKVX_VEE_CTRL0_REG		(QUICKVX_VEE_BASE | 0x00000044)
-/* Control1 Register */
-#define QUICKVX_VEE_CTRL1_REG		(QUICKVX_VEE_BASE | 0x00000048)
-/* Video Enhancement Enable Register */
-#define QUICKVX_VEE_VDOEEN_REG		(QUICKVX_VEE_BASE | 0x0000004C)
-/* Black Level Register */
-#define QUICKVX_VEE_BLCKLEV_REG		(QUICKVX_VEE_BASE | 0x00000050)
-/* White Level Register */
-#define QUICKVX_VEE_WHTLEV_REG		(QUICKVX_VEE_BASE | 0x00000054)
-/* Amplification Limits Register */
-#define QUICKVX_VEE_AMPLMTS_REG		(QUICKVX_VEE_BASE | 0x00000060)
-/* Dithering Mode Register */
-#define QUICKVX_VEE_DITHMOD_REG		(QUICKVX_VEE_BASE | 0x00000064)
-/* Upper Look-up Data Register */
-#define QUICKVX_VEE_ULUD_REG		(QUICKVX_VEE_BASE | 0x00000080)
-/* Lower Look-up Data Register */
-#define QUICKVX_VEE_LLUD_REG		(QUICKVX_VEE_BASE | 0x00000084)
-/* Look-up Address Register */
-#define QUICKVX_VEE_LUADDR_REG		(QUICKVX_VEE_BASE | 0x00000088)
-/* Look-up Write Enable Register */
-#define QUICKVX_VEE_LUWREN_REG		(QUICKVX_VEE_BASE | 0x0000008C)
-/* VEE ID Register */
-#define QUICKVX_VEE_VEEID_REG		(QUICKVX_VEE_BASE | 0x000003FC)
-/* M_11 Register */
-#define QUICKVX_VEE_M_11_REG		(QUICKVX_VEE_BASE | 0x000000C0)
-/* M_12 Register */
-#define QUICKVX_VEE_M_12_REG		(QUICKVX_VEE_BASE | 0x000000C4)
-/* M_13 Register */
-#define QUICKVX_VEE_M_13_REG		(QUICKVX_VEE_BASE | 0x000000C8)
-/* M_21 Register */
-#define QUICKVX_VEE_M_21_REG		(QUICKVX_VEE_BASE | 0x000000CC)
-/* M_22 Register */
-#define QUICKVX_VEE_M_22_REG		(QUICKVX_VEE_BASE | 0x000000D0)
-/* M_23 Register */
-#define QUICKVX_VEE_M_23_REG		(QUICKVX_VEE_BASE | 0x000000D4)
-/* M_31 Register */
-#define QUICKVX_VEE_M_31_REG		(QUICKVX_VEE_BASE | 0x000000D8)
-/* M_32 Register */
-#define QUICKVX_VEE_M_32_REG		(QUICKVX_VEE_BASE | 0x000000DC)
-/* M_33 Register */
-#define QUICKVX_VEE_M_33_REG		(QUICKVX_VEE_BASE | 0x000000E0)
-/* R Offset Register */
-#define QUICKVX_VEE_OFFSET_R_REG	(QUICKVX_VEE_BASE | 0x000000E8)
-/* G Offset Register */
-#define QUICKVX_VEE_OFFSET_G_REG	(QUICKVX_VEE_BASE | 0x000000EC)
-/* B Offset Register */
-#define QUICKVX_VEE_OFFSET_B_REG	(QUICKVX_VEE_BASE | 0x000000F0)
-
-/* LCD Reset Register */
-#define QUICKVX_FB_A2F_LCD_RESET_REG (QUICKVX_FB_A2F_BASE | 0x00000000)
-
-/* Register bit defines */
-/* PLL Lock bit in the PLL Control Register */
-#define QUICKVX_PLL_LOCK_BIT		(1 << 7)
-
-#define QL_SPI_CTRL_rSPISTart(x) (x)
-#define QL_SPI_CTRL_rCPHA(x) (x << 1)
-#define QL_SPI_CTRL_rCPOL(x) (x << 2)
-#define QL_SPI_CTRL_rLSB(x) (x << 3)
-#define QL_SPI_CTRL_rSLVSEL(x) (x << 4)
-#define QL_SPI_CTRL_MASK_rTxDone (1 << 9)
-
-#define QL_SPI_LCD_DEV_ID 0x1c
-#define QL_SPI_LCD_RS(x) (x << 1)
-#define QL_SPI_LCD_RW(x) (x)
-#define QL_SPI_LCD_INDEX_START_BYTE ((QL_SPI_LCD_DEV_ID << 2) | \
-	QL_SPI_LCD_RS(0) | QL_SPI_LCD_RW(0))
-#define QL_SPI_LCD_CMD_START_BYTE ((QL_SPI_LCD_DEV_ID << 2) | \
-	QL_SPI_LCD_RS(1) | QL_SPI_LCD_RW(0))
-#define QL_SPI_CTRL_LCD_START (QL_SPI_CTRL_rSPISTart(1) | \
-	QL_SPI_CTRL_rCPHA(1) | QL_SPI_CTRL_rCPOL(1) | \
-	QL_SPI_CTRL_rLSB(0) | QL_SPI_CTRL_rSLVSEL(0))
-
-int ql_mddi_write(uint32 address, uint32 value)
-{
-	int ret = 0;
-
-	ret = mddi_queue_register_write(address, value, TRUE, 0);
-
-	return ret;
-}
-
-int ql_mddi_read(uint32 address, uint32 *regval)
-{
-	int ret = 0;
-
-	ret = mddi_queue_register_read(address, regval, TRUE, 0);
-	MDDI_MSG_DEBUG("\nql_mddi_read[0x%x]=0x%x", address, *regval);
-
-	return ret;
-}
-
-int ql_send_spi_cmd_to_lcd(uint32 index, uint32 cmd)
-{
-
-	MDDI_MSG_DEBUG("\n %s(): index 0x%x, cmd 0x%x", __func__, index, cmd);
-	/* do the index phase */
-	/* send 24 bits in the index phase */
-	ql_mddi_write(QUICKVX_SPI_TLEN_REG, 23);
-
-	/* send 24 bits in the index phase, starting at bit 23 of TX0 reg */
-	ql_mddi_write(QUICKVX_SPI_TX0_REG,
-		(QL_SPI_LCD_INDEX_START_BYTE << 16) | index);
-
-	/* set start */
-	ql_mddi_write(QUICKVX_SPI_CTRL_REG,  QL_SPI_CTRL_LCD_START);
-
-	/* do the command phase */
-	/* send 24 bits in the cmd phase */
-	ql_mddi_write(QUICKVX_SPI_TLEN_REG, 23);
-
-	/* send 24 bits in the cmd phase, starting at bit 23 of TX0 reg. */
-	ql_mddi_write(QUICKVX_SPI_TX0_REG,
-		(QL_SPI_LCD_CMD_START_BYTE << 16) | cmd);
-
-	/* set start */
-	ql_mddi_write(QUICKVX_SPI_CTRL_REG,  QL_SPI_CTRL_LCD_START);
-
-	return 0;
-}
-
-
-int ql_send_spi_data_from_lcd(uint32 index, uint32 *value)
-{
-
-	MDDI_MSG_DEBUG("\n %s(): index 0x%x", __func__, index);
-	/* do the index phase */
-	/* send 24 bits in the index phase */
-	ql_mddi_write(QUICKVX_SPI_TLEN_REG, 23);
-
-	/* send 24 bits in the index phase, starting at bit 23 of TX0 reg */
-	ql_mddi_write(QUICKVX_SPI_TX0_REG,
-		(QL_SPI_LCD_INDEX_START_BYTE << 16) | index);
-
-	/* set start */
-	ql_mddi_write(QUICKVX_SPI_CTRL_REG,  QL_SPI_CTRL_LCD_START);
-	/* do the command phase */
-	/* send 8 bits  and read 24 bits in the cmd phase, so total 32 bits */
-	ql_mddi_write(QUICKVX_SPI_TLEN_REG, 31);
-
-	/* send 24 bits in the cmd phase, starting at bit 31 of TX0 reg */
-	ql_mddi_write(QUICKVX_SPI_TX0_REG,
-		((QL_SPI_LCD_CMD_START_BYTE << 16)) << 8);
-
-	/* set start */
-	ql_mddi_write(QUICKVX_SPI_CTRL_REG,  QL_SPI_CTRL_LCD_START);
-
-	return 0;
-
-}
-
-/* Global Variables */
-static uint32 mddi_quickvx_rows_per_second;
-static uint32 mddi_quickvx_usecs_per_refresh;
-static uint32 mddi_quickvx_rows_per_refresh;
-
-void mddi_quickvx_configure_registers(void)
-{
-	MDDI_MSG_DEBUG("\n%s(): ", __func__);
-	ql_mddi_write(QUICKVX_CAR_CLKSEL_REG, 0x00007000);
-
-	ql_mddi_write(QUICKVX_RCB_PWMW_REG, 0x0000FFFF);
-
-	ql_mddi_write(QUICKVX_RCB_PWMC_REG, 0x00000001);
-
-	ql_mddi_write(QUICKVX_RCB_CONFDONE_REG, 0x00000000);
-
-	/* display is x width = 480, y width = 864 */
-	ql_mddi_write(QUICKVX_RCB_TCON0_REG, 0x035f01df);
-
-	/* VFP=2, VBP=4, HFP=16, HBP=16 */
-	ql_mddi_write(QUICKVX_RCB_TCON1_REG, 0x01e301e1);
-
-	/* VSW =2, HSW=8 */
-	ql_mddi_write(QUICKVX_RCB_TCON2_REG, 0x000000e1);
-
-	ql_mddi_write(QUICKVX_RCB_DISPATTR_REG, 0x00000000);
-
-	ql_mddi_write(QUICKVX_RCB_USECASE_REG, 0x00000025);
-
-	ql_mddi_write(QUICKVX_RCB_VPARM_REG, 0x00000888);
-
-	ql_mddi_write(QUICKVX_RCB_VEECONF_REG, 0x00000001);
-
-	ql_mddi_write(QUICKVX_RCB_IER_REG, 0x00000000);
-
-	ql_mddi_write(QUICKVX_RCB_RCR_REG, 0x80000010);
-
-	ql_mddi_write(QUICKVX_RCB_CELLBCR_REG, 0x8008746F);
-
-	ql_mddi_write(QUICKVX_RCB_CELLCC_REG, 0x800000A3);
-
-	ql_mddi_write(QUICKVX_RCB_CONFDONE_REG, 0x00000001);
-}
-
-void mddi_quickvx_prim_lcd_init(void)
-{
-	uint32 value;
-
-	MDDI_MSG_DEBUG("\n%s(): ", __func__);
-	ql_send_spi_data_from_lcd(0, &value);
-
-	ql_send_spi_cmd_to_lcd(0x0100, 0x3000); /* power control1 */
-	ql_send_spi_cmd_to_lcd(0x0101, 0x4010); /* power control2 */
-	ql_send_spi_cmd_to_lcd(0x0106, 0x0000); /* auto seq setting */
-	mddi_wait(3);
-
-	ql_mddi_write(QUICKVX_FB_A2F_LCD_RESET_REG, 0x00000001);
-	mddi_wait(1);
-	ql_mddi_write(QUICKVX_FB_A2F_LCD_RESET_REG, 0x00000000);
-	mddi_wait(1);
-	ql_mddi_write(QUICKVX_FB_A2F_LCD_RESET_REG, 0x00000001);
-	mddi_wait(10);
-
-	ql_send_spi_cmd_to_lcd(0x0001, 0x0310); /* driver out control */
-	ql_send_spi_cmd_to_lcd(0x0002, 0x0100); /* lcd ac control */
-	ql_send_spi_cmd_to_lcd(0x0003, 0x0000); /* entry mode */
-	ql_send_spi_cmd_to_lcd(0x0007, 0x0000); /* disp cont1 */
-	ql_send_spi_cmd_to_lcd(0x0008, 0x0004); /* disp cont2 */
-	ql_send_spi_cmd_to_lcd(0x0009, 0x000C); /* disp cont3 */
-	ql_send_spi_cmd_to_lcd(0x000C, 0x4010); /* disp if cont1 */
-	ql_send_spi_cmd_to_lcd(0x000E, 0x0000); /* disp if cont2 */
-	ql_send_spi_cmd_to_lcd(0x0020, 0x013F); /* panel if cont1 */
-	ql_send_spi_cmd_to_lcd(0x0022, 0x7600); /* panel if cont3 */
-	ql_send_spi_cmd_to_lcd(0x0023, 0x1C0A); /* panel if cont4 */
-	ql_send_spi_cmd_to_lcd(0x0024, 0x1C2C); /* panel if cont5 */
-	ql_send_spi_cmd_to_lcd(0x0025, 0x1C4E); /* panel if cont6 */
-	ql_send_spi_cmd_to_lcd(0x0027, 0x0000); /* panel if cont8 */
-	ql_send_spi_cmd_to_lcd(0x0028, 0x760C); /* panel if cont9 */
-	ql_send_spi_cmd_to_lcd(0x0300, 0x0000); /* gamma adj0 */
-	ql_send_spi_cmd_to_lcd(0x0301, 0x0502); /* gamma adj1 */
-	ql_send_spi_cmd_to_lcd(0x0302, 0x0705); /* gamma adj2 */
-	ql_send_spi_cmd_to_lcd(0x0303, 0x0000); /* gamma adj3 */
-	ql_send_spi_cmd_to_lcd(0x0304, 0x0200); /* gamma adj4 */
-	ql_send_spi_cmd_to_lcd(0x0305, 0x0707); /* gamma adj5 */
-	ql_send_spi_cmd_to_lcd(0x0306, 0x1010); /* gamma adj6 */
-	ql_send_spi_cmd_to_lcd(0x0307, 0x0202); /* gamma adj7 */
-	ql_send_spi_cmd_to_lcd(0x0308, 0x0704); /* gamma adj8 */
-	ql_send_spi_cmd_to_lcd(0x0309, 0x0707); /* gamma adj9 */
-	ql_send_spi_cmd_to_lcd(0x030A, 0x0000); /* gamma adja */
-	ql_send_spi_cmd_to_lcd(0x030B, 0x0000); /* gamma adjb */
-	ql_send_spi_cmd_to_lcd(0x030C, 0x0707); /* gamma adjc */
-	ql_send_spi_cmd_to_lcd(0x030D, 0x1010); /* gamma adjd */
-	ql_send_spi_cmd_to_lcd(0x0310, 0x0104); /* gamma adj10 */
-	ql_send_spi_cmd_to_lcd(0x0311, 0x0503); /* gamma adj11 */
-	ql_send_spi_cmd_to_lcd(0x0312, 0x0304); /* gamma adj12 */
-	ql_send_spi_cmd_to_lcd(0x0315, 0x0304); /* gamma adj15 */
-	ql_send_spi_cmd_to_lcd(0x0316, 0x031C); /* gamma adj16 */
-	ql_send_spi_cmd_to_lcd(0x0317, 0x0204); /* gamma adj17 */
-	ql_send_spi_cmd_to_lcd(0x0318, 0x0402); /* gamma adj18 */
-	ql_send_spi_cmd_to_lcd(0x0319, 0x0305); /* gamma adj19 */
-	ql_send_spi_cmd_to_lcd(0x031C, 0x0707); /* gamma adj1c */
-	ql_send_spi_cmd_to_lcd(0x031D, 0x021F); /* gamma adj1d */
-	ql_send_spi_cmd_to_lcd(0x0320, 0x0507); /* gamma adj20 */
-	ql_send_spi_cmd_to_lcd(0x0321, 0x0604); /* gamma adj21 */
-	ql_send_spi_cmd_to_lcd(0x0322, 0x0405); /* gamma adj22 */
-	ql_send_spi_cmd_to_lcd(0x0327, 0x0203); /* gamma adj27 */
-	ql_send_spi_cmd_to_lcd(0x0328, 0x0300); /* gamma adj28 */
-	ql_send_spi_cmd_to_lcd(0x0329, 0x0002); /* gamma adj29 */
-	ql_send_spi_cmd_to_lcd(0x0100, 0x363C); /* power cont1 */
-	mddi_wait(1);
-	ql_send_spi_cmd_to_lcd(0x0101, 0x4003); /* power cont2 */
-	ql_send_spi_cmd_to_lcd(0x0102, 0x0001); /* power cont3 */
-	ql_send_spi_cmd_to_lcd(0x0103, 0x3C58); /* power cont4 */
-	ql_send_spi_cmd_to_lcd(0x010C, 0x0135); /* power cont6 */
-	ql_send_spi_cmd_to_lcd(0x0106, 0x0002); /* auto seq */
-	ql_send_spi_cmd_to_lcd(0x0029, 0x03BF); /* panel if cont10 */
-	ql_send_spi_cmd_to_lcd(0x0106, 0x0003); /* auto seq */
-	mddi_wait(5);
-	ql_send_spi_cmd_to_lcd(0x0101, 0x4010); /* power cont2 */
-	mddi_wait(10);
-}
-
-/* Function to Power On the Primary and Secondary LCD panels */
-static int mddi_quickvx_lcd_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	MDDI_MSG_DEBUG("\n%s(): ", __func__);
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd) {
-		MDDI_MSG_DEBUG("\n mddi_quickvx_lcd_on: Device not found!");
-		return -ENODEV;
-	}
-
-	if (mfd->key != MFD_KEY) {
-		MDDI_MSG_DEBUG("\n mddi_quickvx_lcd_on: Invalid MFD key!");
-		return -EINVAL;
-	}
-
-	mddi_host_client_cnt_reset();
-	mddi_quickvx_configure_registers();
-	mddi_quickvx_prim_lcd_init();
-
-	return 0;
-}
-
-
-/* Function to Power Off the Primary and Secondary LCD panels */
-static int mddi_quickvx_lcd_off(struct platform_device *pdev)
-{
-	MDDI_MSG_DEBUG("\n%s(): ", __func__);
-	mddi_wait(1);
-	ql_send_spi_cmd_to_lcd(0x0106, 0x0002); /* Auto Sequencer setting */
-	mddi_wait(10);
-	ql_send_spi_cmd_to_lcd(0x0106, 0x0000); /* Auto Sequencer setting */
-	ql_send_spi_cmd_to_lcd(0x0029, 0x0002); /* Panel IF control 10 */
-	ql_send_spi_cmd_to_lcd(0x0100, 0x300D); /* Power Control 1 */
-	mddi_wait(1);
-
-	return 0;
-}
-
-/* Function to set the Backlight brightness level */
-static void mddi_quickvx_lcd_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int32 level, i = 0, ret;
-
-	MDDI_MSG_DEBUG("%s(): ", __func__);
-
-	level = mfd->bl_level;
-	MDDI_MSG_DEBUG("\n level = %d", level);
-	if (level < 0) {
-		MDDI_MSG_DEBUG("mddi_quickvx_lcd_set_backlight: "
-			"Invalid backlight level (%d)!\n", level);
-		return;
-	}
-	while (i++ < 3) {
-		ret = pmic_set_led_intensity(LED_LCD, level);
-		if (ret == 0)
-			return;
-		msleep(10);
-	}
-
-	MDDI_MSG_DEBUG("%s: can't set lcd backlight!\n",
-				__func__);
-}
-
-/* Driver Probe function */
-static int __devinit mddi_quickvx_lcd_probe(struct platform_device *pdev)
-{
-	MDDI_MSG_DEBUG("\n%s(): id is %d", __func__, pdev->id);
-	msm_fb_add_device(pdev);
-	return 0;
-}
-
-/* Driver data structure */
-static struct platform_driver this_driver = {
-	.probe  = mddi_quickvx_lcd_probe,
-	.driver	= {
-		.name	= "mddi_quickvx",
-	},
-};
-
-
-/* Primary LCD panel data structure */
-static struct msm_fb_panel_data mddi_quickvx_panel_data0 = {
-	.on					= mddi_quickvx_lcd_on,
-	.off				= mddi_quickvx_lcd_off,
-	.set_backlight		= mddi_quickvx_lcd_set_backlight,
-};
-
-
-/* Primary LCD panel device structure */
-static struct platform_device this_device0 = {
-	.name   = "mddi_quickvx",
-	.id		= MDDI_QUICKVX_1_2,
-	.dev	= {
-		.platform_data = &mddi_quickvx_panel_data0,
-	}
-};
-
-/* Module init - driver main entry point */
-static int __init mddi_quickvx_lcd_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	u32 cid;
-	MDDI_MSG_DEBUG("\n%s(): ", __func__);
-
-	ret = msm_fb_detect_client("mddi_quickvx");
-
-	if (ret == -ENODEV)	{
-		/* Device not found */
-		MDDI_MSG_DEBUG("\n mddi_quickvx_lcd_init: No device found!");
-		return 0;
-	}
-
-	if (ret) {
-		cid = mddi_get_client_id();
-
-		MDDI_MSG_DEBUG("\n cid = 0x%x", cid);
-		if (((cid >> 16) != QUICKVX_MDDI_MFR_CODE) ||
-			((cid & 0xFFFF) != QUICKVX_MDDI_PRD_CODE)) {
-			/* MDDI Client ID not matching */
-			MDDI_MSG_DEBUG("\n mddi_quickvx_lcd_init: "
-				"Client ID missmatch!");
-
-			return 0;
-		}
-		MDDI_MSG_DEBUG("\n mddi_quickvx_lcd_init: "
-			"QuickVX LCD panel detected!");
-	}
-
-#endif /* CONFIG_FB_MSM_MDDI_AUTO_DETECT */
-
-	mddi_quickvx_rows_per_refresh = 872;
-	mddi_quickvx_rows_per_second = 52364;
-	mddi_quickvx_usecs_per_refresh = 16574;
-
-	ret = platform_driver_register(&this_driver);
-
-	if (!ret) {
-		pinfo = &mddi_quickvx_panel_data0.panel_info;
-		pinfo->xres = 480;
-		pinfo->yres = 864;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = MDDI_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-		pinfo->wait_cycle = 0;
-		pinfo->bpp = 24;
-		pinfo->fb_num = 2;
-
-		pinfo->clk_rate = 192000000;
-		pinfo->clk_min = 192000000;
-		pinfo->clk_max = 200000000;
-		pinfo->lcd.rev = 1;
-		pinfo->lcd.vsync_enable = TRUE;
-		pinfo->lcd.refx100 = (mddi_quickvx_rows_per_second \
-			* 100)/mddi_quickvx_rows_per_refresh;
-		pinfo->mddi.is_type1 = TRUE;
-		pinfo->lcd.v_back_porch = 4;
-		pinfo->lcd.v_front_porch = 2;
-		pinfo->lcd.v_pulse_width = 2;
-		pinfo->lcd.hw_vsync_mode = TRUE;
-		pinfo->lcd.vsync_notifier_period = (1 * HZ);
-		pinfo->bl_max = 10;
-		pinfo->bl_min = 0;
-
-		ret = platform_device_register(&this_device0);
-		if (ret) {
-			platform_driver_unregister(&this_driver);
-			MDDI_MSG_DEBUG("mddi_quickvx_lcd_init: "
-				"Primary device registration failed!\n");
-		}
-	}
-
-	return ret;
-}
-
-module_init(mddi_quickvx_lcd_init);
-
diff --git a/drivers/video/msm/mddi_sharp.c b/drivers/video/msm/mddi_sharp.c
deleted file mode 100644
index c10d01a..0000000
--- a/drivers/video/msm/mddi_sharp.c
+++ /dev/null
@@ -1,901 +0,0 @@
-/* Copyright (c) 2008-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-#define SHARP_QVGA_PRIM 1
-#define SHARP_128X128_SECD 2
-
-extern uint32 mddi_host_core_version;
-static boolean mddi_debug_prim_wait = FALSE;
-static boolean mddi_sharp_vsync_wake = TRUE;
-static boolean mddi_sharp_monitor_refresh_value = TRUE;
-static boolean mddi_sharp_report_refresh_measurements = FALSE;
-static uint32 mddi_sharp_rows_per_second = 13830;	/* 5200000/376 */
-static uint32 mddi_sharp_rows_per_refresh = 338;
-static uint32 mddi_sharp_usecs_per_refresh = 24440;	/* (376+338)/5200000 */
-static boolean mddi_sharp_debug_60hz_refresh = FALSE;
-
-extern mddi_gpio_info_type mddi_gpio;
-extern boolean mddi_vsync_detect_enabled;
-static msm_fb_vsync_handler_type mddi_sharp_vsync_handler;
-static void *mddi_sharp_vsync_handler_arg;
-static uint16 mddi_sharp_vsync_attempts;
-
-static void mddi_sharp_prim_lcd_init(void);
-static void mddi_sharp_sub_lcd_init(void);
-static void mddi_sharp_lcd_set_backlight(struct msm_fb_data_type *mfd);
-static void mddi_sharp_vsync_set_handler(msm_fb_vsync_handler_type handler,
-					 void *);
-static void mddi_sharp_lcd_vsync_detected(boolean detected);
-static struct msm_panel_common_pdata *mddi_sharp_pdata;
-
-#define REG_SYSCTL    0x0000
-#define REG_INTR    0x0006
-#define REG_CLKCNF    0x000C
-#define REG_CLKDIV1    0x000E
-#define REG_CLKDIV2    0x0010
-
-#define REG_GIOD    0x0040
-#define REG_GIOA    0x0042
-
-#define REG_AGM      0x010A
-#define REG_FLFT    0x0110
-#define REG_FRGT    0x0112
-#define REG_FTOP    0x0114
-#define REG_FBTM    0x0116
-#define REG_FSTRX    0x0118
-#define REG_FSTRY    0x011A
-#define REG_VRAM    0x0202
-#define REG_SSDCTL    0x0330
-#define REG_SSD0    0x0332
-#define REG_PSTCTL1    0x0400
-#define REG_PSTCTL2    0x0402
-#define REG_PTGCTL    0x042A
-#define REG_PTHP    0x042C
-#define REG_PTHB    0x042E
-#define REG_PTHW    0x0430
-#define REG_PTHF    0x0432
-#define REG_PTVP    0x0434
-#define REG_PTVB    0x0436
-#define REG_PTVW    0x0438
-#define REG_PTVF    0x043A
-#define REG_VBLKS    0x0458
-#define REG_VBLKE    0x045A
-#define REG_SUBCTL    0x0700
-#define REG_SUBTCMD    0x0702
-#define REG_SUBTCMDD  0x0704
-#define REG_REVBYTE    0x0A02
-#define REG_REVCNT    0x0A04
-#define REG_REVATTR    0x0A06
-#define REG_REVFMT    0x0A08
-
-#define SHARP_SUB_UNKNOWN 0xffffffff
-#define SHARP_SUB_HYNIX 1
-#define SHARP_SUB_ROHM  2
-
-static uint32 sharp_subpanel_type = SHARP_SUB_UNKNOWN;
-
-static void sub_through_write(int sub_rs, uint32 sub_data)
-{
-	mddi_queue_register_write(REG_SUBTCMDD, sub_data, FALSE, 0);
-
-	/* CS=1,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x000e | sub_rs, FALSE, 0);
-
-	/* CS=0,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0006 | sub_rs, FALSE, 0);
-
-	/* CS=0,RD=1,WE=0,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0004 | sub_rs, FALSE, 0);
-
-	/* CS=0,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0006 | sub_rs, FALSE, 0);
-
-	/* CS=1,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x000e | sub_rs, TRUE, 0);
-}
-
-static uint32 sub_through_read(int sub_rs)
-{
-	uint32 sub_data;
-
-	/* CS=1,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x000e | sub_rs, FALSE, 0);
-
-	/* CS=0,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0006 | sub_rs, FALSE, 0);
-
-	/* CS=0,RD=1,WE=0,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0002 | sub_rs, TRUE, 0);
-
-	mddi_queue_register_read(REG_SUBTCMDD, &sub_data, TRUE, 0);
-
-	/* CS=0,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x0006 | sub_rs, FALSE, 0);
-
-	/* CS=1,RD=1,WE=1,RS=sub_rs */
-	mddi_queue_register_write(REG_SUBTCMD, 0x000e | sub_rs, TRUE, 0);
-
-	return sub_data;
-}
-
-static void serigo(uint32 ssd)
-{
-	uint32 ssdctl;
-
-	mddi_queue_register_read(REG_SSDCTL, &ssdctl, TRUE, 0);
-	ssdctl = ((ssdctl & 0xE7) | 0x02);
-
-	mddi_queue_register_write(REG_SSD0, ssd, FALSE, 0);
-	mddi_queue_register_write(REG_SSDCTL, ssdctl, TRUE, 0);
-
-	do {
-		mddi_queue_register_read(REG_SSDCTL, &ssdctl, TRUE, 0);
-	} while ((ssdctl & 0x0002) != 0);
-
-	if (mddi_debug_prim_wait)
-		mddi_wait(2);
-}
-
-static void mddi_sharp_lcd_powerdown(void)
-{
-	serigo(0x0131);
-	serigo(0x0300);
-	mddi_wait(40);
-	serigo(0x0135);
-	mddi_wait(20);
-	serigo(0x2122);
-	mddi_wait(20);
-	serigo(0x0201);
-	mddi_wait(20);
-	serigo(0x2100);
-	mddi_wait(20);
-	serigo(0x2000);
-	mddi_wait(20);
-
-	mddi_queue_register_write(REG_PSTCTL1, 0x1, TRUE, 0);
-	mddi_wait(100);
-	mddi_queue_register_write(REG_PSTCTL1, 0x0, TRUE, 0);
-	mddi_wait(2);
-	mddi_queue_register_write(REG_SYSCTL, 0x1, TRUE, 0);
-	mddi_wait(2);
-	mddi_queue_register_write(REG_CLKDIV1, 0x3, TRUE, 0);
-	mddi_wait(2);
-	mddi_queue_register_write(REG_SSDCTL, 0x0000, TRUE, 0);	/* SSDRESET */
-	mddi_queue_register_write(REG_SYSCTL, 0x0, TRUE, 0);
-	mddi_wait(2);
-}
-
-static void mddi_sharp_lcd_set_backlight(struct msm_fb_data_type *mfd)
-{
-	uint32 regdata;
-	int32 level;
-	int max = mfd->panel_info.bl_max;
-	int min = mfd->panel_info.bl_min;
-
-	if (mddi_sharp_pdata && mddi_sharp_pdata->backlight_level) {
-		level = mddi_sharp_pdata->backlight_level(mfd->bl_level,
-							  max,
-							  min);
-
-		if (level < 0)
-			return;
-
-		/* use Rodem GPIO(2:0) to give 8 levels of backlight (7-0) */
-		/* Set lower 3 GPIOs as Outputs (set to 0) */
-		mddi_queue_register_read(REG_GIOA, &regdata, TRUE, 0);
-		mddi_queue_register_write(REG_GIOA, regdata & 0xfff8, TRUE, 0);
-
-		/* Set lower 3 GPIOs as level */
-		mddi_queue_register_read(REG_GIOD, &regdata, TRUE, 0);
-		mddi_queue_register_write(REG_GIOD,
-			  (regdata & 0xfff8) | (0x07 & level), TRUE, 0);
-	}
-}
-
-static void mddi_sharp_prim_lcd_init(void)
-{
-	mddi_queue_register_write(REG_SYSCTL, 0x4000, TRUE, 0);
-	mddi_wait(1);
-	mddi_queue_register_write(REG_SYSCTL, 0x0000, TRUE, 0);
-	mddi_wait(5);
-	mddi_queue_register_write(REG_SYSCTL, 0x0001, FALSE, 0);
-	mddi_queue_register_write(REG_CLKDIV1, 0x000b, FALSE, 0);
-
-	/* new reg write below */
-	if (mddi_sharp_debug_60hz_refresh)
-		mddi_queue_register_write(REG_CLKCNF, 0x070d, FALSE, 0);
-	else
-		mddi_queue_register_write(REG_CLKCNF, 0x0708, FALSE, 0);
-
-	mddi_queue_register_write(REG_SYSCTL, 0x0201, FALSE, 0);
-	mddi_queue_register_write(REG_PTGCTL, 0x0010, FALSE, 0);
-	mddi_queue_register_write(REG_PTHP, 4, FALSE, 0);
-	mddi_queue_register_write(REG_PTHB, 40, FALSE, 0);
-	mddi_queue_register_write(REG_PTHW, 240, FALSE, 0);
-	if (mddi_sharp_debug_60hz_refresh)
-		mddi_queue_register_write(REG_PTHF, 12, FALSE, 0);
-	else
-		mddi_queue_register_write(REG_PTHF, 92, FALSE, 0);
-
-	mddi_wait(1);
-
-	mddi_queue_register_write(REG_PTVP, 1, FALSE, 0);
-	mddi_queue_register_write(REG_PTVB, 2, FALSE, 0);
-	mddi_queue_register_write(REG_PTVW, 320, FALSE, 0);
-	mddi_queue_register_write(REG_PTVF, 15, FALSE, 0);
-
-	mddi_wait(1);
-
-	/* vram_color set REG_AGM???? */
-	mddi_queue_register_write(REG_AGM, 0x0000, TRUE, 0);
-
-	mddi_queue_register_write(REG_SSDCTL, 0x0000, FALSE, 0);
-	mddi_queue_register_write(REG_SSDCTL, 0x0001, TRUE, 0);
-	mddi_wait(1);
-	mddi_queue_register_write(REG_PSTCTL1, 0x0001, TRUE, 0);
-	mddi_wait(10);
-
-	serigo(0x0701);
-	/* software reset */
-	mddi_wait(1);
-	/* Wait over 50us */
-
-	serigo(0x0400);
-	/* DCLK~ACHSYNC~ACVSYNC polarity setting */
-	serigo(0x2900);
-	/* EEPROM start read address setting */
-	serigo(0x2606);
-	/* EEPROM start read register setting */
-	mddi_wait(20);
-	/* Wait over 20ms */
-
-	serigo(0x0503);
-	/* Horizontal timing setting */
-	serigo(0x062C);
-	/* Veritical timing setting */
-	serigo(0x2001);
-	/* power initialize setting(VDC2) */
-	mddi_wait(20);
-	/* Wait over 20ms */
-
-	serigo(0x2120);
-	/* Initialize power setting(CPS) */
-	mddi_wait(20);
-	/* Wait over 20ms */
-
-	serigo(0x2130);
-	/* Initialize power setting(CPS) */
-	mddi_wait(20);
-	/* Wait over 20ms */
-
-	serigo(0x2132);
-	/* Initialize power setting(CPS) */
-	mddi_wait(10);
-	/* Wait over 10ms */
-
-	serigo(0x2133);
-	/* Initialize power setting(CPS) */
-	mddi_wait(20);
-	/* Wait over 20ms */
-
-	serigo(0x0200);
-	/* Panel initialize release(INIT) */
-	mddi_wait(1);
-	/* Wait over 1ms */
-
-	serigo(0x0131);
-	/* Panel setting(CPS) */
-	mddi_wait(1);
-	/* Wait over 1ms */
-
-	mddi_queue_register_write(REG_PSTCTL1, 0x0003, TRUE, 0);
-
-	/* if (FFA LCD is upside down) -> serigo(0x0100); */
-	serigo(0x0130);
-
-	/* Black mask release(display ON) */
-	mddi_wait(1);
-	/* Wait over 1ms */
-
-	if (mddi_sharp_vsync_wake) {
-		mddi_queue_register_write(REG_VBLKS, 0x1001, TRUE, 0);
-		mddi_queue_register_write(REG_VBLKE, 0x1002, TRUE, 0);
-	}
-
-	/* Set the MDP pixel data attributes for Primary Display */
-	mddi_host_write_pix_attr_reg(0x00C3);
-	return;
-
-}
-
-void mddi_sharp_sub_lcd_init(void)
-{
-
-	mddi_queue_register_write(REG_SYSCTL, 0x4000, FALSE, 0);
-	mddi_queue_register_write(REG_SYSCTL, 0x0000, TRUE, 0);
-	mddi_wait(100);
-
-	mddi_queue_register_write(REG_SYSCTL, 0x0001, FALSE, 0);
-	mddi_queue_register_write(REG_CLKDIV1, 0x000b, FALSE, 0);
-	mddi_queue_register_write(REG_CLKCNF, 0x0708, FALSE, 0);
-	mddi_queue_register_write(REG_SYSCTL, 0x0201, FALSE, 0);
-	mddi_queue_register_write(REG_PTGCTL, 0x0010, FALSE, 0);
-	mddi_queue_register_write(REG_PTHP, 4, FALSE, 0);
-	mddi_queue_register_write(REG_PTHB, 40, FALSE, 0);
-	mddi_queue_register_write(REG_PTHW, 128, FALSE, 0);
-	mddi_queue_register_write(REG_PTHF, 92, FALSE, 0);
-	mddi_queue_register_write(REG_PTVP, 1, FALSE, 0);
-	mddi_queue_register_write(REG_PTVB, 2, FALSE, 0);
-	mddi_queue_register_write(REG_PTVW, 128, FALSE, 0);
-	mddi_queue_register_write(REG_PTVF, 15, FALSE, 0);
-
-	/* Now the sub display..... */
-	/* Reset High */
-	mddi_queue_register_write(REG_SUBCTL, 0x0200, FALSE, 0);
-	/* CS=1,RD=1,WE=1,RS=1 */
-	mddi_queue_register_write(REG_SUBTCMD, 0x000f, TRUE, 0);
-	mddi_wait(1);
-	/* Wait 5us */
-
-	if (sharp_subpanel_type == SHARP_SUB_UNKNOWN) {
-		uint32 data;
-
-		sub_through_write(1, 0x05);
-		sub_through_write(1, 0x6A);
-		sub_through_write(1, 0x1D);
-		sub_through_write(1, 0x05);
-		data = sub_through_read(1);
-		if (data == 0x6A) {
-			sharp_subpanel_type = SHARP_SUB_HYNIX;
-		} else {
-			sub_through_write(0, 0x36);
-			sub_through_write(1, 0xA8);
-			sub_through_write(0, 0x09);
-			data = sub_through_read(1);
-			data = sub_through_read(1);
-			if (data == 0x54) {
-				sub_through_write(0, 0x36);
-				sub_through_write(1, 0x00);
-				sharp_subpanel_type = SHARP_SUB_ROHM;
-			}
-		}
-	}
-
-	if (sharp_subpanel_type == SHARP_SUB_HYNIX) {
-		sub_through_write(1, 0x00);	/* Display setting 1 */
-		sub_through_write(1, 0x04);
-		sub_through_write(1, 0x01);
-		sub_through_write(1, 0x05);
-		sub_through_write(1, 0x0280);
-		sub_through_write(1, 0x0301);
-		sub_through_write(1, 0x0402);
-		sub_through_write(1, 0x0500);
-		sub_through_write(1, 0x0681);
-		sub_through_write(1, 0x077F);
-		sub_through_write(1, 0x08C0);
-		sub_through_write(1, 0x0905);
-		sub_through_write(1, 0x0A02);
-		sub_through_write(1, 0x0B00);
-		sub_through_write(1, 0x0C00);
-		sub_through_write(1, 0x0D00);
-		sub_through_write(1, 0x0E00);
-		sub_through_write(1, 0x0F00);
-
-		sub_through_write(1, 0x100B);	/* Display setting 2 */
-		sub_through_write(1, 0x1103);
-		sub_through_write(1, 0x1237);
-		sub_through_write(1, 0x1300);
-		sub_through_write(1, 0x1400);
-		sub_through_write(1, 0x1500);
-		sub_through_write(1, 0x1605);
-		sub_through_write(1, 0x1700);
-		sub_through_write(1, 0x1800);
-		sub_through_write(1, 0x192E);
-		sub_through_write(1, 0x1A00);
-		sub_through_write(1, 0x1B00);
-		sub_through_write(1, 0x1C00);
-
-		sub_through_write(1, 0x151A);	/* Power setting */
-
-		sub_through_write(1, 0x2002);	/* Gradation Palette setting */
-		sub_through_write(1, 0x2107);
-		sub_through_write(1, 0x220C);
-		sub_through_write(1, 0x2310);
-		sub_through_write(1, 0x2414);
-		sub_through_write(1, 0x2518);
-		sub_through_write(1, 0x261C);
-		sub_through_write(1, 0x2720);
-		sub_through_write(1, 0x2824);
-		sub_through_write(1, 0x2928);
-		sub_through_write(1, 0x2A2B);
-		sub_through_write(1, 0x2B2E);
-		sub_through_write(1, 0x2C31);
-		sub_through_write(1, 0x2D34);
-		sub_through_write(1, 0x2E37);
-		sub_through_write(1, 0x2F3A);
-		sub_through_write(1, 0x303C);
-		sub_through_write(1, 0x313E);
-		sub_through_write(1, 0x323F);
-		sub_through_write(1, 0x3340);
-		sub_through_write(1, 0x3441);
-		sub_through_write(1, 0x3543);
-		sub_through_write(1, 0x3646);
-		sub_through_write(1, 0x3749);
-		sub_through_write(1, 0x384C);
-		sub_through_write(1, 0x394F);
-		sub_through_write(1, 0x3A52);
-		sub_through_write(1, 0x3B59);
-		sub_through_write(1, 0x3C60);
-		sub_through_write(1, 0x3D67);
-		sub_through_write(1, 0x3E6E);
-		sub_through_write(1, 0x3F7F);
-		sub_through_write(1, 0x4001);
-		sub_through_write(1, 0x4107);
-		sub_through_write(1, 0x420C);
-		sub_through_write(1, 0x4310);
-		sub_through_write(1, 0x4414);
-		sub_through_write(1, 0x4518);
-		sub_through_write(1, 0x461C);
-		sub_through_write(1, 0x4720);
-		sub_through_write(1, 0x4824);
-		sub_through_write(1, 0x4928);
-		sub_through_write(1, 0x4A2B);
-		sub_through_write(1, 0x4B2E);
-		sub_through_write(1, 0x4C31);
-		sub_through_write(1, 0x4D34);
-		sub_through_write(1, 0x4E37);
-		sub_through_write(1, 0x4F3A);
-		sub_through_write(1, 0x503C);
-		sub_through_write(1, 0x513E);
-		sub_through_write(1, 0x523F);
-		sub_through_write(1, 0x5340);
-		sub_through_write(1, 0x5441);
-		sub_through_write(1, 0x5543);
-		sub_through_write(1, 0x5646);
-		sub_through_write(1, 0x5749);
-		sub_through_write(1, 0x584C);
-		sub_through_write(1, 0x594F);
-		sub_through_write(1, 0x5A52);
-		sub_through_write(1, 0x5B59);
-		sub_through_write(1, 0x5C60);
-		sub_through_write(1, 0x5D67);
-		sub_through_write(1, 0x5E6E);
-		sub_through_write(1, 0x5F7E);
-		sub_through_write(1, 0x6000);
-		sub_through_write(1, 0x6107);
-		sub_through_write(1, 0x620C);
-		sub_through_write(1, 0x6310);
-		sub_through_write(1, 0x6414);
-		sub_through_write(1, 0x6518);
-		sub_through_write(1, 0x661C);
-		sub_through_write(1, 0x6720);
-		sub_through_write(1, 0x6824);
-		sub_through_write(1, 0x6928);
-		sub_through_write(1, 0x6A2B);
-		sub_through_write(1, 0x6B2E);
-		sub_through_write(1, 0x6C31);
-		sub_through_write(1, 0x6D34);
-		sub_through_write(1, 0x6E37);
-		sub_through_write(1, 0x6F3A);
-		sub_through_write(1, 0x703C);
-		sub_through_write(1, 0x713E);
-		sub_through_write(1, 0x723F);
-		sub_through_write(1, 0x7340);
-		sub_through_write(1, 0x7441);
-		sub_through_write(1, 0x7543);
-		sub_through_write(1, 0x7646);
-		sub_through_write(1, 0x7749);
-		sub_through_write(1, 0x784C);
-		sub_through_write(1, 0x794F);
-		sub_through_write(1, 0x7A52);
-		sub_through_write(1, 0x7B59);
-		sub_through_write(1, 0x7C60);
-		sub_through_write(1, 0x7D67);
-		sub_through_write(1, 0x7E6E);
-		sub_through_write(1, 0x7F7D);
-
-		sub_through_write(1, 0x1851);	/* Display on */
-
-		mddi_queue_register_write(REG_AGM, 0x0000, TRUE, 0);
-
-		/* 1 pixel / 1 post clock */
-		mddi_queue_register_write(REG_CLKDIV2, 0x3b00, FALSE, 0);
-
-		/* SUB LCD select */
-		mddi_queue_register_write(REG_PSTCTL2, 0x0080, FALSE, 0);
-
-		/* RS=0,command initiate number=0,select master mode */
-		mddi_queue_register_write(REG_SUBCTL, 0x0202, FALSE, 0);
-
-		/* Sub LCD Data transform start */
-		mddi_queue_register_write(REG_PSTCTL1, 0x0003, FALSE, 0);
-
-	} else if (sharp_subpanel_type == SHARP_SUB_ROHM) {
-
-		sub_through_write(0, 0x01);	/* Display setting */
-		sub_through_write(1, 0x00);
-
-		mddi_wait(1);
-		/* Wait 100us  <----- ******* Update 2005/01/24 */
-
-		sub_through_write(0, 0xB6);
-		sub_through_write(1, 0x0C);
-		sub_through_write(1, 0x4A);
-		sub_through_write(1, 0x20);
-		sub_through_write(0, 0x3A);
-		sub_through_write(1, 0x05);
-		sub_through_write(0, 0xB7);
-		sub_through_write(1, 0x01);
-		sub_through_write(0, 0xBA);
-		sub_through_write(1, 0x20);
-		sub_through_write(1, 0x02);
-		sub_through_write(0, 0x25);
-		sub_through_write(1, 0x4F);
-		sub_through_write(0, 0xBB);
-		sub_through_write(1, 0x00);
-		sub_through_write(0, 0x36);
-		sub_through_write(1, 0x00);
-		sub_through_write(0, 0xB1);
-		sub_through_write(1, 0x05);
-		sub_through_write(0, 0xBE);
-		sub_through_write(1, 0x80);
-		sub_through_write(0, 0x26);
-		sub_through_write(1, 0x01);
-		sub_through_write(0, 0x2A);
-		sub_through_write(1, 0x02);
-		sub_through_write(1, 0x81);
-		sub_through_write(0, 0x2B);
-		sub_through_write(1, 0x00);
-		sub_through_write(1, 0x7F);
-
-		sub_through_write(0, 0x2C);
-		sub_through_write(0, 0x11);	/* Sleep mode off */
-
-		mddi_wait(1);
-		/* Wait 100 ms <----- ******* Update 2005/01/24 */
-
-		sub_through_write(0, 0x29);	/* Display on */
-		sub_through_write(0, 0xB3);
-		sub_through_write(1, 0x20);
-		sub_through_write(1, 0xAA);
-		sub_through_write(1, 0xA0);
-		sub_through_write(1, 0x20);
-		sub_through_write(1, 0x30);
-		sub_through_write(1, 0xA6);
-		sub_through_write(1, 0xFF);
-		sub_through_write(1, 0x9A);
-		sub_through_write(1, 0x9F);
-		sub_through_write(1, 0xAF);
-		sub_through_write(1, 0xBC);
-		sub_through_write(1, 0xCF);
-		sub_through_write(1, 0xDF);
-		sub_through_write(1, 0x20);
-		sub_through_write(1, 0x9C);
-		sub_through_write(1, 0x8A);
-
-		sub_through_write(0, 0x002C);	/* Display on */
-
-		/* 1 pixel / 2 post clock */
-		mddi_queue_register_write(REG_CLKDIV2, 0x7b00, FALSE, 0);
-
-		/* SUB LCD select */
-		mddi_queue_register_write(REG_PSTCTL2, 0x0080, FALSE, 0);
-
-		/* RS=1,command initiate number=0,select master mode */
-		mddi_queue_register_write(REG_SUBCTL, 0x0242, FALSE, 0);
-
-		/* Sub LCD Data transform start */
-		mddi_queue_register_write(REG_PSTCTL1, 0x0003, FALSE, 0);
-
-	}
-
-	/* Set the MDP pixel data attributes for Sub Display */
-	mddi_host_write_pix_attr_reg(0x00C0);
-}
-
-void mddi_sharp_lcd_vsync_detected(boolean detected)
-{
-	/* static timetick_type start_time = 0; */
-	static struct timeval start_time;
-	static boolean first_time = TRUE;
-	/* uint32 mdp_cnt_val = 0; */
-	/* timetick_type elapsed_us; */
-	struct timeval now;
-	uint32 elapsed_us;
-	uint32 num_vsyncs;
-
-	if ((detected) || (mddi_sharp_vsync_attempts > 5)) {
-		if ((detected) && (mddi_sharp_monitor_refresh_value)) {
-			/* if (start_time != 0) */
-			if (!first_time) {
-				jiffies_to_timeval(jiffies, &now);
-				elapsed_us =
-				    (now.tv_sec - start_time.tv_sec) * 1000000 +
-				    now.tv_usec - start_time.tv_usec;
-				/*
-				* LCD is configured for a refresh every usecs,
-				* so to determine the number of vsyncs that
-				* have occurred since the last measurement add
-				* half that to the time difference and divide
-				* by the refresh rate.
-				*/
-				num_vsyncs = (elapsed_us +
-					      (mddi_sharp_usecs_per_refresh >>
-					       1)) /
-				    mddi_sharp_usecs_per_refresh;
-				/*
-				 * LCD is configured for * hsyncs (rows) per
-				 * refresh cycle. Calculate new rows_per_second
-				 * value based upon these new measurements.
-				 * MDP can update with this new value.
-				 */
-				mddi_sharp_rows_per_second =
-				    (mddi_sharp_rows_per_refresh * 1000 *
-				     num_vsyncs) / (elapsed_us / 1000);
-			}
-			/* start_time = timetick_get(); */
-			first_time = FALSE;
-			jiffies_to_timeval(jiffies, &start_time);
-			if (mddi_sharp_report_refresh_measurements) {
-				/* mdp_cnt_val = MDP_LINE_COUNT; */
-			}
-		}
-		/* if detected = TRUE, client initiated wakeup was detected */
-		if (mddi_sharp_vsync_handler != NULL) {
-			(*mddi_sharp_vsync_handler)
-			    (mddi_sharp_vsync_handler_arg);
-			mddi_sharp_vsync_handler = NULL;
-		}
-		mddi_vsync_detect_enabled = FALSE;
-		mddi_sharp_vsync_attempts = 0;
-		/* need to clear this vsync wakeup */
-		if (!mddi_queue_register_write_int(REG_INTR, 0x0000)) {
-			MDDI_MSG_ERR("Vsync interrupt clear failed!\n");
-		}
-		if (!detected) {
-			/* give up after 5 failed attempts but show error */
-			MDDI_MSG_NOTICE("Vsync detection failed!\n");
-		} else if ((mddi_sharp_monitor_refresh_value) &&
-			(mddi_sharp_report_refresh_measurements)) {
-			MDDI_MSG_NOTICE("  Lines Per Second=%d!\n",
-				mddi_sharp_rows_per_second);
-		}
-	} else
-		/* if detected = FALSE, we woke up from hibernation, but did not
-		 * detect client initiated wakeup.
-		 */
-		mddi_sharp_vsync_attempts++;
-}
-
-/* ISR to be executed */
-void mddi_sharp_vsync_set_handler(msm_fb_vsync_handler_type handler, void *arg)
-{
-	boolean error = FALSE;
-	unsigned long flags;
-
-	/* Disable interrupts */
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-	/* INTLOCK(); */
-
-	if (mddi_sharp_vsync_handler != NULL)
-		error = TRUE;
-
-	/* Register the handler for this particular GROUP interrupt source */
-	mddi_sharp_vsync_handler = handler;
-	mddi_sharp_vsync_handler_arg = arg;
-
-	/* Restore interrupts */
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-	/* INTFREE(); */
-
-	if (error)
-		MDDI_MSG_ERR("MDDI: Previous Vsync handler never called\n");
-
-	/* Enable the vsync wakeup */
-	mddi_queue_register_write(REG_INTR, 0x8100, FALSE, 0);
-
-	mddi_sharp_vsync_attempts = 1;
-	mddi_vsync_detect_enabled = TRUE;
-}				/* mddi_sharp_vsync_set_handler */
-
-static int mddi_sharp_lcd_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	mddi_host_client_cnt_reset();
-
-	if (mfd->panel.id == SHARP_QVGA_PRIM)
-		mddi_sharp_prim_lcd_init();
-	else
-		mddi_sharp_sub_lcd_init();
-
-	return 0;
-}
-
-static int mddi_sharp_lcd_off(struct platform_device *pdev)
-{
-	if (mddi_sharp_vsync_handler != NULL) {
-		(*mddi_sharp_vsync_handler)
-			    (mddi_sharp_vsync_handler_arg);
-		mddi_sharp_vsync_handler = NULL;
-		printk(KERN_INFO "%s: clean up vsyn_handler=%x\n", __func__,
-				(int)mddi_sharp_vsync_handler);
-	}
-
-	mddi_sharp_lcd_powerdown();
-	return 0;
-}
-
-static int __devinit mddi_sharp_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		mddi_sharp_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = mddi_sharp_probe,
-	.driver = {
-		.name   = "mddi_sharp_qvga",
-	},
-};
-
-static struct msm_fb_panel_data mddi_sharp_panel_data0 = {
-	.on = mddi_sharp_lcd_on,
-	.off = mddi_sharp_lcd_off,
-	.set_backlight = mddi_sharp_lcd_set_backlight,
-	.set_vsync_notifier = mddi_sharp_vsync_set_handler,
-};
-
-static struct platform_device this_device_0 = {
-	.name   = "mddi_sharp_qvga",
-	.id	= SHARP_QVGA_PRIM,
-	.dev	= {
-		.platform_data = &mddi_sharp_panel_data0,
-	}
-};
-
-static struct msm_fb_panel_data mddi_sharp_panel_data1 = {
-	.on = mddi_sharp_lcd_on,
-	.off = mddi_sharp_lcd_off,
-};
-
-static struct platform_device this_device_1 = {
-	.name   = "mddi_sharp_qvga",
-	.id	= SHARP_128X128_SECD,
-	.dev	= {
-		.platform_data = &mddi_sharp_panel_data1,
-	}
-};
-
-static int __init mddi_sharp_init(void)
-{
-	int ret;
-	struct msm_panel_info *pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	u32 id;
-
-	ret = msm_fb_detect_client("mddi_sharp_qvga");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret) {
-		id = mddi_get_client_id();
-
-		if (((id >> 16) != 0x0) || ((id & 0xffff) != 0x8835))
-			return 0;
-	}
-#endif
-	if (mddi_host_core_version > 8) {
-		/* can use faster refresh with newer hw revisions */
-		mddi_sharp_debug_60hz_refresh = TRUE;
-
-		/* Timing variables for tracking vsync */
-		/* dot_clock = 6.00MHz
-		 * horizontal count = 296
-		 * vertical count = 338
-		 * refresh rate = 6000000/(296+338) = 60Hz
-		 */
-		mddi_sharp_rows_per_second = 20270;	/* 6000000/296 */
-		mddi_sharp_rows_per_refresh = 338;
-		mddi_sharp_usecs_per_refresh = 16674;	/* (296+338)/6000000 */
-	} else {
-		/* Timing variables for tracking vsync */
-		/* dot_clock = 5.20MHz
-		 * horizontal count = 376
-		 * vertical count = 338
-		 * refresh rate = 5200000/(376+338) = 41Hz
-		 */
-		mddi_sharp_rows_per_second = 13830;	/* 5200000/376 */
-		mddi_sharp_rows_per_refresh = 338;
-		mddi_sharp_usecs_per_refresh = 24440;	/* (376+338)/5200000 */
-	}
-
-	ret = platform_driver_register(&this_driver);
-	if (!ret) {
-		pinfo = &mddi_sharp_panel_data0.panel_info;
-		pinfo->xres = 240;
-		pinfo->yres = 320;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = MDDI_PANEL;
-		pinfo->pdest = DISPLAY_1;
-		pinfo->mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-		pinfo->wait_cycle = 0;
-		pinfo->bpp = 18;
-		pinfo->fb_num = 2;
-		pinfo->clk_rate = 122880000;
-		pinfo->clk_min = 120000000;
-		pinfo->clk_max = 125000000;
-		pinfo->lcd.vsync_enable = TRUE;
-		pinfo->mddi.is_type1 = TRUE;
-		pinfo->lcd.refx100 =
-			(mddi_sharp_rows_per_second * 100) /
-			mddi_sharp_rows_per_refresh;
-		pinfo->lcd.v_back_porch = 12;
-		pinfo->lcd.v_front_porch = 6;
-		pinfo->lcd.v_pulse_width = 0;
-		pinfo->lcd.hw_vsync_mode = FALSE;
-		pinfo->lcd.vsync_notifier_period = (1 * HZ);
-		pinfo->bl_max = 7;
-		pinfo->bl_min = 1;
-
-		ret = platform_device_register(&this_device_0);
-		if (ret)
-			platform_driver_unregister(&this_driver);
-
-		pinfo = &mddi_sharp_panel_data1.panel_info;
-		pinfo->xres = 128;
-		pinfo->yres = 128;
-		MSM_FB_SINGLE_MODE_PANEL(pinfo);
-		pinfo->type = MDDI_PANEL;
-		pinfo->pdest = DISPLAY_2;
-		pinfo->mddi.vdopkt = 0x400;
-		pinfo->wait_cycle = 0;
-		pinfo->bpp = 18;
-		pinfo->clk_rate = 122880000;
-		pinfo->clk_min = 120000000;
-		pinfo->clk_max = 125000000;
-		pinfo->fb_num = 2;
-
-		ret = platform_device_register(&this_device_1);
-		if (ret) {
-			platform_device_unregister(&this_device_0);
-			platform_driver_unregister(&this_driver);
-		}
-	}
-
-	if (!ret)
-		mddi_lcd.vsync_detected = mddi_sharp_lcd_vsync_detected;
-
-	return ret;
-}
-
-module_init(mddi_sharp_init);
diff --git a/drivers/video/msm/mddi_toshiba.c b/drivers/video/msm/mddi_toshiba.c
deleted file mode 100644
index f06a2fd..0000000
--- a/drivers/video/msm/mddi_toshiba.c
+++ /dev/null
@@ -1,1753 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-#include "mddi_toshiba.h"
-
-#define TM_GET_DID(id) ((id) & 0xff)
-#define TM_GET_PID(id) (((id) & 0xff00)>>8)
-
-#define MDDI_CLIENT_CORE_BASE  0x108000
-#define LCD_CONTROL_BLOCK_BASE 0x110000
-#define SPI_BLOCK_BASE         0x120000
-#define PWM_BLOCK_BASE         0x140000
-#define SYSTEM_BLOCK1_BASE     0x160000
-
-#define TTBUSSEL    (MDDI_CLIENT_CORE_BASE|0x18)
-#define DPSET0      (MDDI_CLIENT_CORE_BASE|0x1C)
-#define DPSET1      (MDDI_CLIENT_CORE_BASE|0x20)
-#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
-#define DPRUN       (MDDI_CLIENT_CORE_BASE|0x28)
-#define SYSCKENA    (MDDI_CLIENT_CORE_BASE|0x2C)
-
-#define BITMAP0     (MDDI_CLIENT_CORE_BASE|0x44)
-#define BITMAP1     (MDDI_CLIENT_CORE_BASE|0x48)
-#define BITMAP2     (MDDI_CLIENT_CORE_BASE|0x4C)
-#define BITMAP3     (MDDI_CLIENT_CORE_BASE|0x50)
-#define BITMAP4     (MDDI_CLIENT_CORE_BASE|0x54)
-
-#define SRST        (LCD_CONTROL_BLOCK_BASE|0x00)
-#define PORT_ENB    (LCD_CONTROL_BLOCK_BASE|0x04)
-#define START       (LCD_CONTROL_BLOCK_BASE|0x08)
-#define PORT        (LCD_CONTROL_BLOCK_BASE|0x0C)
-
-#define INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
-#define INTMSK      (LCD_CONTROL_BLOCK_BASE|0x1C)
-#define MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
-
-#define PXL         (LCD_CONTROL_BLOCK_BASE|0x30)
-#define HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
-#define HSW         (LCD_CONTROL_BLOCK_BASE|0x38)
-#define HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
-#define HDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x40)
-#define VCYCLE      (LCD_CONTROL_BLOCK_BASE|0x44)
-#define VSW         (LCD_CONTROL_BLOCK_BASE|0x48)
-#define VDE_START   (LCD_CONTROL_BLOCK_BASE|0x4C)
-#define VDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x50)
-#define WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
-#define REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
-#define VSYNIF      (LCD_CONTROL_BLOCK_BASE|0x60)
-#define WRSTB       (LCD_CONTROL_BLOCK_BASE|0x64)
-#define RDSTB       (LCD_CONTROL_BLOCK_BASE|0x68)
-#define ASY_DATA    (LCD_CONTROL_BLOCK_BASE|0x6C)
-#define ASY_DATB    (LCD_CONTROL_BLOCK_BASE|0x70)
-#define ASY_DATC    (LCD_CONTROL_BLOCK_BASE|0x74)
-#define ASY_DATD    (LCD_CONTROL_BLOCK_BASE|0x78)
-#define ASY_DATE    (LCD_CONTROL_BLOCK_BASE|0x7C)
-#define ASY_DATF    (LCD_CONTROL_BLOCK_BASE|0x80)
-#define ASY_DATG    (LCD_CONTROL_BLOCK_BASE|0x84)
-#define ASY_DATH    (LCD_CONTROL_BLOCK_BASE|0x88)
-#define ASY_CMDSET  (LCD_CONTROL_BLOCK_BASE|0x8C)
-#define MONI        (LCD_CONTROL_BLOCK_BASE|0xB0)
-#define VPOS        (LCD_CONTROL_BLOCK_BASE|0xC0)
-
-#define SSICTL      (SPI_BLOCK_BASE|0x00)
-#define SSITIME     (SPI_BLOCK_BASE|0x04)
-#define SSITX       (SPI_BLOCK_BASE|0x08)
-#define SSIINTS     (SPI_BLOCK_BASE|0x14)
-
-#define TIMER0LOAD    (PWM_BLOCK_BASE|0x00)
-#define TIMER0CTRL    (PWM_BLOCK_BASE|0x08)
-#define PWM0OFF       (PWM_BLOCK_BASE|0x1C)
-#define TIMER1LOAD    (PWM_BLOCK_BASE|0x20)
-#define TIMER1CTRL    (PWM_BLOCK_BASE|0x28)
-#define PWM1OFF       (PWM_BLOCK_BASE|0x3C)
-#define TIMER2LOAD    (PWM_BLOCK_BASE|0x40)
-#define TIMER2CTRL    (PWM_BLOCK_BASE|0x48)
-#define PWM2OFF       (PWM_BLOCK_BASE|0x5C)
-#define PWMCR         (PWM_BLOCK_BASE|0x68)
-
-#define GPIOIS      (GPIO_BLOCK_BASE|0x08)
-#define GPIOIEV     (GPIO_BLOCK_BASE|0x10)
-#define GPIOIC      (GPIO_BLOCK_BASE|0x20)
-
-#define WKREQ       (SYSTEM_BLOCK1_BASE|0x00)
-#define CLKENB      (SYSTEM_BLOCK1_BASE|0x04)
-#define DRAMPWR     (SYSTEM_BLOCK1_BASE|0x08)
-#define INTMASK     (SYSTEM_BLOCK1_BASE|0x0C)
-#define CNT_DIS     (SYSTEM_BLOCK1_BASE|0x10)
-
-typedef enum {
-	TOSHIBA_STATE_OFF,
-	TOSHIBA_STATE_PRIM_SEC_STANDBY,
-	TOSHIBA_STATE_PRIM_SEC_READY,
-	TOSHIBA_STATE_PRIM_NORMAL_MODE,
-	TOSHIBA_STATE_SEC_NORMAL_MODE
-} mddi_toshiba_state_t;
-
-static uint32 mddi_toshiba_curr_vpos;
-static boolean mddi_toshiba_monitor_refresh_value = FALSE;
-static boolean mddi_toshiba_report_refresh_measurements = FALSE;
-
-boolean mddi_toshiba_61Hz_refresh = TRUE;
-
-/* Modifications to timing to increase refresh rate to > 60Hz.
- *   20MHz dot clock.
- *   646 total rows.
- *   506 total columns.
- *   refresh rate = 61.19Hz
- */
-static uint32 mddi_toshiba_rows_per_second = 39526;
-static uint32 mddi_toshiba_usecs_per_refresh = 16344;
-static uint32 mddi_toshiba_rows_per_refresh = 646;
-extern boolean mddi_vsync_detect_enabled;
-
-static msm_fb_vsync_handler_type mddi_toshiba_vsync_handler;
-static void *mddi_toshiba_vsync_handler_arg;
-static uint16 mddi_toshiba_vsync_attempts;
-
-static mddi_toshiba_state_t toshiba_state = TOSHIBA_STATE_OFF;
-
-static struct msm_panel_common_pdata *mddi_toshiba_pdata;
-
-static int mddi_toshiba_lcd_on(struct platform_device *pdev);
-static int mddi_toshiba_lcd_off(struct platform_device *pdev);
-
-static void mddi_toshiba_state_transition(mddi_toshiba_state_t a,
-					  mddi_toshiba_state_t b)
-{
-	if (toshiba_state != a) {
-		MDDI_MSG_ERR("toshiba state trans. (%d->%d) found %d\n", a, b,
-			     toshiba_state);
-	}
-	toshiba_state = b;
-}
-
-#define GORDON_REG_IMGCTL1      0x10	/* Image interface control 1   */
-#define GORDON_REG_IMGCTL2      0x11	/* Image interface control 2   */
-#define GORDON_REG_IMGSET1      0x12	/* Image interface settings 1  */
-#define GORDON_REG_IMGSET2      0x13	/* Image interface settings 2  */
-#define GORDON_REG_IVBP1        0x14	/* DM0: Vert back porch        */
-#define GORDON_REG_IHBP1        0x15	/* DM0: Horiz back porch       */
-#define GORDON_REG_IVNUM1       0x16	/* DM0: Num of vert lines      */
-#define GORDON_REG_IHNUM1       0x17	/* DM0: Num of pixels per line */
-#define GORDON_REG_IVBP2        0x18	/* DM1: Vert back porch        */
-#define GORDON_REG_IHBP2        0x19	/* DM1: Horiz back porch       */
-#define GORDON_REG_IVNUM2       0x1A	/* DM1: Num of vert lines      */
-#define GORDON_REG_IHNUM2       0x1B	/* DM1: Num of pixels per line */
-#define GORDON_REG_LCDIFCTL1    0x30	/* LCD interface control 1     */
-#define GORDON_REG_VALTRAN      0x31	/* LCD IF ctl: VALTRAN sync flag */
-#define GORDON_REG_AVCTL        0x33
-#define GORDON_REG_LCDIFCTL2    0x34	/* LCD interface control 2     */
-#define GORDON_REG_LCDIFCTL3    0x35	/* LCD interface control 3     */
-#define GORDON_REG_LCDIFSET1    0x36	/* LCD interface settings 1    */
-#define GORDON_REG_PCCTL        0x3C
-#define GORDON_REG_TPARAM1      0x40
-#define GORDON_REG_TLCDIF1      0x41
-#define GORDON_REG_TSSPB_ST1    0x42
-#define GORDON_REG_TSSPB_ED1    0x43
-#define GORDON_REG_TSCK_ST1     0x44
-#define GORDON_REG_TSCK_WD1     0x45
-#define GORDON_REG_TGSPB_VST1   0x46
-#define GORDON_REG_TGSPB_VED1   0x47
-#define GORDON_REG_TGSPB_CH1    0x48
-#define GORDON_REG_TGCK_ST1     0x49
-#define GORDON_REG_TGCK_ED1     0x4A
-#define GORDON_REG_TPCTL_ST1    0x4B
-#define GORDON_REG_TPCTL_ED1    0x4C
-#define GORDON_REG_TPCHG_ED1    0x4D
-#define GORDON_REG_TCOM_CH1     0x4E
-#define GORDON_REG_THBP1        0x4F
-#define GORDON_REG_TPHCTL1      0x50
-#define GORDON_REG_EVPH1        0x51
-#define GORDON_REG_EVPL1        0x52
-#define GORDON_REG_EVNH1        0x53
-#define GORDON_REG_EVNL1        0x54
-#define GORDON_REG_TBIAS1       0x55
-#define GORDON_REG_TPARAM2      0x56
-#define GORDON_REG_TLCDIF2      0x57
-#define GORDON_REG_TSSPB_ST2    0x58
-#define GORDON_REG_TSSPB_ED2    0x59
-#define GORDON_REG_TSCK_ST2     0x5A
-#define GORDON_REG_TSCK_WD2     0x5B
-#define GORDON_REG_TGSPB_VST2   0x5C
-#define GORDON_REG_TGSPB_VED2   0x5D
-#define GORDON_REG_TGSPB_CH2    0x5E
-#define GORDON_REG_TGCK_ST2     0x5F
-#define GORDON_REG_TGCK_ED2     0x60
-#define GORDON_REG_TPCTL_ST2    0x61
-#define GORDON_REG_TPCTL_ED2    0x62
-#define GORDON_REG_TPCHG_ED2    0x63
-#define GORDON_REG_TCOM_CH2     0x64
-#define GORDON_REG_THBP2        0x65
-#define GORDON_REG_TPHCTL2      0x66
-#define GORDON_REG_EVPH2        0x67
-#define GORDON_REG_EVPL2        0x68
-#define GORDON_REG_EVNH2        0x69
-#define GORDON_REG_EVNL2        0x6A
-#define GORDON_REG_TBIAS2       0x6B
-#define GORDON_REG_POWCTL       0x80
-#define GORDON_REG_POWOSC1      0x81
-#define GORDON_REG_POWOSC2      0x82
-#define GORDON_REG_POWSET       0x83
-#define GORDON_REG_POWTRM1      0x85
-#define GORDON_REG_POWTRM2      0x86
-#define GORDON_REG_POWTRM3      0x87
-#define GORDON_REG_POWTRMSEL    0x88
-#define GORDON_REG_POWHIZ       0x89
-
-void serigo(uint16 reg, uint8 data)
-{
-	uint32 mddi_val = 0;
-	mddi_queue_register_read(SSIINTS, &mddi_val, TRUE, 0);
-	if (mddi_val & (1 << 8))
-		mddi_wait(1);
-	/* No De-assert of CS and send 2 bytes */
-	mddi_val = 0x90000 | ((0x00FF & reg) << 8) | data;
-	mddi_queue_register_write(SSITX, mddi_val, TRUE, 0);
-}
-
-void gordon_init(void)
-{
-       /* Image interface settings ***/
-	serigo(GORDON_REG_IMGCTL2, 0x00);
-	serigo(GORDON_REG_IMGSET1, 0x01);
-
-	/* Exchange the RGB signal for J510(Softbank mobile) */
-	serigo(GORDON_REG_IMGSET2, 0x12);
-	serigo(GORDON_REG_LCDIFSET1, 0x00);
-	mddi_wait(2);
-
-	/* Pre-charge settings */
-	serigo(GORDON_REG_PCCTL, 0x09);
-	serigo(GORDON_REG_LCDIFCTL2, 0x1B);
-	mddi_wait(1);
-}
-
-void gordon_disp_on(void)
-{
-	/*gordon_dispmode setting */
-	/*VGA settings */
-	serigo(GORDON_REG_TPARAM1, 0x30);
-	serigo(GORDON_REG_TLCDIF1, 0x00);
-	serigo(GORDON_REG_TSSPB_ST1, 0x8B);
-	serigo(GORDON_REG_TSSPB_ED1, 0x93);
-	mddi_wait(2);
-	serigo(GORDON_REG_TSCK_ST1, 0x88);
-	serigo(GORDON_REG_TSCK_WD1, 0x00);
-	serigo(GORDON_REG_TGSPB_VST1, 0x01);
-	serigo(GORDON_REG_TGSPB_VED1, 0x02);
-	mddi_wait(2);
-	serigo(GORDON_REG_TGSPB_CH1, 0x5E);
-	serigo(GORDON_REG_TGCK_ST1, 0x80);
-	serigo(GORDON_REG_TGCK_ED1, 0x3C);
-	serigo(GORDON_REG_TPCTL_ST1, 0x50);
-	mddi_wait(2);
-	serigo(GORDON_REG_TPCTL_ED1, 0x74);
-	serigo(GORDON_REG_TPCHG_ED1, 0x78);
-	serigo(GORDON_REG_TCOM_CH1, 0x50);
-	serigo(GORDON_REG_THBP1, 0x84);
-	mddi_wait(2);
-	serigo(GORDON_REG_TPHCTL1, 0x00);
-	serigo(GORDON_REG_EVPH1, 0x70);
-	serigo(GORDON_REG_EVPL1, 0x64);
-	serigo(GORDON_REG_EVNH1, 0x56);
-	mddi_wait(2);
-	serigo(GORDON_REG_EVNL1, 0x48);
-	serigo(GORDON_REG_TBIAS1, 0x88);
-	mddi_wait(2);
-	serigo(GORDON_REG_TPARAM2, 0x28);
-	serigo(GORDON_REG_TLCDIF2, 0x14);
-	serigo(GORDON_REG_TSSPB_ST2, 0x49);
-	serigo(GORDON_REG_TSSPB_ED2, 0x4B);
-	mddi_wait(2);
-	serigo(GORDON_REG_TSCK_ST2, 0x4A);
-	serigo(GORDON_REG_TSCK_WD2, 0x02);
-	serigo(GORDON_REG_TGSPB_VST2, 0x02);
-	serigo(GORDON_REG_TGSPB_VED2, 0x03);
-	mddi_wait(2);
-	serigo(GORDON_REG_TGSPB_CH2, 0x2F);
-	serigo(GORDON_REG_TGCK_ST2, 0x40);
-	serigo(GORDON_REG_TGCK_ED2, 0x1E);
-	serigo(GORDON_REG_TPCTL_ST2, 0x2C);
-	mddi_wait(2);
-	serigo(GORDON_REG_TPCTL_ED2, 0x3A);
-	serigo(GORDON_REG_TPCHG_ED2, 0x3C);
-	serigo(GORDON_REG_TCOM_CH2, 0x28);
-	serigo(GORDON_REG_THBP2, 0x4D);
-	mddi_wait(2);
-	serigo(GORDON_REG_TPHCTL2, 0x1A);
-	mddi_wait(2);
-	serigo(GORDON_REG_IVBP1, 0x02);
-	serigo(GORDON_REG_IHBP1, 0x90);
-	serigo(GORDON_REG_IVNUM1, 0xA0);
-	serigo(GORDON_REG_IHNUM1, 0x78);
-	mddi_wait(2);
-	serigo(GORDON_REG_IVBP2, 0x02);
-	serigo(GORDON_REG_IHBP2, 0x48);
-	serigo(GORDON_REG_IVNUM2, 0x50);
-	serigo(GORDON_REG_IHNUM2, 0x3C);
-	mddi_wait(2);
-	serigo(GORDON_REG_POWCTL, 0x03);
-	mddi_wait(15);
-	serigo(GORDON_REG_POWCTL, 0x07);
-	mddi_wait(15);
-	serigo(GORDON_REG_POWCTL, 0x0F);
-	mddi_wait(15);
-	serigo(GORDON_REG_AVCTL, 0x03);
-	mddi_wait(15);
-	serigo(GORDON_REG_POWCTL, 0x1F);
-	mddi_wait(15);
-	serigo(GORDON_REG_POWCTL, 0x5F);
-	mddi_wait(15);
-	serigo(GORDON_REG_POWCTL, 0x7F);
-	mddi_wait(15);
-	serigo(GORDON_REG_LCDIFCTL1, 0x02);
-	mddi_wait(15);
-	serigo(GORDON_REG_IMGCTL1, 0x00);
-	mddi_wait(15);
-	serigo(GORDON_REG_LCDIFCTL3, 0x00);
-	mddi_wait(15);
-	serigo(GORDON_REG_VALTRAN, 0x01);
-	mddi_wait(15);
-	serigo(GORDON_REG_LCDIFCTL1, 0x03);
-	serigo(GORDON_REG_LCDIFCTL1, 0x03);
-	mddi_wait(1);
-}
-
-void gordon_disp_off(void)
-{
-	serigo(GORDON_REG_LCDIFCTL2, 0x7B);
-	serigo(GORDON_REG_VALTRAN, 0x01);
-	serigo(GORDON_REG_LCDIFCTL1, 0x02);
-	serigo(GORDON_REG_LCDIFCTL3, 0x01);
-	mddi_wait(20);
-	serigo(GORDON_REG_VALTRAN, 0x01);
-	serigo(GORDON_REG_IMGCTL1, 0x01);
-	serigo(GORDON_REG_LCDIFCTL1, 0x00);
-	mddi_wait(20);
-	serigo(GORDON_REG_POWCTL, 0x1F);
-	mddi_wait(40);
-	serigo(GORDON_REG_POWCTL, 0x07);
-	mddi_wait(40);
-	serigo(GORDON_REG_POWCTL, 0x03);
-	mddi_wait(40);
-	serigo(GORDON_REG_POWCTL, 0x00);
-	mddi_wait(40);
-}
-
-void gordon_disp_init(void)
-{
-	gordon_init();
-	mddi_wait(20);
-	gordon_disp_on();
-}
-
-static void toshiba_common_initial_setup(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT) {
-		write_client_reg(DPSET0    , 0x4bec0066, TRUE);
-		write_client_reg(DPSET1    , 0x00000113, TRUE);
-		write_client_reg(DPSUS     , 0x00000000, TRUE);
-		write_client_reg(DPRUN     , 0x00000001, TRUE);
-		mddi_wait(5);
-		write_client_reg(SYSCKENA  , 0x00000001, TRUE);
-		write_client_reg(CLKENB    , 0x0000a0e9, TRUE);
-
-		write_client_reg(GPIODATA  , 0x03FF0000, TRUE);
-		write_client_reg(GPIODIR   , 0x0000024D, TRUE);
-		write_client_reg(GPIOSEL   , 0x00000173, TRUE);
-		write_client_reg(GPIOPC    , 0x03C300C0, TRUE);
-		write_client_reg(WKREQ     , 0x00000000, TRUE);
-		write_client_reg(GPIOIS    , 0x00000000, TRUE);
-		write_client_reg(GPIOIEV   , 0x00000001, TRUE);
-		write_client_reg(GPIOIC    , 0x000003FF, TRUE);
-		write_client_reg(GPIODATA  , 0x00040004, TRUE);
-
-		write_client_reg(GPIODATA  , 0x00080008, TRUE);
-		write_client_reg(DRAMPWR   , 0x00000001, TRUE);
-		write_client_reg(CLKENB    , 0x0000a0eb, TRUE);
-		write_client_reg(PWMCR     , 0x00000000, TRUE);
-		mddi_wait(1);
-
-		write_client_reg(SSICTL    , 0x00060399, TRUE);
-		write_client_reg(SSITIME   , 0x00000100, TRUE);
-		write_client_reg(CNT_DIS   , 0x00000002, TRUE);
-		write_client_reg(SSICTL    , 0x0006039b, TRUE);
-
-		write_client_reg(SSITX     , 0x00000000, TRUE);
-		mddi_wait(7);
-		write_client_reg(SSITX     , 0x00000000, TRUE);
-		mddi_wait(7);
-		write_client_reg(SSITX     , 0x00000000, TRUE);
-		mddi_wait(7);
-
-		write_client_reg(SSITX     , 0x000800BA, TRUE);
-		write_client_reg(SSITX     , 0x00000111, TRUE);
-		write_client_reg(SSITX     , 0x00080036, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x0008003A, TRUE);
-		write_client_reg(SSITX     , 0x00000160, TRUE);
-		write_client_reg(SSITX     , 0x000800B1, TRUE);
-		write_client_reg(SSITX     , 0x0000015D, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B2, TRUE);
-		write_client_reg(SSITX     , 0x00000133, TRUE);
-		write_client_reg(SSITX     , 0x000800B3, TRUE);
-		write_client_reg(SSITX     , 0x00000122, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B4, TRUE);
-		write_client_reg(SSITX     , 0x00000102, TRUE);
-		write_client_reg(SSITX     , 0x000800B5, TRUE);
-		write_client_reg(SSITX     , 0x0000011E, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B6, TRUE);
-		write_client_reg(SSITX     , 0x00000127, TRUE);
-		write_client_reg(SSITX     , 0x000800B7, TRUE);
-		write_client_reg(SSITX     , 0x00000103, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B9, TRUE);
-		write_client_reg(SSITX     , 0x00000124, TRUE);
-		write_client_reg(SSITX     , 0x000800BD, TRUE);
-		write_client_reg(SSITX     , 0x000001A1, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800BB, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		write_client_reg(SSITX     , 0x000800BF, TRUE);
-		write_client_reg(SSITX     , 0x00000101, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800BE, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		write_client_reg(SSITX     , 0x000800C0, TRUE);
-		write_client_reg(SSITX     , 0x00000111, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C1, TRUE);
-		write_client_reg(SSITX     , 0x00000111, TRUE);
-		write_client_reg(SSITX     , 0x000800C2, TRUE);
-		write_client_reg(SSITX     , 0x00000111, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C3, TRUE);
-		write_client_reg(SSITX     , 0x00080132, TRUE);
-		write_client_reg(SSITX     , 0x00000132, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C4, TRUE);
-		write_client_reg(SSITX     , 0x00080132, TRUE);
-		write_client_reg(SSITX     , 0x00000132, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C5, TRUE);
-		write_client_reg(SSITX     , 0x00080132, TRUE);
-		write_client_reg(SSITX     , 0x00000132, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C6, TRUE);
-		write_client_reg(SSITX     , 0x00080132, TRUE);
-		write_client_reg(SSITX     , 0x00000132, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C7, TRUE);
-		write_client_reg(SSITX     , 0x00080164, TRUE);
-		write_client_reg(SSITX     , 0x00000145, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800C8, TRUE);
-		write_client_reg(SSITX     , 0x00000144, TRUE);
-		write_client_reg(SSITX     , 0x000800C9, TRUE);
-		write_client_reg(SSITX     , 0x00000152, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800CA, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800EC, TRUE);
-		write_client_reg(SSITX     , 0x00080101, TRUE);
-		write_client_reg(SSITX     , 0x000001FC, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800CF, TRUE);
-		write_client_reg(SSITX     , 0x00000101, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D0, TRUE);
-		write_client_reg(SSITX     , 0x00080110, TRUE);
-		write_client_reg(SSITX     , 0x00000104, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D1, TRUE);
-		write_client_reg(SSITX     , 0x00000101, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D2, TRUE);
-		write_client_reg(SSITX     , 0x00080100, TRUE);
-		write_client_reg(SSITX     , 0x00000128, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D3, TRUE);
-		write_client_reg(SSITX     , 0x00080100, TRUE);
-		write_client_reg(SSITX     , 0x00000128, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D4, TRUE);
-		write_client_reg(SSITX     , 0x00080126, TRUE);
-		write_client_reg(SSITX     , 0x000001A4, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800D5, TRUE);
-		write_client_reg(SSITX     , 0x00000120, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800EF, TRUE);
-		write_client_reg(SSITX     , 0x00080132, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		mddi_wait(1);
-
-		write_client_reg(BITMAP0   , 0x032001E0, TRUE);
-		write_client_reg(BITMAP1   , 0x032001E0, TRUE);
-		write_client_reg(BITMAP2   , 0x014000F0, TRUE);
-		write_client_reg(BITMAP3   , 0x014000F0, TRUE);
-		write_client_reg(BITMAP4   , 0x014000F0, TRUE);
-		write_client_reg(CLKENB    , 0x0000A1EB, TRUE);
-		write_client_reg(PORT_ENB  , 0x00000001, TRUE);
-		write_client_reg(PORT      , 0x00000004, TRUE);
-		write_client_reg(PXL       , 0x00000002, TRUE);
-		write_client_reg(MPLFBUF   , 0x00000000, TRUE);
-		write_client_reg(HCYCLE    , 0x000000FD, TRUE);
-		write_client_reg(HSW       , 0x00000003, TRUE);
-		write_client_reg(HDE_START , 0x00000007, TRUE);
-		write_client_reg(HDE_SIZE  , 0x000000EF, TRUE);
-		write_client_reg(VCYCLE    , 0x00000325, TRUE);
-		write_client_reg(VSW       , 0x00000001, TRUE);
-		write_client_reg(VDE_START , 0x00000003, TRUE);
-		write_client_reg(VDE_SIZE  , 0x0000031F, TRUE);
-		write_client_reg(START     , 0x00000001, TRUE);
-		mddi_wait(32);
-		write_client_reg(SSITX     , 0x000800BC, TRUE);
-		write_client_reg(SSITX     , 0x00000180, TRUE);
-		write_client_reg(SSITX     , 0x0008003B, TRUE);
-		write_client_reg(SSITX     , 0x00000100, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B0, TRUE);
-		write_client_reg(SSITX     , 0x00000116, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x000800B8, TRUE);
-		write_client_reg(SSITX     , 0x000801FF, TRUE);
-		write_client_reg(SSITX     , 0x000001F5, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX     , 0x00000011, TRUE);
-		mddi_wait(5);
-		write_client_reg(SSITX     , 0x00000029, TRUE);
-		return;
-	}
-
-	if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) {
-		write_client_reg(DPSET0, 0x4BEC0066, TRUE);
-		write_client_reg(DPSET1, 0x00000113, TRUE);
-		write_client_reg(DPSUS, 0x00000000, TRUE);
-		write_client_reg(DPRUN, 0x00000001, TRUE);
-		mddi_wait(14);
-		write_client_reg(SYSCKENA, 0x00000001, TRUE);
-		write_client_reg(CLKENB, 0x000000EF, TRUE);
-		write_client_reg(GPIO_BLOCK_BASE, 0x03FF0000, TRUE);
-		write_client_reg(GPIODIR, 0x0000024D, TRUE);
-		write_client_reg(SYSTEM_BLOCK2_BASE, 0x00000173, TRUE);
-		write_client_reg(GPIOPC, 0x03C300C0, TRUE);
-		write_client_reg(SYSTEM_BLOCK1_BASE, 0x00000000, TRUE);
-		write_client_reg(GPIOIS, 0x00000000, TRUE);
-		write_client_reg(GPIOIEV, 0x00000001, TRUE);
-		write_client_reg(GPIOIC, 0x000003FF, TRUE);
-		write_client_reg(GPIO_BLOCK_BASE, 0x00060006, TRUE);
-		write_client_reg(GPIO_BLOCK_BASE, 0x00080008, TRUE);
-		write_client_reg(GPIO_BLOCK_BASE, 0x02000200, TRUE);
-		write_client_reg(DRAMPWR, 0x00000001, TRUE);
-		write_client_reg(TIMER0CTRL, 0x00000060, TRUE);
-		write_client_reg(PWM_BLOCK_BASE, 0x00001388, TRUE);
-		write_client_reg(PWM0OFF, 0x00001387, TRUE);
-		write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
-		write_client_reg(TIMER1LOAD, 0x00001388, TRUE);
-		write_client_reg(PWM1OFF, 0x00001387, TRUE);
-		write_client_reg(TIMER0CTRL, 0x000000E0, TRUE);
-		write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
-		write_client_reg(PWMCR, 0x00000003, TRUE);
-		mddi_wait(1);
-		write_client_reg(SPI_BLOCK_BASE, 0x00063111, TRUE);
-		write_client_reg(SSITIME, 0x00000100, TRUE);
-		write_client_reg(SPI_BLOCK_BASE, 0x00063113, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(CLKENB, 0x0000A1EF, TRUE);
-		write_client_reg(START, 0x00000000, TRUE);
-		write_client_reg(WRSTB, 0x0000003F, TRUE);
-		write_client_reg(RDSTB, 0x00000432, TRUE);
-		write_client_reg(PORT_ENB, 0x00000002, TRUE);
-		write_client_reg(VSYNIF, 0x00000000, TRUE);
-		write_client_reg(ASY_DATA, 0x80000000, TRUE);
-		write_client_reg(ASY_DATB, 0x00000001, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-		mddi_wait(10);
-		write_client_reg(ASY_DATA, 0x80000000, TRUE);
-		write_client_reg(ASY_DATB, 0x80000000, TRUE);
-		write_client_reg(ASY_DATC, 0x80000000, TRUE);
-		write_client_reg(ASY_DATD, 0x80000000, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000009, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000008, TRUE);
-		write_client_reg(ASY_DATA, 0x80000007, TRUE);
-		write_client_reg(ASY_DATB, 0x00004005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-		mddi_wait(20);
-		write_client_reg(ASY_DATA, 0x80000059, TRUE);
-		write_client_reg(ASY_DATB, 0x00000000, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-
-		write_client_reg(VSYNIF, 0x00000001, TRUE);
-		write_client_reg(PORT_ENB, 0x00000001, TRUE);
-	} else {
-		write_client_reg(DPSET0, 0x4BEC0066, TRUE);
-		write_client_reg(DPSET1, 0x00000113, TRUE);
-		write_client_reg(DPSUS, 0x00000000, TRUE);
-		write_client_reg(DPRUN, 0x00000001, TRUE);
-		mddi_wait(14);
-		write_client_reg(SYSCKENA, 0x00000001, TRUE);
-		write_client_reg(CLKENB, 0x000000EF, TRUE);
-		write_client_reg(GPIODATA, 0x03FF0000, TRUE);
-		write_client_reg(GPIODIR, 0x0000024D, TRUE);
-		write_client_reg(GPIOSEL, 0x00000173, TRUE);
-		write_client_reg(GPIOPC, 0x03C300C0, TRUE);
-		write_client_reg(WKREQ, 0x00000000, TRUE);
-		write_client_reg(GPIOIS, 0x00000000, TRUE);
-		write_client_reg(GPIOIEV, 0x00000001, TRUE);
-		write_client_reg(GPIOIC, 0x000003FF, TRUE);
-		write_client_reg(GPIODATA, 0x00060006, TRUE);
-		write_client_reg(GPIODATA, 0x00080008, TRUE);
-		write_client_reg(GPIODATA, 0x02000200, TRUE);
-
-		if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA) {
-			mddi_wait(400);
-			write_client_reg(DRAMPWR, 0x00000001, TRUE);
-
-			write_client_reg(CNT_DIS, 0x00000002, TRUE);
-			write_client_reg(BITMAP0, 0x01E00320, TRUE);
-			write_client_reg(PORT_ENB, 0x00000001, TRUE);
-			write_client_reg(PORT, 0x00000004, TRUE);
-			write_client_reg(PXL, 0x0000003A, TRUE);
-			write_client_reg(MPLFBUF, 0x00000000, TRUE);
-			write_client_reg(HCYCLE, 0x00000253, TRUE);
-			write_client_reg(HSW, 0x00000003, TRUE);
-			write_client_reg(HDE_START, 0x00000017, TRUE);
-			write_client_reg(HDE_SIZE, 0x0000018F, TRUE);
-			write_client_reg(VCYCLE, 0x000001FF, TRUE);
-			write_client_reg(VSW, 0x00000001, TRUE);
-			write_client_reg(VDE_START, 0x00000003, TRUE);
-			write_client_reg(VDE_SIZE, 0x000001DF, TRUE);
-			write_client_reg(START, 0x00000001, TRUE);
-			mddi_wait(1);
-			write_client_reg(TIMER0CTRL, 0x00000060, TRUE);
-			write_client_reg(TIMER0LOAD, 0x00001388, TRUE);
-			write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
-			write_client_reg(TIMER1LOAD, 0x00001388, TRUE);
-			write_client_reg(PWM1OFF, 0x00000087, TRUE);
-		} else {
-			write_client_reg(DRAMPWR, 0x00000001, TRUE);
-			write_client_reg(TIMER0CTRL, 0x00000060, TRUE);
-			write_client_reg(TIMER0LOAD, 0x00001388, TRUE);
-			write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
-			write_client_reg(TIMER1LOAD, 0x00001388, TRUE);
-			write_client_reg(PWM1OFF, 0x00001387, TRUE);
-		}
-
-		write_client_reg(TIMER0CTRL, 0x000000E0, TRUE);
-		write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
-		write_client_reg(PWMCR, 0x00000003, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSICTL, 0x00000799, TRUE);
-		write_client_reg(SSITIME, 0x00000100, TRUE);
-		write_client_reg(SSICTL, 0x0000079b, TRUE);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000000, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x000800BA, TRUE);
-		write_client_reg(SSITX, 0x00000111, TRUE);
-		write_client_reg(SSITX, 0x00080036, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800BB, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		write_client_reg(SSITX, 0x0008003A, TRUE);
-		write_client_reg(SSITX, 0x00000160, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800BF, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		write_client_reg(SSITX, 0x000800B1, TRUE);
-		write_client_reg(SSITX, 0x0000015D, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800B2, TRUE);
-		write_client_reg(SSITX, 0x00000133, TRUE);
-		write_client_reg(SSITX, 0x000800B3, TRUE);
-		write_client_reg(SSITX, 0x00000122, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800B4, TRUE);
-		write_client_reg(SSITX, 0x00000102, TRUE);
-		write_client_reg(SSITX, 0x000800B5, TRUE);
-		write_client_reg(SSITX, 0x0000011F, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800B6, TRUE);
-		write_client_reg(SSITX, 0x00000128, TRUE);
-		write_client_reg(SSITX, 0x000800B7, TRUE);
-		write_client_reg(SSITX, 0x00000103, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800B9, TRUE);
-		write_client_reg(SSITX, 0x00000120, TRUE);
-		write_client_reg(SSITX, 0x000800BD, TRUE);
-		write_client_reg(SSITX, 0x00000102, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800BE, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		write_client_reg(SSITX, 0x000800C0, TRUE);
-		write_client_reg(SSITX, 0x00000111, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C1, TRUE);
-		write_client_reg(SSITX, 0x00000111, TRUE);
-		write_client_reg(SSITX, 0x000800C2, TRUE);
-		write_client_reg(SSITX, 0x00000111, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C3, TRUE);
-		write_client_reg(SSITX, 0x0008010A, TRUE);
-		write_client_reg(SSITX, 0x0000010A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C4, TRUE);
-		write_client_reg(SSITX, 0x00080160, TRUE);
-		write_client_reg(SSITX, 0x00000160, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C5, TRUE);
-		write_client_reg(SSITX, 0x00080160, TRUE);
-		write_client_reg(SSITX, 0x00000160, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C6, TRUE);
-		write_client_reg(SSITX, 0x00080160, TRUE);
-		write_client_reg(SSITX, 0x00000160, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C7, TRUE);
-		write_client_reg(SSITX, 0x00080133, TRUE);
-		write_client_reg(SSITX, 0x00000143, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800C8, TRUE);
-		write_client_reg(SSITX, 0x00000144, TRUE);
-		write_client_reg(SSITX, 0x000800C9, TRUE);
-		write_client_reg(SSITX, 0x00000133, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800CA, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800EC, TRUE);
-		write_client_reg(SSITX, 0x00080102, TRUE);
-		write_client_reg(SSITX, 0x00000118, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800CF, TRUE);
-		write_client_reg(SSITX, 0x00000101, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D0, TRUE);
-		write_client_reg(SSITX, 0x00080110, TRUE);
-		write_client_reg(SSITX, 0x00000104, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D1, TRUE);
-		write_client_reg(SSITX, 0x00000101, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D2, TRUE);
-		write_client_reg(SSITX, 0x00080100, TRUE);
-		write_client_reg(SSITX, 0x0000013A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D3, TRUE);
-		write_client_reg(SSITX, 0x00080100, TRUE);
-		write_client_reg(SSITX, 0x0000013A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D4, TRUE);
-		write_client_reg(SSITX, 0x00080124, TRUE);
-		write_client_reg(SSITX, 0x0000016E, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x000800D5, TRUE);
-		write_client_reg(SSITX, 0x00000124, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800ED, TRUE);
-		write_client_reg(SSITX, 0x00080101, TRUE);
-		write_client_reg(SSITX, 0x0000010A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D6, TRUE);
-		write_client_reg(SSITX, 0x00000101, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D7, TRUE);
-		write_client_reg(SSITX, 0x00080110, TRUE);
-		write_client_reg(SSITX, 0x0000010A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D8, TRUE);
-		write_client_reg(SSITX, 0x00000101, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800D9, TRUE);
-		write_client_reg(SSITX, 0x00080100, TRUE);
-		write_client_reg(SSITX, 0x00000114, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800DE, TRUE);
-		write_client_reg(SSITX, 0x00080100, TRUE);
-		write_client_reg(SSITX, 0x00000114, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800DF, TRUE);
-		write_client_reg(SSITX, 0x00080112, TRUE);
-		write_client_reg(SSITX, 0x0000013F, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E0, TRUE);
-		write_client_reg(SSITX, 0x0000010B, TRUE);
-		write_client_reg(SSITX, 0x000800E2, TRUE);
-		write_client_reg(SSITX, 0x00000101, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E3, TRUE);
-		write_client_reg(SSITX, 0x00000136, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E4, TRUE);
-		write_client_reg(SSITX, 0x00080100, TRUE);
-		write_client_reg(SSITX, 0x00000103, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E5, TRUE);
-		write_client_reg(SSITX, 0x00080102, TRUE);
-		write_client_reg(SSITX, 0x00000104, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E6, TRUE);
-		write_client_reg(SSITX, 0x00000103, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E7, TRUE);
-		write_client_reg(SSITX, 0x00080104, TRUE);
-		write_client_reg(SSITX, 0x0000010A, TRUE);
-		mddi_wait(2);
-		write_client_reg(SSITX, 0x000800E8, TRUE);
-		write_client_reg(SSITX, 0x00000104, TRUE);
-		write_client_reg(CLKENB, 0x000001EF, TRUE);
-		write_client_reg(START, 0x00000000, TRUE);
-		write_client_reg(WRSTB, 0x0000003F, TRUE);
-		write_client_reg(RDSTB, 0x00000432, TRUE);
-		write_client_reg(PORT_ENB, 0x00000002, TRUE);
-		write_client_reg(VSYNIF, 0x00000000, TRUE);
-		write_client_reg(ASY_DATA, 0x80000000, TRUE);
-		write_client_reg(ASY_DATB, 0x00000001, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-		mddi_wait(10);
-		write_client_reg(ASY_DATA, 0x80000000, TRUE);
-		write_client_reg(ASY_DATB, 0x80000000, TRUE);
-		write_client_reg(ASY_DATC, 0x80000000, TRUE);
-		write_client_reg(ASY_DATD, 0x80000000, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000009, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000008, TRUE);
-		write_client_reg(ASY_DATA, 0x80000007, TRUE);
-		write_client_reg(ASY_DATB, 0x00004005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-		mddi_wait(20);
-		write_client_reg(ASY_DATA, 0x80000059, TRUE);
-		write_client_reg(ASY_DATB, 0x00000000, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-		write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-		write_client_reg(VSYNIF, 0x00000001, TRUE);
-		write_client_reg(PORT_ENB, 0x00000001, TRUE);
-	}
-
-	mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_STANDBY,
-				      TOSHIBA_STATE_PRIM_SEC_READY);
-}
-
-static void toshiba_prim_start(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) {
-		write_client_reg(BITMAP1, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP2, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP3, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP4, 0x00DC00B0, TRUE);
-		write_client_reg(CLKENB, 0x000001EF, TRUE);
-		write_client_reg(PORT_ENB, 0x00000001, TRUE);
-		write_client_reg(PORT, 0x00000016, TRUE);
-		write_client_reg(PXL, 0x00000002, TRUE);
-		write_client_reg(MPLFBUF, 0x00000000, TRUE);
-		write_client_reg(HCYCLE, 0x00000185, TRUE);
-		write_client_reg(HSW, 0x00000018, TRUE);
-		write_client_reg(HDE_START, 0x0000004A, TRUE);
-		write_client_reg(HDE_SIZE, 0x000000EF, TRUE);
-		write_client_reg(VCYCLE, 0x0000028E, TRUE);
-		write_client_reg(VSW, 0x00000004, TRUE);
-		write_client_reg(VDE_START, 0x00000009, TRUE);
-		write_client_reg(VDE_SIZE, 0x0000027F, TRUE);
-		write_client_reg(START, 0x00000001, TRUE);
-		write_client_reg(SYSTEM_BLOCK1_BASE, 0x00000002, TRUE);
-	} else{
-
-		write_client_reg(VSYNIF, 0x00000001, TRUE);
-		write_client_reg(PORT_ENB, 0x00000001, TRUE);
-		write_client_reg(BITMAP1, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP2, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP3, 0x01E000F0, TRUE);
-		write_client_reg(BITMAP4, 0x00DC00B0, TRUE);
-		write_client_reg(CLKENB, 0x000001EF, TRUE);
-		write_client_reg(PORT_ENB, 0x00000001, TRUE);
-		write_client_reg(PORT, 0x00000004, TRUE);
-		write_client_reg(PXL, 0x00000002, TRUE);
-		write_client_reg(MPLFBUF, 0x00000000, TRUE);
-
-		if (mddi_toshiba_61Hz_refresh) {
-			write_client_reg(HCYCLE, 0x000000FC, TRUE);
-			mddi_toshiba_rows_per_second = 39526;
-			mddi_toshiba_rows_per_refresh = 646;
-			mddi_toshiba_usecs_per_refresh = 16344;
-		} else {
-			write_client_reg(HCYCLE, 0x0000010b, TRUE);
-			mddi_toshiba_rows_per_second = 37313;
-			mddi_toshiba_rows_per_refresh = 646;
-			mddi_toshiba_usecs_per_refresh = 17313;
-		}
-
-		write_client_reg(HSW, 0x00000003, TRUE);
-		write_client_reg(HDE_START, 0x00000007, TRUE);
-		write_client_reg(HDE_SIZE, 0x000000EF, TRUE);
-		write_client_reg(VCYCLE, 0x00000285, TRUE);
-		write_client_reg(VSW, 0x00000001, TRUE);
-		write_client_reg(VDE_START, 0x00000003, TRUE);
-		write_client_reg(VDE_SIZE, 0x0000027F, TRUE);
-		write_client_reg(START, 0x00000001, TRUE);
-		mddi_wait(10);
-		write_client_reg(SSITX, 0x000800BC, TRUE);
-		write_client_reg(SSITX, 0x00000180, TRUE);
-		write_client_reg(SSITX, 0x0008003B, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x000800B0, TRUE);
-		write_client_reg(SSITX, 0x00000116, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x000800B8, TRUE);
-		write_client_reg(SSITX, 0x000801FF, TRUE);
-		write_client_reg(SSITX, 0x000001F5, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x00000011, TRUE);
-		write_client_reg(SSITX, 0x00000029, TRUE);
-		write_client_reg(WKREQ, 0x00000000, TRUE);
-		write_client_reg(WAKEUP, 0x00000000, TRUE);
-		write_client_reg(INTMSK, 0x00000001, TRUE);
-	}
-
-	mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_READY,
-				      TOSHIBA_STATE_PRIM_NORMAL_MODE);
-}
-
-static void toshiba_sec_start(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(PORT_ENB, 0x00000002, TRUE);
-	write_client_reg(CLKENB, 0x000011EF, TRUE);
-	write_client_reg(BITMAP0, 0x028001E0, TRUE);
-	write_client_reg(BITMAP1, 0x00000000, TRUE);
-	write_client_reg(BITMAP2, 0x00000000, TRUE);
-	write_client_reg(BITMAP3, 0x00000000, TRUE);
-	write_client_reg(BITMAP4, 0x00DC00B0, TRUE);
-	write_client_reg(PORT, 0x00000000, TRUE);
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(MPLFBUF, 0x00000004, TRUE);
-	write_client_reg(HCYCLE, 0x0000006B, TRUE);
-	write_client_reg(HSW, 0x00000003, TRUE);
-	write_client_reg(HDE_START, 0x00000007, TRUE);
-	write_client_reg(HDE_SIZE, 0x00000057, TRUE);
-	write_client_reg(VCYCLE, 0x000000E6, TRUE);
-	write_client_reg(VSW, 0x00000001, TRUE);
-	write_client_reg(VDE_START, 0x00000003, TRUE);
-	write_client_reg(VDE_SIZE, 0x000000DB, TRUE);
-	write_client_reg(ASY_DATA, 0x80000001, TRUE);
-	write_client_reg(ASY_DATB, 0x0000011B, TRUE);
-	write_client_reg(ASY_DATC, 0x80000002, TRUE);
-	write_client_reg(ASY_DATD, 0x00000700, TRUE);
-	write_client_reg(ASY_DATE, 0x80000003, TRUE);
-	write_client_reg(ASY_DATF, 0x00000230, TRUE);
-	write_client_reg(ASY_DATG, 0x80000008, TRUE);
-	write_client_reg(ASY_DATH, 0x00000402, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000009, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_DATC, 0x8000000B, TRUE);
-	write_client_reg(ASY_DATD, 0x00000000, TRUE);
-	write_client_reg(ASY_DATE, 0x8000000C, TRUE);
-	write_client_reg(ASY_DATF, 0x00000000, TRUE);
-	write_client_reg(ASY_DATG, 0x8000000D, TRUE);
-	write_client_reg(ASY_DATH, 0x00000409, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x8000000E, TRUE);
-	write_client_reg(ASY_DATB, 0x00000409, TRUE);
-	write_client_reg(ASY_DATC, 0x80000030, TRUE);
-	write_client_reg(ASY_DATD, 0x00000000, TRUE);
-	write_client_reg(ASY_DATE, 0x80000031, TRUE);
-	write_client_reg(ASY_DATF, 0x00000100, TRUE);
-	write_client_reg(ASY_DATG, 0x80000032, TRUE);
-	write_client_reg(ASY_DATH, 0x00000104, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000033, TRUE);
-	write_client_reg(ASY_DATB, 0x00000400, TRUE);
-	write_client_reg(ASY_DATC, 0x80000034, TRUE);
-	write_client_reg(ASY_DATD, 0x00000306, TRUE);
-	write_client_reg(ASY_DATE, 0x80000035, TRUE);
-	write_client_reg(ASY_DATF, 0x00000706, TRUE);
-	write_client_reg(ASY_DATG, 0x80000036, TRUE);
-	write_client_reg(ASY_DATH, 0x00000707, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000037, TRUE);
-	write_client_reg(ASY_DATB, 0x00000004, TRUE);
-	write_client_reg(ASY_DATC, 0x80000038, TRUE);
-	write_client_reg(ASY_DATD, 0x00000000, TRUE);
-	write_client_reg(ASY_DATE, 0x80000039, TRUE);
-	write_client_reg(ASY_DATF, 0x00000000, TRUE);
-	write_client_reg(ASY_DATG, 0x8000003A, TRUE);
-	write_client_reg(ASY_DATH, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000044, TRUE);
-	write_client_reg(ASY_DATB, 0x0000AF00, TRUE);
-	write_client_reg(ASY_DATC, 0x80000045, TRUE);
-	write_client_reg(ASY_DATD, 0x0000DB00, TRUE);
-	write_client_reg(ASY_DATE, 0x08000042, TRUE);
-	write_client_reg(ASY_DATF, 0x0000DB00, TRUE);
-	write_client_reg(ASY_DATG, 0x80000021, TRUE);
-	write_client_reg(ASY_DATH, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(PXL, 0x0000000C, TRUE);
-	write_client_reg(VSYNIF, 0x00000001, TRUE);
-	write_client_reg(ASY_DATA, 0x80000022, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000003, TRUE);
-	write_client_reg(START, 0x00000001, TRUE);
-	mddi_wait(60);
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(START, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000050, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_DATC, 0x80000051, TRUE);
-	write_client_reg(ASY_DATD, 0x00000E00, TRUE);
-	write_client_reg(ASY_DATE, 0x80000052, TRUE);
-	write_client_reg(ASY_DATF, 0x00000D01, TRUE);
-	write_client_reg(ASY_DATG, 0x80000053, TRUE);
-	write_client_reg(ASY_DATH, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	write_client_reg(ASY_DATA, 0x80000058, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_DATC, 0x8000005A, TRUE);
-	write_client_reg(ASY_DATD, 0x00000E01, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000009, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000008, TRUE);
-	write_client_reg(ASY_DATA, 0x80000011, TRUE);
-	write_client_reg(ASY_DATB, 0x00000812, TRUE);
-	write_client_reg(ASY_DATC, 0x80000012, TRUE);
-	write_client_reg(ASY_DATD, 0x00000003, TRUE);
-	write_client_reg(ASY_DATE, 0x80000013, TRUE);
-	write_client_reg(ASY_DATF, 0x00000909, TRUE);
-	write_client_reg(ASY_DATG, 0x80000010, TRUE);
-	write_client_reg(ASY_DATH, 0x00000040, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	mddi_wait(40);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000340, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(60);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00003340, TRUE);
-	write_client_reg(ASY_DATC, 0x80000007, TRUE);
-	write_client_reg(ASY_DATD, 0x00004007, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000009, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000008, TRUE);
-	mddi_wait(1);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004017, TRUE);
-	write_client_reg(ASY_DATC, 0x8000005B, TRUE);
-	write_client_reg(ASY_DATD, 0x00000000, TRUE);
-	write_client_reg(ASY_DATE, 0x80000059, TRUE);
-	write_client_reg(ASY_DATF, 0x00000011, TRUE);
-	write_client_reg(ASY_CMDSET, 0x0000000D, TRUE);
-	write_client_reg(ASY_CMDSET, 0x0000000C, TRUE);
-	mddi_wait(20);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	/* LTPS I/F control */
-	write_client_reg(ASY_DATB, 0x00000019, TRUE);
-	/* Direct cmd transfer enable */
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	/* Direct cmd transfer disable */
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(20);
-	/* Index setting of SUB LCDD */
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	/* LTPS I/F control */
-	write_client_reg(ASY_DATB, 0x00000079, TRUE);
-	/* Direct cmd transfer enable */
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	/* Direct cmd transfer disable */
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(20);
-	/* Index setting of SUB LCDD */
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	/* LTPS I/F control */
-	write_client_reg(ASY_DATB, 0x000003FD, TRUE);
-	/* Direct cmd transfer enable */
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	/* Direct cmd transfer disable */
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(20);
-	mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_SEC_READY,
-				      TOSHIBA_STATE_SEC_NORMAL_MODE);
-}
-
-static void toshiba_prim_lcd_off(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) {
-		gordon_disp_off();
-	} else{
-
-		/* Main panel power off (Deep standby in) */
-		write_client_reg(SSITX, 0x000800BC, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-		write_client_reg(SSITX, 0x00000028, TRUE);
-		mddi_wait(1);
-		write_client_reg(SSITX, 0x000800B8, TRUE);
-		write_client_reg(SSITX, 0x00000180, TRUE);
-		write_client_reg(SSITX, 0x00000102, TRUE);
-		write_client_reg(SSITX, 0x00000010, TRUE);
-	}
-	write_client_reg(PORT, 0x00000003, TRUE);
-	write_client_reg(REGENB, 0x00000001, TRUE);
-	mddi_wait(1);
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(START, 0x00000000, TRUE);
-	write_client_reg(REGENB, 0x00000001, TRUE);
-	mddi_wait(3);
-	if (TM_GET_PID(mfd->panel.id) != LCD_SHARP_2P4_VGA) {
-		write_client_reg(SSITX, 0x000800B0, TRUE);
-		write_client_reg(SSITX, 0x00000100, TRUE);
-	}
-	mddi_toshiba_state_transition(TOSHIBA_STATE_PRIM_NORMAL_MODE,
-				      TOSHIBA_STATE_PRIM_SEC_STANDBY);
-}
-
-static void toshiba_sec_lcd_off(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(PORT_ENB, 0x00000002, TRUE);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004016, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000019, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x0000000B, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000002, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(4);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000300, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(4);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004004, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(PORT, 0x00000000, TRUE);
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(START, 0x00000000, TRUE);
-	write_client_reg(VSYNIF, 0x00000001, TRUE);
-	write_client_reg(PORT_ENB, 0x00000001, TRUE);
-	write_client_reg(REGENB, 0x00000001, TRUE);
-	mddi_toshiba_state_transition(TOSHIBA_STATE_SEC_NORMAL_MODE,
-				      TOSHIBA_STATE_PRIM_SEC_STANDBY);
-}
-
-static void toshiba_sec_cont_update_start(struct msm_fb_data_type *mfd)
-{
-
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(PORT_ENB, 0x00000002, TRUE);
-	write_client_reg(INTMASK, 0x00000001, TRUE);
-	write_client_reg(TTBUSSEL, 0x0000000B, TRUE);
-	write_client_reg(MONI, 0x00000008, TRUE);
-	write_client_reg(CLKENB, 0x000000EF, TRUE);
-	write_client_reg(CLKENB, 0x000010EF, TRUE);
-	write_client_reg(CLKENB, 0x000011EF, TRUE);
-	write_client_reg(BITMAP4, 0x00DC00B0, TRUE);
-	write_client_reg(HCYCLE, 0x0000006B, TRUE);
-	write_client_reg(HSW, 0x00000003, TRUE);
-	write_client_reg(HDE_START, 0x00000002, TRUE);
-	write_client_reg(HDE_SIZE, 0x00000057, TRUE);
-	write_client_reg(VCYCLE, 0x000000E6, TRUE);
-	write_client_reg(VSW, 0x00000001, TRUE);
-	write_client_reg(VDE_START, 0x00000003, TRUE);
-	write_client_reg(VDE_SIZE, 0x000000DB, TRUE);
-	write_client_reg(WRSTB, 0x00000015, TRUE);
-	write_client_reg(MPLFBUF, 0x00000004, TRUE);
-	write_client_reg(ASY_DATA, 0x80000021, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_DATC, 0x80000022, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000007, TRUE);
-	write_client_reg(PXL, 0x00000089, TRUE);
-	write_client_reg(VSYNIF, 0x00000001, TRUE);
-	mddi_wait(2);
-}
-
-static void toshiba_sec_cont_update_stop(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(START, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	mddi_wait(3);
-	write_client_reg(SRST, 0x00000002, TRUE);
-	mddi_wait(3);
-	write_client_reg(SRST, 0x00000003, TRUE);
-}
-
-static void toshiba_sec_backlight_on(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(TIMER0CTRL, 0x00000060, TRUE);
-	write_client_reg(TIMER0LOAD, 0x00001388, TRUE);
-	write_client_reg(PWM0OFF, 0x00000001, TRUE);
-	write_client_reg(TIMER1CTRL, 0x00000060, TRUE);
-	write_client_reg(TIMER1LOAD, 0x00001388, TRUE);
-	write_client_reg(PWM1OFF, 0x00001387, TRUE);
-	write_client_reg(TIMER0CTRL, 0x000000E0, TRUE);
-	write_client_reg(TIMER1CTRL, 0x000000E0, TRUE);
-	write_client_reg(PWMCR, 0x00000003, TRUE);
-}
-
-static void toshiba_sec_sleep_in(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(PORT_ENB, 0x00000002, TRUE);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004016, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000019, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x0000000B, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000002, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(4);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000300, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(4);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000000, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004004, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(PORT, 0x00000000, TRUE);
-	write_client_reg(PXL, 0x00000000, TRUE);
-	write_client_reg(START, 0x00000000, TRUE);
-	write_client_reg(REGENB, 0x00000001, TRUE);
-	/* Sleep in sequence */
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000302, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-}
-
-static void toshiba_sec_sleep_out(struct msm_fb_data_type *mfd)
-{
-	if (TM_GET_PID(mfd->panel.id) == LCD_TOSHIBA_2P4_WVGA_PT)
-		return;
-
-	write_client_reg(VSYNIF, 0x00000000, TRUE);
-	write_client_reg(PORT_ENB, 0x00000002, TRUE);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000300, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	/*  Display ON sequence */
-	write_client_reg(ASY_DATA, 0x80000011, TRUE);
-	write_client_reg(ASY_DATB, 0x00000812, TRUE);
-	write_client_reg(ASY_DATC, 0x80000012, TRUE);
-	write_client_reg(ASY_DATD, 0x00000003, TRUE);
-	write_client_reg(ASY_DATE, 0x80000013, TRUE);
-	write_client_reg(ASY_DATF, 0x00000909, TRUE);
-	write_client_reg(ASY_DATG, 0x80000010, TRUE);
-	write_client_reg(ASY_DATH, 0x00000040, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000001, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000000, TRUE);
-	mddi_wait(4);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00000340, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(6);
-	write_client_reg(ASY_DATA, 0x80000010, TRUE);
-	write_client_reg(ASY_DATB, 0x00003340, TRUE);
-	write_client_reg(ASY_DATC, 0x80000007, TRUE);
-	write_client_reg(ASY_DATD, 0x00004007, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000009, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000008, TRUE);
-	mddi_wait(1);
-	write_client_reg(ASY_DATA, 0x80000007, TRUE);
-	write_client_reg(ASY_DATB, 0x00004017, TRUE);
-	write_client_reg(ASY_DATC, 0x8000005B, TRUE);
-	write_client_reg(ASY_DATD, 0x00000000, TRUE);
-	write_client_reg(ASY_DATE, 0x80000059, TRUE);
-	write_client_reg(ASY_DATF, 0x00000011, TRUE);
-	write_client_reg(ASY_CMDSET, 0x0000000D, TRUE);
-	write_client_reg(ASY_CMDSET, 0x0000000C, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000019, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x00000079, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-	write_client_reg(ASY_DATA, 0x80000059, TRUE);
-	write_client_reg(ASY_DATB, 0x000003FD, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000005, TRUE);
-	write_client_reg(ASY_CMDSET, 0x00000004, TRUE);
-	mddi_wait(2);
-}
-
-static void mddi_toshiba_lcd_set_backlight(struct msm_fb_data_type *mfd)
-{
-	int32 level;
-	int ret = -EPERM;
-	int max = mfd->panel_info.bl_max;
-	int min = mfd->panel_info.bl_min;
-	int i = 0;
-
-	if (mddi_toshiba_pdata && mddi_toshiba_pdata->pmic_backlight) {
-		while (i++ < 3) {
-			ret = mddi_toshiba_pdata->pmic_backlight(mfd->bl_level);
-			if (!ret)
-				return;
-			msleep(10);
-		}
-		printk(KERN_WARNING "%s: pmic_backlight Failed\n", __func__);
-	}
-
-
-	if (ret && mddi_toshiba_pdata && mddi_toshiba_pdata->backlight_level) {
-		level = mddi_toshiba_pdata->backlight_level(mfd->bl_level,
-								max, min);
-
-		if (level < 0)
-			return;
-
-		if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA)
-			write_client_reg(TIMER0LOAD, 0x00001388, TRUE);
-	} else {
-		if (!max)
-			level = 0;
-		else
-			level = (mfd->bl_level * 4999) / max;
-	}
-
-	write_client_reg(PWM0OFF, level, TRUE);
-}
-
-static void mddi_toshiba_vsync_set_handler(msm_fb_vsync_handler_type handler,	/* ISR to be executed */
-					   void *arg)
-{
-	boolean error = FALSE;
-	unsigned long flags;
-
-	/* Disable interrupts */
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-	/* INTLOCK(); */
-
-	if (mddi_toshiba_vsync_handler != NULL) {
-		error = TRUE;
-	} else {
-		/* Register the handler for this particular GROUP interrupt source */
-		mddi_toshiba_vsync_handler = handler;
-		mddi_toshiba_vsync_handler_arg = arg;
-	}
-
-	/* Restore interrupts */
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-	/* MDDI_INTFREE(); */
-	if (error) {
-		MDDI_MSG_ERR("MDDI: Previous Vsync handler never called\n");
-	} else {
-		/* Enable the vsync wakeup */
-		mddi_queue_register_write(INTMSK, 0x0000, FALSE, 0);
-
-		mddi_toshiba_vsync_attempts = 1;
-		mddi_vsync_detect_enabled = TRUE;
-	}
-}				/* mddi_toshiba_vsync_set_handler */
-
-static void mddi_toshiba_lcd_vsync_detected(boolean detected)
-{
-	/* static timetick_type start_time = 0; */
-	static struct timeval start_time;
-	static boolean first_time = TRUE;
-	/* uint32 mdp_cnt_val = 0; */
-	/* timetick_type elapsed_us; */
-	struct timeval now;
-	uint32 elapsed_us;
-	uint32 num_vsyncs;
-
-	if ((detected) || (mddi_toshiba_vsync_attempts > 5)) {
-		if ((detected) && (mddi_toshiba_monitor_refresh_value)) {
-			/* if (start_time != 0) */
-			if (!first_time) {
-				jiffies_to_timeval(jiffies, &now);
-				elapsed_us =
-				    (now.tv_sec - start_time.tv_sec) * 1000000 +
-				    now.tv_usec - start_time.tv_usec;
-				/*
-				 * LCD is configured for a refresh every usecs,
-				 *  so to determine the number of vsyncs that
-				 *  have occurred since the last measurement
-				 *  add half that to the time difference and
-				 *  divide by the refresh rate.
-				 */
-				num_vsyncs = (elapsed_us +
-					      (mddi_toshiba_usecs_per_refresh >>
-					       1)) /
-				    mddi_toshiba_usecs_per_refresh;
-				/*
-				 * LCD is configured for * hsyncs (rows) per
-				 * refresh cycle. Calculate new rows_per_second
-				 * value based upon these new measurements.
-				 * MDP can update with this new value.
-				 */
-				mddi_toshiba_rows_per_second =
-				    (mddi_toshiba_rows_per_refresh * 1000 *
-				     num_vsyncs) / (elapsed_us / 1000);
-			}
-			/* start_time = timetick_get(); */
-			first_time = FALSE;
-			jiffies_to_timeval(jiffies, &start_time);
-			if (mddi_toshiba_report_refresh_measurements) {
-				(void)mddi_queue_register_read_int(VPOS,
-								   &mddi_toshiba_curr_vpos);
-				/* mdp_cnt_val = MDP_LINE_COUNT; */
-			}
-		}
-		/* if detected = TRUE, client initiated wakeup was detected */
-		if (mddi_toshiba_vsync_handler != NULL) {
-			(*mddi_toshiba_vsync_handler)
-			    (mddi_toshiba_vsync_handler_arg);
-			mddi_toshiba_vsync_handler = NULL;
-		}
-		mddi_vsync_detect_enabled = FALSE;
-		mddi_toshiba_vsync_attempts = 0;
-		/* need to disable the interrupt wakeup */
-		if (!mddi_queue_register_write_int(INTMSK, 0x0001))
-			MDDI_MSG_ERR("Vsync interrupt disable failed!\n");
-		if (!detected) {
-			/* give up after 5 failed attempts but show error */
-			MDDI_MSG_NOTICE("Vsync detection failed!\n");
-		} else if ((mddi_toshiba_monitor_refresh_value) &&
-			   (mddi_toshiba_report_refresh_measurements)) {
-			MDDI_MSG_NOTICE("  Last Line Counter=%d!\n",
-					mddi_toshiba_curr_vpos);
-		/* MDDI_MSG_NOTICE("  MDP Line Counter=%d!\n",mdp_cnt_val); */
-			MDDI_MSG_NOTICE("  Lines Per Second=%d!\n",
-					mddi_toshiba_rows_per_second);
-		}
-		/* clear the interrupt */
-		if (!mddi_queue_register_write_int(INTFLG, 0x0001))
-			MDDI_MSG_ERR("Vsync interrupt clear failed!\n");
-	} else {
-		/* if detected = FALSE, we woke up from hibernation, but did not
-		 * detect client initiated wakeup.
-		 */
-		mddi_toshiba_vsync_attempts++;
-	}
-}
-
-static void mddi_toshiba_prim_init(struct msm_fb_data_type *mfd)
-{
-
-	switch (toshiba_state) {
-	case TOSHIBA_STATE_PRIM_SEC_READY:
-		break;
-	case TOSHIBA_STATE_OFF:
-		toshiba_state = TOSHIBA_STATE_PRIM_SEC_STANDBY;
-		toshiba_common_initial_setup(mfd);
-		break;
-	case TOSHIBA_STATE_PRIM_SEC_STANDBY:
-		toshiba_common_initial_setup(mfd);
-		break;
-	case TOSHIBA_STATE_SEC_NORMAL_MODE:
-		toshiba_sec_cont_update_stop(mfd);
-		toshiba_sec_sleep_in(mfd);
-		toshiba_sec_sleep_out(mfd);
-		toshiba_sec_lcd_off(mfd);
-		toshiba_common_initial_setup(mfd);
-		break;
-	default:
-		MDDI_MSG_ERR("mddi_toshiba_prim_init from state %d\n",
-			     toshiba_state);
-	}
-
-	toshiba_prim_start(mfd);
-	if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA)
-		gordon_disp_init();
-	mddi_host_write_pix_attr_reg(0x00C3);
-}
-
-static void mddi_toshiba_sec_init(struct msm_fb_data_type *mfd)
-{
-
-	switch (toshiba_state) {
-	case TOSHIBA_STATE_PRIM_SEC_READY:
-		break;
-	case TOSHIBA_STATE_PRIM_SEC_STANDBY:
-		toshiba_common_initial_setup(mfd);
-		break;
-	case TOSHIBA_STATE_PRIM_NORMAL_MODE:
-		toshiba_prim_lcd_off(mfd);
-		toshiba_common_initial_setup(mfd);
-		break;
-	default:
-		MDDI_MSG_ERR("mddi_toshiba_sec_init from state %d\n",
-			     toshiba_state);
-	}
-
-	toshiba_sec_start(mfd);
-	toshiba_sec_backlight_on(mfd);
-	toshiba_sec_cont_update_start(mfd);
-	mddi_host_write_pix_attr_reg(0x0400);
-}
-
-static void mddi_toshiba_lcd_powerdown(struct msm_fb_data_type *mfd)
-{
-	switch (toshiba_state) {
-	case TOSHIBA_STATE_PRIM_SEC_READY:
-		mddi_toshiba_prim_init(mfd);
-		mddi_toshiba_lcd_powerdown(mfd);
-		return;
-	case TOSHIBA_STATE_PRIM_SEC_STANDBY:
-		break;
-	case TOSHIBA_STATE_PRIM_NORMAL_MODE:
-		toshiba_prim_lcd_off(mfd);
-		break;
-	case TOSHIBA_STATE_SEC_NORMAL_MODE:
-		toshiba_sec_cont_update_stop(mfd);
-		toshiba_sec_sleep_in(mfd);
-		toshiba_sec_sleep_out(mfd);
-		toshiba_sec_lcd_off(mfd);
-		break;
-	default:
-		MDDI_MSG_ERR("mddi_toshiba_lcd_powerdown from state %d\n",
-			     toshiba_state);
-	}
-}
-
-static int mddi_sharpgordon_firsttime = 1;
-
-static int mddi_toshiba_lcd_on(struct platform_device *pdev)
-{
-	struct msm_fb_data_type *mfd;
-	mfd = platform_get_drvdata(pdev);
-	if (!mfd)
-		return -ENODEV;
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	mddi_host_client_cnt_reset();
-
-	if (TM_GET_DID(mfd->panel.id) == TOSHIBA_VGA_PRIM)
-		mddi_toshiba_prim_init(mfd);
-	else
-		mddi_toshiba_sec_init(mfd);
-	if (TM_GET_PID(mfd->panel.id) == LCD_SHARP_2P4_VGA) {
-		if (mddi_sharpgordon_firsttime) {
-			mddi_sharpgordon_firsttime = 0;
-			write_client_reg(REGENB, 0x00000001, TRUE);
-		}
-	}
-	return 0;
-}
-
-static int mddi_toshiba_lcd_off(struct platform_device *pdev)
-{
-	if (mddi_toshiba_vsync_handler != NULL) {
-		(*mddi_toshiba_vsync_handler)
-			    (mddi_toshiba_vsync_handler_arg);
-		mddi_toshiba_vsync_handler = NULL;
-		printk(KERN_INFO "%s: clean up vsyn_handler=%x\n", __func__,
-				(int)mddi_toshiba_vsync_handler);
-	}
-
-	mddi_toshiba_lcd_powerdown(platform_get_drvdata(pdev));
-	return 0;
-}
-
-static int __devinit mddi_toshiba_lcd_probe(struct platform_device *pdev)
-{
-	if (pdev->id == 0) {
-		mddi_toshiba_pdata = pdev->dev.platform_data;
-		return 0;
-	}
-
-	msm_fb_add_device(pdev);
-
-	return 0;
-}
-
-static struct platform_driver this_driver = {
-	.probe  = mddi_toshiba_lcd_probe,
-	.driver = {
-		.name   = "mddi_toshiba",
-	},
-};
-
-static struct msm_fb_panel_data toshiba_panel_data = {
-	.on 		= mddi_toshiba_lcd_on,
-	.off 		= mddi_toshiba_lcd_off,
-};
-
-static int ch_used[3];
-
-int mddi_toshiba_device_register(struct msm_panel_info *pinfo,
-					u32 channel, u32 panel)
-{
-	struct platform_device *pdev = NULL;
-	int ret;
-
-	if ((channel >= 3) || ch_used[channel])
-		return -ENODEV;
-
-	if ((channel != TOSHIBA_VGA_PRIM) &&
-	    mddi_toshiba_pdata && mddi_toshiba_pdata->panel_num)
-		if (mddi_toshiba_pdata->panel_num() < 2)
-			return -ENODEV;
-
-	ch_used[channel] = TRUE;
-
-	pdev = platform_device_alloc("mddi_toshiba", (panel << 8)|channel);
-	if (!pdev)
-		return -ENOMEM;
-
-	if (channel == TOSHIBA_VGA_PRIM) {
-		toshiba_panel_data.set_backlight =
-				mddi_toshiba_lcd_set_backlight;
-
-		if (pinfo->lcd.vsync_enable) {
-			toshiba_panel_data.set_vsync_notifier =
-				mddi_toshiba_vsync_set_handler;
-			mddi_lcd.vsync_detected =
-				mddi_toshiba_lcd_vsync_detected;
-		}
-	} else {
-		toshiba_panel_data.set_backlight = NULL;
-		toshiba_panel_data.set_vsync_notifier = NULL;
-	}
-
-	toshiba_panel_data.panel_info = *pinfo;
-
-	ret = platform_device_add_data(pdev, &toshiba_panel_data,
-		sizeof(toshiba_panel_data));
-	if (ret) {
-		printk(KERN_ERR
-		  "%s: platform_device_add_data failed!\n", __func__);
-		goto err_device_put;
-	}
-
-	ret = platform_device_add(pdev);
-	if (ret) {
-		printk(KERN_ERR
-		  "%s: platform_device_register failed!\n", __func__);
-		goto err_device_put;
-	}
-
-	return 0;
-
-err_device_put:
-	platform_device_put(pdev);
-	return ret;
-}
-
-static int __init mddi_toshiba_lcd_init(void)
-{
-	return platform_driver_register(&this_driver);
-}
-
-module_init(mddi_toshiba_lcd_init);
diff --git a/drivers/video/msm/mddi_toshiba.h b/drivers/video/msm/mddi_toshiba.h
deleted file mode 100644
index 854817f..0000000
--- a/drivers/video/msm/mddi_toshiba.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Copyright (c) 2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef MDDI_TOSHIBA_H
-#define MDDI_TOSHIBA_H
-
-#define TOSHIBA_VGA_PRIM 1
-#define TOSHIBA_VGA_SECD 2
-
-#define LCD_TOSHIBA_2P4_VGA 	0
-#define LCD_TOSHIBA_2P4_WVGA 	1
-#define LCD_TOSHIBA_2P4_WVGA_PT	2
-#define LCD_SHARP_2P4_VGA 	3
-
-#define GPIO_BLOCK_BASE        0x150000
-#define SYSTEM_BLOCK2_BASE     0x170000
-
-#define GPIODIR     (GPIO_BLOCK_BASE|0x04)
-#define GPIOSEL     (SYSTEM_BLOCK2_BASE|0x00)
-#define GPIOPC      (GPIO_BLOCK_BASE|0x28)
-#define GPIODATA    (GPIO_BLOCK_BASE|0x00)
-
-#define write_client_reg(__X, __Y, __Z) {\
-  mddi_queue_register_write(__X, __Y, TRUE, 0);\
-}
-
-#endif /* MDDI_TOSHIBA_H */
diff --git a/drivers/video/msm/mddi_toshiba_vga.c b/drivers/video/msm/mddi_toshiba_vga.c
deleted file mode 100644
index 3b4a85d..0000000
--- a/drivers/video/msm/mddi_toshiba_vga.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright (c) 2009-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-#include "mddi_toshiba.h"
-
-static uint32 read_client_reg(uint32 addr)
-{
-	uint32 val;
-	mddi_queue_register_read(addr, &val, TRUE, 0);
-	return val;
-}
-
-static uint32 toshiba_lcd_gpio_read(void)
-{
-	uint32 val;
-
-	write_client_reg(GPIODIR, 0x0000000C, TRUE);
-	write_client_reg(GPIOSEL, 0x00000000, TRUE);
-	write_client_reg(GPIOSEL, 0x00000000, TRUE);
-	write_client_reg(GPIOPC, 0x03CF00C0, TRUE);
-	val = read_client_reg(GPIODATA) & 0x2C0;
-
-	return val;
-}
-
-static u32 mddi_toshiba_panel_detect(void)
-{
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	uint32 lcd_gpio;
-	u32 mddi_toshiba_lcd = LCD_TOSHIBA_2P4_VGA;
-
-	/* Toshiba display requires larger drive_lo value */
-	mddi_host_reg_out(DRIVE_LO, 0x0050);
-
-	lcd_gpio = toshiba_lcd_gpio_read();
-	switch (lcd_gpio) {
-	case 0x0080:
-		mddi_toshiba_lcd = LCD_SHARP_2P4_VGA;
-		break;
-
-	case 0x00C0:
-	default:
-		mddi_toshiba_lcd = LCD_TOSHIBA_2P4_VGA;
-		break;
-	}
-
-	return mddi_toshiba_lcd;
-}
-
-static int __init mddi_toshiba_vga_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-	u32 panel;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	u32 id;
-
-	ret = msm_fb_detect_client("mddi_toshiba_vga");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret) {
-		id = mddi_get_client_id();
-		if ((id >> 16) != 0xD263)
-			return 0;
-	}
-#endif
-
-	panel = mddi_toshiba_panel_detect();
-
-	pinfo.xres = 480;
-	pinfo.yres = 640;
-	pinfo.type = MDDI_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 18;
-	pinfo.lcd.vsync_enable = TRUE;
-	pinfo.mddi.is_type1 = TRUE;
-	pinfo.lcd.refx100 = 6118;
-	pinfo.lcd.v_back_porch = 6;
-	pinfo.lcd.v_front_porch = 0;
-	pinfo.lcd.v_pulse_width = 0;
-	pinfo.lcd.hw_vsync_mode = FALSE;
-	pinfo.lcd.vsync_notifier_period = (1 * HZ);
-	pinfo.bl_max = 99;
-	pinfo.bl_min = 1;
-	pinfo.clk_rate = 122880000;
-	pinfo.clk_min =  120000000;
-	pinfo.clk_max =  200000000;
-	pinfo.fb_num = 2;
-
-	ret = mddi_toshiba_device_register(&pinfo, TOSHIBA_VGA_PRIM, panel);
-	if (ret) {
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-		return ret;
-	}
-
-	pinfo.xres = 176;
-	pinfo.yres = 220;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = MDDI_PANEL;
-	pinfo.pdest = DISPLAY_2;
-	pinfo.mddi.vdopkt = 0x400;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 18;
-	pinfo.clk_rate = 122880000;
-	pinfo.clk_min =  120000000;
-	pinfo.clk_max =  200000000;
-	pinfo.fb_num = 2;
-
-	ret = mddi_toshiba_device_register(&pinfo, TOSHIBA_VGA_SECD, panel);
-	if (ret)
-		printk(KERN_WARNING
-			"%s: failed to register device!\n", __func__);
-
-	return ret;
-}
-
-module_init(mddi_toshiba_vga_init);
diff --git a/drivers/video/msm/mddi_toshiba_wvga.c b/drivers/video/msm/mddi_toshiba_wvga.c
deleted file mode 100644
index 7e7b036..0000000
--- a/drivers/video/msm/mddi_toshiba_wvga.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (c) 2009-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddi_toshiba.h"
-
-static int __init mddi_toshiba_wvga_init(void)
-{
-	int ret;
-	struct msm_panel_info pinfo;
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	if (msm_fb_detect_client("mddi_toshiba_wvga"))
-		return 0;
-#endif
-
-	pinfo.xres = 800;
-	pinfo.yres = 480;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.pdest = DISPLAY_2;
-	pinfo.type = MDDI_PANEL;
-	pinfo.mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 18;
-	pinfo.lcd.vsync_enable = TRUE;
-	pinfo.mddi.is_type1 = TRUE;
-	pinfo.lcd.refx100 = 6118;
-	pinfo.lcd.v_back_porch = 6;
-	pinfo.lcd.v_front_porch = 0;
-	pinfo.lcd.v_pulse_width = 0;
-	pinfo.lcd.hw_vsync_mode = FALSE;
-	pinfo.lcd.vsync_notifier_period = (1 * HZ);
-	pinfo.bl_max = 4;
-	pinfo.bl_min = 1;
-	pinfo.clk_rate = 192000000;
-	pinfo.clk_min =  190000000;
-	pinfo.clk_max =  200000000;
-	pinfo.fb_num = 2;
-
-	ret = mddi_toshiba_device_register(&pinfo, TOSHIBA_VGA_PRIM,
-					   LCD_TOSHIBA_2P4_WVGA);
-	if (ret) {
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-		return ret;
-	}
-
-	return ret;
-}
-
-module_init(mddi_toshiba_wvga_init);
diff --git a/drivers/video/msm/mddi_toshiba_wvga_pt.c b/drivers/video/msm/mddi_toshiba_wvga_pt.c
deleted file mode 100644
index bdb04ff..0000000
--- a/drivers/video/msm/mddi_toshiba_wvga_pt.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-#include "mddi_toshiba.h"
-
-static struct msm_panel_info pinfo;
-
-static int __init mddi_toshiba_wvga_pt_init(void)
-{
-	int ret;
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-	uint id;
-
-	ret = msm_fb_detect_client("mddi_toshiba_wvga_pt");
-	if (ret == -ENODEV)
-		return 0;
-
-	if (ret) {
-		id = mddi_get_client_id();
-		if (id != 0xd2638722)
-			return 0;
-	}
-#endif
-
-	pinfo.xres = 480;
-	pinfo.yres = 800;
-	MSM_FB_SINGLE_MODE_PANEL(&pinfo);
-	pinfo.type = MDDI_PANEL;
-	pinfo.pdest = DISPLAY_1;
-	pinfo.mddi.vdopkt = MDDI_DEFAULT_PRIM_PIX_ATTR;
-	pinfo.wait_cycle = 0;
-	pinfo.bpp = 18;
-	pinfo.lcd.vsync_enable = TRUE;
-	pinfo.lcd.refx100 = 6102; /* adjust refx100 to prevent tearing */
-	pinfo.mddi.is_type1 = TRUE;
-	pinfo.lcd.v_back_porch = 8;     /* vsw=10 + vbp = 8 */
-	pinfo.lcd.v_front_porch = 2;
-	pinfo.lcd.v_pulse_width = 10;
-	pinfo.lcd.hw_vsync_mode = FALSE;
-	pinfo.lcd.vsync_notifier_period = (1 * HZ);
-	pinfo.bl_max = 15;
-	pinfo.bl_min = 1;
-	pinfo.clk_rate = 222750000;
-	pinfo.clk_min =  200000000;
-	pinfo.clk_max =  240000000;
-	pinfo.fb_num = 2;
-
-	ret = mddi_toshiba_device_register(&pinfo, TOSHIBA_VGA_PRIM,
-						LCD_TOSHIBA_2P4_WVGA_PT);
-	if (ret)
-		printk(KERN_ERR "%s: failed to register device!\n", __func__);
-
-	return ret;
-}
-
-module_init(mddi_toshiba_wvga_pt_init);
diff --git a/drivers/video/msm/mddihost.c b/drivers/video/msm/mddihost.c
deleted file mode 100644
index c2a7af3..0000000
--- a/drivers/video/msm/mddihost.c
+++ /dev/null
@@ -1,626 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-#include <linux/clk.h>
-#include <mach/clk.h>
-
-struct semaphore mddi_host_mutex;
-
-struct clk *mddi_io_clk;
-static boolean mddi_host_powered = FALSE;
-static boolean mddi_host_initialized = FALSE;
-extern uint32 *mddi_reg_read_value_ptr;
-
-mddi_lcd_func_type mddi_lcd;
-
-extern mddi_client_capability_type mddi_client_capability_pkt;
-
-#ifdef MDDI_HOST_WINDOW_WORKAROUND
-/* Tables showing number of rows that would cause a packet length
- * ending in 0x02, for each number of columns. These tables have
- * been generated for MDDI packets that have 16 and 16 bits-per-pixel.
- * This is a work-around for MDDI clients that declare a CRC error
- * on MDDI packets where ((length & 0x00ff) == 0x02).
- */
-static uint16 error_vals_16bpp[] = {
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 12, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 10, 0, 0, 0, 14, 0, 0, 0, 2, 0, 0, 4, 6, 12, 0,
-0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0,
-0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 11, 4, 0, 12, 0,
-0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0,
-0, 10, 0, 1, 0, 14, 0, 0, 0, 2, 0, 3, 4, 6, 12, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 12, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 10, 0, 0, 0, 14, 0, 0, 0, 2, 0, 0, 4, 6, 12, 0,
-0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0,
-0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 11, 4, 0, 12, 0,
-0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0,
-};
-
-static uint16 error_vals_18bpp[] = {
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 14,
-0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 9, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 7,
-0, 0, 0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0, 0, 0, 6,
-14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-7, 0, 0, 0, 0, 0, 0, 4, 0, 16, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3,
-0, 7, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 9, 0
-};
-#endif
-
-#ifdef FEATURE_MDDI_HITACHI
-extern void mddi_hitachi_window_adjust(uint16 x1,
-				       uint16 x2, uint16 y1, uint16 y2);
-#endif
-
-extern void mddi_toshiba_lcd_init(void);
-
-#ifdef FEATURE_MDDI_S6D0142
-extern void mddi_s6d0142_lcd_init(void);
-extern void mddi_s6d0142_window_adjust(uint16 x1,
-				       uint16 x2,
-				       uint16 y1,
-				       uint16 y2,
-				       mddi_llist_done_cb_type done_cb);
-#endif
-
-void mddi_init(void)
-{
-	if (mddi_host_initialized)
-		return;
-
-	mddi_host_initialized = TRUE;
-
-	sema_init(&mddi_host_mutex, 1);
-
-	if (!mddi_host_powered) {
-		down(&mddi_host_mutex);
-		mddi_host_init(MDDI_HOST_PRIM);
-		mddi_host_powered = TRUE;
-		up(&mddi_host_mutex);
-		mdelay(10);
-	}
-}
-
-int mddi_host_register_read(uint32 reg_addr,
-     uint32 *reg_value_ptr, boolean wait, mddi_host_type host) {
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-	int ret = 0;
-
-	if (in_interrupt())
-		MDDI_MSG_CRIT("Called from ISR context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		mddi_init();
-	}
-
-	down(&mddi_host_mutex);
-
-	mddi_reg_read_value_ptr = reg_value_ptr;
-	curr_llist_idx = mddi_get_reg_read_llist_item(host, TRUE);
-	if (curr_llist_idx == UNASSIGNED_INDEX) {
-		up(&mddi_host_mutex);
-
-		/* need to change this to some sort of wait */
-		MDDI_MSG_ERR("Attempting to queue up more than 1 reg read\n");
-		return -EINVAL;
-	}
-
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_ptr->link_controller_flags = 0x11;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count = 0;
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->packet_data_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = 0x8001;
-	regacc_pkt_ptr->register_address = reg_addr;
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, wait,
-				   NULL, host);
-	/* need to check if we can write the pointer or not */
-
-	up(&mddi_host_mutex);
-
-	if (wait) {
-		int wait_ret;
-
-		mddi_linked_list_notify_type *llist_notify_ptr;
-		llist_notify_ptr = &llist_extern_notify[host][curr_llist_idx];
-		wait_ret = wait_for_completion_timeout(
-					&(llist_notify_ptr->done_comp), 5 * HZ);
-
-		if (wait_ret <= 0)
-			ret = -EBUSY;
-
-		if (wait_ret < 0)
-			printk(KERN_ERR "%s: failed to wait for completion!\n",
-				__func__);
-		else if (!wait_ret)
-			printk(KERN_ERR "%s: Timed out waiting!\n", __func__);
-
-		if (!ret && (mddi_reg_read_value_ptr == reg_value_ptr) &&
-			(*reg_value_ptr == -EBUSY)) {
-			printk(KERN_ERR "%s - failed to get data from client",
-				   __func__);
-			mddi_reg_read_value_ptr = NULL;
-			ret = -EBUSY;
-		}
-	}
-
-	MDDI_MSG_DEBUG("Reg Read value=0x%x\n", *reg_value_ptr);
-
-	return ret;
-}				/* mddi_host_register_read */
-
-int mddi_host_register_write(uint32 reg_addr,
-     uint32 reg_val, enum mddi_data_packet_size_type packet_size,
-     boolean wait, mddi_llist_done_cb_type done_cb, mddi_host_type host) {
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_linked_list_type *curr_llist_dma_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-	int ret = 0;
-
-	if (in_interrupt())
-		MDDI_MSG_CRIT("Called from ISR context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		mddi_init();
-	}
-
-	down(&mddi_host_mutex);
-
-	curr_llist_idx = mddi_get_next_free_llist_item(host, TRUE);
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_dma_ptr = &llist_dma_extern[host][curr_llist_idx];
-
-	curr_llist_ptr->link_controller_flags = 1;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count = 4;
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count +
-					(uint16)packet_size;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = 0x0001;
-	regacc_pkt_ptr->register_address = reg_addr;
-	regacc_pkt_ptr->register_data_list[0] = reg_val;
-
-	MDDI_MSG_DEBUG("Reg Access write reg=0x%x, value=0x%x\n",
-		       regacc_pkt_ptr->register_address,
-		       regacc_pkt_ptr->register_data_list[0]);
-
-	regacc_pkt_ptr = &curr_llist_dma_ptr->packet_header.register_pkt;
-	curr_llist_ptr->packet_data_pointer =
-	    (void *)(&regacc_pkt_ptr->register_data_list[0]);
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, wait,
-				   done_cb, host);
-
-	up(&mddi_host_mutex);
-
-	if (wait) {
-		int wait_ret;
-
-		mddi_linked_list_notify_type *llist_notify_ptr;
-		llist_notify_ptr = &llist_extern_notify[host][curr_llist_idx];
-		wait_ret = wait_for_completion_timeout(
-					&(llist_notify_ptr->done_comp), 5 * HZ);
-
-		if (wait_ret <= 0)
-			ret = -EBUSY;
-
-		if (wait_ret < 0)
-			printk(KERN_ERR "%s: failed to wait for completion!\n",
-				__func__);
-		else if (!wait_ret)
-			printk(KERN_ERR "%s: Timed out waiting!\n", __func__);
-	}
-
-	return ret;
-}				/* mddi_host_register_write */
-
-boolean mddi_host_register_read_int
-    (uint32 reg_addr, uint32 *reg_value_ptr, mddi_host_type host) {
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-
-	if (!in_interrupt())
-		MDDI_MSG_CRIT("Called from TASK context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		return FALSE;
-	}
-
-	if (down_trylock(&mddi_host_mutex) != 0)
-		return FALSE;
-
-	mddi_reg_read_value_ptr = reg_value_ptr;
-	curr_llist_idx = mddi_get_reg_read_llist_item(host, FALSE);
-	if (curr_llist_idx == UNASSIGNED_INDEX) {
-		up(&mddi_host_mutex);
-		return FALSE;
-	}
-
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_ptr->link_controller_flags = 0x11;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count = 0;
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->packet_data_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = 0x8001;
-	regacc_pkt_ptr->register_address = reg_addr;
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, FALSE,
-				   NULL, host);
-	/* need to check if we can write the pointer or not */
-
-	up(&mddi_host_mutex);
-
-	return TRUE;
-
-}				/* mddi_host_register_read */
-
-boolean mddi_host_register_write_int
-    (uint32 reg_addr,
-     uint32 reg_val, mddi_llist_done_cb_type done_cb, mddi_host_type host) {
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_linked_list_type *curr_llist_dma_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-
-	if (!in_interrupt())
-		MDDI_MSG_CRIT("Called from TASK context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		return FALSE;
-	}
-
-	if (down_trylock(&mddi_host_mutex) != 0)
-		return FALSE;
-
-	curr_llist_idx = mddi_get_next_free_llist_item(host, FALSE);
-	if (curr_llist_idx == UNASSIGNED_INDEX) {
-		up(&mddi_host_mutex);
-		return FALSE;
-	}
-
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_dma_ptr = &llist_dma_extern[host][curr_llist_idx];
-
-	curr_llist_ptr->link_controller_flags = 1;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count = 4;
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count + 4;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = 0x0001;
-	regacc_pkt_ptr->register_address = reg_addr;
-	regacc_pkt_ptr->register_data_list[0] = reg_val;
-
-	regacc_pkt_ptr = &curr_llist_dma_ptr->packet_header.register_pkt;
-	curr_llist_ptr->packet_data_pointer =
-	    (void *)(&(regacc_pkt_ptr->register_data_list[0]));
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, FALSE,
-				   done_cb, host);
-	up(&mddi_host_mutex);
-
-	return TRUE;
-
-}				/* mddi_host_register_write */
-
-void mddi_wait(uint16 time_ms)
-{
-	mdelay(time_ms);
-}
-
-void mddi_client_lcd_vsync_detected(boolean detected)
-{
-	if (mddi_lcd.vsync_detected)
-		(*mddi_lcd.vsync_detected) (detected);
-}
-
-/* extended version of function includes done callback */
-void mddi_window_adjust_ext(struct msm_fb_data_type *mfd,
-			    uint16 x1,
-			    uint16 x2,
-			    uint16 y1,
-			    uint16 y2, mddi_llist_done_cb_type done_cb)
-{
-#ifdef FEATURE_MDDI_HITACHI
-	if (mfd->panel.id == HITACHI)
-		mddi_hitachi_window_adjust(x1, x2, y1, y2);
-#elif defined(FEATURE_MDDI_S6D0142)
-	if (mfd->panel.id == MDDI_LCD_S6D0142)
-		mddi_s6d0142_window_adjust(x1, x2, y1, y2, done_cb);
-#else
-	/* Do nothing then... except avoid lint/compiler warnings */
-	(void)x1;
-	(void)x2;
-	(void)y1;
-	(void)y2;
-	(void)done_cb;
-#endif
-}
-
-void mddi_window_adjust(struct msm_fb_data_type *mfd,
-			uint16 x1, uint16 x2, uint16 y1, uint16 y2)
-{
-	mddi_window_adjust_ext(mfd, x1, x2, y1, y2, NULL);
-}
-
-#ifdef MDDI_HOST_WINDOW_WORKAROUND
-uint16 mddi_assign_pkt_height(uint16 pkt_width,
-	uint16 pkt_height, uint16 bpp)
-{
-	uint16 new_pkt_height;
-	uint16 problem_height = 0;
-
-	if (pkt_width <= 240) {
-		if (bpp == 16)
-			problem_height = error_vals_16bpp[pkt_width-1];
-		else if (bpp == 18)
-			problem_height = error_vals_18bpp[pkt_width-1];
-		else {
-			printk(KERN_ERR"Invalid bpp value");
-			return -EINVAL;
-		}
-	}
-	if (problem_height == pkt_height)
-		new_pkt_height = problem_height - 1;
-	else
-		new_pkt_height = pkt_height;
-
-	return new_pkt_height;
-}
-#endif
-
-#ifdef ENABLE_MDDI_MULTI_READ_WRITE
-int mddi_host_register_multiwrite(uint32 reg_addr,
-	uint32 *value_list_ptr,
-	uint32 value_count, boolean wait, mddi_llist_done_cb_type done_cb,
-	mddi_host_type host)
-{
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_linked_list_type *curr_llist_dma_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-	int ret = 0;
-
-	if (!value_list_ptr || !value_count ||
-		value_count > MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR) {
-		MDDI_MSG_ERR("\n Invalid value_list or value_count");
-		return -EINVAL;
-	}
-
-	if (in_interrupt())
-		MDDI_MSG_CRIT("Called from ISR context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		mddi_init();
-	}
-
-	down(&mddi_host_mutex);
-
-	curr_llist_idx = mddi_get_next_free_llist_item(host, TRUE);
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_dma_ptr = &llist_dma_extern[host][curr_llist_idx];
-
-	curr_llist_ptr->link_controller_flags = 1;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count =
-		(uint16)(value_count * 4);
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count
-		+ curr_llist_ptr->packet_data_count;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = value_count;
-	regacc_pkt_ptr->register_address = reg_addr;
-	memcpy((void *)&regacc_pkt_ptr->register_data_list[0], value_list_ptr,
-		   curr_llist_ptr->packet_data_count);
-
-	regacc_pkt_ptr = &curr_llist_dma_ptr->packet_header.register_pkt;
-	curr_llist_ptr->packet_data_pointer =
-		(void *)(&regacc_pkt_ptr->register_data_list[0]);
-	MDDI_MSG_DEBUG("MultiReg Access write reg=0x%x, value[0]=0x%x\n",
-		       regacc_pkt_ptr->register_address,
-		       regacc_pkt_ptr->register_data_list[0]);
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, wait,
-				   done_cb, host);
-
-	up(&mddi_host_mutex);
-
-	if (wait) {
-		int wait_ret;
-
-		mddi_linked_list_notify_type *llist_notify_ptr;
-		llist_notify_ptr = &llist_extern_notify[host][curr_llist_idx];
-		wait_ret = wait_for_completion_timeout(
-					&(llist_notify_ptr->done_comp), 5 * HZ);
-
-		if (wait_ret <= 0)
-			ret = -EBUSY;
-
-		if (wait_ret < 0)
-			printk(KERN_ERR "%s: failed to wait for completion!\n",
-				__func__);
-		else if (!wait_ret)
-			printk(KERN_ERR "%s: Timed out waiting!\n", __func__);
-	}
-
-	return ret;
-}
-
-int mddi_host_register_multiread(uint32 reg_addr,
-	uint32 *value_list_ptr, uint32 value_count,
-	boolean wait, mddi_host_type host) {
-	mddi_linked_list_type *curr_llist_ptr;
-	mddi_register_access_packet_type *regacc_pkt_ptr;
-	uint16 curr_llist_idx;
-	int ret = 0;
-
-	if (!value_list_ptr || !value_count ||
-		value_count >= MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR) {
-		MDDI_MSG_ERR("\n Invalid value_list or value_count");
-		return -EINVAL;
-	}
-
-	if (in_interrupt())
-		MDDI_MSG_CRIT("Called from ISR context\n");
-
-	if (!mddi_host_powered) {
-		MDDI_MSG_ERR("MDDI powered down!\n");
-		mddi_init();
-	}
-
-	down(&mddi_host_mutex);
-
-	mddi_reg_read_value_ptr = value_list_ptr;
-	curr_llist_idx = mddi_get_reg_read_llist_item(host, TRUE);
-	if (curr_llist_idx == UNASSIGNED_INDEX) {
-		up(&mddi_host_mutex);
-
-		/* need to change this to some sort of wait */
-		MDDI_MSG_ERR("Attempting to queue up more than 1 reg read\n");
-		return -EINVAL;
-	}
-
-	curr_llist_ptr = &llist_extern[host][curr_llist_idx];
-	curr_llist_ptr->link_controller_flags = 0x11;
-	curr_llist_ptr->packet_header_count = 14;
-	curr_llist_ptr->packet_data_count = 0;
-
-	curr_llist_ptr->next_packet_pointer = NULL;
-	curr_llist_ptr->packet_data_pointer = NULL;
-	curr_llist_ptr->reserved = 0;
-
-	regacc_pkt_ptr = &curr_llist_ptr->packet_header.register_pkt;
-
-	regacc_pkt_ptr->packet_length = curr_llist_ptr->packet_header_count;
-	regacc_pkt_ptr->packet_type = 146;	/* register access packet */
-	regacc_pkt_ptr->bClient_ID = 0;
-	regacc_pkt_ptr->read_write_info = 0x8000 | value_count;
-	regacc_pkt_ptr->register_address = reg_addr;
-
-	/* now adjust pointers */
-	mddi_queue_forward_packets(curr_llist_idx, curr_llist_idx, wait,
-				   NULL, host);
-	/* need to check if we can write the pointer or not */
-
-	up(&mddi_host_mutex);
-
-	if (wait) {
-		int wait_ret;
-
-		mddi_linked_list_notify_type *llist_notify_ptr;
-		llist_notify_ptr = &llist_extern_notify[host][curr_llist_idx];
-		wait_ret = wait_for_completion_timeout(
-					&(llist_notify_ptr->done_comp), 5 * HZ);
-
-		if (wait_ret <= 0)
-			ret = -EBUSY;
-
-		if (wait_ret < 0)
-			printk(KERN_ERR "%s: failed to wait for completion!\n",
-				__func__);
-		else if (!wait_ret)
-			printk(KERN_ERR "%s: Timed out waiting!\n", __func__);
-
-		if (!ret && (mddi_reg_read_value_ptr == value_list_ptr) &&
-			(*value_list_ptr == -EBUSY)) {
-			printk(KERN_ERR "%s - failed to get data from client",
-				   __func__);
-			mddi_reg_read_value_ptr = NULL;
-			ret = -EBUSY;
-		}
-	}
-
-	MDDI_MSG_DEBUG("MultiReg Read value[0]=0x%x\n", *value_list_ptr);
-
-	return ret;
-}
-#endif
diff --git a/drivers/video/msm/mddihost.h b/drivers/video/msm/mddihost.h
deleted file mode 100644
index db2df38..0000000
--- a/drivers/video/msm/mddihost.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef MDDIHOST_H
-#define MDDIHOST_H
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include "linux/proc_fs.h"
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-
-#include <mach/hardware.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/types.h>
-#include <linux/dma-mapping.h>
-
-#include "msm_fb_panel.h"
-
-#undef FEATURE_MDDI_MC4
-#undef FEATURE_MDDI_S6D0142
-#undef FEATURE_MDDI_HITACHI
-#define FEATURE_MDDI_SHARP
-#define FEATURE_MDDI_TOSHIBA
-#undef FEATURE_MDDI_E751
-#define FEATURE_MDDI_CORONA
-#define FEATURE_MDDI_PRISM
-
-#define T_MSM7500
-
-typedef enum {
-	format_16bpp,
-	format_18bpp,
-	format_24bpp
-} mddi_video_format;
-
-typedef enum {
-	MDDI_LCD_NONE = 0,
-	MDDI_LCD_MC4,
-	MDDI_LCD_S6D0142,
-	MDDI_LCD_SHARP,
-	MDDI_LCD_E751,
-	MDDI_LCD_CORONA,
-	MDDI_LCD_HITACHI,
-	MDDI_LCD_TOSHIBA,
-	MDDI_LCD_PRISM,
-	MDDI_LCD_TP2,
-	MDDI_NUM_LCD_TYPES,
-	MDDI_LCD_DEFAULT = MDDI_LCD_TOSHIBA
-} mddi_lcd_type;
-
-typedef enum {
-	MDDI_HOST_PRIM = 0,
-	MDDI_HOST_EXT,
-	MDDI_NUM_HOST_CORES
-} mddi_host_type;
-
-typedef enum {
-	MDDI_DRIVER_RESET,	/* host core registers have not been written. */
-	MDDI_DRIVER_DISABLED,	/* registers written, interrupts disabled. */
-	MDDI_DRIVER_ENABLED	/* registers written, interrupts enabled. */
-} mddi_host_driver_state_type;
-
-typedef enum {
-	MDDI_GPIO_INT_0 = 0,
-	MDDI_GPIO_INT_1,
-	MDDI_GPIO_INT_2,
-	MDDI_GPIO_INT_3,
-	MDDI_GPIO_INT_4,
-	MDDI_GPIO_INT_5,
-	MDDI_GPIO_INT_6,
-	MDDI_GPIO_INT_7,
-	MDDI_GPIO_INT_8,
-	MDDI_GPIO_INT_9,
-	MDDI_GPIO_INT_10,
-	MDDI_GPIO_INT_11,
-	MDDI_GPIO_INT_12,
-	MDDI_GPIO_INT_13,
-	MDDI_GPIO_INT_14,
-	MDDI_GPIO_INT_15,
-	MDDI_GPIO_NUM_INTS
-} mddi_gpio_int_type;
-
-enum mddi_data_packet_size_type {
-	MDDI_DATA_PACKET_4_BYTES  = 4,
-	MDDI_DATA_PACKET_8_BYTES  = 8,
-	MDDI_DATA_PACKET_12_BYTES = 12,
-	MDDI_DATA_PACKET_16_BYTES = 16,
-	MDDI_DATA_PACKET_24_BYTES = 24
-};
-
-typedef struct {
-	uint32 addr;
-	uint32 value;
-} mddi_reg_write_type;
-
-boolean mddi_vsync_set_handler(msm_fb_vsync_handler_type handler, void *arg);
-
-typedef void (*mddi_llist_done_cb_type) (void);
-
-typedef void (*mddi_rev_handler_type) (void *);
-
-boolean mddi_set_rev_handler(mddi_rev_handler_type handler, uint16 pkt_type);
-
-#define MDDI_DEFAULT_PRIM_PIX_ATTR 0xC3
-#define MDDI_DEFAULT_SECD_PIX_ATTR 0xC0
-
-typedef int gpio_int_polarity_type;
-typedef int gpio_int_handler_type;
-
-typedef struct {
-	void (*vsync_detected) (boolean);
-} mddi_lcd_func_type;
-
-extern mddi_lcd_func_type mddi_lcd;
-extern int irq_enabled;
-extern unsigned char mddi_timer_shutdown_flag;
-extern struct mutex mddi_timer_lock;
-
-void mddi_init(void);
-void mddi_powerdown(void);
-
-void mddi_host_start_ext_display(void);
-void mddi_host_stop_ext_display(void);
-
-extern spinlock_t mddi_host_spin_lock;
-#ifdef T_MSM7500
-void mddi_reset(void);
-#ifdef FEATURE_DUAL_PROC_MODEM_DISPLAY
-void mddi_host_switch_proc_control(boolean on);
-#endif
-#endif
-void mddi_host_exit_power_collapse(void);
-
-void mddi_queue_splash_screen
-    (void *buf_ptr,
-     boolean clear_area,
-     int16 src_width,
-     int16 src_starting_row,
-     int16 src_starting_column,
-     int16 num_of_rows,
-     int16 num_of_columns, int16 dst_starting_row, int16 dst_starting_column);
-
-void mddi_queue_image
-    (void *buf_ptr,
-     uint8 stereo_video,
-     boolean clear_area,
-     int16 src_width,
-     int16 src_starting_row,
-     int16 src_starting_column,
-     int16 num_of_rows,
-     int16 num_of_columns, int16 dst_starting_row, int16 dst_starting_column);
-
-int mddi_host_register_read
-    (uint32 reg_addr,
-     uint32 *reg_value_ptr, boolean wait, mddi_host_type host_idx);
-int mddi_host_register_write
-    (uint32 reg_addr, uint32 reg_val,
-     enum mddi_data_packet_size_type packet_size,
-     boolean wait, mddi_llist_done_cb_type done_cb, mddi_host_type host);
-boolean mddi_host_register_write_int
-    (uint32 reg_addr,
-     uint32 reg_val, mddi_llist_done_cb_type done_cb, mddi_host_type host);
-boolean mddi_host_register_read_int
-    (uint32 reg_addr, uint32 *reg_value_ptr, mddi_host_type host_idx);
-void mddi_queue_register_write_static
-    (uint32 reg_addr,
-     uint32 reg_val, boolean wait, mddi_llist_done_cb_type done_cb);
-void mddi_queue_static_window_adjust
-    (const mddi_reg_write_type *reg_write,
-     uint16 num_writes, mddi_llist_done_cb_type done_cb);
-
-#ifdef ENABLE_MDDI_MULTI_READ_WRITE
-int mddi_host_register_multiwrite(uint32 reg_addr,
-	uint32 *value_list_ptr, uint32 value_count,
-    boolean wait, mddi_llist_done_cb_type done_cb,
-	mddi_host_type host);
-int mddi_host_register_multiread(uint32 reg_addr,
-	uint32 *value_list_ptr, uint32 value_count,
-	boolean wait, mddi_host_type host);
-#endif
-
-#define mddi_queue_register_read(reg, val_ptr, wait, sig) \
-	mddi_host_register_read(reg, val_ptr, wait, MDDI_HOST_PRIM)
-#define mddi_queue_register_write(reg, val, wait, sig) \
-	mddi_host_register_write(reg, val, MDDI_DATA_PACKET_4_BYTES,\
-	wait, NULL, MDDI_HOST_PRIM)
-#define mddi_queue_register_write_extn(reg, val, pkt_size, wait, sig) \
-	mddi_host_register_write(reg, val, pkt_size, \
-	wait, NULL, MDDI_HOST_PRIM)
-#define mddi_queue_register_write_int(reg, val) \
-	mddi_host_register_write_int(reg, val, NULL, MDDI_HOST_PRIM)
-#define mddi_queue_register_read_int(reg, val_ptr) \
-	mddi_host_register_read_int(reg, val_ptr, MDDI_HOST_PRIM)
-#define mddi_queue_register_writes(reg_ptr, val, wait, sig) \
-	mddi_host_register_writes(reg_ptr, val, wait, sig, MDDI_HOST_PRIM)
-
-void mddi_wait(uint16 time_ms);
-void mddi_assign_max_pkt_dimensions(uint16 image_cols,
-				    uint16 image_rows,
-				    uint16 bpp,
-				    uint16 *max_cols, uint16 * max_rows);
-#ifdef MDDI_HOST_WINDOW_WORKAROUND
-uint16 mddi_assign_pkt_height(uint16 pkt_width, uint16 pkt_height, uint16 bpp);
-#endif
-void mddi_queue_reverse_encapsulation(boolean wait);
-int mddi_client_power(unsigned int client_id);
-void mddi_disable(int lock);
-void mddi_window_adjust(struct msm_fb_data_type *mfd,
-	uint16 x1, uint16 x2, uint16 y1, uint16 y2);
-void mddi_send_fw_link_skew_cal(mddi_host_type host_idx);
-int pmdh_clk_func(int enable);
-
-#endif /* MDDIHOST_H */
diff --git a/drivers/video/msm/mddihost_e.c b/drivers/video/msm/mddihost_e.c
deleted file mode 100644
index 275e4ee..0000000
--- a/drivers/video/msm/mddihost_e.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-#include <linux/clk.h>
-#include <mach/clk.h>
-
-extern struct semaphore mddi_host_mutex;
-static boolean mddi_host_ext_powered = FALSE;
-
-void mddi_host_start_ext_display(void)
-{
-	down(&mddi_host_mutex);
-
-	if (!mddi_host_ext_powered) {
-		mddi_host_init(MDDI_HOST_EXT);
-
-		mddi_host_ext_powered = TRUE;
-	}
-
-	up(&mddi_host_mutex);
-}
-
-void mddi_host_stop_ext_display(void)
-{
-	down(&mddi_host_mutex);
-
-	if (mddi_host_ext_powered) {
-		mddi_host_powerdown(MDDI_HOST_EXT);
-
-		mddi_host_ext_powered = FALSE;
-	}
-
-	up(&mddi_host_mutex);
-}
diff --git a/drivers/video/msm/mddihosti.c b/drivers/video/msm/mddihosti.c
deleted file mode 100644
index b4429f6..0000000
--- a/drivers/video/msm/mddihosti.c
+++ /dev/null
@@ -1,2268 +0,0 @@
-/* Copyright (c) 2008-2010, 2012 The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-#include <linux/mm.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-
-#include "msm_fb_panel.h"
-#include "mddihost.h"
-#include "mddihosti.h"
-
-#define FEATURE_MDDI_UNDERRUN_RECOVERY
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-static void mddi_read_rev_packet(byte *data_ptr);
-#endif
-
-struct timer_list mddi_host_timer;
-
-#define MDDI_DEFAULT_TIMER_LENGTH 5000	/* 5 seconds */
-uint32 mddi_rtd_frequency = 60000;	/* send RTD every 60 seconds */
-uint32 mddi_client_status_frequency = 60000;	/* get status pkt every 60 secs */
-
-boolean mddi_vsync_detect_enabled = FALSE;
-mddi_gpio_info_type mddi_gpio;
-
-uint32 mddi_host_core_version;
-boolean mddi_debug_log_statistics = FALSE;
-/* #define FEATURE_MDDI_HOST_ENABLE_EARLY_HIBERNATION */
-/* default to TRUE in case MDP does not vote */
-static boolean mddi_host_mdp_active_flag = TRUE;
-static uint32 mddi_log_stats_counter;
-uint32 mddi_log_stats_frequency = 4000;
-int32 mddi_client_type;
-
-#define MDDI_DEFAULT_REV_PKT_SIZE            0x20
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-static boolean mddi_rev_ptr_workaround = TRUE;
-static uint32 mddi_reg_read_retry;
-static uint32 mddi_reg_read_retry_max = 20;
-static boolean mddi_enable_reg_read_retry = TRUE;
-static boolean mddi_enable_reg_read_retry_once = FALSE;
-
-#define MDDI_MAX_REV_PKT_SIZE                0x60
-
-#define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE  0x60
-
-#define MDDI_VIDEO_REV_PKT_SIZE              0x40
-#define MDDI_REV_BUFFER_SIZE  MDDI_MAX_REV_PKT_SIZE
-static byte rev_packet_data[MDDI_MAX_REV_PKT_SIZE];
-#endif /* FEATURE_MDDI_DISABLE_REVERSE */
-/* leave these variables so graphics will compile */
-
-#define MDDI_MAX_REV_DATA_SIZE  128
-/*lint -d__align(x) */
-boolean mddi_debug_clear_rev_data = TRUE;
-
-uint32 *mddi_reg_read_value_ptr;
-
-mddi_client_capability_type mddi_client_capability_pkt;
-static boolean mddi_client_capability_request = FALSE;
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-
-#define MAX_MDDI_REV_HANDLERS 2
-#define INVALID_PKT_TYPE 0xFFFF
-
-typedef struct {
-	mddi_rev_handler_type handler;	/* ISR to be executed */
-	uint16 pkt_type;
-} mddi_rev_pkt_handler_type;
-static mddi_rev_pkt_handler_type mddi_rev_pkt_handler[MAX_MDDI_REV_HANDLERS] =
-    { {NULL, INVALID_PKT_TYPE}, {NULL, INVALID_PKT_TYPE} };
-
-static boolean mddi_rev_encap_user_request = FALSE;
-static mddi_linked_list_notify_type mddi_rev_user;
-
-spinlock_t mddi_host_spin_lock;
-extern uint32 mdp_in_processing;
-#endif
-
-typedef enum {
-	MDDI_REV_IDLE
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	    , MDDI_REV_REG_READ_ISSUED,
-	MDDI_REV_REG_READ_SENT,
-	MDDI_REV_ENCAP_ISSUED,
-	MDDI_REV_STATUS_REQ_ISSUED,
-	MDDI_REV_CLIENT_CAP_ISSUED
-#endif
-} mddi_rev_link_state_type;
-
-typedef enum {
-	MDDI_LINK_DISABLED,
-	MDDI_LINK_HIBERNATING,
-	MDDI_LINK_ACTIVATING,
-	MDDI_LINK_ACTIVE
-} mddi_host_link_state_type;
-
-typedef struct {
-	uint32 count;
-	uint32 in_count;
-	uint32 disp_req_count;
-	uint32 state_change_count;
-	uint32 ll_done_count;
-	uint32 rev_avail_count;
-	uint32 error_count;
-	uint32 rev_encap_count;
-	uint32 llist_ptr_write_1;
-	uint32 llist_ptr_write_2;
-} mddi_host_int_type;
-
-typedef struct {
-	uint32 fwd_crc_count;
-	uint32 rev_crc_count;
-	uint32 pri_underflow;
-	uint32 sec_underflow;
-	uint32 rev_overflow;
-	uint32 pri_overwrite;
-	uint32 sec_overwrite;
-	uint32 rev_overwrite;
-	uint32 dma_failure;
-	uint32 rtd_failure;
-	uint32 reg_read_failure;
-#ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
-	uint32 pri_underrun_detected;
-#endif
-} mddi_host_stat_type;
-
-typedef struct {
-	uint32 rtd_cnt;
-	uint32 rev_enc_cnt;
-	uint32 vid_cnt;
-	uint32 reg_acc_cnt;
-	uint32 cli_stat_cnt;
-	uint32 cli_cap_cnt;
-	uint32 reg_read_cnt;
-	uint32 link_active_cnt;
-	uint32 link_hibernate_cnt;
-	uint32 vsync_response_cnt;
-	uint32 fwd_crc_cnt;
-	uint32 rev_crc_cnt;
-} mddi_log_params_struct_type;
-
-typedef struct {
-	uint32 rtd_value;
-	uint32 rtd_counter;
-	uint32 client_status_cnt;
-	boolean rev_ptr_written;
-	uint8 *rev_ptr_start;
-	uint8 *rev_ptr_curr;
-	uint32 mddi_rev_ptr_write_val;
-	dma_addr_t rev_data_dma_addr;
-	uint16 rev_pkt_size;
-	mddi_rev_link_state_type rev_state;
-	mddi_host_link_state_type link_state;
-	mddi_host_driver_state_type driver_state;
-	boolean disable_hibernation;
-	uint32 saved_int_reg;
-	uint32 saved_int_en;
-	mddi_linked_list_type *llist_ptr;
-	dma_addr_t llist_dma_addr;
-	mddi_linked_list_type *llist_dma_ptr;
-	uint32 *rev_data_buf;
-	struct completion mddi_llist_avail_comp;
-	boolean mddi_waiting_for_llist_avail;
-	mddi_host_int_type int_type;
-	mddi_host_stat_type stats;
-	mddi_log_params_struct_type log_parms;
-	mddi_llist_info_type llist_info;
-	mddi_linked_list_notify_type llist_notify[MDDI_MAX_NUM_LLIST_ITEMS];
-} mddi_host_cntl_type;
-
-static mddi_host_type mddi_curr_host = MDDI_HOST_PRIM;
-static mddi_host_cntl_type mhctl[MDDI_NUM_HOST_CORES];
-mddi_linked_list_type *llist_extern[MDDI_NUM_HOST_CORES];
-mddi_linked_list_type *llist_dma_extern[MDDI_NUM_HOST_CORES];
-mddi_linked_list_notify_type *llist_extern_notify[MDDI_NUM_HOST_CORES];
-static mddi_log_params_struct_type prev_parms[MDDI_NUM_HOST_CORES];
-
-extern uint32 mdp_total_vdopkts;
-
-static boolean mddi_host_io_clock_on = FALSE;
-static boolean mddi_host_hclk_on = FALSE;
-
-int int_mddi_pri_flag = FALSE;
-int int_mddi_ext_flag = FALSE;
-
-static void mddi_report_errors(uint32 int_reg)
-{
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if (int_reg & MDDI_INT_PRI_UNDERFLOW) {
-		pmhctl->stats.pri_underflow++;
-		MDDI_MSG_ERR("!!! MDDI Primary Underflow !!!\n");
-	}
-	if (int_reg & MDDI_INT_SEC_UNDERFLOW) {
-		pmhctl->stats.sec_underflow++;
-		MDDI_MSG_ERR("!!! MDDI Secondary Underflow !!!\n");
-	}
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	if (int_reg & MDDI_INT_REV_OVERFLOW) {
-		pmhctl->stats.rev_overflow++;
-		MDDI_MSG_ERR("!!! MDDI Reverse Overflow !!!\n");
-		pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-		mddi_host_reg_out(REV_PTR, pmhctl->mddi_rev_ptr_write_val);
-
-	}
-	if (int_reg & MDDI_INT_CRC_ERROR)
-		MDDI_MSG_ERR("!!! MDDI Reverse CRC Error !!!\n");
-#endif
-	if (int_reg & MDDI_INT_PRI_OVERWRITE) {
-		pmhctl->stats.pri_overwrite++;
-		MDDI_MSG_ERR("!!! MDDI Primary Overwrite !!!\n");
-	}
-	if (int_reg & MDDI_INT_SEC_OVERWRITE) {
-		pmhctl->stats.sec_overwrite++;
-		MDDI_MSG_ERR("!!! MDDI Secondary Overwrite !!!\n");
-	}
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	if (int_reg & MDDI_INT_REV_OVERWRITE) {
-		pmhctl->stats.rev_overwrite++;
-		/* This will show up normally and is not a problem */
-		MDDI_MSG_DEBUG("MDDI Reverse Overwrite!\n");
-	}
-	if (int_reg & MDDI_INT_RTD_FAILURE) {
-		mddi_host_reg_outm(INTEN, MDDI_INT_RTD_FAILURE, 0);
-		pmhctl->stats.rtd_failure++;
-		MDDI_MSG_ERR("!!! MDDI RTD Failure !!!\n");
-	}
-#endif
-	if (int_reg & MDDI_INT_DMA_FAILURE) {
-		pmhctl->stats.dma_failure++;
-		MDDI_MSG_ERR("!!! MDDI DMA Abort !!!\n");
-	}
-}
-
-static void mddi_host_enable_io_clock(void)
-{
-	if (!MDDI_HOST_IS_IO_CLOCK_ON)
-		MDDI_HOST_ENABLE_IO_CLOCK;
-}
-
-static void mddi_host_enable_hclk(void)
-{
-
-	if (!MDDI_HOST_IS_HCLK_ON)
-		MDDI_HOST_ENABLE_HCLK;
-}
-
-static void mddi_host_disable_io_clock(void)
-{
-#ifndef FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE
-	if (MDDI_HOST_IS_IO_CLOCK_ON)
-		MDDI_HOST_DISABLE_IO_CLOCK;
-#endif
-}
-
-static void mddi_host_disable_hclk(void)
-{
-#ifndef FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE
-	if (MDDI_HOST_IS_HCLK_ON)
-		MDDI_HOST_DISABLE_HCLK;
-#endif
-}
-
-static void mddi_vote_to_sleep(mddi_host_type host_idx, boolean sleep)
-{
-	uint16 vote_mask;
-
-	if (host_idx == MDDI_HOST_PRIM)
-		vote_mask = 0x01;
-	else
-		vote_mask = 0x02;
-}
-
-static void mddi_report_state_change(uint32 int_reg)
-{
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if ((pmhctl->saved_int_reg & MDDI_INT_IN_HIBERNATION) &&
-	    (pmhctl->saved_int_reg & MDDI_INT_LINK_ACTIVE)) {
-		/* recover from condition where the io_clock was turned off by the
-		   clock driver during a transition to hibernation. The io_clock
-		   disable is to prevent MDP/MDDI underruns when changing ARM
-		   clock speeds. In the process of halting the ARM, the hclk
-		   divider needs to be set to 1. When it is set to 1, there is
-		   a small time (usecs) when hclk is off or slow, and this can
-		   cause an underrun. To prevent the underrun, clock driver turns
-		   off the MDDI io_clock before making the change. */
-		mddi_host_reg_out(CMD, MDDI_CMD_POWERUP);
-	}
-
-	if (int_reg & MDDI_INT_LINK_ACTIVE) {
-		pmhctl->link_state = MDDI_LINK_ACTIVE;
-		pmhctl->log_parms.link_active_cnt++;
-		pmhctl->rtd_value = mddi_host_reg_in(RTD_VAL);
-		MDDI_MSG_DEBUG("!!! MDDI Active RTD:0x%x!!!\n",
-			       pmhctl->rtd_value);
-		/* now interrupt on hibernation */
-		mddi_host_reg_outm(INTEN,
-				   (MDDI_INT_IN_HIBERNATION |
-				    MDDI_INT_LINK_ACTIVE),
-				   MDDI_INT_IN_HIBERNATION);
-
-#ifdef DEBUG_MDDIHOSTI
-		/* if gpio interrupt is enabled, start polling at fastest
-		 * registered rate
-		 */
-		if (mddi_gpio.polling_enabled) {
-			timer_reg(&mddi_gpio_poll_timer,
-		mddi_gpio_poll_timer_cb, 0, mddi_gpio.polling_interval, 0);
-		}
-#endif
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (mddi_rev_ptr_workaround) {
-			/* HW CR: need to reset reverse register stuff */
-			pmhctl->rev_ptr_written = FALSE;
-			pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-		}
-#endif
-		/* vote on sleep */
-		mddi_vote_to_sleep(host_idx, FALSE);
-
-		if (host_idx == MDDI_HOST_PRIM) {
-			if (mddi_vsync_detect_enabled) {
-				/*
-				 * Indicate to client specific code that vsync
-				 * was enabled, but we did not detect a client
-				 * intiated wakeup. The client specific
-				 * handler can either reassert vsync detection,
-				 * or treat this as a valid vsync.
-				 */
-				mddi_client_lcd_vsync_detected(FALSE);
-				pmhctl->log_parms.vsync_response_cnt++;
-			}
-		}
-	}
-	if (int_reg & MDDI_INT_IN_HIBERNATION) {
-		pmhctl->link_state = MDDI_LINK_HIBERNATING;
-		pmhctl->log_parms.link_hibernate_cnt++;
-		MDDI_MSG_DEBUG("!!! MDDI Hibernating !!!\n");
-
-		if (mddi_client_type == 2) {
-			mddi_host_reg_out(PAD_CTL, 0x402a850f);
-			mddi_host_reg_out(PAD_CAL, 0x10220020);
-			mddi_host_reg_out(TA1_LEN, 0x0010);
-			mddi_host_reg_out(TA2_LEN, 0x0040);
-		}
-		/* now interrupt on link_active */
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-		mddi_host_reg_outm(INTEN,
-				   (MDDI_INT_MDDI_IN |
-				    MDDI_INT_IN_HIBERNATION |
-				    MDDI_INT_LINK_ACTIVE),
-				   MDDI_INT_LINK_ACTIVE);
-#else
-		mddi_host_reg_outm(INTEN,
-				   (MDDI_INT_MDDI_IN |
-				    MDDI_INT_IN_HIBERNATION |
-				    MDDI_INT_LINK_ACTIVE),
-				   (MDDI_INT_MDDI_IN | MDDI_INT_LINK_ACTIVE));
-
-		pmhctl->rtd_counter = mddi_rtd_frequency;
-
-		if (pmhctl->rev_state != MDDI_REV_IDLE) {
-			/* a rev_encap will not wake up the link, so we do that here */
-			pmhctl->link_state = MDDI_LINK_ACTIVATING;
-			mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-		}
-#endif
-
-		if (pmhctl->disable_hibernation) {
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
-			mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-			pmhctl->link_state = MDDI_LINK_ACTIVATING;
-		}
-#ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
-		if ((pmhctl->llist_info.transmitting_start_idx !=
-		     UNASSIGNED_INDEX)
-		    &&
-		    ((pmhctl->
-		      saved_int_reg & (MDDI_INT_PRI_LINK_LIST_DONE |
-				       MDDI_INT_PRI_PTR_READ)) ==
-		     MDDI_INT_PRI_PTR_READ)) {
-			mddi_linked_list_type *llist_dma;
-			llist_dma = pmhctl->llist_dma_ptr;
-			/*
-			 * All indications are that we have not received a
-			 * linked list done interrupt, due to an underrun
-			 * condition. Recovery attempt is to send again.
-			 */
-			dma_coherent_pre_ops();
-			/* Write to primary pointer register again */
-			mddi_host_reg_out(PRI_PTR,
-					  &llist_dma[pmhctl->llist_info.
-						     transmitting_start_idx]);
-			pmhctl->stats.pri_underrun_detected++;
-		}
-#endif
-
-		/* vote on sleep */
-		if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
-			mddi_vote_to_sleep(host_idx, TRUE);
-		}
-
-#ifdef DEBUG_MDDIHOSTI
-		/* need to stop polling timer */
-		if (mddi_gpio.polling_enabled) {
-			(void) timer_clr(&mddi_gpio_poll_timer, T_NONE);
-		}
-#endif
-	}
-}
-
-void mddi_host_timer_service(unsigned long data)
-{
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	unsigned long flags;
-#endif
-	mddi_host_type host_idx;
-	mddi_host_cntl_type *pmhctl;
-
-	unsigned long time_ms = MDDI_DEFAULT_TIMER_LENGTH;
-	init_timer(&mddi_host_timer);
-	for (host_idx = MDDI_HOST_PRIM; host_idx < MDDI_NUM_HOST_CORES;
-	     host_idx++) {
-		pmhctl = &(mhctl[host_idx]);
-		mddi_log_stats_counter += (uint32) time_ms;
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		pmhctl->rtd_counter += (uint32) time_ms;
-		pmhctl->client_status_cnt += (uint32) time_ms;
-
-		if (host_idx == MDDI_HOST_PRIM) {
-			if (pmhctl->client_status_cnt >=
-			    mddi_client_status_frequency) {
-				if ((pmhctl->link_state ==
-				     MDDI_LINK_HIBERNATING)
-				    && (pmhctl->client_status_cnt >
-					mddi_client_status_frequency)) {
-					/*
-					 * special case where we are hibernating
-					 * and mddi_host_isr is not firing, so
-					 * kick the link so that the status can
-					 * be retrieved
-					 */
-
-					/* need to wake up link before issuing
-					 * rev encap command
-					 */
-					MDDI_MSG_INFO("wake up link!\n");
-					spin_lock_irqsave(&mddi_host_spin_lock,
-							  flags);
-					mddi_host_enable_hclk();
-					mddi_host_enable_io_clock();
-					pmhctl->link_state =
-					    MDDI_LINK_ACTIVATING;
-					mddi_host_reg_out(CMD,
-							  MDDI_CMD_LINK_ACTIVE);
-					spin_unlock_irqrestore
-					    (&mddi_host_spin_lock, flags);
-				} else
-				    if ((pmhctl->link_state == MDDI_LINK_ACTIVE)
-					&& pmhctl->disable_hibernation) {
-					/*
-					 * special case where we have disabled
-					 * hibernation and mddi_host_isr
-					 * is not firing, so enable interrupt
-					 * for no pkts pending, which will
-					 * generate an interrupt
-					 */
-					MDDI_MSG_INFO("kick isr!\n");
-					spin_lock_irqsave(&mddi_host_spin_lock,
-							  flags);
-					mddi_host_enable_hclk();
-					mddi_host_reg_outm(INTEN,
-							   MDDI_INT_NO_CMD_PKTS_PEND,
-							   MDDI_INT_NO_CMD_PKTS_PEND);
-					spin_unlock_irqrestore
-					    (&mddi_host_spin_lock, flags);
-				}
-			}
-		}
-#endif /* #ifndef FEATURE_MDDI_DISABLE_REVERSE */
-	}
-
-	/* Check if logging is turned on */
-	for (host_idx = MDDI_HOST_PRIM; host_idx < MDDI_NUM_HOST_CORES;
-	     host_idx++) {
-		mddi_log_params_struct_type *prev_ptr = &(prev_parms[host_idx]);
-		pmhctl = &(mhctl[host_idx]);
-
-		if (mddi_debug_log_statistics) {
-
-			/* get video pkt count from MDP, since MDDI sw cannot know this */
-			pmhctl->log_parms.vid_cnt = mdp_total_vdopkts;
-
-			if (mddi_log_stats_counter >= mddi_log_stats_frequency) {
-				/* mddi_log_stats_counter = 0; */
-				if (mddi_debug_log_statistics) {
-					MDDI_MSG_NOTICE
-					    ("MDDI Statistics since last report:\n");
-					MDDI_MSG_NOTICE("  Packets sent:\n");
-					MDDI_MSG_NOTICE
-					    ("    %d RTD packet(s)\n",
-					     pmhctl->log_parms.rtd_cnt -
-					     prev_ptr->rtd_cnt);
-					if (prev_ptr->rtd_cnt !=
-					    pmhctl->log_parms.rtd_cnt) {
-						unsigned long flags;
-						spin_lock_irqsave
-						    (&mddi_host_spin_lock,
-						     flags);
-						mddi_host_enable_hclk();
-						pmhctl->rtd_value =
-						    mddi_host_reg_in(RTD_VAL);
-						spin_unlock_irqrestore
-						    (&mddi_host_spin_lock,
-						     flags);
-						MDDI_MSG_NOTICE
-						    ("      RTD value=%d\n",
-						     pmhctl->rtd_value);
-					}
-					MDDI_MSG_NOTICE
-					    ("    %d VIDEO packets\n",
-					     pmhctl->log_parms.vid_cnt -
-					     prev_ptr->vid_cnt);
-					MDDI_MSG_NOTICE
-					    ("    %d Register Access packets\n",
-					     pmhctl->log_parms.reg_acc_cnt -
-					     prev_ptr->reg_acc_cnt);
-					MDDI_MSG_NOTICE
-					    ("    %d Reverse Encapsulation packet(s)\n",
-					     pmhctl->log_parms.rev_enc_cnt -
-					     prev_ptr->rev_enc_cnt);
-					if (prev_ptr->rev_enc_cnt !=
-					    pmhctl->log_parms.rev_enc_cnt) {
-						/* report # of reverse CRC errors */
-						MDDI_MSG_NOTICE
-						    ("      %d reverse CRC errors detected\n",
-						     pmhctl->log_parms.
-						     rev_crc_cnt -
-						     prev_ptr->rev_crc_cnt);
-					}
-					MDDI_MSG_NOTICE
-					    ("  Packets received:\n");
-					MDDI_MSG_NOTICE
-					    ("    %d Client Status packets",
-					     pmhctl->log_parms.cli_stat_cnt -
-					     prev_ptr->cli_stat_cnt);
-					if (prev_ptr->cli_stat_cnt !=
-					    pmhctl->log_parms.cli_stat_cnt) {
-						MDDI_MSG_NOTICE
-						    ("      %d forward CRC errors reported\n",
-						     pmhctl->log_parms.
-						     fwd_crc_cnt -
-						     prev_ptr->fwd_crc_cnt);
-					}
-					MDDI_MSG_NOTICE
-					    ("    %d Register Access Read packets\n",
-					     pmhctl->log_parms.reg_read_cnt -
-					     prev_ptr->reg_read_cnt);
-
-					if (pmhctl->link_state ==
-					    MDDI_LINK_ACTIVE) {
-						MDDI_MSG_NOTICE
-						    ("  Current Link Status: Active\n");
-					} else
-					    if ((pmhctl->link_state ==
-						 MDDI_LINK_HIBERNATING)
-						|| (pmhctl->link_state ==
-						    MDDI_LINK_ACTIVATING)) {
-						MDDI_MSG_NOTICE
-						    ("  Current Link Status: Hibernation\n");
-					} else {
-						MDDI_MSG_NOTICE
-						    ("  Current Link Status: Inactive\n");
-					}
-					MDDI_MSG_NOTICE
-					    ("    Active state entered %d times\n",
-					     pmhctl->log_parms.link_active_cnt -
-					     prev_ptr->link_active_cnt);
-					MDDI_MSG_NOTICE
-					    ("    Hibernation state entered %d times\n",
-					     pmhctl->log_parms.
-					     link_hibernate_cnt -
-					     prev_ptr->link_hibernate_cnt);
-				}
-			}
-			prev_parms[host_idx] = pmhctl->log_parms;
-		}
-	}
-	if (mddi_log_stats_counter >= mddi_log_stats_frequency)
-		mddi_log_stats_counter = 0;
-
-	mutex_lock(&mddi_timer_lock);
-	if (!mddi_timer_shutdown_flag) {
-		mddi_host_timer.function = mddi_host_timer_service;
-		mddi_host_timer.data = 0;
-		mddi_host_timer.expires = jiffies + ((time_ms * HZ) / 1000);
-		add_timer(&mddi_host_timer);
-	}
-	mutex_unlock(&mddi_timer_lock);
-
-	return;
-}				/* mddi_host_timer_cb */
-
-static void mddi_process_link_list_done(void)
-{
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	/* normal forward linked list packet(s) were sent */
-	if (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) {
-		MDDI_MSG_ERR("**** getting LL done, but no list ****\n");
-	} else {
-		uint16 idx;
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (pmhctl->rev_state == MDDI_REV_REG_READ_ISSUED) {
-			/* special case where a register read packet was sent */
-			pmhctl->rev_state = MDDI_REV_REG_READ_SENT;
-			if (pmhctl->llist_info.reg_read_idx == UNASSIGNED_INDEX) {
-				MDDI_MSG_ERR
-				    ("**** getting LL done, but no list ****\n");
-			}
-		}
-#endif
-		for (idx = pmhctl->llist_info.transmitting_start_idx;;) {
-			uint16 next_idx = pmhctl->llist_notify[idx].next_idx;
-			/* with reg read we don't release the waiting tcb until after
-			 * the reverse encapsulation has completed.
-			 */
-			if (idx != pmhctl->llist_info.reg_read_idx) {
-				/* notify task that may be waiting on this completion */
-				if (pmhctl->llist_notify[idx].waiting) {
-					complete(&
-						 (pmhctl->llist_notify[idx].
-						  done_comp));
-				}
-				if (pmhctl->llist_notify[idx].done_cb != NULL) {
-					(*(pmhctl->llist_notify[idx].done_cb))
-					    ();
-				}
-
-				pmhctl->llist_notify[idx].in_use = FALSE;
-				pmhctl->llist_notify[idx].waiting = FALSE;
-				pmhctl->llist_notify[idx].done_cb = NULL;
-				if (idx < MDDI_NUM_DYNAMIC_LLIST_ITEMS) {
-					/* static LLIST items are configured only once */
-					pmhctl->llist_notify[idx].next_idx =
-					    UNASSIGNED_INDEX;
-				}
-				/*
-				 * currently, all linked list packets are
-				 * register access, so we can increment the
-				 * counter for that packet type here.
-				 */
-				pmhctl->log_parms.reg_acc_cnt++;
-			}
-			if (idx == pmhctl->llist_info.transmitting_end_idx)
-				break;
-			idx = next_idx;
-			if (idx == UNASSIGNED_INDEX)
-				MDDI_MSG_CRIT("MDDI linked list corruption!\n");
-		}
-
-		pmhctl->llist_info.transmitting_start_idx = UNASSIGNED_INDEX;
-		pmhctl->llist_info.transmitting_end_idx = UNASSIGNED_INDEX;
-
-		if (pmhctl->mddi_waiting_for_llist_avail) {
-			if (!
-			    (pmhctl->
-			     llist_notify[pmhctl->llist_info.next_free_idx].
-			     in_use)) {
-				pmhctl->mddi_waiting_for_llist_avail = FALSE;
-				complete(&(pmhctl->mddi_llist_avail_comp));
-			}
-		}
-	}
-
-	/* Turn off MDDI_INT_PRI_LINK_LIST_DONE interrupt */
-	mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE, 0);
-
-}
-
-static void mddi_queue_forward_linked_list(void)
-{
-	uint16 first_pkt_index;
-	mddi_linked_list_type *llist_dma;
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-	llist_dma = pmhctl->llist_dma_ptr;
-
-	first_pkt_index = UNASSIGNED_INDEX;
-
-	if (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) {
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (pmhctl->llist_info.reg_read_waiting) {
-			if (pmhctl->rev_state == MDDI_REV_IDLE) {
-				/*
-				 * we have a register read to send and
-				 * can send it now
-				 */
-				pmhctl->rev_state = MDDI_REV_REG_READ_ISSUED;
-				mddi_reg_read_retry = 0;
-				first_pkt_index =
-				    pmhctl->llist_info.waiting_start_idx;
-				pmhctl->llist_info.reg_read_waiting = FALSE;
-			}
-		} else
-#endif
-		{
-			/*
-			 * not register read to worry about, go ahead and write
-			 * anything that may be on the waiting list.
-			 */
-			first_pkt_index = pmhctl->llist_info.waiting_start_idx;
-		}
-	}
-
-	if (first_pkt_index != UNASSIGNED_INDEX) {
-		pmhctl->llist_info.transmitting_start_idx =
-		    pmhctl->llist_info.waiting_start_idx;
-		pmhctl->llist_info.transmitting_end_idx =
-		    pmhctl->llist_info.waiting_end_idx;
-		pmhctl->llist_info.waiting_start_idx = UNASSIGNED_INDEX;
-		pmhctl->llist_info.waiting_end_idx = UNASSIGNED_INDEX;
-
-		/* write to the primary pointer register */
-		MDDI_MSG_DEBUG("MDDI writing primary ptr with idx=%d\n",
-			       first_pkt_index);
-
-		pmhctl->int_type.llist_ptr_write_2++;
-
-		dma_coherent_pre_ops();
-		mddi_host_reg_out(PRI_PTR, &llist_dma[first_pkt_index]);
-
-		/* enable interrupt when complete */
-		mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE,
-				   MDDI_INT_PRI_LINK_LIST_DONE);
-
-	}
-
-}
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-static void mddi_read_rev_packet(byte *data_ptr)
-{
-	uint16 i, length;
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	uint8 *rev_ptr_overflow =
-	    (pmhctl->rev_ptr_start + MDDI_REV_BUFFER_SIZE);
-
-	/* first determine the length and handle invalid lengths */
-	length = *pmhctl->rev_ptr_curr++;
-	if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
-		pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-	length |= ((*pmhctl->rev_ptr_curr++) << 8);
-	if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
-		pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-	if (length > (pmhctl->rev_pkt_size - 2)) {
-		MDDI_MSG_ERR("Invalid rev pkt length %d\n", length);
-		/* rev_pkt_size should always be <= rev_ptr_size so limit to packet size */
-		length = pmhctl->rev_pkt_size - 2;
-	}
-
-	/* If the data pointer is NULL, just increment the pmhctl->rev_ptr_curr.
-	 * Loop around if necessary. Don't bother reading the data.
-	 */
-	if (data_ptr == NULL) {
-		pmhctl->rev_ptr_curr += length;
-		if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
-			pmhctl->rev_ptr_curr -= MDDI_REV_BUFFER_SIZE;
-		return;
-	}
-
-	data_ptr[0] = length & 0x0ff;
-	data_ptr[1] = length >> 8;
-	data_ptr += 2;
-	/* copy the data to data_ptr byte-at-a-time */
-	for (i = 0; (i < length) && (pmhctl->rev_ptr_curr < rev_ptr_overflow);
-	     i++)
-		*data_ptr++ = *pmhctl->rev_ptr_curr++;
-	if (pmhctl->rev_ptr_curr >= rev_ptr_overflow)
-		pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-	for (; (i < length) && (pmhctl->rev_ptr_curr < rev_ptr_overflow); i++)
-		*data_ptr++ = *pmhctl->rev_ptr_curr++;
-}
-
-static void mddi_process_rev_packets(void)
-{
-	uint32 rev_packet_count;
-	word i;
-	uint32 crc_errors;
-	boolean mddi_reg_read_successful = FALSE;
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	pmhctl->log_parms.rev_enc_cnt++;
-	if ((pmhctl->rev_state != MDDI_REV_ENCAP_ISSUED) &&
-	    (pmhctl->rev_state != MDDI_REV_STATUS_REQ_ISSUED) &&
-	    (pmhctl->rev_state != MDDI_REV_CLIENT_CAP_ISSUED)) {
-		MDDI_MSG_ERR("Wrong state %d for reverse int\n",
-			     pmhctl->rev_state);
-	}
-	/* Turn off MDDI_INT_REV_AVAIL interrupt */
-	mddi_host_reg_outm(INTEN, MDDI_INT_REV_DATA_AVAIL, 0);
-
-	/* Clear rev data avail int */
-	mddi_host_reg_out(INT, MDDI_INT_REV_DATA_AVAIL);
-
-	/* Get Number of packets */
-	rev_packet_count = mddi_host_reg_in(REV_PKT_CNT);
-
-#ifndef T_MSM7500
-	/* Clear out rev packet counter */
-	mddi_host_reg_out(REV_PKT_CNT, 0x0000);
-#endif
-
-#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
-	if ((pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED) &&
-	    (rev_packet_count > 0) &&
-	    (mddi_host_core_version == 0x28 ||
-	     mddi_host_core_version == 0x30)) {
-
-		uint32 int_reg;
-		uint32 max_count = 0;
-
-		mddi_host_reg_out(REV_PTR, pmhctl->mddi_rev_ptr_write_val);
-		int_reg = mddi_host_reg_in(INT);
-		while ((int_reg & 0x100000) == 0) {
-			udelay(3);
-			int_reg = mddi_host_reg_in(INT);
-			if (++max_count > 100)
-				break;
-		}
-	}
-#endif
-
-	/* Get CRC error count */
-	crc_errors = mddi_host_reg_in(REV_CRC_ERR);
-	if (crc_errors != 0) {
-		pmhctl->log_parms.rev_crc_cnt += crc_errors;
-		pmhctl->stats.rev_crc_count += crc_errors;
-		MDDI_MSG_ERR("!!! MDDI %d Reverse CRC Error(s) !!!\n",
-			     crc_errors);
-#ifndef T_MSM7500
-		/* Clear CRC error count */
-		mddi_host_reg_out(REV_CRC_ERR, 0x0000);
-#endif
-		/* also issue an RTD to attempt recovery */
-		pmhctl->rtd_counter = mddi_rtd_frequency;
-	}
-
-	pmhctl->rtd_value = mddi_host_reg_in(RTD_VAL);
-
-	MDDI_MSG_DEBUG("MDDI rev pkt cnt=%d, ptr=0x%x, RTD:0x%x\n",
-		       rev_packet_count,
-		       pmhctl->rev_ptr_curr - pmhctl->rev_ptr_start,
-		       pmhctl->rtd_value);
-
-	if (rev_packet_count >= 1) {
-		mddi_invalidate_cache_lines((uint32 *) pmhctl->rev_ptr_start,
-					    MDDI_REV_BUFFER_SIZE);
-	} else {
-		MDDI_MSG_ERR("Reverse pkt sent, no data rxd\n");
-		if (mddi_reg_read_value_ptr)
-			*mddi_reg_read_value_ptr = -EBUSY;
-	}
-	/* order the reads */
-	dma_coherent_post_ops();
-	for (i = 0; i < rev_packet_count; i++) {
-		mddi_rev_packet_type *rev_pkt_ptr;
-
-		mddi_read_rev_packet(rev_packet_data);
-
-		rev_pkt_ptr = (mddi_rev_packet_type *) rev_packet_data;
-
-		if (rev_pkt_ptr->packet_length > pmhctl->rev_pkt_size) {
-			MDDI_MSG_ERR("!!!invalid packet size: %d\n",
-				     rev_pkt_ptr->packet_length);
-		}
-
-		MDDI_MSG_DEBUG("MDDI rev pkt 0x%x size 0x%x\n",
-			       rev_pkt_ptr->packet_type,
-			       rev_pkt_ptr->packet_length);
-
-		/* Do whatever you want to do with the data based on the packet type */
-		switch (rev_pkt_ptr->packet_type) {
-		case 66:	/* Client Capability */
-			{
-				mddi_client_capability_type
-				    *client_capability_pkt_ptr;
-
-				client_capability_pkt_ptr =
-				    (mddi_client_capability_type *)
-				    rev_packet_data;
-				MDDI_MSG_NOTICE
-				    ("Client Capability: Week=%d, Year=%d\n",
-				     client_capability_pkt_ptr->
-				     Week_of_Manufacture,
-				     client_capability_pkt_ptr->
-				     Year_of_Manufacture);
-				memcpy((void *)&mddi_client_capability_pkt,
-				       (void *)rev_packet_data,
-				       sizeof(mddi_client_capability_type));
-				pmhctl->log_parms.cli_cap_cnt++;
-			}
-			break;
-
-		case 70:	/* Display Status */
-			{
-				mddi_client_status_type *client_status_pkt_ptr;
-
-				client_status_pkt_ptr =
-				    (mddi_client_status_type *) rev_packet_data;
-				if ((client_status_pkt_ptr->crc_error_count !=
-				     0)
-				    || (client_status_pkt_ptr->
-					reverse_link_request != 0)) {
-					MDDI_MSG_ERR
-					    ("Client Status: RevReq=%d, CrcErr=%d\n",
-					     client_status_pkt_ptr->
-					     reverse_link_request,
-					     client_status_pkt_ptr->
-					     crc_error_count);
-				} else {
-					MDDI_MSG_DEBUG
-					    ("Client Status: RevReq=%d, CrcErr=%d\n",
-					     client_status_pkt_ptr->
-					     reverse_link_request,
-					     client_status_pkt_ptr->
-					     crc_error_count);
-				}
-				pmhctl->log_parms.fwd_crc_cnt +=
-				    client_status_pkt_ptr->crc_error_count;
-				pmhctl->stats.fwd_crc_count +=
-				    client_status_pkt_ptr->crc_error_count;
-				pmhctl->log_parms.cli_stat_cnt++;
-			}
-			break;
-
-		case 146:	/* register access packet */
-			{
-				mddi_register_access_packet_type
-				    * regacc_pkt_ptr;
-				uint32 data_count;
-
-				regacc_pkt_ptr =
-				    (mddi_register_access_packet_type *)
-				    rev_packet_data;
-
-				/* Bits[0:13] - read data count */
-				data_count = regacc_pkt_ptr->read_write_info
-					& 0x3FFF;
-				MDDI_MSG_DEBUG("\n MDDI rev read: 0x%x",
-					regacc_pkt_ptr->read_write_info);
-				MDDI_MSG_DEBUG("Reg Acc parse reg=0x%x,"
-					"value=0x%x\n", regacc_pkt_ptr->
-					register_address, regacc_pkt_ptr->
-					register_data_list[0]);
-
-				/* Copy register value to location passed in */
-				if (mddi_reg_read_value_ptr) {
-#if defined(T_MSM6280) && !defined(T_MSM7200)
-					/* only least significant 16 bits are valid with 6280 */
-					*mddi_reg_read_value_ptr =
-					    regacc_pkt_ptr->
-					    register_data_list[0] & 0x0000ffff;
-					mddi_reg_read_successful = TRUE;
-					mddi_reg_read_value_ptr = NULL;
-#else
-				if (data_count && data_count <=
-					MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR) {
-					memcpy(mddi_reg_read_value_ptr,
-						(void *)&regacc_pkt_ptr->
-						register_data_list[0],
-						data_count * 4);
-					mddi_reg_read_successful = TRUE;
-					mddi_reg_read_value_ptr = NULL;
-				}
-#endif
-				}
-
-#ifdef DEBUG_MDDIHOSTI
-				if ((mddi_gpio.polling_enabled) &&
-				    (regacc_pkt_ptr->register_address ==
-				     mddi_gpio.polling_reg)) {
-					/*
-					 * ToDo: need to call Linux GPIO call
-					 * here...
-					 */
-					 mddi_client_lcd_gpio_poll(
-					 regacc_pkt_ptr->register_data_list[0]);
-				}
-#endif
-				pmhctl->log_parms.reg_read_cnt++;
-			}
-			break;
-
-		case INVALID_PKT_TYPE:	/* 0xFFFF */
-			MDDI_MSG_ERR("!!!INVALID_PKT_TYPE rcvd\n");
-			break;
-
-		default:	/* any other packet */
-			{
-				uint16 hdlr;
-
-				for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS;
-				     hdlr++) {
-					if (mddi_rev_pkt_handler[hdlr].
-							handler == NULL)
-						continue;
-					if (mddi_rev_pkt_handler[hdlr].
-					    pkt_type ==
-					    rev_pkt_ptr->packet_type) {
-						(*(mddi_rev_pkt_handler[hdlr].
-						  handler)) (rev_pkt_ptr);
-					/* pmhctl->rev_state = MDDI_REV_IDLE; */
-						break;
-					}
-				}
-				if (hdlr >= MAX_MDDI_REV_HANDLERS)
-					MDDI_MSG_ERR("MDDI unknown rev pkt\n");
-			}
-			break;
-		}
-	}
-	if ((pmhctl->rev_ptr_curr + pmhctl->rev_pkt_size) >=
-	    (pmhctl->rev_ptr_start + MDDI_REV_BUFFER_SIZE)) {
-		pmhctl->rev_ptr_written = FALSE;
-	}
-
-	if (pmhctl->rev_state == MDDI_REV_ENCAP_ISSUED) {
-		pmhctl->rev_state = MDDI_REV_IDLE;
-		if (mddi_rev_user.waiting) {
-			mddi_rev_user.waiting = FALSE;
-			complete(&(mddi_rev_user.done_comp));
-		} else if (pmhctl->llist_info.reg_read_idx == UNASSIGNED_INDEX) {
-			MDDI_MSG_ERR
-			    ("Reverse Encap state, but no reg read in progress\n");
-		} else {
-			if ((!mddi_reg_read_successful) &&
-			    (mddi_reg_read_retry < mddi_reg_read_retry_max) &&
-			    (mddi_enable_reg_read_retry)) {
-				/*
-				 * There is a race condition that can happen
-				 * where the reverse encapsulation message is
-				 * sent out by the MDDI host before the register
-				 * read packet is sent. As a work-around for
-				 * that problem we issue the reverse
-				 * encapsulation one more time before giving up.
-				 */
-				if (mddi_enable_reg_read_retry_once)
-					mddi_reg_read_retry =
-					    mddi_reg_read_retry_max;
-				else
-					mddi_reg_read_retry++;
-				pmhctl->rev_state = MDDI_REV_REG_READ_SENT;
-				pmhctl->stats.reg_read_failure++;
-			} else {
-				uint16 reg_read_idx =
-				    pmhctl->llist_info.reg_read_idx;
-
-				mddi_reg_read_retry = 0;
-				if (pmhctl->llist_notify[reg_read_idx].waiting) {
-					complete(&
-						 (pmhctl->
-						  llist_notify[reg_read_idx].
-						  done_comp));
-				}
-				pmhctl->llist_info.reg_read_idx =
-				    UNASSIGNED_INDEX;
-				if (pmhctl->llist_notify[reg_read_idx].
-				    done_cb != NULL) {
-					(*
-					 (pmhctl->llist_notify[reg_read_idx].
-					  done_cb)) ();
-				}
-				pmhctl->llist_notify[reg_read_idx].next_idx =
-				    UNASSIGNED_INDEX;
-				pmhctl->llist_notify[reg_read_idx].in_use =
-				    FALSE;
-				pmhctl->llist_notify[reg_read_idx].waiting =
-				    FALSE;
-				pmhctl->llist_notify[reg_read_idx].done_cb =
-				    NULL;
-				if (!mddi_reg_read_successful)
-					pmhctl->stats.reg_read_failure++;
-			}
-		}
-	} else if (pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED) {
-#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
-		if (mddi_host_core_version == 0x28 ||
-		    mddi_host_core_version == 0x30) {
-			mddi_host_reg_out(FIFO_ALLOC, 0x00);
-			pmhctl->rev_ptr_written = TRUE;
-			mddi_host_reg_out(REV_PTR,
-				pmhctl->mddi_rev_ptr_write_val);
-			pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-			mddi_host_reg_out(CMD, 0xC00);
-		}
-#endif
-
-		if (mddi_rev_user.waiting) {
-			mddi_rev_user.waiting = FALSE;
-			complete(&(mddi_rev_user.done_comp));
-		}
-		pmhctl->rev_state = MDDI_REV_IDLE;
-	} else {
-		pmhctl->rev_state = MDDI_REV_IDLE;
-	}
-
-	/* pmhctl->rev_state = MDDI_REV_IDLE; */
-
-	/* Re-enable interrupt */
-	mddi_host_reg_outm(INTEN, MDDI_INT_REV_DATA_AVAIL,
-			   MDDI_INT_REV_DATA_AVAIL);
-
-}
-
-static void mddi_issue_reverse_encapsulation(void)
-{
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-	/* Only issue a reverse encapsulation packet if:
-	 * 1) another reverse is not in progress (MDDI_REV_IDLE).
-	 * 2) a register read has been sent (MDDI_REV_REG_READ_SENT).
-	 * 3) forward is not in progress, because of a hw bug in client that
-	 *    causes forward crc errors on packet immediately after rev encap.
-	 */
-	if (((pmhctl->rev_state == MDDI_REV_IDLE) ||
-	     (pmhctl->rev_state == MDDI_REV_REG_READ_SENT)) &&
-	    (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
-	    (!mdp_in_processing)) {
-		uint32 mddi_command = MDDI_CMD_SEND_REV_ENCAP;
-
-		if ((pmhctl->rev_state == MDDI_REV_REG_READ_SENT) ||
-		    (mddi_rev_encap_user_request == TRUE)) {
-			mddi_host_enable_io_clock();
-			if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
-				/* need to wake up link before issuing rev encap command */
-				MDDI_MSG_DEBUG("wake up link!\n");
-				pmhctl->link_state = MDDI_LINK_ACTIVATING;
-				mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-			} else {
-				if (pmhctl->rtd_counter >= mddi_rtd_frequency) {
-					MDDI_MSG_DEBUG
-					    ("mddi sending RTD command!\n");
-					mddi_host_reg_out(CMD,
-							  MDDI_CMD_SEND_RTD);
-					pmhctl->rtd_counter = 0;
-					pmhctl->log_parms.rtd_cnt++;
-				}
-				if (pmhctl->rev_state != MDDI_REV_REG_READ_SENT) {
-					/* this is generic reverse request by user, so
-					 * reset the waiting flag. */
-					mddi_rev_encap_user_request = FALSE;
-				}
-				/* link is active so send reverse encap to get register read results */
-				pmhctl->rev_state = MDDI_REV_ENCAP_ISSUED;
-				mddi_command = MDDI_CMD_SEND_REV_ENCAP;
-				MDDI_MSG_DEBUG("sending rev encap!\n");
-			}
-		} else
-		    if ((pmhctl->client_status_cnt >=
-			 mddi_client_status_frequency)
-			|| mddi_client_capability_request) {
-			mddi_host_enable_io_clock();
-			if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
-				/* only wake up the link if it client status is overdue */
-				if ((pmhctl->client_status_cnt >=
-				     (mddi_client_status_frequency * 2))
-				    || mddi_client_capability_request) {
-					/* need to wake up link before issuing rev encap command */
-					MDDI_MSG_DEBUG("wake up link!\n");
-					pmhctl->link_state =
-					    MDDI_LINK_ACTIVATING;
-					mddi_host_reg_out(CMD,
-							  MDDI_CMD_LINK_ACTIVE);
-				}
-			} else {
-				if (pmhctl->rtd_counter >= mddi_rtd_frequency) {
-					MDDI_MSG_DEBUG
-					    ("mddi sending RTD command!\n");
-					mddi_host_reg_out(CMD,
-							  MDDI_CMD_SEND_RTD);
-					pmhctl->rtd_counter = 0;
-					pmhctl->log_parms.rtd_cnt++;
-				}
-				/* periodically get client status */
-				MDDI_MSG_DEBUG
-				    ("mddi sending rev enc! (get status)\n");
-				if (mddi_client_capability_request) {
-					pmhctl->rev_state =
-					    MDDI_REV_CLIENT_CAP_ISSUED;
-					mddi_command = MDDI_CMD_GET_CLIENT_CAP;
-					mddi_client_capability_request = FALSE;
-				} else {
-					pmhctl->rev_state =
-					    MDDI_REV_STATUS_REQ_ISSUED;
-					pmhctl->client_status_cnt = 0;
-					mddi_command =
-					    MDDI_CMD_GET_CLIENT_STATUS;
-				}
-			}
-		}
-		if ((pmhctl->rev_state == MDDI_REV_ENCAP_ISSUED) ||
-		    (pmhctl->rev_state == MDDI_REV_STATUS_REQ_ISSUED) ||
-		    (pmhctl->rev_state == MDDI_REV_CLIENT_CAP_ISSUED)) {
-			pmhctl->int_type.rev_encap_count++;
-#if defined(T_MSM6280) && !defined(T_MSM7200)
-			mddi_rev_pointer_written = TRUE;
-			mddi_host_reg_out(REV_PTR, mddi_rev_ptr_write_val);
-			mddi_rev_ptr_curr = mddi_rev_ptr_start;
-			/* force new rev ptr command */
-			mddi_host_reg_out(CMD, 0xC00);
-#else
-			if (!pmhctl->rev_ptr_written) {
-				MDDI_MSG_DEBUG("writing reverse pointer!\n");
-				pmhctl->rev_ptr_written = TRUE;
-#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
-				if ((pmhctl->rev_state ==
-				     MDDI_REV_CLIENT_CAP_ISSUED) &&
-				    (mddi_host_core_version == 0x28 ||
-				     mddi_host_core_version == 0x30)) {
-					pmhctl->rev_ptr_written = FALSE;
-					mddi_host_reg_out(FIFO_ALLOC, 0x02);
-				} else
-					mddi_host_reg_out(REV_PTR,
-						  pmhctl->
-						  mddi_rev_ptr_write_val);
-#else
-				mddi_host_reg_out(REV_PTR,
-						  pmhctl->
-						  mddi_rev_ptr_write_val);
-#endif
-			}
-#endif
-			if (mddi_debug_clear_rev_data) {
-				uint16 i;
-				for (i = 0; i < MDDI_MAX_REV_DATA_SIZE / 4; i++)
-					pmhctl->rev_data_buf[i] = 0xdddddddd;
-				/* clean cache */
-				mddi_flush_cache_lines(pmhctl->rev_data_buf,
-						       MDDI_MAX_REV_DATA_SIZE);
-			}
-
-			/* send reverse encapsulation to get needed data */
-			mddi_host_reg_out(CMD, mddi_command);
-		}
-	}
-
-}
-
-static void mddi_process_client_initiated_wakeup(void)
-{
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	/* Disable MDDI_INT Interrupt, we detect client initiated wakeup one
-	 * time for each entry into hibernation */
-	mddi_host_reg_outm(INTEN, MDDI_INT_MDDI_IN, 0);
-
-	if (host_idx == MDDI_HOST_PRIM) {
-		if (mddi_vsync_detect_enabled) {
-			mddi_host_enable_io_clock();
-#ifndef MDDI_HOST_DISP_LISTEN
-			/* issue command to bring up link */
-			/* need to do this to clear the vsync condition */
-			if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
-				pmhctl->link_state = MDDI_LINK_ACTIVATING;
-				mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-			}
-#endif
-			/*
-			 * Indicate to client specific code that vsync was
-			 * enabled, and we did not detect a client initiated
-			 * wakeup. The client specific handler can clear the
-			 * condition if necessary to prevent subsequent
-			 * client initiated wakeups.
-			 */
-			mddi_client_lcd_vsync_detected(TRUE);
-			pmhctl->log_parms.vsync_response_cnt++;
-			MDDI_MSG_NOTICE("MDDI_INT_IN condition\n");
-
-		}
-	}
-
-	if (mddi_gpio.polling_enabled) {
-		mddi_host_enable_io_clock();
-		/* check interrupt status now */
-		(void)mddi_queue_register_read_int(mddi_gpio.polling_reg,
-						   &mddi_gpio.polling_val);
-	}
-}
-#endif /* FEATURE_MDDI_DISABLE_REVERSE */
-
-static void mddi_host_isr(void)
-{
-	uint32 int_reg, int_en;
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	uint32 status_reg;
-#endif
-	mddi_host_type host_idx = mddi_curr_host;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if (!MDDI_HOST_IS_HCLK_ON) {
-		MDDI_HOST_ENABLE_HCLK;
-	}
-	int_reg = mddi_host_reg_in(INT);
-	int_en = mddi_host_reg_in(INTEN);
-	pmhctl->saved_int_reg = int_reg;
-	pmhctl->saved_int_en = int_en;
-	int_reg = int_reg & int_en;
-	pmhctl->int_type.count++;
-
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	status_reg = mddi_host_reg_in(STAT);
-
-	if ((int_reg & MDDI_INT_MDDI_IN) ||
-	    ((int_en & MDDI_INT_MDDI_IN) &&
-	     ((int_reg == 0) || (status_reg & MDDI_STAT_CLIENT_WAKEUP_REQ)))) {
-		/*
-		 * The MDDI_IN condition will clear itself, and so it is
-		 * possible that MDDI_IN was the reason for the isr firing,
-		 * even though the interrupt register does not have the
-		 * MDDI_IN bit set. To check if this was the case we need to
-		 * look at the status register bit that signifies a client
-		 * initiated wakeup. If the status register bit is set, as well
-		 * as the MDDI_IN interrupt enabled, then we treat this as a
-		 * client initiated wakeup.
-		 */
-		if (int_reg & MDDI_INT_MDDI_IN)
-			pmhctl->int_type.in_count++;
-		mddi_process_client_initiated_wakeup();
-	}
-#endif
-
-	if (int_reg & MDDI_INT_LINK_STATE_CHANGES) {
-		pmhctl->int_type.state_change_count++;
-		mddi_report_state_change(int_reg);
-	}
-
-	if (int_reg & MDDI_INT_PRI_LINK_LIST_DONE) {
-		pmhctl->int_type.ll_done_count++;
-		mddi_process_link_list_done();
-	}
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	if (int_reg & MDDI_INT_REV_DATA_AVAIL) {
-		pmhctl->int_type.rev_avail_count++;
-		mddi_process_rev_packets();
-	}
-#endif
-
-	if (int_reg & MDDI_INT_ERROR_CONDITIONS) {
-		pmhctl->int_type.error_count++;
-		mddi_report_errors(int_reg);
-
-		mddi_host_reg_out(INT, int_reg & MDDI_INT_ERROR_CONDITIONS);
-	}
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	mddi_issue_reverse_encapsulation();
-
-	if ((pmhctl->rev_state != MDDI_REV_ENCAP_ISSUED) &&
-	    (pmhctl->rev_state != MDDI_REV_STATUS_REQ_ISSUED))
-#endif
-		/* don't want simultaneous reverse and forward with Eagle */
-		mddi_queue_forward_linked_list();
-
-	if (int_reg & MDDI_INT_NO_CMD_PKTS_PEND) {
-		/* this interrupt is used to kick the isr when hibernation is disabled */
-		mddi_host_reg_outm(INTEN, MDDI_INT_NO_CMD_PKTS_PEND, 0);
-	}
-
-	if ((!mddi_host_mdp_active_flag) &&
-	    (!mddi_vsync_detect_enabled) &&
-	    (pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
-	    (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) &&
-	    (pmhctl->rev_state == MDDI_REV_IDLE)) {
-		if (pmhctl->link_state == MDDI_LINK_HIBERNATING) {
-			mddi_host_disable_io_clock();
-			mddi_host_disable_hclk();
-		}
-#ifdef FEATURE_MDDI_HOST_ENABLE_EARLY_HIBERNATION
-		else if ((pmhctl->link_state == MDDI_LINK_ACTIVE) &&
-			 (!pmhctl->disable_hibernation)) {
-			mddi_host_reg_out(CMD, MDDI_CMD_POWERDOWN);
-		}
-#endif
-	}
-}
-
-static void mddi_host_isr_primary(void)
-{
-	mddi_curr_host = MDDI_HOST_PRIM;
-	mddi_host_isr();
-}
-
-irqreturn_t mddi_pmdh_isr_proxy(int irq, void *ptr)
-{
-	mddi_host_isr_primary();
-	return IRQ_HANDLED;
-}
-
-static void mddi_host_isr_external(void)
-{
-	mddi_curr_host = MDDI_HOST_EXT;
-	mddi_host_isr();
-	mddi_curr_host = MDDI_HOST_PRIM;
-}
-
-irqreturn_t mddi_emdh_isr_proxy(int irq, void *ptr)
-{
-	mddi_host_isr_external();
-	return IRQ_HANDLED;
-}
-
-static void mddi_host_initialize_registers(mddi_host_type host_idx)
-{
-	uint32 pad_reg_val;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if (pmhctl->driver_state == MDDI_DRIVER_ENABLED)
-		return;
-
-	/* turn on HCLK to MDDI host core */
-	mddi_host_enable_hclk();
-
-	/* MDDI Reset command */
-	mddi_host_reg_out(CMD, MDDI_CMD_RESET);
-
-	/* Version register (= 0x01) */
-	mddi_host_reg_out(VERSION, 0x0001);
-
-	/* Bytes per subframe register */
-	mddi_host_reg_out(BPS, MDDI_HOST_BYTES_PER_SUBFRAME);
-
-	/* Subframes per media frames register (= 0x03) */
-	mddi_host_reg_out(SPM, 0x0003);
-
-	/* Turn Around 1 register (= 0x05) */
-	mddi_host_reg_out(TA1_LEN, 0x0005);
-
-	/* Turn Around 2 register (= 0x0C) */
-	mddi_host_reg_out(TA2_LEN, MDDI_HOST_TA2_LEN);
-
-	/* Drive hi register (= 0x96) */
-	mddi_host_reg_out(DRIVE_HI, 0x0096);
-
-	/* Drive lo register (= 0x32) */
-	mddi_host_reg_out(DRIVE_LO, 0x0032);
-
-	/* Display wakeup count register (= 0x3c) */
-	mddi_host_reg_out(DISP_WAKE, 0x003c);
-
-	/* Reverse Rate Divisor register (= 0x2) */
-	mddi_host_reg_out(REV_RATE_DIV, MDDI_HOST_REV_RATE_DIV);
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	/* Reverse Pointer Size */
-	mddi_host_reg_out(REV_SIZE, MDDI_REV_BUFFER_SIZE);
-
-	/* Rev Encap Size */
-	mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
-#endif
-
-	/* Periodic Rev Encap */
-	/* don't send periodically */
-	mddi_host_reg_out(CMD, MDDI_CMD_PERIODIC_REV_ENCAP);
-
-	pad_reg_val = mddi_host_reg_in(PAD_CTL);
-	if (pad_reg_val == 0) {
-		/* If we are turning on band gap, need to wait 5us before turning
-		 * on the rest of the PAD */
-		mddi_host_reg_out(PAD_CTL, 0x08000);
-		udelay(5);
-	}
-#ifdef T_MSM7200
-	/* Recommendation from PAD hw team */
-	mddi_host_reg_out(PAD_CTL, 0xa850a);
-#else
-	/* Recommendation from PAD hw team */
-	mddi_host_reg_out(PAD_CTL, 0xa850f);
-#endif
-
-	pad_reg_val = 0x00220020;
-
-#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
-	mddi_host_reg_out(PAD_IO_CTL, 0x00320000);
-	mddi_host_reg_out(PAD_CAL, pad_reg_val);
-#endif
-
-	mddi_host_core_version = mddi_host_reg_inm(CORE_VER, 0xffff);
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	if (mddi_host_core_version >= 8)
-		mddi_rev_ptr_workaround = FALSE;
-	pmhctl->rev_ptr_curr = pmhctl->rev_ptr_start;
-#endif
-
-	if ((mddi_host_core_version > 8) && (mddi_host_core_version < 0x19))
-		mddi_host_reg_out(TEST, 0x2);
-
-	/* Need an even number for counts */
-	mddi_host_reg_out(DRIVER_START_CNT, 0x60006);
-
-#ifndef T_MSM7500
-	/* Setup defaults for MDP related register */
-	mddi_host_reg_out(MDP_VID_FMT_DES, 0x5666);
-	mddi_host_reg_out(MDP_VID_PIX_ATTR, 0x00C3);
-	mddi_host_reg_out(MDP_VID_CLIENTID, 0);
-#endif
-
-	/* automatically hibernate after 1 empty subframe */
-	if (pmhctl->disable_hibernation)
-		mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
-	else
-		mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
-
-	/* Bring up link if display (client) requests it */
-#ifdef MDDI_HOST_DISP_LISTEN
-	mddi_host_reg_out(CMD, MDDI_CMD_DISP_LISTEN);
-#else
-	mddi_host_reg_out(CMD, MDDI_CMD_DISP_IGNORE);
-#endif
-
-}
-
-void mddi_host_configure_interrupts(mddi_host_type host_idx, boolean enable)
-{
-	unsigned long flags;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-
-	/* turn on HCLK to MDDI host core if it has been disabled */
-	mddi_host_enable_hclk();
-	/* Clear MDDI Interrupt enable reg */
-	mddi_host_reg_out(INTEN, 0);
-
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-	if (enable) {
-		pmhctl->driver_state = MDDI_DRIVER_ENABLED;
-
-		if (host_idx == MDDI_HOST_PRIM) {
-			if (request_irq
-			    (INT_MDDI_PRI, mddi_pmdh_isr_proxy, IRQF_DISABLED,
-			     "PMDH", 0) != 0)
-				printk(KERN_ERR
-				       "a mddi: unable to request_irq\n");
-			else {
-				int_mddi_pri_flag = TRUE;
-				irq_enabled = 1;
-			}
-		} else {
-			if (request_irq
-			    (INT_MDDI_EXT, mddi_emdh_isr_proxy, IRQF_DISABLED,
-			     "EMDH", 0) != 0)
-				printk(KERN_ERR
-				       "b mddi: unable to request_irq\n");
-			else
-				int_mddi_ext_flag = TRUE;
-		}
-
-		/* Set MDDI Interrupt enable reg -- Enable Reverse data avail */
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-		mddi_host_reg_out(INTEN,
-				  MDDI_INT_ERROR_CONDITIONS |
-				  MDDI_INT_LINK_STATE_CHANGES);
-#else
-		/* Reverse Pointer register */
-		pmhctl->rev_ptr_written = FALSE;
-
-		mddi_host_reg_out(INTEN,
-				  MDDI_INT_REV_DATA_AVAIL |
-				  MDDI_INT_ERROR_CONDITIONS |
-				  MDDI_INT_LINK_STATE_CHANGES);
-		pmhctl->rtd_counter = mddi_rtd_frequency;
-		pmhctl->client_status_cnt = 0;
-#endif
-	} else {
-		if (pmhctl->driver_state == MDDI_DRIVER_ENABLED)
-			pmhctl->driver_state = MDDI_DRIVER_DISABLED;
-	}
-
-}
-
-/*
- * mddi_host_client_cnt_reset:
- * reset client_status_cnt to 0 to make sure host does not
- * send RTD cmd to client right after resume before mddi
- * client be powered up. this fix "MDDI RTD Failure" problem
- */
-void mddi_host_client_cnt_reset(void)
-{
-	unsigned long flags;
-	mddi_host_cntl_type *pmhctl;
-
-	pmhctl = &(mhctl[MDDI_HOST_PRIM]);
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-	pmhctl->client_status_cnt = 0;
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-}
-
-static void mddi_host_powerup(mddi_host_type host_idx)
-{
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if (pmhctl->link_state != MDDI_LINK_DISABLED)
-		return;
-
-	/* enable IO_CLK and hclk to MDDI host core */
-	mddi_host_enable_io_clock();
-
-	mddi_host_initialize_registers(host_idx);
-	mddi_host_configure_interrupts(host_idx, TRUE);
-
-	pmhctl->link_state = MDDI_LINK_ACTIVATING;
-
-	/* Link activate command */
-	mddi_host_reg_out(CMD, MDDI_CMD_LINK_ACTIVE);
-
-#ifdef CLKRGM_MDDI_IO_CLOCK_IN_MHZ
-	MDDI_MSG_NOTICE("MDDI Host: Activating Link %d Mbps\n",
-			CLKRGM_MDDI_IO_CLOCK_IN_MHZ * 2);
-#else
-	MDDI_MSG_NOTICE("MDDI Host: Activating Link\n");
-#endif
-
-	/* Initialize the timer */
-	if (host_idx == MDDI_HOST_PRIM)
-		mddi_host_timer_service(0);
-}
-
-void mddi_send_fw_link_skew_cal(mddi_host_type host_idx)
-{
-	mddi_host_reg_out(CMD, MDDI_CMD_FW_LINK_SKEW_CAL);
-	MDDI_MSG_DEBUG("%s: Skew Calibration done!!\n", __func__);
-}
-
-
-void mddi_host_init(mddi_host_type host_idx)
-/* Write out the MDDI configuration registers */
-{
-	static boolean initialized = FALSE;
-	mddi_host_cntl_type *pmhctl;
-
-	if (host_idx >= MDDI_NUM_HOST_CORES) {
-		MDDI_MSG_ERR("Invalid host core index\n");
-		return;
-	}
-
-	if (!initialized) {
-		uint16 idx;
-		mddi_host_type host;
-
-		for (host = MDDI_HOST_PRIM; host < MDDI_NUM_HOST_CORES; host++) {
-			pmhctl = &(mhctl[host]);
-			initialized = TRUE;
-
-			pmhctl->llist_ptr =
-			    dma_alloc_coherent(NULL, MDDI_LLIST_POOL_SIZE,
-					       &(pmhctl->llist_dma_addr),
-					       GFP_KERNEL);
-			pmhctl->llist_dma_ptr =
-			    (mddi_linked_list_type *) (void *)pmhctl->
-			    llist_dma_addr;
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-			pmhctl->rev_data_buf = NULL;
-			if (pmhctl->llist_ptr == NULL)
-#else
-			mddi_rev_user.waiting = FALSE;
-			init_completion(&(mddi_rev_user.done_comp));
-			pmhctl->rev_data_buf =
-			    dma_alloc_coherent(NULL, MDDI_MAX_REV_DATA_SIZE,
-					       &(pmhctl->rev_data_dma_addr),
-					       GFP_KERNEL);
-			if ((pmhctl->llist_ptr == NULL)
-			    || (pmhctl->rev_data_buf == NULL))
-#endif
-			{
-				MDDI_MSG_CRIT
-				    ("unable to alloc non-cached memory\n");
-			}
-			llist_extern[host] = pmhctl->llist_ptr;
-			llist_dma_extern[host] = pmhctl->llist_dma_ptr;
-			llist_extern_notify[host] = pmhctl->llist_notify;
-
-			for (idx = 0; idx < UNASSIGNED_INDEX; idx++) {
-				init_completion(&
-						(pmhctl->llist_notify[idx].
-						 done_comp));
-			}
-			init_completion(&(pmhctl->mddi_llist_avail_comp));
-			spin_lock_init(&mddi_host_spin_lock);
-			pmhctl->mddi_waiting_for_llist_avail = FALSE;
-			pmhctl->mddi_rev_ptr_write_val =
-			    (uint32) (void *)(pmhctl->rev_data_dma_addr);
-			pmhctl->rev_ptr_start = (void *)pmhctl->rev_data_buf;
-
-			pmhctl->rev_pkt_size = MDDI_DEFAULT_REV_PKT_SIZE;
-			pmhctl->rev_state = MDDI_REV_IDLE;
-#ifdef IMAGE_MODEM_PROC
-			/* assume hibernation state is last state from APPS proc, so that
-			 * we don't reinitialize the host core */
-			pmhctl->link_state = MDDI_LINK_HIBERNATING;
-#else
-			pmhctl->link_state = MDDI_LINK_DISABLED;
-#endif
-			pmhctl->driver_state = MDDI_DRIVER_DISABLED;
-			pmhctl->disable_hibernation = FALSE;
-
-			/* initialize llist variables */
-			pmhctl->llist_info.transmitting_start_idx =
-			    UNASSIGNED_INDEX;
-			pmhctl->llist_info.transmitting_end_idx =
-			    UNASSIGNED_INDEX;
-			pmhctl->llist_info.waiting_start_idx = UNASSIGNED_INDEX;
-			pmhctl->llist_info.waiting_end_idx = UNASSIGNED_INDEX;
-			pmhctl->llist_info.reg_read_idx = UNASSIGNED_INDEX;
-			pmhctl->llist_info.next_free_idx =
-			    MDDI_FIRST_DYNAMIC_LLIST_IDX;
-			pmhctl->llist_info.reg_read_waiting = FALSE;
-
-			mddi_vsync_detect_enabled = FALSE;
-			mddi_gpio.polling_enabled = FALSE;
-
-			pmhctl->int_type.count = 0;
-			pmhctl->int_type.in_count = 0;
-			pmhctl->int_type.disp_req_count = 0;
-			pmhctl->int_type.state_change_count = 0;
-			pmhctl->int_type.ll_done_count = 0;
-			pmhctl->int_type.rev_avail_count = 0;
-			pmhctl->int_type.error_count = 0;
-			pmhctl->int_type.rev_encap_count = 0;
-			pmhctl->int_type.llist_ptr_write_1 = 0;
-			pmhctl->int_type.llist_ptr_write_2 = 0;
-
-			pmhctl->stats.fwd_crc_count = 0;
-			pmhctl->stats.rev_crc_count = 0;
-			pmhctl->stats.pri_underflow = 0;
-			pmhctl->stats.sec_underflow = 0;
-			pmhctl->stats.rev_overflow = 0;
-			pmhctl->stats.pri_overwrite = 0;
-			pmhctl->stats.sec_overwrite = 0;
-			pmhctl->stats.rev_overwrite = 0;
-			pmhctl->stats.dma_failure = 0;
-			pmhctl->stats.rtd_failure = 0;
-			pmhctl->stats.reg_read_failure = 0;
-#ifdef FEATURE_MDDI_UNDERRUN_RECOVERY
-			pmhctl->stats.pri_underrun_detected = 0;
-#endif
-
-			pmhctl->log_parms.rtd_cnt = 0;
-			pmhctl->log_parms.rev_enc_cnt = 0;
-			pmhctl->log_parms.vid_cnt = 0;
-			pmhctl->log_parms.reg_acc_cnt = 0;
-			pmhctl->log_parms.cli_stat_cnt = 0;
-			pmhctl->log_parms.cli_cap_cnt = 0;
-			pmhctl->log_parms.reg_read_cnt = 0;
-			pmhctl->log_parms.link_active_cnt = 0;
-			pmhctl->log_parms.link_hibernate_cnt = 0;
-			pmhctl->log_parms.fwd_crc_cnt = 0;
-			pmhctl->log_parms.rev_crc_cnt = 0;
-			pmhctl->log_parms.vsync_response_cnt = 0;
-
-			prev_parms[host_idx] = pmhctl->log_parms;
-			mddi_client_capability_pkt.packet_length = 0;
-		}
-
-#ifndef T_MSM7500
-		/* tell clock driver we are user of this PLL */
-		MDDI_HOST_ENABLE_IO_CLOCK;
-#endif
-	}
-
-	mddi_host_powerup(host_idx);
-	pmhctl = &(mhctl[host_idx]);
-}
-
-#ifdef CONFIG_FB_MSM_MDDI_AUTO_DETECT
-static uint32 mddi_client_id;
-
-uint32 mddi_get_client_id(void)
-{
-
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	static boolean client_detection_try = FALSE;
-	mddi_host_cntl_type *pmhctl;
-	unsigned long flags;
-	uint16 saved_rev_pkt_size;
-	int ret;
-
-	if (!client_detection_try) {
-		/* Toshiba display requires larger drive_lo value */
-		mddi_host_reg_out(DRIVE_LO, 0x0050);
-
-		pmhctl = &(mhctl[MDDI_HOST_PRIM]);
-
-		saved_rev_pkt_size = pmhctl->rev_pkt_size;
-
-		/* Increase Rev Encap Size */
-		pmhctl->rev_pkt_size = MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE;
-		mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
-
-		/* disable hibernation temporarily */
-		if (!pmhctl->disable_hibernation)
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE);
-
-		mddi_rev_user.waiting = TRUE;
-		INIT_COMPLETION(mddi_rev_user.done_comp);
-
-		spin_lock_irqsave(&mddi_host_spin_lock, flags);
-
-		/* turn on clock(s), if they have been disabled */
-		mddi_host_enable_hclk();
-		mddi_host_enable_io_clock();
-
-		mddi_client_capability_request = TRUE;
-
-		if (pmhctl->rev_state == MDDI_REV_IDLE) {
-			/* attempt to send the reverse encapsulation now */
-			mddi_issue_reverse_encapsulation();
-		}
-		spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-		wait_for_completion_killable(&(mddi_rev_user.done_comp));
-
-		/* Set Rev Encap Size back to its original value */
-		pmhctl->rev_pkt_size = saved_rev_pkt_size;
-		mddi_host_reg_out(REV_ENCAP_SZ, pmhctl->rev_pkt_size);
-
-		/* reenable auto-hibernate */
-		if (!pmhctl->disable_hibernation)
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
-
-		mddi_host_reg_out(DRIVE_LO, 0x0032);
-		client_detection_try = TRUE;
-
-		mddi_client_id = (mddi_client_capability_pkt.Mfr_Name<<16) |
-				mddi_client_capability_pkt.Product_Code;
-
-		if (!mddi_client_id)
-			mddi_disable(1);
-
-		ret = mddi_client_power(mddi_client_id);
-		if (ret < 0)
-			MDDI_MSG_ERR("mddi_client_power return %d", ret);
-	}
-
-#endif
-
-	return mddi_client_id;
-}
-#endif
-
-void mddi_host_powerdown(mddi_host_type host_idx)
-{
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if (host_idx >= MDDI_NUM_HOST_CORES) {
-		MDDI_MSG_ERR("Invalid host core index\n");
-		return;
-	}
-
-	if (pmhctl->driver_state == MDDI_DRIVER_RESET) {
-		return;
-	}
-
-	if (host_idx == MDDI_HOST_PRIM) {
-		/* disable timer */
-		del_timer(&mddi_host_timer);
-	}
-
-	mddi_host_configure_interrupts(host_idx, FALSE);
-
-	/* turn on HCLK to MDDI host core if it has been disabled */
-	mddi_host_enable_hclk();
-
-	/* MDDI Reset command */
-	mddi_host_reg_out(CMD, MDDI_CMD_RESET);
-
-	/* Pad Control Register */
-	mddi_host_reg_out(PAD_CTL, 0x0);
-
-	/* disable IO_CLK and hclk to MDDI host core */
-	mddi_host_disable_io_clock();
-	mddi_host_disable_hclk();
-
-	pmhctl->link_state = MDDI_LINK_DISABLED;
-	pmhctl->driver_state = MDDI_DRIVER_RESET;
-
-	MDDI_MSG_NOTICE("MDDI Host: Disabling Link\n");
-
-}
-
-uint16 mddi_get_next_free_llist_item(mddi_host_type host_idx, boolean wait)
-{
-	unsigned long flags;
-	uint16 ret_idx;
-	boolean forced_wait = FALSE;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	ret_idx = pmhctl->llist_info.next_free_idx;
-
-	pmhctl->llist_info.next_free_idx++;
-	if (pmhctl->llist_info.next_free_idx >= MDDI_NUM_DYNAMIC_LLIST_ITEMS)
-		pmhctl->llist_info.next_free_idx = MDDI_FIRST_DYNAMIC_LLIST_IDX;
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-	if (pmhctl->llist_notify[ret_idx].in_use) {
-		if (!wait) {
-			pmhctl->llist_info.next_free_idx = ret_idx;
-			ret_idx = UNASSIGNED_INDEX;
-		} else {
-			forced_wait = TRUE;
-			INIT_COMPLETION(pmhctl->mddi_llist_avail_comp);
-		}
-	}
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-	if (forced_wait) {
-		wait_for_completion_killable(&
-						  (pmhctl->
-						   mddi_llist_avail_comp));
-		MDDI_MSG_ERR("task waiting on mddi llist item\n");
-	}
-
-	if (ret_idx != UNASSIGNED_INDEX) {
-		pmhctl->llist_notify[ret_idx].waiting = FALSE;
-		pmhctl->llist_notify[ret_idx].done_cb = NULL;
-		pmhctl->llist_notify[ret_idx].in_use = TRUE;
-		pmhctl->llist_notify[ret_idx].next_idx = UNASSIGNED_INDEX;
-	}
-
-	return ret_idx;
-}
-
-uint16 mddi_get_reg_read_llist_item(mddi_host_type host_idx, boolean wait)
-{
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-	MDDI_MSG_CRIT("No reverse link available\n");
-	(void)wait;
-	return FALSE;
-#else
-	unsigned long flags;
-	uint16 ret_idx;
-	boolean error = FALSE;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-	if (pmhctl->llist_info.reg_read_idx != UNASSIGNED_INDEX) {
-		/* need to block here or is this an error condition? */
-		error = TRUE;
-		ret_idx = UNASSIGNED_INDEX;
-	}
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-	if (!error) {
-		ret_idx = pmhctl->llist_info.reg_read_idx =
-		    mddi_get_next_free_llist_item(host_idx, wait);
-		/* clear the reg_read_waiting flag */
-		pmhctl->llist_info.reg_read_waiting = FALSE;
-	}
-
-	if (error)
-		MDDI_MSG_ERR("***** Reg read still in progress! ****\n");
-	return ret_idx;
-#endif
-
-}
-
-void mddi_queue_forward_packets(uint16 first_llist_idx,
-				uint16 last_llist_idx,
-				boolean wait,
-				mddi_llist_done_cb_type llist_done_cb,
-				mddi_host_type host_idx)
-{
-	unsigned long flags;
-	mddi_linked_list_type *llist;
-	mddi_linked_list_type *llist_dma;
-	mddi_host_cntl_type *pmhctl = &(mhctl[host_idx]);
-
-	if ((first_llist_idx >= UNASSIGNED_INDEX) ||
-	    (last_llist_idx >= UNASSIGNED_INDEX)) {
-		MDDI_MSG_ERR("MDDI queueing invalid linked list\n");
-		return;
-	}
-
-	if (pmhctl->link_state == MDDI_LINK_DISABLED)
-		MDDI_MSG_CRIT("MDDI host powered down!\n");
-
-	llist = pmhctl->llist_ptr;
-	llist_dma = pmhctl->llist_dma_ptr;
-
-	/* clean cache so MDDI host can read data */
-	memory_barrier();
-
-	pmhctl->llist_notify[last_llist_idx].waiting = wait;
-	if (wait)
-		INIT_COMPLETION(pmhctl->llist_notify[last_llist_idx].done_comp);
-	pmhctl->llist_notify[last_llist_idx].done_cb = llist_done_cb;
-
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-
-	if ((pmhctl->llist_info.transmitting_start_idx == UNASSIGNED_INDEX) &&
-	    (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) &&
-	    (pmhctl->rev_state == MDDI_REV_IDLE)) {
-		/* no packets are currently transmitting */
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
-			/* This is the special case where the packet is a register read. */
-			pmhctl->rev_state = MDDI_REV_REG_READ_ISSUED;
-			mddi_reg_read_retry = 0;
-			/* mddi_rev_reg_read_attempt = 1; */
-		}
-#endif
-		/* assign transmitting index values */
-		pmhctl->llist_info.transmitting_start_idx = first_llist_idx;
-		pmhctl->llist_info.transmitting_end_idx = last_llist_idx;
-
-		/* turn on clock(s), if they have been disabled */
-		mddi_host_enable_hclk();
-		mddi_host_enable_io_clock();
-		pmhctl->int_type.llist_ptr_write_1++;
-		/* Write to primary pointer register */
-		dma_coherent_pre_ops();
-		mddi_host_reg_out(PRI_PTR, &llist_dma[first_llist_idx]);
-
-		/* enable interrupt when complete */
-		mddi_host_reg_outm(INTEN, MDDI_INT_PRI_LINK_LIST_DONE,
-				   MDDI_INT_PRI_LINK_LIST_DONE);
-
-	} else if (pmhctl->llist_info.waiting_start_idx == UNASSIGNED_INDEX) {
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
-			/*
-			 * we have a register read to send but need to wait
-			 * for current reverse activity to end or there are
-			 * packets currently transmitting
-			 */
-			/* mddi_rev_reg_read_attempt = 0; */
-			pmhctl->llist_info.reg_read_waiting = TRUE;
-		}
-#endif
-
-		/* assign waiting index values */
-		pmhctl->llist_info.waiting_start_idx = first_llist_idx;
-		pmhctl->llist_info.waiting_end_idx = last_llist_idx;
-	} else {
-		uint16 prev_end_idx = pmhctl->llist_info.waiting_end_idx;
-#ifndef FEATURE_MDDI_DISABLE_REVERSE
-		if (first_llist_idx == pmhctl->llist_info.reg_read_idx) {
-			/*
-			 * we have a register read to send but need to wait
-			 * for current reverse activity to end or there are
-			 * packets currently transmitting
-			 */
-			/* mddi_rev_reg_read_attempt = 0; */
-			pmhctl->llist_info.reg_read_waiting = TRUE;
-		}
-#endif
-
-		llist = pmhctl->llist_ptr;
-
-		/* clear end flag in previous last packet */
-		llist[prev_end_idx].link_controller_flags = 0;
-		pmhctl->llist_notify[prev_end_idx].next_idx = first_llist_idx;
-
-		/* set the next_packet_pointer of the previous last packet */
-		llist[prev_end_idx].next_packet_pointer =
-		    (void *)(&llist_dma[first_llist_idx]);
-
-		/* clean cache so MDDI host can read data */
-		memory_barrier();
-
-		/* assign new waiting last index value */
-		pmhctl->llist_info.waiting_end_idx = last_llist_idx;
-	}
-
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-}
-
-void mddi_host_write_pix_attr_reg(uint32 value)
-{
-	(void)value;
-}
-
-void mddi_queue_reverse_encapsulation(boolean wait)
-{
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-	MDDI_MSG_CRIT("No reverse link available\n");
-	(void)wait;
-#else
-	unsigned long flags;
-	boolean error = FALSE;
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
-
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-
-	/* turn on clock(s), if they have been disabled */
-	mddi_host_enable_hclk();
-	mddi_host_enable_io_clock();
-
-	if (wait) {
-		if (!mddi_rev_user.waiting) {
-			mddi_rev_user.waiting = TRUE;
-			INIT_COMPLETION(mddi_rev_user.done_comp);
-		} else
-			error = TRUE;
-	}
-	mddi_rev_encap_user_request = TRUE;
-
-	if (pmhctl->rev_state == MDDI_REV_IDLE) {
-		/* attempt to send the reverse encapsulation now */
-		mddi_host_type orig_host_idx = mddi_curr_host;
-		mddi_curr_host = host_idx;
-		mddi_issue_reverse_encapsulation();
-		mddi_curr_host = orig_host_idx;
-	}
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-	if (error) {
-		MDDI_MSG_ERR("Reverse Encap request already in progress\n");
-	} else if (wait)
-		wait_for_completion_killable(&(mddi_rev_user.done_comp));
-#endif
-}
-
-/* ISR to be executed */
-boolean mddi_set_rev_handler(mddi_rev_handler_type handler, uint16 pkt_type)
-{
-#ifdef FEATURE_MDDI_DISABLE_REVERSE
-	MDDI_MSG_CRIT("No reverse link available\n");
-	(void)handler;
-	(void)pkt_type;
-	return (FALSE);
-#else
-	unsigned long flags;
-	uint16 hdlr;
-	boolean handler_set = FALSE;
-	boolean overwrite = FALSE;
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
-
-	/* Disable interrupts */
-	spin_lock_irqsave(&mddi_host_spin_lock, flags);
-
-	for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS; hdlr++) {
-		if (mddi_rev_pkt_handler[hdlr].pkt_type == pkt_type) {
-			mddi_rev_pkt_handler[hdlr].handler = handler;
-			if (handler == NULL) {
-				/* clearing handler from table */
-				mddi_rev_pkt_handler[hdlr].pkt_type =
-				    INVALID_PKT_TYPE;
-				handler_set = TRUE;
-				if (pkt_type == 0x10) {	/* video stream packet */
-					/* ensure HCLK on to MDDI host core before register write */
-					mddi_host_enable_hclk();
-					/* No longer getting video, so reset rev encap size to default */
-					pmhctl->rev_pkt_size =
-					    MDDI_DEFAULT_REV_PKT_SIZE;
-					mddi_host_reg_out(REV_ENCAP_SZ,
-							  pmhctl->rev_pkt_size);
-				}
-			} else {
-				/* already a handler for this packet */
-				overwrite = TRUE;
-			}
-			break;
-		}
-	}
-	if ((hdlr >= MAX_MDDI_REV_HANDLERS) && (handler != NULL)) {
-		/* assigning new handler */
-		for (hdlr = 0; hdlr < MAX_MDDI_REV_HANDLERS; hdlr++) {
-			if (mddi_rev_pkt_handler[hdlr].pkt_type ==
-			    INVALID_PKT_TYPE) {
-				if ((pkt_type == 0x10) &&	/* video stream packet */
-				    (pmhctl->rev_pkt_size <
-				     MDDI_VIDEO_REV_PKT_SIZE)) {
-					/* ensure HCLK on to MDDI host core before register write */
-					mddi_host_enable_hclk();
-					/* Increase Rev Encap Size */
-					pmhctl->rev_pkt_size =
-					    MDDI_VIDEO_REV_PKT_SIZE;
-					mddi_host_reg_out(REV_ENCAP_SZ,
-							  pmhctl->rev_pkt_size);
-				}
-				mddi_rev_pkt_handler[hdlr].handler = handler;
-				mddi_rev_pkt_handler[hdlr].pkt_type = pkt_type;
-				handler_set = TRUE;
-				break;
-			}
-		}
-	}
-
-	/* Restore interrupts */
-	spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-
-	if (overwrite)
-		MDDI_MSG_ERR("Overwriting previous rev packet handler\n");
-
-	return handler_set;
-
-#endif
-}				/* mddi_set_rev_handler */
-
-void mddi_host_disable_hibernation(boolean disable)
-{
-	mddi_host_type host_idx = MDDI_HOST_PRIM;
-	mddi_host_cntl_type *pmhctl = &(mhctl[MDDI_HOST_PRIM]);
-
-	if (disable) {
-		pmhctl->disable_hibernation = TRUE;
-		/* hibernation will be turned off by isr next time it is entered */
-	} else {
-		if (pmhctl->disable_hibernation) {
-			unsigned long flags;
-			spin_lock_irqsave(&mddi_host_spin_lock, flags);
-			if (!MDDI_HOST_IS_HCLK_ON)
-				MDDI_HOST_ENABLE_HCLK;
-			mddi_host_reg_out(CMD, MDDI_CMD_HIBERNATE | 1);
-			spin_unlock_irqrestore(&mddi_host_spin_lock, flags);
-			pmhctl->disable_hibernation = FALSE;
-		}
-	}
-}
-
-void mddi_mhctl_remove(mddi_host_type host_idx)
-{
-	mddi_host_cntl_type *pmhctl;
-
-	pmhctl = &(mhctl[host_idx]);
-
-	dma_free_coherent(NULL, MDDI_LLIST_POOL_SIZE, (void *)pmhctl->llist_ptr,
-			  pmhctl->llist_dma_addr);
-
-	dma_free_coherent(NULL, MDDI_MAX_REV_DATA_SIZE,
-			  (void *)pmhctl->rev_data_buf,
-			  pmhctl->rev_data_dma_addr);
-}
diff --git a/drivers/video/msm/mddihosti.h b/drivers/video/msm/mddihosti.h
deleted file mode 100644
index 96675a0..0000000
--- a/drivers/video/msm/mddihosti.h
+++ /dev/null
@@ -1,552 +0,0 @@
-/* Copyright (c) 2008-2010, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef MDDIHOSTI_H
-#define MDDIHOSTI_H
-
-#include "msm_fb.h"
-#include "mddihost.h"
-#include <linux/clk.h>
-
-/* Register offsets in MDDI, applies to both msm_pmdh_base and
- * (u32)msm_emdh_base. */
-#define MDDI_CMD   		0x0000
-#define MDDI_VERSION   		0x0004
-#define MDDI_PRI_PTR		0x0008
-#define MDDI_BPS		0x0010
-#define MDDI_SPM		0x0014
-#define MDDI_INT		0x0018
-#define MDDI_INTEN		0x001c
-#define MDDI_REV_PTR		0x0020
-#define MDDI_REV_SIZE		0x0024
-#define MDDI_STAT		0x0028
-#define MDDI_REV_RATE_DIV	0x002c
-#define MDDI_REV_CRC_ERR	0x0030
-#define MDDI_TA1_LEN		0x0034
-#define MDDI_TA2_LEN		0x0038
-#define MDDI_TEST		0x0040
-#define MDDI_REV_PKT_CNT	0x0044
-#define MDDI_DRIVE_HI		0x0048
-#define MDDI_DRIVE_LO		0x004c
-#define MDDI_DISP_WAKE		0x0050
-#define MDDI_REV_ENCAP_SZ	0x0054
-#define MDDI_RTD_VAL		0x0058
-#define MDDI_PAD_CTL		0x0068
-#define MDDI_DRIVER_START_CNT	0x006c
-#define MDDI_CORE_VER		0x008c
-#define MDDI_FIFO_ALLOC         0x0090
-#define MDDI_PAD_IO_CTL         0x00a0
-#define MDDI_PAD_CAL            0x00a4
-
-#ifdef ENABLE_MDDI_MULTI_READ_WRITE
-#define MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR 128
-#else
-#define MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR 1
-#endif
-
-extern int32 mddi_client_type;
-extern u32 mddi_msg_level;
-
-/* No longer need to write to clear these registers */
-#define xxxx_mddi_host_reg_outm(reg, mask, val)  \
-do { \
-	if (host_idx == MDDI_HOST_PRIM) \
-		mddi_host_reg_outm_pmdh(reg, mask, val); \
-	else \
-		mddi_host_reg_outm_emdh(reg, mask, val); \
-} while (0)
-
-#define mddi_host_reg_outm(reg, mask, val) \
-do { \
-	unsigned long __addr; \
-	if (host_idx == MDDI_HOST_PRIM) \
-		__addr = (u32)msm_pmdh_base + MDDI_##reg; \
-	else \
-		__addr = (u32)msm_emdh_base + MDDI_##reg; \
-	writel((readl(__addr) & ~(mask)) | ((val) & (mask)), __addr); \
-} while (0)
-
-#define xxxx_mddi_host_reg_out(reg, val) \
-do { \
-	if (host_idx == MDDI_HOST_PRIM)  \
-		mddi_host_reg_out_pmdh(reg, val); \
-	else \
-		mddi_host_reg_out_emdh(reg, val); \
-	} while (0)
-
-#define mddi_host_reg_out(reg, val) \
-do { \
-	if (host_idx == MDDI_HOST_PRIM) \
-		writel(val, (u32)msm_pmdh_base + MDDI_##reg); \
-	else \
-		writel(val, (u32)msm_emdh_base + MDDI_##reg); \
-} while (0)
-
-#define xxxx_mddi_host_reg_in(reg)  \
-  ((host_idx) ? \
-     mddi_host_reg_in_emdh(reg) : mddi_host_reg_in_pmdh(reg));
-
-#define mddi_host_reg_in(reg) \
-((host_idx) ? \
-	readl((u32)msm_emdh_base + MDDI_##reg) : \
-	readl((u32)msm_pmdh_base + MDDI_##reg)) \
-
-#define xxxx_mddi_host_reg_inm(reg, mask)  \
-  ((host_idx) ? \
-    mddi_host_reg_inm_emdh(reg, mask) : \
-    mddi_host_reg_inm_pmdh(reg, mask);)
-
-#define mddi_host_reg_inm(reg, mask) \
-((host_idx) ? \
-	readl((u32)msm_emdh_base + MDDI_##reg) & (mask) : \
-	readl((u32)msm_pmdh_base + MDDI_##reg) & (mask)) \
-
-/* Using non-cacheable pmem, so do nothing */
-#define mddi_invalidate_cache_lines(addr_start, num_bytes)
-/*
- * Using non-cacheable pmem, so do nothing with cache
- * but, ensure write goes out to memory
- */
-#define mddi_flush_cache_lines(addr_start, num_bytes)  \
-    (void) addr_start; \
-    (void) num_bytes;  \
-    memory_barrier()
-
-/* Since this translates to Remote Procedure Calls to check on clock status
-* just use a local variable to keep track of io_clock */
-#define MDDI_HOST_IS_IO_CLOCK_ON mddi_host_io_clock_on
-#define MDDI_HOST_ENABLE_IO_CLOCK
-#define MDDI_HOST_DISABLE_IO_CLOCK
-#define MDDI_HOST_IS_HCLK_ON mddi_host_hclk_on
-#define MDDI_HOST_ENABLE_HCLK
-#define MDDI_HOST_DISABLE_HCLK
-#define FEATURE_MDDI_HOST_IO_CLOCK_CONTROL_DISABLE
-#define FEATURE_MDDI_HOST_HCLK_CONTROL_DISABLE
-
-#define TRAMP_MDDI_HOST_ISR TRAMP_MDDI_PRI_ISR
-#define TRAMP_MDDI_HOST_EXT_ISR TRAMP_MDDI_EXT_ISR
-#define MDP_LINE_COUNT_BMSK  0x3ff
-#define MDP_SYNC_STATUS  0x000c
-#define MDP_LINE_COUNT      \
-(readl(msm_mdp_base + MDP_SYNC_STATUS) & MDP_LINE_COUNT_BMSK)
-
-/* MDP sends 256 pixel packets, so lower value hibernates more without
-* significantly increasing latency of waiting for next subframe */
-#define MDDI_HOST_BYTES_PER_SUBFRAME  0x3C00
-
-#if defined(CONFIG_FB_MSM_MDP31) || defined(CONFIG_FB_MSM_MDP40)
-#define MDDI_HOST_TA2_LEN       0x001a
-#define MDDI_HOST_REV_RATE_DIV  0x0004
-#else
-#define MDDI_HOST_TA2_LEN       0x000c
-#define MDDI_HOST_REV_RATE_DIV  0x0002
-#endif
-
-#define MDDI_MSG_EMERG(msg, ...)    \
-	if (mddi_msg_level > 0)  \
-		printk(KERN_EMERG msg, ## __VA_ARGS__);
-#define MDDI_MSG_ALERT(msg, ...)    \
-	if (mddi_msg_level > 1)  \
-		printk(KERN_ALERT msg, ## __VA_ARGS__);
-#define MDDI_MSG_CRIT(msg, ...)    \
-	if (mddi_msg_level > 2)  \
-		printk(KERN_CRIT msg, ## __VA_ARGS__);
-#define MDDI_MSG_ERR(msg, ...)    \
-	if (mddi_msg_level > 3)  \
-		printk(KERN_ERR msg, ## __VA_ARGS__);
-#define MDDI_MSG_WARNING(msg, ...)    \
-	if (mddi_msg_level > 4)  \
-		printk(KERN_WARNING msg, ## __VA_ARGS__);
-#define MDDI_MSG_NOTICE(msg, ...)    \
-	if (mddi_msg_level > 5)  \
-		printk(KERN_NOTICE msg, ## __VA_ARGS__);
-#define MDDI_MSG_INFO(msg, ...)    \
-	if (mddi_msg_level > 6)  \
-		printk(KERN_INFO msg, ## __VA_ARGS__);
-#define MDDI_MSG_DEBUG(msg, ...)    \
-	if (mddi_msg_level > 7)  \
-		printk(KERN_DEBUG msg, ## __VA_ARGS__);
-
-#define GCC_PACKED __attribute__((packed))
-typedef struct GCC_PACKED {
-	uint16 packet_length;
-	/* total # of bytes in the packet not including
-		the packet_length field. */
-
-	uint16 packet_type;
-	/* A Packet Type of 70 identifies the packet as
-		a Client status Packet. */
-
-	uint16 bClient_ID;
-	/* This field is reserved for future use and shall
-		be set to zero. */
-
-} mddi_rev_packet_type;
-
-typedef struct GCC_PACKED {
-	uint16 packet_length;
-	/* total # of bytes in the packet not including
-		the packet_length field. */
-
-	uint16 packet_type;
-	/* A Packet Type of 70 identifies the packet as
-		a Client status Packet. */
-
-	uint16 bClient_ID;
-	/* This field is reserved for future use and shall
-		be set to zero. */
-
-	uint16 reverse_link_request;
-	/* 16 bit unsigned integer with number of bytes client
-		needs in the * reverse encapsulation message
-		to transmit data. */
-
-	uint8 crc_error_count;
-	uint8 capability_change;
-	uint16 graphics_busy_flags;
-
-	uint16 parameter_CRC;
-	/* 16-bit CRC of all the bytes in the packet
-		including Packet Length. */
-
-} mddi_client_status_type;
-
-typedef struct GCC_PACKED {
-	uint16 packet_length;
-	/* total # of bytes in the packet not including
-		the packet_length field. */
-
-	uint16 packet_type;
-	/* A Packet Type of 66 identifies the packet as
-		a Client Capability Packet. */
-
-	uint16 bClient_ID;
-	/* This field is reserved for future use and
-		shall be set to zero. */
-
-	uint16 Protocol_Version;
-	uint16 Minimum_Protocol_Version;
-	uint16 Data_Rate_Capability;
-	uint8 Interface_Type_Capability;
-	uint8 Number_of_Alt_Displays;
-	uint16 PostCal_Data_Rate;
-	uint16 Bitmap_Width;
-	uint16 Bitmap_Height;
-	uint16 Display_Window_Width;
-	uint16 Display_Window_Height;
-	uint32 Color_Map_Size;
-	uint16 Color_Map_RGB_Width;
-	uint16 RGB_Capability;
-	uint8 Monochrome_Capability;
-	uint8 Reserved_1;
-	uint16 Y_Cb_Cr_Capability;
-	uint16 Bayer_Capability;
-	uint16 Alpha_Cursor_Image_Planes;
-	uint32 Client_Feature_Capability_Indicators;
-	uint8 Maximum_Video_Frame_Rate_Capability;
-	uint8 Minimum_Video_Frame_Rate_Capability;
-	uint16 Minimum_Sub_frame_Rate;
-	uint16 Audio_Buffer_Depth;
-	uint16 Audio_Channel_Capability;
-	uint16 Audio_Sample_Rate_Capability;
-	uint8 Audio_Sample_Resolution;
-	uint8 Mic_Audio_Sample_Resolution;
-	uint16 Mic_Sample_Rate_Capability;
-	uint8 Keyboard_Data_Format;
-	uint8 pointing_device_data_format;
-	uint16 content_protection_type;
-	uint16 Mfr_Name;
-	uint16 Product_Code;
-	uint16 Reserved_3;
-	uint32 Serial_Number;
-	uint8 Week_of_Manufacture;
-	uint8 Year_of_Manufacture;
-
-	uint16 parameter_CRC;
-	/* 16-bit CRC of all the bytes in the packet including Packet Length. */
-
-} mddi_client_capability_type;
-
-typedef struct GCC_PACKED {
-	uint16 packet_length;
-	/* total # of bytes in the packet not including the packet_length field. */
-
-	uint16 packet_type;
-	/* A Packet Type of 16 identifies the packet as a Video Stream Packet. */
-
-	uint16 bClient_ID;
-	/* This field is reserved for future use and shall be set to zero. */
-
-	uint16 video_data_format_descriptor;
-	/* format of each pixel in the Pixel Data in the present stream in the
-	 * present packet.
-	 * If bits [15:13] = 000 monochrome
-	 * If bits [15:13] = 001 color pixels (palette).
-	 * If bits [15:13] = 010 color pixels in raw RGB
-	 * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
-	 * If bits [15:13] = 100 Bayer pixels
-	 */
-
-	uint16 pixel_data_attributes;
-	/* interpreted as follows:
-	 * Bits [1:0] = 11  pixel data is displayed to both eyes
-	 * Bits [1:0] = 10  pixel data is routed to the left eye only.
-	 * Bits [1:0] = 01  pixel data is routed to the right eye only.
-	 * Bits [1:0] = 00  pixel data is routed to the alternate display.
-	 * Bit 2 is 0  Pixel Data is in the standard progressive format.
-	 * Bit 2 is 1  Pixel Data is in interlace format.
-	 * Bit 3 is 0  Pixel Data is in the standard progressive format.
-	 * Bit 3 is 1  Pixel Data is in alternate pixel format.
-	 * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
-	 * Bit 4 is 1  Pixel Data is to or from the camera.
-	 * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
-	 * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
-	 *             X Start, and Y Start parameters are not defined and
-	 *             shall be ignored by the client.
-	 * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
-	 * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
-	 * Bits [7:6] = 11  Pixel data is written to all image buffers.
-	 * Bits [7:6] = 10  Invalid. Reserved for future use.
-	 * Bits 8 through 11 alternate display number.
-	 * Bits 12 through 14 are reserved for future use and shall be set to zero.
-	 * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
-	 */
-
-	uint16 x_left_edge;
-	uint16 y_top_edge;
-	/* X,Y coordinate of the top left edge of the screen window */
-
-	uint16 x_right_edge;
-	uint16 y_bottom_edge;
-	/*  X,Y coordinate of the bottom right edge of the window being updated. */
-
-	uint16 x_start;
-	uint16 y_start;
-	/*  (X Start, Y Start) is the first pixel in the Pixel Data field below. */
-
-	uint16 pixel_count;
-	/*  number of pixels in the Pixel Data field below. */
-
-	uint16 parameter_CRC;
-	/*  16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
-
-	uint16 reserved;
-	/* 16-bit variable to make structure align on 4 byte boundary */
-
-} mddi_video_stream_packet_type;
-
-typedef struct GCC_PACKED {
-	uint16 packet_length;
-	/* total # of bytes in the packet not including the packet_length field. */
-
-	uint16 packet_type;
-	/* A Packet Type of 146 identifies the packet as a Register Access Packet. */
-
-	uint16 bClient_ID;
-	/* This field is reserved for future use and shall be set to zero. */
-
-	uint16 read_write_info;
-	/* Bits 13:0  a 14-bit unsigned integer that specifies the number of
-	 *            32-bit Register Data List items to be transferred in the
-	 *            Register Data List field.
-	 * Bits[15:14] = 00  Write to register(s);
-	 * Bits[15:14] = 10  Read from register(s);
-	 * Bits[15:14] = 11  Response to a Read.
-	 * Bits[15:14] = 01  this value is reserved for future use. */
-
-	uint32 register_address;
-	/* the register address that is to be written to or read from. */
-
-	uint16 parameter_CRC;
-	/* 16-bit CRC of all bytes from the Packet Length to the Register Address. */
-
-	uint32 register_data_list[MDDI_HOST_MAX_CLIENT_REG_IN_SAME_ADDR];
-	/* list of 4-byte register data values for/from client registers */
-	/* For multi-read/write, 512(128 * 4) bytes of data available */
-
-} mddi_register_access_packet_type;
-
-typedef union GCC_PACKED {
-	mddi_video_stream_packet_type video_pkt;
-	mddi_register_access_packet_type register_pkt;
-#ifdef ENABLE_MDDI_MULTI_READ_WRITE
-	/* add 1008 byte pad to ensure 1024 byte llist struct, that can be
-	 * manipulated easily with cache */
-	uint32 alignment_pad[252];	/* 1008 bytes */
-#else
-	/* add 48 byte pad to ensure 64 byte llist struct, that can be
-	 * manipulated easily with cache */
-	uint32 alignment_pad[12];	/* 48 bytes */
-#endif
-} mddi_packet_header_type;
-
-typedef struct GCC_PACKED mddi_host_llist_struct {
-	uint16 link_controller_flags;
-	uint16 packet_header_count;
-	uint16 packet_data_count;
-	void *packet_data_pointer;
-	struct mddi_host_llist_struct *next_packet_pointer;
-	uint16 reserved;
-	mddi_packet_header_type packet_header;
-} mddi_linked_list_type;
-
-typedef struct {
-	struct completion done_comp;
-	mddi_llist_done_cb_type done_cb;
-	uint16 next_idx;
-	boolean waiting;
-	boolean in_use;
-} mddi_linked_list_notify_type;
-
-#ifdef ENABLE_MDDI_MULTI_READ_WRITE
-#define MDDI_LLIST_POOL_SIZE 0x10000
-#else
-#define MDDI_LLIST_POOL_SIZE 0x1000
-#endif
-#define MDDI_MAX_NUM_LLIST_ITEMS (MDDI_LLIST_POOL_SIZE / \
-		 sizeof(mddi_linked_list_type))
-#define UNASSIGNED_INDEX MDDI_MAX_NUM_LLIST_ITEMS
-#define MDDI_FIRST_DYNAMIC_LLIST_IDX 0
-
-/* Static llist items can be used for applications that frequently send
- * the same set of packets using the linked list interface. */
-/* Here we configure for 6 static linked list items:
- *  The 1st is used for a the adaptive backlight setting.
- *  and the remaining 5 are used for sending window adjustments for
- *  MDDI clients that need windowing info sent separate from video
- *  packets. */
-#define MDDI_NUM_STATIC_ABL_ITEMS 1
-#define MDDI_NUM_STATIC_WINDOW_ITEMS 5
-#define MDDI_NUM_STATIC_LLIST_ITEMS (MDDI_NUM_STATIC_ABL_ITEMS + \
-				MDDI_NUM_STATIC_WINDOW_ITEMS)
-#define MDDI_NUM_DYNAMIC_LLIST_ITEMS (MDDI_MAX_NUM_LLIST_ITEMS - \
-				MDDI_NUM_STATIC_LLIST_ITEMS)
-
-#define MDDI_FIRST_STATIC_LLIST_IDX  MDDI_NUM_DYNAMIC_LLIST_ITEMS
-#define MDDI_FIRST_STATIC_ABL_IDX  MDDI_FIRST_STATIC_LLIST_IDX
-#define MDDI_FIRST_STATIC_WINDOW_IDX  (MDDI_FIRST_STATIC_LLIST_IDX + \
-				MDDI_NUM_STATIC_ABL_ITEMS)
-
-/* GPIO registers */
-#define VSYNC_WAKEUP_REG          0x80
-#define GPIO_REG                  0x81
-#define GPIO_OUTPUT_REG           0x82
-#define GPIO_INTERRUPT_REG        0x83
-#define GPIO_INTERRUPT_ENABLE_REG 0x84
-#define GPIO_POLARITY_REG         0x85
-
-/* Interrupt Bits */
-#define MDDI_INT_PRI_PTR_READ       0x0001
-#define MDDI_INT_SEC_PTR_READ       0x0002
-#define MDDI_INT_REV_DATA_AVAIL     0x0004
-#define MDDI_INT_DISP_REQ           0x0008
-#define MDDI_INT_PRI_UNDERFLOW      0x0010
-#define MDDI_INT_SEC_UNDERFLOW      0x0020
-#define MDDI_INT_REV_OVERFLOW       0x0040
-#define MDDI_INT_CRC_ERROR          0x0080
-#define MDDI_INT_MDDI_IN            0x0100
-#define MDDI_INT_PRI_OVERWRITE      0x0200
-#define MDDI_INT_SEC_OVERWRITE      0x0400
-#define MDDI_INT_REV_OVERWRITE      0x0800
-#define MDDI_INT_DMA_FAILURE        0x1000
-#define MDDI_INT_LINK_ACTIVE        0x2000
-#define MDDI_INT_IN_HIBERNATION     0x4000
-#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
-#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
-#define MDDI_INT_NO_CMD_PKTS_PEND   0x20000
-#define MDDI_INT_RTD_FAILURE        0x40000
-
-#define MDDI_INT_ERROR_CONDITIONS ( \
-	MDDI_INT_PRI_UNDERFLOW | MDDI_INT_SEC_UNDERFLOW | \
-	MDDI_INT_REV_OVERFLOW | MDDI_INT_CRC_ERROR | \
-	MDDI_INT_PRI_OVERWRITE | MDDI_INT_SEC_OVERWRITE | \
-	MDDI_INT_RTD_FAILURE | \
-	MDDI_INT_REV_OVERWRITE | MDDI_INT_DMA_FAILURE)
-
-#define MDDI_INT_LINK_STATE_CHANGES ( \
-	MDDI_INT_LINK_ACTIVE | MDDI_INT_IN_HIBERNATION)
-
-/* Status Bits */
-#define MDDI_STAT_LINK_ACTIVE        0x0001
-#define MDDI_STAT_NEW_REV_PTR        0x0002
-#define MDDI_STAT_NEW_PRI_PTR        0x0004
-#define MDDI_STAT_NEW_SEC_PTR        0x0008
-#define MDDI_STAT_IN_HIBERNATION     0x0010
-#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
-#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
-#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
-#define MDDI_STAT_PENDING_REV_ENCAP  0x0100
-#define MDDI_STAT_PENDING_POWERDOWN  0x0200
-#define MDDI_STAT_RTD_MEAS_FAIL      0x0800
-#define MDDI_STAT_CLIENT_WAKEUP_REQ  0x1000
-
-/* Command Bits */
-#define MDDI_CMD_POWERDOWN           0x0100
-#define MDDI_CMD_POWERUP             0x0200
-#define MDDI_CMD_HIBERNATE           0x0300
-#define MDDI_CMD_RESET               0x0400
-#define MDDI_CMD_DISP_IGNORE         0x0501
-#define MDDI_CMD_DISP_LISTEN         0x0500
-#define MDDI_CMD_SEND_REV_ENCAP      0x0600
-#define MDDI_CMD_GET_CLIENT_CAP      0x0601
-#define MDDI_CMD_GET_CLIENT_STATUS   0x0602
-#define MDDI_CMD_SEND_RTD            0x0700
-#define MDDI_CMD_LINK_ACTIVE         0x0900
-#define MDDI_CMD_PERIODIC_REV_ENCAP  0x0A00
-#define MDDI_CMD_FW_LINK_SKEW_CAL    0x0D00
-
-extern void mddi_host_init(mddi_host_type host);
-extern void mddi_host_powerdown(mddi_host_type host);
-extern uint16 mddi_get_next_free_llist_item(mddi_host_type host, boolean wait);
-extern uint16 mddi_get_reg_read_llist_item(mddi_host_type host, boolean wait);
-extern void mddi_queue_forward_packets(uint16 first_llist_idx,
-				       uint16 last_llist_idx,
-				       boolean wait,
-				       mddi_llist_done_cb_type llist_done_cb,
-				       mddi_host_type host);
-
-extern void mddi_host_write_pix_attr_reg(uint32 value);
-extern void mddi_client_lcd_gpio_poll(uint32 poll_reg_val);
-extern void mddi_client_lcd_vsync_detected(boolean detected);
-extern void mddi_host_disable_hibernation(boolean disable);
-
-extern mddi_linked_list_type *llist_extern[];
-extern mddi_linked_list_type *llist_dma_extern[];
-extern mddi_linked_list_notify_type *llist_extern_notify[];
-extern struct timer_list mddi_host_timer;
-
-typedef struct {
-	uint16 transmitting_start_idx;
-	uint16 transmitting_end_idx;
-	uint16 waiting_start_idx;
-	uint16 waiting_end_idx;
-	uint16 reg_read_idx;
-	uint16 next_free_idx;
-	boolean reg_read_waiting;
-} mddi_llist_info_type;
-
-extern mddi_llist_info_type mddi_llist;
-
-#define MDDI_GPIO_DEFAULT_POLLING_INTERVAL 200
-typedef struct {
-	uint32 polling_reg;
-	uint32 polling_val;
-	uint32 polling_interval;
-	boolean polling_enabled;
-} mddi_gpio_info_type;
-
-uint32 mddi_get_client_id(void);
-void mddi_mhctl_remove(mddi_host_type host_idx);
-void mddi_host_timer_service(unsigned long data);
-void mddi_host_client_cnt_reset(void);
-#endif /* MDDIHOSTI_H */
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
deleted file mode 100644
index 7d6d448..0000000
--- a/drivers/video/msm/mdp.c
+++ /dev/null
@@ -1,3268 +0,0 @@
-/* drivers/video/msm_fb/mdp.c
- *
- * MSM MDP Interface (used by framebuffer core)
- *
- * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
- * Copyright (C) 2007 Google Incorporated
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/hrtimer.h>
-#include <linux/clk.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/pm_runtime.h>
-#include <linux/regulator/consumer.h>
-#include <asm/system.h>
-#include <asm/mach-types.h>
-#include <linux/semaphore.h>
-#include <linux/uaccess.h>
-#include <mach/event_timer.h>
-#include <mach/clk.h>
-#include "mdp.h"
-#include "msm_fb.h"
-#ifdef CONFIG_FB_MSM_MDP40
-#include "mdp4.h"
-#endif
-#include "mipi_dsi.h"
-
-uint32 mdp4_extn_disp;
-
-static struct clk *mdp_clk;
-static struct clk *mdp_pclk;
-static struct clk *mdp_lut_clk;
-int mdp_rev;
-int mdp_iommu_split_domain;
-u32 mdp_max_clk = 200000000;
-u64 mdp_max_bw = 2000000000;
-
-static struct platform_device *mdp_init_pdev;
-static struct regulator *footswitch, *dsi_pll_vdda, *dsi_pll_vddio;
-static unsigned int mdp_footswitch_on;
-
-struct completion mdp_ppp_comp;
-struct semaphore mdp_ppp_mutex;
-struct semaphore mdp_pipe_ctrl_mutex;
-
-unsigned long mdp_timer_duration = (HZ/20);   /* 50 msecond */
-
-boolean mdp_ppp_waiting = FALSE;
-uint32 mdp_tv_underflow_cnt;
-uint32 mdp_lcdc_underflow_cnt;
-
-boolean mdp_current_clk_on = FALSE;
-boolean mdp_is_in_isr = FALSE;
-
-struct vsync vsync_cntrl;
-
-/*
- * legacy mdp_in_processing is only for DMA2-MDDI
- * this applies to DMA2 block only
- */
-uint32 mdp_in_processing = FALSE;
-
-#ifdef CONFIG_FB_MSM_MDP40
-uint32 mdp_intr_mask = MDP4_ANY_INTR_MASK;
-#else
-uint32 mdp_intr_mask = MDP_ANY_INTR_MASK;
-#endif
-
-MDP_BLOCK_TYPE mdp_debug[MDP_MAX_BLOCK];
-
-atomic_t mdp_block_power_cnt[MDP_MAX_BLOCK];
-
-spinlock_t mdp_spin_lock;
-struct workqueue_struct *mdp_dma_wq;	/*mdp dma wq */
-struct workqueue_struct *mdp_vsync_wq;	/*mdp vsync wq */
-
-struct workqueue_struct *mdp_hist_wq;	/*mdp histogram wq */
-bool mdp_pp_initialized = FALSE;
-
-static struct workqueue_struct *mdp_pipe_ctrl_wq; /* mdp mdp pipe ctrl wq */
-static struct delayed_work mdp_pipe_ctrl_worker;
-
-static boolean mdp_suspended = FALSE;
-ulong mdp4_display_intf;
-DEFINE_MUTEX(mdp_suspend_mutex);
-
-#ifdef CONFIG_FB_MSM_MDP40
-struct mdp_dma_data dma2_data;
-struct mdp_dma_data dma_s_data;
-struct mdp_dma_data dma_e_data;
-#else
-static struct mdp_dma_data dma2_data;
-static struct mdp_dma_data dma_s_data;
-#ifndef CONFIG_FB_MSM_MDP303
-static struct mdp_dma_data dma_e_data;
-#endif
-#endif
-
-#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
-struct mdp_dma_data dma_wb_data;
-#endif
-
-static struct mdp_dma_data dma3_data;
-
-extern ktime_t mdp_dma2_last_update_time;
-
-extern uint32 mdp_dma2_update_time_in_usec;
-extern int mdp_lcd_rd_cnt_offset_slow;
-extern int mdp_lcd_rd_cnt_offset_fast;
-extern int mdp_usec_diff_threshold;
-
-extern int first_pixel_start_x;
-extern int first_pixel_start_y;
-
-#ifdef MSM_FB_ENABLE_DBGFS
-struct dentry *mdp_dir;
-#endif
-
-#if defined(CONFIG_PM) && !defined(CONFIG_HAS_EARLYSUSPEND)
-static int mdp_suspend(struct platform_device *pdev, pm_message_t state);
-#else
-#define mdp_suspend NULL
-#endif
-
-struct timeval mdp_dma2_timeval;
-struct timeval mdp_ppp_timeval;
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static struct early_suspend early_suspend;
-#endif
-
-static u32 mdp_irq;
-
-static uint32 mdp_prim_panel_type = NO_PANEL;
-#ifndef CONFIG_FB_MSM_MDP22
-
-struct list_head mdp_hist_lut_list;
-DEFINE_MUTEX(mdp_hist_lut_list_mutex);
-
-uint32_t mdp_block2base(uint32_t block)
-{
-	uint32_t base = 0x0;
-	switch (block) {
-	case MDP_BLOCK_DMA_P:
-		base = 0x90000;
-		break;
-	case MDP_BLOCK_DMA_S:
-		base = 0xA0000;
-		break;
-	case MDP_BLOCK_VG_1:
-		base = 0x20000;
-		break;
-	case MDP_BLOCK_VG_2:
-		base = 0x30000;
-		break;
-	case MDP_BLOCK_RGB_1:
-		base = 0x40000;
-		break;
-	case MDP_BLOCK_RGB_2:
-		base = 0x50000;
-		break;
-	case MDP_BLOCK_OVERLAY_0:
-		base = 0x10000;
-		break;
-	case MDP_BLOCK_OVERLAY_1:
-		base = 0x18000;
-		break;
-	case MDP_BLOCK_OVERLAY_2:
-		base = (mdp_rev >= MDP_REV_43) ? 0x88000 : 0;
-		break;
-	default:
-		break;
-	}
-	return base;
-}
-
-static uint32_t mdp_pp_block2hist_lut(uint32_t block)
-{
-	uint32_t valid = 0;
-	switch (block) {
-	case MDP_BLOCK_DMA_P:
-		valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
-		break;
-	case MDP_BLOCK_DMA_S:
-		valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
-		break;
-	case MDP_BLOCK_VG_1:
-		valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
-		break;
-	case MDP_BLOCK_VG_2:
-		valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
-		break;
-	default:
-		break;
-	}
-	return valid;
-}
-
-static void mdp_hist_lut_init_mgmt(struct mdp_hist_lut_mgmt *mgmt,
-		uint32_t block)
-{
-	mutex_init(&mgmt->lock);
-	mgmt->block = block;
-
-	mutex_lock(&mdp_hist_lut_list_mutex);
-	list_add(&mgmt->list, &mdp_hist_lut_list);
-	mutex_unlock(&mdp_hist_lut_list_mutex);
-}
-
-static int mdp_hist_lut_destroy(void)
-{
-	struct mdp_hist_lut_mgmt *temp;
-	struct list_head *pos, *q;
-
-	mutex_lock(&mdp_hist_lut_list_mutex);
-	list_for_each_safe(pos, q, &mdp_hist_lut_list) {
-		temp = list_entry(pos, struct mdp_hist_lut_mgmt, list);
-		list_del(pos);
-		kfree(temp);
-	}
-	mutex_unlock(&mdp_hist_lut_list_mutex);
-	return 0;
-}
-
-static int mdp_hist_lut_init(void)
-{
-	struct mdp_hist_lut_mgmt *temp;
-
-	if (mdp_pp_initialized)
-		return -EEXIST;
-
-	INIT_LIST_HEAD(&mdp_hist_lut_list);
-
-	if (mdp_rev >= MDP_REV_30) {
-		temp = kmalloc(sizeof(struct mdp_hist_lut_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit;
-		mdp_hist_lut_init_mgmt(temp, MDP_BLOCK_DMA_P);
-	}
-
-	if (mdp_rev >= MDP_REV_40) {
-		temp = kmalloc(sizeof(struct mdp_hist_lut_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		mdp_hist_lut_init_mgmt(temp, MDP_BLOCK_VG_1);
-
-		temp = kmalloc(sizeof(struct mdp_hist_lut_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		mdp_hist_lut_init_mgmt(temp, MDP_BLOCK_VG_2);
-	}
-
-	if (mdp_rev > MDP_REV_42) {
-		temp = kmalloc(sizeof(struct mdp_hist_lut_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		mdp_hist_lut_init_mgmt(temp, MDP_BLOCK_DMA_S);
-	}
-	return 0;
-
-exit_list:
-	mdp_hist_lut_destroy();
-exit:
-	pr_err("Failed initializing histogram LUT memory\n");
-	return -ENOMEM;
-}
-
-static int mdp_hist_lut_block2mgmt(uint32_t block,
-		struct mdp_hist_lut_mgmt **mgmt)
-{
-	struct mdp_hist_lut_mgmt *temp, *output;
-	int ret = 0;
-
-	output = NULL;
-
-	mutex_lock(&mdp_hist_lut_list_mutex);
-	list_for_each_entry(temp, &mdp_hist_lut_list, list) {
-		if (temp->block == block)
-			output = temp;
-	}
-	mutex_unlock(&mdp_hist_lut_list_mutex);
-
-	if (output == NULL)
-		ret = -EINVAL;
-	else
-		*mgmt = output;
-
-	return ret;
-}
-
-#define MDP_HIST_LUT_SIZE (256)
-static int mdp_hist_lut_write_off(struct mdp_hist_lut_data *data,
-		struct mdp_hist_lut_info *info, uint32_t offset)
-{
-	int i;
-	uint32_t element[MDP_HIST_LUT_SIZE];
-	uint32_t base = mdp_block2base(info->block);
-	uint32_t sel = info->bank_sel;
-
-
-	if (data->len != MDP_HIST_LUT_SIZE) {
-		pr_err("%s: data->len != %d", __func__, MDP_HIST_LUT_SIZE);
-		return -EINVAL;
-	}
-
-	if (copy_from_user(&element, data->data,
-				MDP_HIST_LUT_SIZE * sizeof(uint32_t))) {
-		pr_err("%s: Error copying histogram data", __func__);
-		return -ENOMEM;
-	}
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	for (i = 0; i < MDP_HIST_LUT_SIZE; i++)
-		MDP_OUTP(MDP_BASE + base + offset + (0x400*(sel)) + (4*i),
-				element[i]);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	return 0;
-}
-
-static int mdp_hist_lut_write(struct mdp_hist_lut_data *data,
-						struct mdp_hist_lut_info *info)
-{
-	int ret = 0;
-
-	if (data->block != info->block) {
-		ret = -1;
-		pr_err("%s, data/info mdp_block mismatch! %d != %d\n",
-				__func__, data->block, info->block);
-		goto error;
-	}
-
-	switch (data->block) {
-	case MDP_BLOCK_VG_1:
-	case MDP_BLOCK_VG_2:
-		ret = mdp_hist_lut_write_off(data, info, 0x3400);
-		break;
-	case MDP_BLOCK_DMA_P:
-	case MDP_BLOCK_DMA_S:
-		ret = mdp_hist_lut_write_off(data, info, 0x4800);
-		break;
-	default:
-		ret = -EINVAL;
-		goto error;
-	}
-
-error:
-	return ret;
-}
-
-#define MDP_HIST_LUT_VG_EN_MASK (0x20000)
-#define MDP_HIST_LUT_VG_EN_SHIFT (17)
-#define MDP_HIST_LUT_VG_EN_OFFSET (0x0058)
-#define MDP_HIST_LUT_VG_SEL_OFFSET (0x0064)
-static void mdp_hist_lut_commit_vg(struct mdp_hist_lut_info *info)
-{
-	uint32_t out_en, temp_en;
-	uint32_t base = mdp_block2base(info->block);
-	temp_en = (info->is_enabled) ? (1 << MDP_HIST_LUT_VG_EN_SHIFT) : 0x0;
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	out_en = inpdw(MDP_BASE + base + MDP_HIST_LUT_VG_EN_OFFSET) &
-						~MDP_HIST_LUT_VG_EN_MASK;
-	MDP_OUTP(MDP_BASE + base + MDP_HIST_LUT_VG_EN_OFFSET, out_en | temp_en);
-
-	if (info->has_sel_update)
-		MDP_OUTP(MDP_BASE + base + MDP_HIST_LUT_VG_SEL_OFFSET,
-								info->bank_sel);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-}
-
-#define MDP_HIST_LUT_DMA_EN_MASK (0x7)
-#define MDP_HIST_LUT_DMA_SEL_MASK (0x400)
-#define MDP_HIST_LUT_DMA_SEL_SHIFT (10)
-#define MDP_HIST_LUT_DMA_P_OFFSET (0x0070)
-#define MDP_HIST_LUT_DMA_S_OFFSET (0x0028)
-static void mdp_hist_lut_commit_dma(struct mdp_hist_lut_info *info)
-{
-	uint32_t out, temp, mask;
-	uint32_t base = mdp_block2base(info->block);
-	uint32_t offset = (info->block == MDP_BLOCK_DMA_P) ?
-		MDP_HIST_LUT_DMA_P_OFFSET : MDP_HIST_LUT_DMA_S_OFFSET;
-
-	mask = MDP_HIST_LUT_DMA_EN_MASK;
-	temp = (info->is_enabled) ? 0x7 : 0x0;
-
-	if (info->has_sel_update) {
-		mask |= MDP_HIST_LUT_DMA_SEL_MASK;
-		temp |=  ((info->bank_sel & 0x1) << MDP_HIST_LUT_DMA_SEL_SHIFT);
-	}
-
-	out = inpdw(MDP_BASE + base + offset) & ~mask;
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	MDP_OUTP(MDP_BASE + base + offset, out | temp);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-}
-
-static void mdp_hist_lut_commit_info(struct mdp_hist_lut_info *info)
-{
-	switch (info->block) {
-	case MDP_BLOCK_VG_1:
-	case MDP_BLOCK_VG_2:
-		mdp_hist_lut_commit_vg(info);
-		break;
-	case MDP_BLOCK_DMA_P:
-	case MDP_BLOCK_DMA_S:
-		mdp_hist_lut_commit_dma(info);
-		break;
-	default:
-		goto error;
-	}
-
-error:
-	return;
-}
-
-static void mdp_hist_lut_update_info(struct mdp_hist_lut_info *info, int ops)
-{
-	info->bank_sel = (ops & 0x8) >> 3;
-	info->is_enabled = (ops & 0x1) ? TRUE : FALSE;
-	info->has_sel_update = (ops & 0x10) ? TRUE : FALSE;
-}
-
-int mdp_hist_lut_config(struct mdp_hist_lut_data *data)
-{
-	struct mdp_hist_lut_mgmt *mgmt = NULL;
-	struct mdp_hist_lut_info info;
-	int ret = 0;
-
-	if (!mdp_pp_block2hist_lut(data->block)) {
-		ret = -ENOTTY;
-		goto error;
-	}
-
-	ret = mdp_hist_lut_block2mgmt(data->block, &mgmt);
-	if (ret)
-		goto error;
-
-	mutex_lock(&mgmt->lock);
-
-	info.block = mgmt->block;
-
-	mdp_hist_lut_update_info(&info, data->ops);
-
-	switch ((data->ops & 0x6) >> 1) {
-	case 0x1:
-		pr_info("%s: histogram LUT read not supported\n", __func__);
-		break;
-	case 0x2:
-		ret = mdp_hist_lut_write(data, &info);
-		if (ret)
-			goto error_lock;
-		break;
-	default:
-		break;
-	}
-
-	mdp_hist_lut_commit_info(&info);
-
-error_lock:
-	mutex_unlock(&mgmt->lock);
-error:
-	return ret;
-}
-
-DEFINE_MUTEX(mdp_lut_push_sem);
-static int mdp_lut_i;
-static int mdp_lut_hw_update(struct fb_cmap *cmap)
-{
-	int i;
-	u16 *c[3];
-	u16 r, g, b;
-
-	c[0] = cmap->green;
-	c[1] = cmap->blue;
-	c[2] = cmap->red;
-
-	if (cmap->start > MDP_HIST_LUT_SIZE || cmap->len > MDP_HIST_LUT_SIZE ||
-			(cmap->start + cmap->len > MDP_HIST_LUT_SIZE)) {
-		pr_err("mdp_lut_hw_update invalid arguments\n");
-		return -EINVAL;
-	}
-	for (i = 0; i < cmap->len; i++) {
-		if (copy_from_user(&r, cmap->red++, sizeof(r)) ||
-		    copy_from_user(&g, cmap->green++, sizeof(g)) ||
-		    copy_from_user(&b, cmap->blue++, sizeof(b)))
-			return -EFAULT;
-
-#ifdef CONFIG_FB_MSM_MDP40
-		MDP_OUTP(MDP_BASE + 0x94800 +
-#else
-		MDP_OUTP(MDP_BASE + 0x93800 +
-#endif
-			(0x400*mdp_lut_i) + cmap->start*4 + i*4,
-				((g & 0xff) |
-				 ((b & 0xff) << 8) |
-				 ((r & 0xff) << 16)));
-	}
-
-	return 0;
-}
-
-static int mdp_lut_push;
-static int mdp_lut_push_i;
-static int mdp_lut_update_nonlcdc(struct fb_info *info, struct fb_cmap *cmap)
-{
-	int ret;
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	mdp_clk_ctrl(1);
-	ret = mdp_lut_hw_update(cmap);
-	mdp_clk_ctrl(0);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	if (ret)
-		return ret;
-
-	mutex_lock(&mdp_lut_push_sem);
-	mdp_lut_push = 1;
-	mdp_lut_push_i = mdp_lut_i;
-	mutex_unlock(&mdp_lut_push_sem);
-
-	mdp_lut_i = (mdp_lut_i + 1)%2;
-
-	return 0;
-}
-
-static int mdp_lut_update_lcdc(struct fb_info *info, struct fb_cmap *cmap)
-{
-	int ret;
-	uint32_t out;
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	mdp_clk_ctrl(1);
-	ret = mdp_lut_hw_update(cmap);
-
-	if (ret) {
-		mdp_clk_ctrl(0);
-		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-		return ret;
-	}
-
-	/*mask off non LUT select bits*/
-	out = inpdw(MDP_BASE + 0x90070);
-	MDP_OUTP(MDP_BASE + 0x90070, (mdp_lut_i << 10) | 0x7 | out);
-	mdp_clk_ctrl(0);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-	mdp_lut_i = (mdp_lut_i + 1)%2;
-
-	return 0;
-}
-
-static void mdp_lut_enable(void)
-{
-	uint32_t out;
-	if (mdp_lut_push) {
-		mutex_lock(&mdp_lut_push_sem);
-		mdp_lut_push = 0;
-		out = inpdw(MDP_BASE + 0x90070) & ~((0x1 << 10) | 0x7);
-		MDP_OUTP(MDP_BASE + 0x90070,
-				(mdp_lut_push_i << 10) | 0x7 | out);
-		mutex_unlock(&mdp_lut_push_sem);
-	}
-}
-
-#define MDP_REV42_HIST_MAX_BIN 128
-#define MDP_REV41_HIST_MAX_BIN 32
-
-#define MDP_HIST_DATA32_R_OFF 0x0100
-#define MDP_HIST_DATA32_G_OFF 0x0200
-#define MDP_HIST_DATA32_B_OFF 0x0300
-
-#define MDP_HIST_DATA128_R_OFF 0x0400
-#define MDP_HIST_DATA128_G_OFF 0x0800
-#define MDP_HIST_DATA128_B_OFF 0x0C00
-
-#define MDP_HIST_DATA_LUMA_OFF 0x0200
-
-#define MDP_HIST_EXTRA_DATA0_OFF 0x0028
-#define MDP_HIST_EXTRA_DATA1_OFF 0x002C
-
-struct mdp_hist_mgmt *mdp_hist_mgmt_array[MDP_HIST_MGMT_MAX];
-
-void __mdp_histogram_kickoff(struct mdp_hist_mgmt *mgmt)
-{
-	char *mdp_hist_base = MDP_BASE + mgmt->base;
-	if (mgmt->mdp_is_hist_data == TRUE) {
-		MDP_OUTP(mdp_hist_base + 0x0004, mgmt->frame_cnt);
-		MDP_OUTP(mdp_hist_base, 1);
-	}
-}
-
-void __mdp_histogram_reset(struct mdp_hist_mgmt *mgmt)
-{
-	char *mdp_hist_base = MDP_BASE + mgmt->base;
-	MDP_OUTP(mdp_hist_base + 0x000C, 1);
-}
-
-static void mdp_hist_read_work(struct work_struct *data);
-
-static int mdp_hist_init_mgmt(struct mdp_hist_mgmt *mgmt, uint32_t block)
-{
-	uint32_t bins, extra, index, intr = 0, term = 0;
-	init_completion(&mgmt->mdp_hist_comp);
-	mutex_init(&mgmt->mdp_hist_mutex);
-	mutex_init(&mgmt->mdp_do_hist_mutex);
-	mgmt->block = block;
-	mgmt->base = mdp_block2base(block);
-	mgmt->mdp_is_hist_start = FALSE;
-	mgmt->mdp_is_hist_data = FALSE;
-	mgmt->mdp_is_hist_valid = FALSE;
-	mgmt->mdp_is_hist_init = FALSE;
-	mgmt->frame_cnt = 0;
-	mgmt->bit_mask = 0;
-	mgmt->num_bins = 0;
-	switch (block) {
-	case MDP_BLOCK_DMA_P:
-		term = MDP_HISTOGRAM_TERM_DMA_P;
-		intr = (mdp_rev >= MDP_REV_40) ? INTR_DMA_P_HISTOGRAM :
-								MDP_HIST_DONE;
-		bins = (mdp_rev >= MDP_REV_42) ? MDP_REV42_HIST_MAX_BIN :
-			MDP_REV41_HIST_MAX_BIN;
-		extra = 2;
-		mgmt->base += (mdp_rev >= MDP_REV_40) ? 0x5000 : 0x4000;
-		index = MDP_HIST_MGMT_DMA_P;
-		break;
-	case MDP_BLOCK_DMA_S:
-		term = MDP_HISTOGRAM_TERM_DMA_S;
-		intr = INTR_DMA_S_HISTOGRAM;
-		bins = MDP_REV42_HIST_MAX_BIN;
-		extra = 2;
-		mgmt->base += 0x5000;
-		index = MDP_HIST_MGMT_DMA_S;
-		break;
-	case MDP_BLOCK_VG_1:
-		term = MDP_HISTOGRAM_TERM_VG_1;
-		intr = INTR_VG1_HISTOGRAM;
-		bins = MDP_REV42_HIST_MAX_BIN;
-		extra = 1;
-		mgmt->base += 0x6000;
-		index = MDP_HIST_MGMT_VG_1;
-		break;
-	case MDP_BLOCK_VG_2:
-		term = MDP_HISTOGRAM_TERM_VG_2;
-		intr = INTR_VG2_HISTOGRAM;
-		bins = MDP_REV42_HIST_MAX_BIN;
-		extra = 1;
-		mgmt->base += 0x6000;
-		index = MDP_HIST_MGMT_VG_2;
-		break;
-	default:
-		term = MDP_HISTOGRAM_TERM_DMA_P;
-		intr = (mdp_rev >= MDP_REV_40) ? INTR_DMA_P_HISTOGRAM :
-								MDP_HIST_DONE;
-		bins = (mdp_rev >= MDP_REV_42) ? MDP_REV42_HIST_MAX_BIN :
-			MDP_REV41_HIST_MAX_BIN;
-		extra = 2;
-		mgmt->base += (mdp_rev >= MDP_REV_40) ? 0x5000 : 0x4000;
-		index = MDP_HIST_MGMT_DMA_P;
-	}
-	mgmt->irq_term = term;
-	mgmt->intr = intr;
-
-	mgmt->c0 = kmalloc(bins * sizeof(uint32_t), GFP_KERNEL);
-	if (mgmt->c0 == NULL)
-		goto error;
-
-	mgmt->c1 = kmalloc(bins * sizeof(uint32_t), GFP_KERNEL);
-	if (mgmt->c1 == NULL)
-		goto error_1;
-
-	mgmt->c2 = kmalloc(bins * sizeof(uint32_t), GFP_KERNEL);
-	if (mgmt->c2 == NULL)
-		goto error_2;
-
-	mgmt->extra_info = kmalloc(extra * sizeof(uint32_t), GFP_KERNEL);
-	if (mgmt->extra_info == NULL)
-		goto error_extra;
-
-	INIT_WORK(&mgmt->mdp_histogram_worker, mdp_hist_read_work);
-	mgmt->hist = NULL;
-
-	mdp_hist_mgmt_array[index] = mgmt;
-	return 0;
-
-error_extra:
-	kfree(mgmt->c2);
-error_2:
-	kfree(mgmt->c1);
-error_1:
-	kfree(mgmt->c0);
-error:
-	return -ENOMEM;
-}
-
-static void mdp_hist_del_mgmt(struct mdp_hist_mgmt *mgmt)
-{
-	kfree(mgmt->extra_info);
-	kfree(mgmt->c2);
-	kfree(mgmt->c1);
-	kfree(mgmt->c0);
-}
-
-static int mdp_histogram_destroy(void)
-{
-	struct mdp_hist_mgmt *temp;
-	int i;
-
-	for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
-		temp = mdp_hist_mgmt_array[i];
-		if (!temp)
-			continue;
-		mdp_hist_del_mgmt(temp);
-		kfree(temp);
-		mdp_hist_mgmt_array[i] = NULL;
-	}
-	return 0;
-}
-
-static int mdp_histogram_init(void)
-{
-	struct mdp_hist_mgmt *temp;
-	int i, ret;
-
-	if (mdp_pp_initialized)
-		return -EEXIST;
-
-	mdp_hist_wq = alloc_workqueue("mdp_hist_wq",
-					WQ_NON_REENTRANT | WQ_UNBOUND, 0);
-
-	for (i = 0; i < MDP_HIST_MGMT_MAX; i++)
-		mdp_hist_mgmt_array[i] = NULL;
-
-	if (mdp_rev >= MDP_REV_30) {
-		temp = kmalloc(sizeof(struct mdp_hist_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit;
-		ret = mdp_hist_init_mgmt(temp, MDP_BLOCK_DMA_P);
-		if (ret) {
-			kfree(temp);
-			goto exit;
-		}
-	}
-
-	if (mdp_rev >= MDP_REV_40) {
-		temp = kmalloc(sizeof(struct mdp_hist_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		ret = mdp_hist_init_mgmt(temp, MDP_BLOCK_VG_1);
-		if (ret)
-			goto exit_list;
-
-		temp = kmalloc(sizeof(struct mdp_hist_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		ret = mdp_hist_init_mgmt(temp, MDP_BLOCK_VG_2);
-		if (ret)
-			goto exit_list;
-	}
-
-	if (mdp_rev >= MDP_REV_42) {
-		temp = kmalloc(sizeof(struct mdp_hist_mgmt), GFP_KERNEL);
-		if (!temp)
-			goto exit_list;
-		ret = mdp_hist_init_mgmt(temp, MDP_BLOCK_DMA_S);
-		if (ret)
-			goto exit_list;
-	}
-
-	return 0;
-
-exit_list:
-	mdp_histogram_destroy();
-exit:
-	return -ENOMEM;
-}
-
-int mdp_histogram_block2mgmt(uint32_t block, struct mdp_hist_mgmt **mgmt)
-{
-	struct mdp_hist_mgmt *temp, *output;
-	int i, ret = 0;
-
-	output = NULL;
-
-	for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
-		temp = mdp_hist_mgmt_array[i];
-		if (!temp)
-			continue;
-
-		if (temp->block == block) {
-			output = temp;
-			break;
-		}
-	}
-
-	if (output == NULL)
-		ret = -EINVAL;
-	else
-		*mgmt = output;
-
-	return ret;
-}
-
-static int mdp_histogram_enable(struct mdp_hist_mgmt *mgmt)
-{
-	uint32_t base;
-	unsigned long flag;
-	if (mgmt->mdp_is_hist_data == TRUE) {
-		pr_err("%s histogram already started\n", __func__);
-		return -EINVAL;
-	}
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	base = (uint32_t) (MDP_BASE + mgmt->base);
-	/*First make sure that device is not collecting histogram*/
-	mgmt->mdp_is_hist_data = FALSE;
-	mgmt->mdp_is_hist_valid = FALSE;
-	mgmt->mdp_is_hist_init = FALSE;
-	spin_lock_irqsave(&mdp_spin_lock, flag);
-	outp32(MDP_INTR_CLEAR, mgmt->intr);
-	mdp_intr_mask &= ~mgmt->intr;
-	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-	MDP_OUTP(base + 0x001C, 0);
-	MDP_OUTP(base + 0x0018, INTR_HIST_DONE | INTR_HIST_RESET_SEQ_DONE);
-	MDP_OUTP(base + 0x0024, 0);
-	spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-	cancel_work_sync(&mgmt->mdp_histogram_worker);
-	mutex_lock(&mgmt->mdp_hist_mutex);
-
-	/*Then initialize histogram*/
-	INIT_COMPLETION(mgmt->mdp_hist_comp);
-
-	spin_lock_irqsave(&mdp_spin_lock, flag);
-	MDP_OUTP(base + 0x0018, INTR_HIST_DONE | INTR_HIST_RESET_SEQ_DONE);
-	MDP_OUTP(base + 0x0010, 1);
-	MDP_OUTP(base + 0x001C, INTR_HIST_DONE | INTR_HIST_RESET_SEQ_DONE);
-
-	outp32(MDP_INTR_CLEAR, mgmt->intr);
-	mdp_intr_mask |= mgmt->intr;
-	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-	mdp_enable_irq(mgmt->irq_term);
-	spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-	MDP_OUTP(base + 0x0004, mgmt->frame_cnt);
-	if (mgmt->block != MDP_BLOCK_VG_1 && mgmt->block != MDP_BLOCK_VG_2)
-		MDP_OUTP(base + 0x0008, mgmt->bit_mask);
-	mgmt->mdp_is_hist_data = TRUE;
-	mgmt->mdp_is_hist_valid = TRUE;
-	mgmt->mdp_is_hist_init = FALSE;
-	__mdp_histogram_reset(mgmt);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-	return 0;
-}
-
-static int mdp_histogram_disable(struct mdp_hist_mgmt *mgmt)
-{
-	uint32_t base, status;
-	unsigned long flag;
-	if (mgmt->mdp_is_hist_data == FALSE) {
-		pr_err("%s histogram already stopped\n", __func__);
-		return -EINVAL;
-	}
-
-	mgmt->mdp_is_hist_data = FALSE;
-	mgmt->mdp_is_hist_valid = FALSE;
-	mgmt->mdp_is_hist_init = FALSE;
-
-	base = (uint32_t) (MDP_BASE + mgmt->base);
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	spin_lock_irqsave(&mdp_spin_lock, flag);
-	outp32(MDP_INTR_CLEAR, mgmt->intr);
-	mdp_intr_mask &= ~mgmt->intr;
-	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-	mdp_disable_irq_nosync(mgmt->irq_term);
-	spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-	if (mdp_rev >= MDP_REV_42)
-		MDP_OUTP(base + 0x0020, 1);
-	status = inpdw(base + 0x001C);
-	status &= ~(INTR_HIST_DONE | INTR_HIST_RESET_SEQ_DONE);
-	MDP_OUTP(base + 0x001C, status);
-
-	MDP_OUTP(base + 0x0018, INTR_HIST_DONE | INTR_HIST_RESET_SEQ_DONE);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	if (mgmt->hist != NULL) {
-		mgmt->hist = NULL;
-		complete(&mgmt->mdp_hist_comp);
-	}
-
-	return 0;
-}
-
-/*call when spanning mgmt_array only*/
-int _mdp_histogram_ctrl(boolean en, struct mdp_hist_mgmt *mgmt)
-{
-	int ret = 0;
-
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (mgmt->mdp_is_hist_start == TRUE) {
-		if (en)
-			ret = mdp_histogram_enable(mgmt);
-		else
-			ret = mdp_histogram_disable(mgmt);
-	}
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-
-	if (en == false)
-		cancel_work_sync(&mgmt->mdp_histogram_worker);
-
-	return ret;
-}
-
-int mdp_histogram_ctrl(boolean en, uint32_t block)
-{
-	struct mdp_hist_mgmt *mgmt = NULL;
-	int ret = 0;
-
-	ret = mdp_histogram_block2mgmt(block, &mgmt);
-	if (ret)
-		goto error;
-
-	ret = _mdp_histogram_ctrl(en, mgmt);
-error:
-	return ret;
-}
-
-int mdp_histogram_ctrl_all(boolean en)
-{
-	struct mdp_hist_mgmt *temp;
-	int i, ret = 0, ret_temp = 0;
-
-	for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
-		temp = mdp_hist_mgmt_array[i];
-		if (!temp)
-			continue;
-
-		ret_temp = _mdp_histogram_ctrl(en, temp);
-		if (ret_temp)
-			ret = ret_temp;
-	}
-	return ret;
-}
-
-int mdp_histogram_start(struct mdp_histogram_start_req *req)
-{
-	struct mdp_hist_mgmt *mgmt = NULL;
-	int ret;
-
-	ret = mdp_histogram_block2mgmt(req->block, &mgmt);
-	if (ret) {
-		ret = -ENOTTY;
-		goto error;
-	}
-
-	mutex_lock(&mgmt->mdp_do_hist_mutex);
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (mgmt->mdp_is_hist_start == TRUE) {
-		pr_err("%s histogram already started\n", __func__);
-		ret = -EPERM;
-		goto error_lock;
-	}
-
-	mgmt->block = req->block;
-	mgmt->frame_cnt = req->frame_cnt;
-	mgmt->bit_mask = req->bit_mask;
-	mgmt->num_bins = req->num_bins;
-
-	ret = mdp_histogram_enable(mgmt);
-
-	mgmt->mdp_is_hist_start = TRUE;
-
-error_lock:
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-	mutex_unlock(&mgmt->mdp_do_hist_mutex);
-error:
-	return ret;
-}
-
-int mdp_histogram_stop(struct fb_info *info, uint32_t block)
-{
-	struct msm_fb_data_type *mfd = (struct msm_fb_data_type *) info->par;
-	struct mdp_hist_mgmt *mgmt = NULL;
-	int ret;
-
-	ret = mdp_histogram_block2mgmt(block, &mgmt);
-	if (ret) {
-		ret = -ENOTTY;
-		goto error;
-	}
-
-	mutex_lock(&mgmt->mdp_do_hist_mutex);
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (mgmt->mdp_is_hist_start == FALSE) {
-		pr_err("%s histogram already stopped\n", __func__);
-		ret = -EPERM;
-		goto error_lock;
-	}
-
-	mgmt->mdp_is_hist_start = FALSE;
-
-	if (!mfd->panel_power_on) {
-		mgmt->mdp_is_hist_data = FALSE;
-		if (mgmt->hist != NULL) {
-			mgmt->hist = NULL;
-			complete(&mgmt->mdp_hist_comp);
-		}
-		ret = -EINVAL;
-		goto error_lock;
-	}
-
-	ret = mdp_histogram_disable(mgmt);
-
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-	cancel_work_sync(&mgmt->mdp_histogram_worker);
-	mutex_unlock(&mgmt->mdp_do_hist_mutex);
-	return ret;
-
-error_lock:
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-	mutex_unlock(&mgmt->mdp_do_hist_mutex);
-error:
-	return ret;
-}
-
-/*call from within mdp_hist_mutex context*/
-static int _mdp_histogram_read_dma_data(struct mdp_hist_mgmt *mgmt)
-{
-	char *mdp_hist_base;
-	uint32_t r_data_offset, g_data_offset, b_data_offset;
-	int i, ret = 0;
-
-	mdp_hist_base = MDP_BASE + mgmt->base;
-
-	r_data_offset = (32 == mgmt->num_bins) ? MDP_HIST_DATA32_R_OFF :
-		MDP_HIST_DATA128_R_OFF;
-	g_data_offset = (32 == mgmt->num_bins) ? MDP_HIST_DATA32_G_OFF :
-		MDP_HIST_DATA128_G_OFF;
-	b_data_offset = (32 == mgmt->num_bins) ? MDP_HIST_DATA32_B_OFF :
-		MDP_HIST_DATA128_B_OFF;
-
-	if (mgmt->c0 == NULL || mgmt->c1 == NULL || mgmt->c2 == NULL) {
-		ret = -ENOMEM;
-		goto hist_err;
-	}
-
-	if (!mgmt->hist) {
-		pr_err("%s: mgmt->hist not set, mgmt->hist = 0x%08x",
-		__func__, (uint32_t) mgmt->hist);
-		return -EINVAL;
-	}
-
-	if (mgmt->hist->bin_cnt != mgmt->num_bins) {
-		pr_err("%s, bins config = %d, bin requested = %d", __func__,
-					mgmt->num_bins, mgmt->hist->bin_cnt);
-		return -EINVAL;
-	}
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	mdp_clk_ctrl(1);
-	for (i = 0; i < mgmt->num_bins; i++) {
-		mgmt->c0[i] = inpdw(mdp_hist_base + r_data_offset + (4*i));
-		mgmt->c1[i] = inpdw(mdp_hist_base + g_data_offset + (4*i));
-		mgmt->c2[i] = inpdw(mdp_hist_base + b_data_offset + (4*i));
-	}
-
-	if (mdp_rev >= MDP_REV_42) {
-		if (mgmt->extra_info) {
-			mgmt->extra_info[0] = inpdw(mdp_hist_base +
-					MDP_HIST_EXTRA_DATA0_OFF);
-			mgmt->extra_info[1] = inpdw(mdp_hist_base +
-					MDP_HIST_EXTRA_DATA0_OFF + 4);
-		} else
-			ret = -ENOMEM;
-	}
-	mdp_clk_ctrl(0);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	if (!ret)
-		return ret;
-
-hist_err:
-	pr_err("%s: invalid hist buffer\n", __func__);
-	return ret;
-}
-
-/*call from within mdp_hist_mutex context*/
-static int _mdp_histogram_read_vg_data(struct mdp_hist_mgmt *mgmt)
-{
-	char *mdp_hist_base;
-	int i, ret = 0;
-
-	mdp_hist_base = MDP_BASE + mgmt->base;
-
-	if (mgmt->c0 == NULL) {
-		ret = -ENOMEM;
-		goto hist_err;
-	}
-
-	if (!mgmt->hist) {
-		pr_err("%s: mgmt->hist not set", __func__);
-		return -EINVAL;
-	}
-
-	if (mgmt->hist->bin_cnt != mgmt->num_bins) {
-		pr_err("%s, bins config = %d, bin requested = %d", __func__,
-					mgmt->num_bins, mgmt->hist->bin_cnt);
-		return -EINVAL;
-	}
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	mdp_clk_ctrl(1);
-	for (i = 0; i < mgmt->num_bins; i++)
-		mgmt->c0[i] = inpdw(mdp_hist_base + MDP_HIST_DATA_LUMA_OFF +
-									(4*i));
-
-	if (mdp_rev >= MDP_REV_42) {
-		if (mgmt->extra_info) {
-			mgmt->extra_info[0] = inpdw(mdp_hist_base +
-						MDP_HIST_EXTRA_DATA0_OFF);
-		} else
-			ret = -ENOMEM;
-	}
-	mdp_clk_ctrl(0);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	if (!ret)
-		return ret;
-
-hist_err:
-	pr_err("%s: invalid hist buffer\n", __func__);
-	return ret;
-}
-
-static void mdp_hist_read_work(struct work_struct *data)
-{
-	struct mdp_hist_mgmt *mgmt = container_of(data, struct mdp_hist_mgmt,
-							mdp_histogram_worker);
-	int ret = 0;
-	bool hist_ready;
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (mgmt->mdp_is_hist_data == FALSE) {
-		pr_debug("%s, Histogram disabled before read.\n", __func__);
-		ret = -EINVAL;
-		goto error;
-	}
-
-	if (mgmt->hist == NULL) {
-		if ((mgmt->mdp_is_hist_init == TRUE) &&
-			((!completion_done(&mgmt->mdp_hist_comp)) &&
-			waitqueue_active(&mgmt->mdp_hist_comp.wait)))
-			pr_err("mgmt->hist invalid NULL\n");
-		ret = -EINVAL;
-	}
-	hist_ready = (mgmt->mdp_is_hist_init && mgmt->mdp_is_hist_valid);
-
-	if (!ret && hist_ready) {
-		switch (mgmt->block) {
-		case MDP_BLOCK_DMA_P:
-		case MDP_BLOCK_DMA_S:
-			ret = _mdp_histogram_read_dma_data(mgmt);
-			break;
-		case MDP_BLOCK_VG_1:
-		case MDP_BLOCK_VG_2:
-			ret = _mdp_histogram_read_vg_data(mgmt);
-			break;
-		default:
-			pr_err("%s, invalid MDP block = %d\n", __func__,
-								mgmt->block);
-			ret = -EINVAL;
-			goto error;
-		}
-	}
-	/*
-	 * if read was triggered by an underrun or failed copying,
-	 * don't wake up readers
-	 */
-	if (!ret && hist_ready) {
-		mgmt->hist = NULL;
-		if (waitqueue_active(&mgmt->mdp_hist_comp.wait))
-			complete(&mgmt->mdp_hist_comp);
-	}
-
-	if (mgmt->mdp_is_hist_valid == FALSE)
-			mgmt->mdp_is_hist_valid = TRUE;
-	if (mgmt->mdp_is_hist_init == FALSE)
-			mgmt->mdp_is_hist_init = TRUE;
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	if (!ret && hist_ready)
-		__mdp_histogram_kickoff(mgmt);
-	else
-		__mdp_histogram_reset(mgmt);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-error:
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-}
-
-/*call from within mdp_hist_mutex*/
-static int _mdp_copy_hist_data(struct mdp_histogram_data *hist,
-						struct mdp_hist_mgmt *mgmt)
-{
-	int ret;
-
-	if (hist->c0) {
-		ret = copy_to_user(hist->c0, mgmt->c0,
-		sizeof(uint32_t) * (hist->bin_cnt));
-		if (ret)
-			goto err;
-	}
-	if (hist->c1) {
-		ret = copy_to_user(hist->c1, mgmt->c1,
-		sizeof(uint32_t) * (hist->bin_cnt));
-		if (ret)
-			goto err;
-	}
-	if (hist->c2) {
-		ret = copy_to_user(hist->c2, mgmt->c2,
-		sizeof(uint32_t) * (hist->bin_cnt));
-		if (ret)
-			goto err;
-	}
-	if (hist->extra_info) {
-		ret = copy_to_user(hist->extra_info, mgmt->extra_info,
-		sizeof(uint32_t) * ((hist->block > MDP_BLOCK_VG_2) ? 2 : 1));
-		if (ret)
-			goto err;
-	}
-err:
-	return ret;
-}
-
-#define MDP_HISTOGRAM_TIMEOUT_MS	84 /*5 Frames*/
-static int mdp_do_histogram(struct fb_info *info,
-					struct mdp_histogram_data *hist)
-{
-	struct mdp_hist_mgmt *mgmt = NULL;
-	int ret = 0;
-	unsigned long timeout = (MDP_HISTOGRAM_TIMEOUT_MS * HZ) / 1000;
-
-	ret = mdp_histogram_block2mgmt(hist->block, &mgmt);
-	if (ret) {
-		pr_info("%s - %d", __func__, __LINE__);
-		ret = -EINVAL;
-		return ret;
-	}
-
-	mutex_lock(&mgmt->mdp_do_hist_mutex);
-	if (!mgmt->frame_cnt || (mgmt->num_bins == 0)) {
-		pr_info("%s - frame_cnt = %d, num_bins = %d", __func__,
-		mgmt->frame_cnt, mgmt->num_bins);
-		ret = -EINVAL;
-		goto error;
-}
-	if ((mdp_rev <= MDP_REV_41 && hist->bin_cnt > MDP_REV41_HIST_MAX_BIN)
-		|| (mdp_rev == MDP_REV_42 &&
-				hist->bin_cnt > MDP_REV42_HIST_MAX_BIN)) {
-		pr_info("%s - mdp_rev = %d, num_bins = %d", __func__, mdp_rev,
-								hist->bin_cnt);
-		ret = -EINVAL;
-		goto error;
-}
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (!mgmt->mdp_is_hist_data) {
-		pr_info("%s - hist_data = false!", __func__);
-		ret = -EINVAL;
-		goto error_lock;
-	}
-
-	if (!mgmt->mdp_is_hist_start) {
-		pr_err("%s histogram not started\n", __func__);
-		ret = -EPERM;
-		goto error_lock;
-	}
-
-	if (mgmt->hist != NULL) {
-		pr_err("%s; histogram attempted to be read twice\n", __func__);
-		ret = -EPERM;
-		goto error_lock;
-	}
-	INIT_COMPLETION(mgmt->mdp_hist_comp);
-	mgmt->hist = hist;
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-
-	ret = wait_for_completion_killable_timeout(&mgmt->mdp_hist_comp,
-								timeout);
-	if (ret <= 0) {
-		if (!ret) {
-			mgmt->hist = NULL;
-			ret = -ETIMEDOUT;
-			pr_debug("%s: bin collection timedout", __func__);
-		} else {
-			mgmt->hist = NULL;
-			pr_debug("%s: bin collection interrupted", __func__);
-		}
-		goto error;
-	}
-
-	mutex_lock(&mgmt->mdp_hist_mutex);
-	if (mgmt->mdp_is_hist_data && mgmt->mdp_is_hist_init)
-		ret =  _mdp_copy_hist_data(hist, mgmt);
-	else
-		ret = -ENODATA;
-error_lock:
-	mutex_unlock(&mgmt->mdp_hist_mutex);
-error:
-	mutex_unlock(&mgmt->mdp_do_hist_mutex);
-	return ret;
-}
-#endif
-
-#ifdef CONFIG_FB_MSM_MDP303
-/* vsync_isr_handler: Called from isr context*/
-static void vsync_isr_handler(void)
-{
-	vsync_cntrl.vsync_time = ktime_get();
-}
-#endif
-
-ssize_t mdp_dma_show_event(struct device *dev,
-		struct device_attribute *attr, char *buf)
-{
-	ssize_t ret = 0;
-
-	if (atomic_read(&vsync_cntrl.suspend) > 0 ||
-		atomic_read(&vsync_cntrl.vsync_resume) == 0)
-		return 0;
-
-	INIT_COMPLETION(vsync_cntrl.vsync_wait);
-
-	wait_for_completion(&vsync_cntrl.vsync_wait);
-	ret = snprintf(buf, PAGE_SIZE, "VSYNC=%llu",
-			ktime_to_ns(vsync_cntrl.vsync_time));
-	buf[strlen(buf) + 1] = '\0';
-	return ret;
-}
-
-/* Returns < 0 on error, 0 on timeout, or > 0 on successful wait */
-int mdp_ppp_pipe_wait(void)
-{
-	int ret = 1;
-	boolean wait;
-	unsigned long flag;
-
-	/* wait 5 seconds for the operation to complete before declaring
-	the MDP hung */
-	spin_lock_irqsave(&mdp_spin_lock, flag);
-	wait = mdp_ppp_waiting;
-	spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-	if (wait == TRUE) {
-		ret = wait_for_completion_interruptible_timeout(&mdp_ppp_comp,
-								5 * HZ);
-		if (!ret)
-			printk(KERN_ERR "%s: Timed out waiting for the MDP.\n",
-				__func__);
-	}
-
-	return ret;
-}
-
-#define MAX_VSYNC_GAP		4
-#define DEFAULT_FRAME_RATE	60
-
-u32 mdp_get_panel_framerate(struct msm_fb_data_type *mfd)
-{
-	u32 frame_rate = 0, pixel_rate = 0, total_pixel;
-	struct msm_panel_info *panel_info = &mfd->panel_info;
-
-	pixel_rate =
-		(panel_info->type == MIPI_CMD_PANEL ||
-		 panel_info->type == MIPI_VIDEO_PANEL) ?
-		panel_info->mipi.dsi_pclk_rate :
-		panel_info->clk_rate;
-
-	if (!pixel_rate)
-		pr_warn("%s pixel rate is zero\n", __func__);
-
-	total_pixel =
-		(panel_info->lcdc.h_back_porch +
-		 panel_info->lcdc.h_front_porch +
-		 panel_info->lcdc.h_pulse_width +
-		 panel_info->xres) *
-		(panel_info->lcdc.v_back_porch +
-		 panel_info->lcdc.v_front_porch +
-		 panel_info->lcdc.v_pulse_width +
-		 panel_info->yres);
-
-	if (total_pixel)
-		frame_rate = pixel_rate / total_pixel;
-	else
-		pr_warn("%s total pixels are zero\n", __func__);
-
-	if (mfd->dest == DISPLAY_LCD) {
-		if (panel_info->type == MDDI_PANEL && panel_info->mddi.is_type1)
-			frame_rate = panel_info->lcd.refx100 / (100 * 2);
-		else if (panel_info->type != MIPI_CMD_PANEL)
-			frame_rate = panel_info->lcd.refx100 / 100;
-	}
-
-	if (frame_rate == 0) {
-		frame_rate = DEFAULT_FRAME_RATE;
-		pr_warn("%s frame rate=%d is default\n", __func__, frame_rate);
-	}
-	pr_debug("%s frame rate=%d total_pixel=%d, pixel_rate=%d\n", __func__,
-		frame_rate, total_pixel, pixel_rate);
-
-	return frame_rate;
-}
-
-static int mdp_diff_to_next_vsync(ktime_t cur_time,
-			ktime_t last_vsync, u32 vsync_period)
-{
-	int diff_from_last, diff_to_next;
-	/*
-	 * Get interval beween last vsync and current time
-	 * Current time = CPU programming MDP for next Vsync
-	 */
-	diff_from_last =
-		(ktime_to_us(ktime_sub(cur_time, last_vsync)));
-	diff_from_last /= USEC_PER_MSEC;
-	/*
-	 * If the last Vsync occurred too long ago, skip programming
-	 * the timer
-	 */
-	if (diff_from_last < (vsync_period * MAX_VSYNC_GAP)) {
-		if (diff_from_last > vsync_period)
-			diff_to_next =
-				(diff_from_last - vsync_period) % vsync_period;
-		else
-			diff_to_next = vsync_period - diff_from_last;
-	} else {
-		/* mark it out of range */
-		diff_to_next = vsync_period + 1;
-	}
-	return diff_to_next;
-}
-
-void mdp_update_pm(struct msm_fb_data_type *mfd, ktime_t pre_vsync)
-{
-	u32 vsync_period;
-	int diff_to_next;
-	ktime_t cur_time, wakeup_time;
-
-	if (!mfd->cpu_pm_hdl)
-		return;
-	vsync_period = mfd->panel_info.frame_interval;
-	cur_time = ktime_get();
-	diff_to_next = mdp_diff_to_next_vsync(cur_time,
-					      pre_vsync,
-					      vsync_period);
-	if (diff_to_next > vsync_period)
-		return;
-	pr_debug("%s cur_time %d, pre_vsync %d, to_next %d\n",
-		 __func__,
-		 (int)ktime_to_ms(cur_time),
-		 (int)ktime_to_ms(pre_vsync),
-		 diff_to_next);
-	wakeup_time = ktime_add_ns(cur_time, diff_to_next * NSEC_PER_MSEC);
-	activate_event_timer(mfd->cpu_pm_hdl, wakeup_time);
-}
-
-static DEFINE_SPINLOCK(mdp_lock);
-static int mdp_irq_mask;
-static int mdp_irq_enabled;
-
-/*
- * mdp_enable_irq: can not be called from isr
- */
-void mdp_enable_irq(uint32 term)
-{
-	unsigned long irq_flags;
-
-	spin_lock_irqsave(&mdp_lock, irq_flags);
-	if (mdp_irq_mask & term) {
-		printk(KERN_ERR "%s: MDP IRQ term-0x%x is already set, mask=%x irq=%d\n",
-				__func__, term, mdp_irq_mask, mdp_irq_enabled);
-	} else {
-		mdp_irq_mask |= term;
-		if (mdp_irq_mask && !mdp_irq_enabled) {
-			mdp_irq_enabled = 1;
-			enable_irq(mdp_irq);
-		}
-	}
-	spin_unlock_irqrestore(&mdp_lock, irq_flags);
-}
-
-/*
- * mdp_disable_irq: can not be called from isr
- */
-void mdp_disable_irq(uint32 term)
-{
-	unsigned long irq_flags;
-
-	spin_lock_irqsave(&mdp_lock, irq_flags);
-	if (!(mdp_irq_mask & term)) {
-		printk(KERN_ERR "%s: MDP IRQ term-0x%x is NOT set, mask=%x irq=%d\n",
-				__func__, term, mdp_irq_mask, mdp_irq_enabled);
-	} else {
-		mdp_irq_mask &= ~term;
-		if (!mdp_irq_mask && mdp_irq_enabled) {
-			mdp_irq_enabled = 0;
-			disable_irq(mdp_irq);
-		}
-	}
-	spin_unlock_irqrestore(&mdp_lock, irq_flags);
-}
-
-void mdp_disable_irq_nosync(uint32 term)
-{
-	spin_lock(&mdp_lock);
-	if (!(mdp_irq_mask & term)) {
-		printk(KERN_ERR "%s: MDP IRQ term-0x%x is NOT set, mask=%x irq=%d\n",
-				__func__, term, mdp_irq_mask, mdp_irq_enabled);
-	} else {
-		mdp_irq_mask &= ~term;
-		if (!mdp_irq_mask && mdp_irq_enabled) {
-			mdp_irq_enabled = 0;
-			disable_irq_nosync(mdp_irq);
-		}
-	}
-	spin_unlock(&mdp_lock);
-}
-
-void mdp_pipe_kickoff(uint32 term, struct msm_fb_data_type *mfd)
-{
-	unsigned long flag;
-	/* complete all the writes before starting */
-	wmb();
-
-	/* kick off PPP engine */
-	if (term == MDP_PPP_TERM) {
-		if (mdp_debug[MDP_PPP_BLOCK])
-			jiffies_to_timeval(jiffies, &mdp_ppp_timeval);
-
-		/* let's turn on PPP block */
-		mdp_pipe_ctrl(MDP_PPP_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-
-		mdp_enable_irq(term);
-		INIT_COMPLETION(mdp_ppp_comp);
-		spin_lock_irqsave(&mdp_spin_lock, flag);
-		mdp_ppp_waiting = TRUE;
-		spin_unlock_irqrestore(&mdp_spin_lock, flag);
-		outpdw(MDP_BASE + 0x30, 0x1000);
-		wait_for_completion_killable(&mdp_ppp_comp);
-		mdp_disable_irq(term);
-
-		if (mdp_debug[MDP_PPP_BLOCK]) {
-			struct timeval now;
-
-			jiffies_to_timeval(jiffies, &now);
-			mdp_ppp_timeval.tv_usec =
-			    now.tv_usec - mdp_ppp_timeval.tv_usec;
-			MSM_FB_DEBUG("MDP-PPP: %d\n",
-				    (int)mdp_ppp_timeval.tv_usec);
-		}
-	} else if (term == MDP_DMA2_TERM) {
-		if (mdp_debug[MDP_DMA2_BLOCK]) {
-			MSM_FB_DEBUG("MDP-DMA2: %d\n",
-				    (int)mdp_dma2_timeval.tv_usec);
-			jiffies_to_timeval(jiffies, &mdp_dma2_timeval);
-		}
-		/* DMA update timestamp */
-		mdp_dma2_last_update_time = ktime_get_real();
-		/* let's turn on DMA2 block */
-#ifdef CONFIG_FB_MSM_MDP22
-		outpdw(MDP_CMD_DEBUG_ACCESS_BASE + 0x0044, 0x0);/* start DMA */
-#else
-		mdp_lut_enable();
-
-#ifdef CONFIG_FB_MSM_MDP40
-		outpdw(MDP_BASE + 0x000c, 0x0);	/* start DMA */
-#else
-		outpdw(MDP_BASE + 0x0044, 0x0);	/* start DMA */
-
-#ifdef CONFIG_FB_MSM_MDP303
-
-#ifdef CONFIG_FB_MSM_MIPI_DSI
-		mipi_dsi_cmd_mdp_start();
-#endif
-
-#endif
-
-#endif
-#endif
-#ifdef CONFIG_FB_MSM_MDP40
-	} else if (term == MDP_DMA_S_TERM) {
-		mdp_pipe_ctrl(MDP_DMA_S_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x0010, 0x0);	/* start DMA */
-	} else if (term == MDP_DMA_E_TERM) {
-		mdp_pipe_ctrl(MDP_DMA_E_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x0014, 0x0);	/* start DMA */
-	} else if (term == MDP_OVERLAY0_TERM) {
-		mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x0004, 0);
-	} else if (term == MDP_OVERLAY1_TERM) {
-		mdp_pipe_ctrl(MDP_OVERLAY1_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x0008, 0);
-	} else if (term == MDP_OVERLAY2_TERM) {
-		mdp_pipe_ctrl(MDP_OVERLAY2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x00D0, 0);
-	}
-#else
-	} else if (term == MDP_DMA_S_TERM) {
-		mdp_pipe_ctrl(MDP_DMA_S_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x0048, 0x0);	/* start DMA */
-	} else if (term == MDP_DMA_E_TERM) {
-		mdp_pipe_ctrl(MDP_DMA_E_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		outpdw(MDP_BASE + 0x004C, 0x0);
-	}
-#endif
-}
-
-static struct platform_device *pdev_list[MSM_FB_MAX_DEV_LIST];
-static int pdev_list_cnt;
-
-static void mdp_pipe_ctrl_workqueue_handler(struct work_struct *work)
-{
-	mdp_pipe_ctrl(MDP_MASTER_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-}
-
-static int mdp_clk_rate;
-
-#ifdef CONFIG_FB_MSM_NO_MDP_PIPE_CTRL
-
-/*
- * mdp_clk_disable_unprepare(void) called from thread context
- */
-static void mdp_clk_disable_unprepare(void)
-{
-	mb();
-	vsync_clk_disable_unprepare();
-
-	if (mdp_clk != NULL)
-		clk_disable_unprepare(mdp_clk);
-
-	if (mdp_pclk != NULL)
-		clk_disable_unprepare(mdp_pclk);
-
-	if (mdp_lut_clk != NULL)
-		clk_disable_unprepare(mdp_lut_clk);
-}
-
-/*
- * mdp_clk_prepare_enable(void) called from thread context
- */
-static void mdp_clk_prepare_enable(void)
-{
-	if (mdp_clk != NULL)
-		clk_prepare_enable(mdp_clk);
-
-	if (mdp_pclk != NULL)
-		clk_prepare_enable(mdp_pclk);
-
-	if (mdp_lut_clk != NULL)
-		clk_prepare_enable(mdp_lut_clk);
-
-	vsync_clk_prepare_enable();
-}
-
-/*
- * mdp_clk_ctrl: called from thread context
- */
-void mdp_clk_ctrl(int on)
-{
-	static int mdp_clk_cnt;
-
-	mutex_lock(&mdp_suspend_mutex);
-	if (on) {
-		if (mdp_clk_cnt == 0)
-			mdp_clk_prepare_enable();
-		mdp_clk_cnt++;
-	} else {
-		if (mdp_clk_cnt) {
-			mdp_clk_cnt--;
-			if (mdp_clk_cnt == 0)
-				mdp_clk_disable_unprepare();
-		} else
-			pr_err("%s: %d: mdp clk off is invalid\n",
-			       __func__, __LINE__);
-	}
-	pr_debug("%s: on=%d cnt=%d\n", __func__, on, mdp_clk_cnt);
-	mutex_unlock(&mdp_suspend_mutex);
-}
-
-
-
-void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state,
-		   boolean isr)
-{
-	/* do nothing */
-}
-#else
-void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state,
-		   boolean isr)
-{
-	boolean mdp_all_blocks_off = TRUE;
-	int i;
-	unsigned long flag;
-	struct msm_fb_panel_data *pdata;
-
-	/*
-	 * It is assumed that if isr = TRUE then start = OFF
-	 * if start = ON when isr = TRUE it could happen that the usercontext
-	 * could turn off the clocks while the interrupt is updating the
-	 * power to ON
-	 */
-	WARN_ON(isr == TRUE && state == MDP_BLOCK_POWER_ON);
-
-	spin_lock_irqsave(&mdp_spin_lock, flag);
-	if (MDP_BLOCK_POWER_ON == state) {
-		atomic_inc(&mdp_block_power_cnt[block]);
-
-		if (MDP_DMA2_BLOCK == block)
-			mdp_in_processing = TRUE;
-	} else {
-		atomic_dec(&mdp_block_power_cnt[block]);
-
-		if (atomic_read(&mdp_block_power_cnt[block]) < 0) {
-			/*
-			* Master has to serve a request to power off MDP always
-			* It also has a timer to power off.  So, in case of
-			* timer expires first and DMA2 finishes later,
-			* master has to power off two times
-			* There shouldn't be multiple power-off request for
-			* other blocks
-			*/
-			if (block != MDP_MASTER_BLOCK) {
-				MSM_FB_INFO("mdp_block_power_cnt[block=%d] \
-				multiple power-off request\n", block);
-			}
-			atomic_set(&mdp_block_power_cnt[block], 0);
-		}
-
-		if (MDP_DMA2_BLOCK == block)
-			mdp_in_processing = FALSE;
-	}
-	spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-	/*
-	 * If it's in isr, we send our request to workqueue.
-	 * Otherwise, processing happens in the current context
-	 */
-	if (isr) {
-		if (mdp_current_clk_on) {
-			/* checking all blocks power state */
-			for (i = 0; i < MDP_MAX_BLOCK; i++) {
-				if (atomic_read(&mdp_block_power_cnt[i]) > 0) {
-					mdp_all_blocks_off = FALSE;
-					break;
-				}
-			}
-
-			if (mdp_all_blocks_off) {
-				/* send workqueue to turn off mdp power */
-				queue_delayed_work(mdp_pipe_ctrl_wq,
-						   &mdp_pipe_ctrl_worker,
-						   mdp_timer_duration);
-			}
-		}
-	} else {
-		down(&mdp_pipe_ctrl_mutex);
-		/* checking all blocks power state */
-		for (i = 0; i < MDP_MAX_BLOCK; i++) {
-			if (atomic_read(&mdp_block_power_cnt[i]) > 0) {
-				mdp_all_blocks_off = FALSE;
-				break;
-			}
-		}
-
-		/*
-		 * find out whether a delayable work item is currently
-		 * pending
-		 */
-
-		if (delayed_work_pending(&mdp_pipe_ctrl_worker)) {
-			/*
-			 * try to cancel the current work if it fails to
-			 * stop (which means del_timer can't delete it
-			 * from the list, it's about to expire and run),
-			 * we have to let it run. queue_delayed_work won't
-			 * accept the next job which is same as
-			 * queue_delayed_work(mdp_timer_duration = 0)
-			 */
-			cancel_delayed_work(&mdp_pipe_ctrl_worker);
-		}
-
-		if ((mdp_all_blocks_off) && (mdp_current_clk_on)) {
-			mutex_lock(&mdp_suspend_mutex);
-			if (block == MDP_MASTER_BLOCK || mdp_suspended) {
-				mdp_current_clk_on = FALSE;
-				mb();
-				/* turn off MDP clks */
-				mdp_vsync_clk_disable();
-				for (i = 0; i < pdev_list_cnt; i++) {
-					pdata = (struct msm_fb_panel_data *)
-						pdev_list[i]->dev.platform_data;
-					if (pdata && pdata->clk_func)
-						pdata->clk_func(0);
-				}
-				if (mdp_clk != NULL) {
-					mdp_clk_rate = clk_get_rate(mdp_clk);
-					clk_disable_unprepare(mdp_clk);
-					if (mdp_hw_revision <=
-						MDP4_REVISION_V2_1 &&
-						mdp_clk_rate > 122880000) {
-						clk_set_rate(mdp_clk,
-							 122880000);
-					}
-					MSM_FB_DEBUG("MDP CLK OFF\n");
-				}
-				if (mdp_pclk != NULL) {
-					clk_disable_unprepare(mdp_pclk);
-					MSM_FB_DEBUG("MDP PCLK OFF\n");
-				}
-				if (mdp_lut_clk != NULL)
-					clk_disable_unprepare(mdp_lut_clk);
-			} else {
-				/* send workqueue to turn off mdp power */
-				queue_delayed_work(mdp_pipe_ctrl_wq,
-						   &mdp_pipe_ctrl_worker,
-						   mdp_timer_duration);
-			}
-			mutex_unlock(&mdp_suspend_mutex);
-		} else if ((!mdp_all_blocks_off) && (!mdp_current_clk_on)) {
-			mdp_current_clk_on = TRUE;
-			/* turn on MDP clks */
-			for (i = 0; i < pdev_list_cnt; i++) {
-				pdata = (struct msm_fb_panel_data *)
-					pdev_list[i]->dev.platform_data;
-				if (pdata && pdata->clk_func)
-					pdata->clk_func(1);
-			}
-			if (mdp_clk != NULL) {
-				if (mdp_hw_revision <=
-					MDP4_REVISION_V2_1 &&
-					mdp_clk_rate > 122880000) {
-					clk_set_rate(mdp_clk,
-						 mdp_clk_rate);
-				}
-				clk_prepare_enable(mdp_clk);
-				MSM_FB_DEBUG("MDP CLK ON\n");
-			}
-			if (mdp_pclk != NULL) {
-				clk_prepare_enable(mdp_pclk);
-				MSM_FB_DEBUG("MDP PCLK ON\n");
-			}
-			if (mdp_lut_clk != NULL)
-				clk_prepare_enable(mdp_lut_clk);
-			mdp_vsync_clk_enable();
-		}
-		up(&mdp_pipe_ctrl_mutex);
-	}
-}
-
-void mdp_clk_ctrl(int on)
-{
-	/* do nothing */
-}
-#endif
-
-void mdp_histogram_handle_isr(struct mdp_hist_mgmt *mgmt)
-{
-	uint32 isr, mask;
-	char *base_addr = MDP_BASE + mgmt->base;
-	isr = inpdw(base_addr + MDP_HIST_INTR_STATUS_OFF);
-	mask = inpdw(base_addr + MDP_HIST_INTR_ENABLE_OFF);
-	outpdw(base_addr + MDP_HIST_INTR_CLEAR_OFF, isr);
-	mb();
-	isr &= mask;
-	if (isr & INTR_HIST_RESET_SEQ_DONE)
-		__mdp_histogram_kickoff(mgmt);
-	else if (isr & INTR_HIST_DONE)
-		queue_work(mdp_hist_wq, &mgmt->mdp_histogram_worker);
-}
-
-#ifndef CONFIG_FB_MSM_MDP40
-irqreturn_t mdp_isr(int irq, void *ptr)
-{
-	uint32 mdp_interrupt = 0;
-	struct mdp_dma_data *dma;
-	unsigned long flag;
-	struct mdp_hist_mgmt *mgmt = NULL;
-	int i, ret;
-	int vsync_isr, disabled_clocks;
-	/* Ensure all the register write are complete */
-	mb();
-
-	mdp_is_in_isr = TRUE;
-
-	mdp_interrupt = inp32(MDP_INTR_STATUS);
-	outp32(MDP_INTR_CLEAR, mdp_interrupt);
-
-	mdp_interrupt &= mdp_intr_mask;
-
-	if (mdp_interrupt & TV_ENC_UNDERRUN) {
-		mdp_interrupt &= ~(TV_ENC_UNDERRUN);
-		mdp_tv_underflow_cnt++;
-	}
-
-	if (!mdp_interrupt)
-		goto out;
-
-	/*Primary Vsync interrupt*/
-	if (mdp_interrupt & MDP_PRIM_RDPTR) {
-		spin_lock_irqsave(&mdp_spin_lock, flag);
-		vsync_isr = vsync_cntrl.vsync_irq_enabled;
-		disabled_clocks = vsync_cntrl.disabled_clocks;
-		if ((!vsync_isr && !vsync_cntrl.disabled_clocks)
-			|| (!vsync_isr && vsync_cntrl.vsync_dma_enabled)) {
-			mdp_intr_mask &= ~MDP_PRIM_RDPTR;
-			outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-			mdp_disable_irq_nosync(MDP_VSYNC_TERM);
-			vsync_cntrl.disabled_clocks = 1;
-		} else if (vsync_isr) {
-			vsync_isr_handler();
-		}
-		vsync_cntrl.vsync_dma_enabled = 0;
-		spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-		complete(&vsync_cntrl.vsync_comp);
-		if (!vsync_isr && !disabled_clocks)
-			mdp_pipe_ctrl(MDP_CMD_BLOCK,
-				MDP_BLOCK_POWER_OFF, TRUE);
-
-		complete_all(&vsync_cntrl.vsync_wait);
-	}
-
-	/* DMA3 TV-Out Start */
-	if (mdp_interrupt & TV_OUT_DMA3_START) {
-		/* let's disable TV out interrupt */
-		mdp_intr_mask &= ~TV_OUT_DMA3_START;
-		outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-
-		dma = &dma3_data;
-		if (dma->waiting) {
-			dma->waiting = FALSE;
-			complete(&dma->comp);
-		}
-	}
-
-	if (mdp_rev >= MDP_REV_30) {
-		/* Only DMA_P histogram exists for this MDP rev*/
-		if (mdp_interrupt & MDP_HIST_DONE) {
-			ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_P, &mgmt);
-			if (!ret)
-				mdp_histogram_handle_isr(mgmt);
-			outp32(MDP_INTR_CLEAR, MDP_HIST_DONE);
-		}
-
-		/* LCDC UnderFlow */
-		if (mdp_interrupt & LCDC_UNDERFLOW) {
-			mdp_lcdc_underflow_cnt++;
-			/*when underflow happens HW resets all the histogram
-			  registers that were set before so restore them back
-			  to normal.*/
-			for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
-				mgmt = mdp_hist_mgmt_array[i];
-				if (!mgmt)
-					continue;
-				mgmt->mdp_is_hist_valid = FALSE;
-			}
-		}
-
-		/* LCDC Frame Start */
-		if (mdp_interrupt & LCDC_FRAME_START) {
-			dma = &dma2_data;
-			spin_lock_irqsave(&mdp_spin_lock, flag);
-			vsync_isr = vsync_cntrl.vsync_irq_enabled;
-			/* let's disable LCDC interrupt */
-			if (dma->waiting) {
-				dma->waiting = FALSE;
-				complete(&dma->comp);
-			}
-
-			if (!vsync_isr) {
-				mdp_intr_mask &= ~LCDC_FRAME_START;
-				outp32(MDP_INTR_ENABLE, mdp_intr_mask);
-				mdp_disable_irq_nosync(MDP_VSYNC_TERM);
-				vsync_cntrl.disabled_clocks = 1;
-			} else {
-				vsync_isr_handler();
-			}
-			spin_unlock_irqrestore(&mdp_spin_lock, flag);
-
-			if (!vsync_isr)
-				mdp_pipe_ctrl(MDP_CMD_BLOCK,
-					MDP_BLOCK_POWER_OFF, TRUE);
-
-			complete_all(&vsync_cntrl.vsync_wait);
-		}
-
-		/* DMA2 LCD-Out Complete */
-		if (mdp_interrupt & MDP_DMA_S_DONE) {
-			dma = &dma_s_data;
-			dma->busy = FALSE;
-			mdp_pipe_ctrl(MDP_DMA_S_BLOCK, MDP_BLOCK_POWER_OFF,
-									TRUE);
-			complete(&dma->comp);
-		}
-
-		/* DMA_E LCD-Out Complete */
-		if (mdp_interrupt & MDP_DMA_E_DONE) {
-			dma = &dma_s_data;
-			dma->busy = FALSE;
-			mdp_pipe_ctrl(MDP_DMA_E_BLOCK, MDP_BLOCK_POWER_OFF,
-									TRUE);
-			complete(&dma->comp);
-		}
-	}
-
-	/* DMA2 LCD-Out Complete */
-	if (mdp_interrupt & MDP_DMA_P_DONE) {
-		struct timeval now;
-
-		mdp_dma2_last_update_time = ktime_sub(ktime_get_real(),
-			mdp_dma2_last_update_time);
-		if (mdp_debug[MDP_DMA2_BLOCK]) {
-			jiffies_to_timeval(jiffies, &now);
-			mdp_dma2_timeval.tv_usec =
-			    now.tv_usec - mdp_dma2_timeval.tv_usec;
-		}
-#ifndef CONFIG_FB_MSM_MDP303
-		dma = &dma2_data;
-		spin_lock_irqsave(&mdp_spin_lock, flag);
-		dma->busy = FALSE;
-		spin_unlock_irqrestore(&mdp_spin_lock, flag);
-		mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
-		complete(&dma->comp);
-#else
-		if (mdp_prim_panel_type == MIPI_CMD_PANEL) {
-			dma = &dma2_data;
-			spin_lock_irqsave(&mdp_spin_lock, flag);
-			dma->busy = FALSE;
-			spin_unlock_irqrestore(&mdp_spin_lock, flag);
-			mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF,
-				TRUE);
-			mdp_disable_irq_nosync(MDP_DMA2_TERM);
-			complete(&dma->comp);
-		}
-#endif
-	}
-
-	/* PPP Complete */
-	if (mdp_interrupt & MDP_PPP_DONE) {
-#ifdef	CONFIG_FB_MSM_MDP31
-		MDP_OUTP(MDP_BASE + 0x00100, 0xFFFF);
-#endif
-		mdp_pipe_ctrl(MDP_PPP_BLOCK, MDP_BLOCK_POWER_OFF, TRUE);
-		spin_lock_irqsave(&mdp_spin_lock, flag);
-		if (mdp_ppp_waiting) {
-			mdp_ppp_waiting = FALSE;
-			complete(&mdp_ppp_comp);
-		}
-		spin_unlock_irqrestore(&mdp_spin_lock, flag);
-	}
-
-out:
-mdp_is_in_isr = FALSE;
-
-	return IRQ_HANDLED;
-}
-#endif
-
-static void mdp_drv_init(void)
-{
-	int i;
-
-	for (i = 0; i < MDP_MAX_BLOCK; i++) {
-		mdp_debug[i] = 0;
-	}
-
-	/* initialize spin lock and workqueue */
-	spin_lock_init(&mdp_spin_lock);
-	mdp_dma_wq = create_singlethread_workqueue("mdp_dma_wq");
-	mdp_vsync_wq = create_singlethread_workqueue("mdp_vsync_wq");
-	mdp_pipe_ctrl_wq = create_singlethread_workqueue("mdp_pipe_ctrl_wq");
-	INIT_DELAYED_WORK(&mdp_pipe_ctrl_worker,
-			  mdp_pipe_ctrl_workqueue_handler);
-
-	/* initialize semaphore */
-	init_completion(&mdp_ppp_comp);
-	sema_init(&mdp_ppp_mutex, 1);
-	sema_init(&mdp_pipe_ctrl_mutex, 1);
-
-	dma2_data.busy = FALSE;
-	dma2_data.dmap_busy = FALSE;
-	dma2_data.waiting = FALSE;
-	init_completion(&dma2_data.comp);
-	init_completion(&vsync_cntrl.vsync_comp);
-	init_completion(&dma2_data.dmap_comp);
-	sema_init(&dma2_data.mutex, 1);
-	mutex_init(&dma2_data.ov_mutex);
-
-	dma3_data.busy = FALSE;
-	dma3_data.waiting = FALSE;
-	init_completion(&dma3_data.comp);
-	sema_init(&dma3_data.mutex, 1);
-
-	dma_s_data.busy = FALSE;
-	dma_s_data.waiting = FALSE;
-	init_completion(&dma_s_data.comp);
-	sema_init(&dma_s_data.mutex, 1);
-
-#ifndef CONFIG_FB_MSM_MDP303
-	dma_e_data.busy = FALSE;
-	dma_e_data.waiting = FALSE;
-	init_completion(&dma_e_data.comp);
-	mutex_init(&dma_e_data.ov_mutex);
-#endif
-#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
-	dma_wb_data.busy = FALSE;
-	dma_wb_data.waiting = FALSE;
-	init_completion(&dma_wb_data.comp);
-	mutex_init(&dma_wb_data.ov_mutex);
-#endif
-
-	/* initializing mdp power block counter to 0 */
-	for (i = 0; i < MDP_MAX_BLOCK; i++) {
-		atomic_set(&mdp_block_power_cnt[i], 0);
-	}
-	vsync_cntrl.disabled_clocks = 1;
-	init_completion(&vsync_cntrl.vsync_wait);
-	atomic_set(&vsync_cntrl.vsync_resume, 1);
-#ifdef MSM_FB_ENABLE_DBGFS
-	{
-		struct dentry *root;
-		char sub_name[] = "mdp";
-
-		root = msm_fb_get_debugfs_root();
-		if (root != NULL) {
-			mdp_dir = debugfs_create_dir(sub_name, root);
-
-			if (mdp_dir) {
-				msm_fb_debugfs_file_create(mdp_dir,
-					"dma2_update_time_in_usec",
-					(u32 *) &mdp_dma2_update_time_in_usec);
-				msm_fb_debugfs_file_create(mdp_dir,
-					"vs_rdcnt_slow",
-					(u32 *) &mdp_lcd_rd_cnt_offset_slow);
-				msm_fb_debugfs_file_create(mdp_dir,
-					"vs_rdcnt_fast",
-					(u32 *) &mdp_lcd_rd_cnt_offset_fast);
-				msm_fb_debugfs_file_create(mdp_dir,
-					"mdp_usec_diff_threshold",
-					(u32 *) &mdp_usec_diff_threshold);
-				msm_fb_debugfs_file_create(mdp_dir,
-					"mdp_current_clk_on",
-					(u32 *) &mdp_current_clk_on);
-#ifdef CONFIG_FB_MSM_LCDC
-				msm_fb_debugfs_file_create(mdp_dir,
-					"lcdc_start_x",
-					(u32 *) &first_pixel_start_x);
-				msm_fb_debugfs_file_create(mdp_dir,
-					"lcdc_start_y",
-					(u32 *) &first_pixel_start_y);
-#endif
-			}
-		}
-	}
-#endif
-}
-
-static int mdp_probe(struct platform_device *pdev);
-static int mdp_remove(struct platform_device *pdev);
-
-static int mdp_runtime_suspend(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: suspending...\n");
-	return 0;
-}
-
-static int mdp_runtime_resume(struct device *dev)
-{
-	dev_dbg(dev, "pm_runtime: resuming...\n");
-	return 0;
-}
-
-static struct dev_pm_ops mdp_dev_pm_ops = {
-	.runtime_suspend = mdp_runtime_suspend,
-	.runtime_resume = mdp_runtime_resume,
-};
-
-
-static struct platform_driver mdp_driver = {
-	.probe = mdp_probe,
-	.remove = mdp_remove,
-#ifndef CONFIG_HAS_EARLYSUSPEND
-	.suspend = mdp_suspend,
-	.resume = NULL,
-#endif
-	.shutdown = NULL,
-	.driver = {
-		/*
-		 * Driver name must match the device name added in
-		 * platform.c.
-		 */
-		.name = "mdp",
-		.pm = &mdp_dev_pm_ops,
-	},
-};
-
-static int mdp_off(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd = platform_get_drvdata(pdev);
-
-	pr_debug("%s:+\n", __func__);
-	mdp_histogram_ctrl_all(FALSE);
-	atomic_set(&vsync_cntrl.suspend, 1);
-	atomic_set(&vsync_cntrl.vsync_resume, 0);
-	complete_all(&vsync_cntrl.vsync_wait);
-	mdp_clk_ctrl(1);
-	if (mfd->panel.type == MIPI_CMD_PANEL)
-		mdp4_dsi_cmd_off(pdev);
-	else if (mfd->panel.type == MIPI_VIDEO_PANEL)
-		mdp4_dsi_video_off(pdev);
-	else if (mfd->panel.type == HDMI_PANEL ||
-			mfd->panel.type == LCDC_PANEL ||
-			mfd->panel.type == LVDS_PANEL)
-		mdp4_lcdc_off(pdev);
-	else if (mfd->panel.type == MDDI_PANEL)
-		mdp4_mddi_off(pdev);
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-	ret = panel_next_off(pdev);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-	mdp_clk_ctrl(0);
-#ifdef CONFIG_MSM_BUS_SCALING
-	mdp_bus_scale_update_request(0, 0);
-#endif
-	if (mdp_rev >= MDP_REV_41 && mfd->panel.type == MIPI_CMD_PANEL)
-		mdp_dsi_cmd_overlay_suspend(mfd);
-	pr_debug("%s:-\n", __func__);
-	return ret;
-}
-
-#ifdef CONFIG_FB_MSM_MDP303
-unsigned is_mdp4_hw_reset(void)
-{
-	return 0;
-}
-void mdp4_hw_init(void)
-{
-	/* empty */
-}
-
-#endif
-static int mdp_on(struct platform_device *pdev)
-{
-	int ret = 0;
-	struct msm_fb_data_type *mfd;
-	mfd = platform_get_drvdata(pdev);
-
-	pr_debug("%s:+\n", __func__);
-
-	if (mdp_rev >= MDP_REV_40) {
-		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		mdp_clk_ctrl(1);
-		mdp4_hw_init();
-		outpdw(MDP_BASE + 0x0038, mdp4_display_intf);
-		if (mfd->panel.type == MIPI_CMD_PANEL) {
-			mdp_vsync_cfg_regs(mfd, FALSE);
-			mdp4_dsi_cmd_on(pdev);
-		} else if (mfd->panel.type == MIPI_VIDEO_PANEL) {
-			mdp4_dsi_video_on(pdev);
-		} else if (mfd->panel.type == HDMI_PANEL ||
-				mfd->panel.type == LCDC_PANEL ||
-				mfd->panel.type == LVDS_PANEL) {
-			mdp4_lcdc_on(pdev);
-		} else if (mfd->panel.type == MDDI_PANEL) {
-			mdp_vsync_cfg_regs(mfd, FALSE);
-			mdp4_mddi_on(pdev);
-		}
-
-		mdp_clk_ctrl(0);
-		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-	}
-
-	if (mdp_rev == MDP_REV_303 && mfd->panel.type == MIPI_CMD_PANEL) {
-
-		vsync_cntrl.dev = mfd->fbi->dev;
-		atomic_set(&vsync_cntrl.suspend, 0);
-		atomic_set(&vsync_cntrl.vsync_resume, 1);
-	}
-
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-
-	ret = panel_next_on(pdev);
-	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-
-	mdp_histogram_ctrl_all(TRUE);
-
-	if (ret == 0)
-		ret = panel_next_late_init(pdev);
-
-	pr_debug("%s:-\n", __func__);
-
-	return ret;
-}
-
-static int mdp_resource_initialized;
-static struct msm_panel_common_pdata *mdp_pdata;
-
-uint32 mdp_hw_revision;
-
-/*
- * mdp_hw_revision:
- * 0 == V1
- * 1 == V2
- * 2 == V2.1
- *
- */
-void mdp_hw_version(void)
-{
-	char *cp;
-	uint32 *hp;
-
-	if (mdp_pdata == NULL)
-		return;
-
-	mdp_hw_revision = MDP4_REVISION_NONE;
-	if (mdp_pdata->hw_revision_addr == 0)
-		return;
-
-	/* tlmmgpio2 shadow */
-	cp = (char *)ioremap(mdp_pdata->hw_revision_addr, 0x16);
-
-	if (cp == NULL)
-		return;
-
-	hp = (uint32 *)cp;	/* HW_REVISION_NUMBER */
-	mdp_hw_revision = *hp;
-	iounmap(cp);
-
-	mdp_hw_revision >>= 28;	/* bit 31:28 */
-	mdp_hw_revision &= 0x0f;
-
-	MSM_FB_DEBUG("%s: mdp_hw_revision=%x\n",
-				__func__, mdp_hw_revision);
-}
-
-#ifdef CONFIG_MSM_BUS_SCALING
-
-#ifndef MDP_BUS_VECTOR_ENTRY
-#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val)		\
-	{						\
-		.src = MSM_BUS_MASTER_MDP_PORT0,	\
-		.dst = MSM_BUS_SLAVE_EBI_CH0,		\
-		.ab  = (ab_val),			\
-		.ib  = (ib_val),			\
-	}
-#endif
-/*
- *    Entry 0 hold 0 request
- *    Entry 1 and 2 do ping pong request
- */
-static struct msm_bus_vectors mdp_bus_vectors[] = {
-	MDP_BUS_VECTOR_ENTRY(0, 0),
-	MDP_BUS_VECTOR_ENTRY( 128000000,  160000000),
-	MDP_BUS_VECTOR_ENTRY( 128000000,  160000000),
-};
-
-static struct msm_bus_paths mdp_bus_usecases[ARRAY_SIZE(mdp_bus_vectors)];
-static struct msm_bus_scale_pdata mdp_bus_scale_table = {
-	.usecase = mdp_bus_usecases,
-	.num_usecases = ARRAY_SIZE(mdp_bus_usecases),
-	.name = "mdp",
-};
-static uint32_t mdp_bus_scale_handle;
-static int mdp_bus_scale_register(void)
-{
-	struct msm_bus_scale_pdata *bus_pdata = &mdp_bus_scale_table;
-	int i;
-	for (i = 0; i < bus_pdata->num_usecases; i++) {
-		mdp_bus_usecases[i].num_paths = 1;
-		mdp_bus_usecases[i].vectors = &mdp_bus_vectors[i];
-	}
-	mdp_bus_scale_handle = msm_bus_scale_register_client(bus_pdata);
-	if (!mdp_bus_scale_handle) {
-		pr_err("%s: not able to get bus scale!\n", __func__);
-		return -ENOMEM;
-	}
-	return 0;
-}
-
-int mdp_bus_scale_update_request(u64 ab, u64 ib)
-{
-	static int bus_index = 1;
-
-	if (mdp_bus_scale_handle < 1) {
-		pr_err("%s invalid bus handle\n", __func__);
-		return -EINVAL;
-	}
-
-	if (!ab)
-		return msm_bus_scale_client_update_request
-			(mdp_bus_scale_handle, 0);
-
-	/* ping pong bus_index between table entry 1 and 2 */
-	bus_index++;
-	bus_index = (bus_index > 2) ? 1 : bus_index;
-
-	mdp_bus_usecases[bus_index].vectors->ab = min(ab, mdp_max_bw);
-	ib = max(ib, ab);
-	mdp_bus_usecases[bus_index].vectors->ib = min(ib, mdp_max_bw);
-
-	pr_debug("%s: handle=%d index=%d ab=%llu ib=%llu\n", __func__,
-		 (u32)mdp_bus_scale_handle, bus_index,
-		 mdp_bus_usecases[bus_index].vectors->ab,
-		 mdp_bus_usecases[bus_index].vectors->ib);
-
-	return msm_bus_scale_client_update_request
-		(mdp_bus_scale_handle, bus_index);
-}
-#endif
-DEFINE_MUTEX(mdp_clk_lock);
-int mdp_set_core_clk(u32 rate)
-{
-	int ret = -EINVAL;
-	if (mdp_clk)
-		ret = clk_set_rate(mdp_clk, rate);
-	if (ret)
-		pr_err("%s unable to set mdp clk rate", __func__);
-	else
-		pr_debug("%s mdp clk rate to be set %d: actual rate %ld\n",
-			__func__, rate, clk_get_rate(mdp_clk));
-	return ret;
-}
-
-int mdp_clk_round_rate(u32 rate)
-{
-	return clk_round_rate(mdp_clk, rate);
-}
-
-unsigned long mdp_get_core_clk(void)
-{
-	unsigned long clk_rate = 0;
-	if (mdp_clk) {
-		mutex_lock(&mdp_clk_lock);
-		clk_rate = clk_get_rate(mdp_clk);
-		mutex_unlock(&mdp_clk_lock);
-	}
-
-	return clk_rate;
-}
-
-static int mdp_irq_clk_setup(struct platform_device *pdev,
-	char cont_splashScreen)
-{
-	int ret;
-
-#ifdef CONFIG_FB_MSM_MDP40
-	ret = request_irq(mdp_irq, mdp4_isr, IRQF_DISABLED, "MDP", 0);
-#else
-	ret = request_irq(mdp_irq, mdp_isr, IRQF_DISABLED, "MDP", 0);
-#endif
-	if (ret) {
-		printk(KERN_ERR "mdp request_irq() failed!\n");
-		return ret;
-	}
-	disable_irq(mdp_irq);
-
-	dsi_pll_vdda = regulator_get(&pdev->dev, "dsi_pll_vdda");
-	if (IS_ERR(dsi_pll_vdda)) {
-		dsi_pll_vdda = NULL;
-	} else {
-		if (mdp_rev == MDP_REV_42 || mdp_rev == MDP_REV_44) {
-			ret = regulator_set_voltage(dsi_pll_vdda, 1200000,
-				1200000);
-			if (ret) {
-				pr_err("set_voltage failed for dsi_pll_vdda, ret=%d\n",
-					ret);
-			}
-		}
-	}
-
-	dsi_pll_vddio = regulator_get(&pdev->dev, "dsi_pll_vddio");
-	if (IS_ERR(dsi_pll_vddio)) {
-		dsi_pll_vddio = NULL;
-	} else {
-		if (mdp_rev == MDP_REV_42) {
-			ret = regulator_set_voltage(dsi_pll_vddio, 1800000,
-				1800000);
-			if (ret) {
-				pr_err("set_voltage failed for dsi_pll_vddio, ret=%d\n",
-					ret);
-			}
-		}
-	}
-
-	footswitch = regulator_get(&pdev->dev, "vdd");
-	if (IS_ERR(footswitch)) {
-		footswitch = NULL;
-	} else {
-		regulator_enable(footswitch);
-		mdp_footswitch_on = 1;
-	}
-
-	mdp_clk = clk_get(&pdev->dev, "core_clk");
-	if (IS_ERR(mdp_clk)) {
-		ret = PTR_ERR(mdp_clk);
-		printk(KERN_ERR "can't get mdp_clk error:%d!\n", ret);
-		free_irq(mdp_irq, 0);
-		return ret;
-	}
-
-	mdp_pclk = clk_get(&pdev->dev, "iface_clk");
-	if (IS_ERR(mdp_pclk))
-		mdp_pclk = NULL;
-
-	if (mdp_rev >= MDP_REV_42) {
-		mdp_lut_clk = clk_get(&pdev->dev, "lut_clk");
-		if (IS_ERR(mdp_lut_clk)) {
-			ret = PTR_ERR(mdp_lut_clk);
-			pr_err("can't get mdp_clk error:%d!\n", ret);
-			clk_put(mdp_clk);
-			free_irq(mdp_irq, 0);
-			return ret;
-		}
-	} else {
-		mdp_lut_clk = NULL;
-	}
-
-#ifdef CONFIG_FB_MSM_MDP40
-
-	if (mdp_pdata)
-		mdp_max_clk = mdp_pdata->mdp_max_clk;
-	else
-		pr_err("%s cannot get mdp max clk!\n", __func__);
-
-	if (!mdp_max_clk)
-		pr_err("%s mdp max clk is zero!\n", __func__);
-
-	if (cont_splashScreen)
-		mdp_clk_rate = clk_get_rate(mdp_clk);
-	else
-		mdp_clk_rate = mdp_max_clk;
-
-	mutex_lock(&mdp_clk_lock);
-	clk_set_rate(mdp_clk, mdp_clk_rate);
-	if (mdp_lut_clk != NULL)
-		clk_set_rate(mdp_lut_clk, mdp_clk_rate);
-	mutex_unlock(&mdp_clk_lock);
-
-	MSM_FB_DEBUG("mdp_clk: mdp_clk=%d\n", (int)clk_get_rate(mdp_clk));
-#endif
-
-	if (mdp_rev == MDP_REV_42 && !cont_splashScreen) {
-		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
-		/* DSI Video Timing generator disable */
-		outpdw(MDP_BASE + 0xE0000, 0x0);
-		/* Clear MDP Interrupt Enable register */
-		outpdw(MDP_BASE + 0x50, 0x0);
-		/* Set Overlay Proc 0 to reset state */
-		outpdw(MDP_BASE + 0x10004, 0x3);
-		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
-	}
-	return 0;
-}
-
-static int mdp_probe(struct platform_device *pdev)
-{
-	struct platform_device *msm_fb_dev = NULL;
-	struct msm_fb_data_type *mfd;
-	struct msm_fb_panel_data *pdata = NULL;
-	int rc;
-	resource_size_t  size ;
-	unsigned long flag;
-	u32 frame_rate;
-#ifdef CONFIG_FB_MSM_MDP40
-	int intf, if_no;
-#endif
-#if defined(CONFIG_FB_MSM_MIPI_DSI) && defined(CONFIG_FB_MSM_MDP40)
-	struct mipi_panel_info *mipi;
-#endif
-
-	if ((pdev->id == 0) && (pdev->num_resources > 0)) {
-		mdp_init_pdev = pdev;
-		mdp_pdata = pdev->dev.platform_data;
-
-		size =  resource_size(&pdev->resource[0]);
-		msm_mdp_base = ioremap(pdev->resource[0].start, size);
-
-		MSM_FB_DEBUG("MDP HW Base phy_Address = 0x%x virt = 0x%x\n",
-			(int)pdev->resource[0].start, (int)msm_mdp_base);
-
-		if (unlikely(!msm_mdp_base))
-			return -ENOMEM;
-
-		mdp_irq = platform_get_irq(pdev, 0);
-		if (mdp_irq < 0) {
-			pr_err("mdp: can not get mdp irq\n");
-			return -ENOMEM;
-		}
-
-		mdp_rev = mdp_pdata->mdp_rev;
-
-		mdp_iommu_split_domain = mdp_pdata->mdp_iommu_split_domain;
-
-		rc = mdp_irq_clk_setup(pdev, mdp_pdata->cont_splash_enabled);
-
-		if (rc)
-			return rc;
-
-		mdp_clk_ctrl(1);
-
-		mdp_hw_version();
-
-		/* initializing mdp hw */
-#ifdef CONFIG_FB_MSM_MDP40
-		if (!(mdp_pdata->cont_splash_enabled))
-			mdp4_hw_init();
-#else
-		mdp_hw_init(mdp_pdata->cont_splash_enabled);
-#endif
-
-#ifdef CONFIG_FB_MSM_OVERLAY
-		mdp_hw_cursor_init();
-#endif
-
-		if (!(mdp_pdata->cont_splash_enabled))
-			mdp_clk_ctrl(0);
-
-		mdp_resource_initialized = 1;
-		return 0;
-	}
-
-	if (!mdp_resource_initialized)
-		return -EPERM;
-
-	mfd = platform_get_drvdata(pdev);
-
-	if (!mfd)
-		return -ENODEV;
-
-	if (mfd->key != MFD_KEY)
-		return -EINVAL;
-
-	if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST)
-		return -ENOMEM;
-
-	msm_fb_dev = platform_device_alloc("msm_fb", pdev->id);
-	if (!msm_fb_dev)
-		return -ENOMEM;
-
-	/* link to the latest pdev */
-	mfd->pdev = msm_fb_dev;
-	mfd->mdp_rev = mdp_rev;
-	mfd->vsync_init = NULL;
-
-	mfd->ov0_wb_buf = MDP_ALLOC(sizeof(struct mdp_buf_type));
-	mfd->ov1_wb_buf = MDP_ALLOC(sizeof(struct mdp_buf_type));
-	memset((void *)mfd->ov0_wb_buf, 0, sizeof(struct mdp_buf_type));
-	memset((void *)mfd->ov1_wb_buf, 0, sizeof(struct mdp_buf_type));
-
-	if (mdp_pdata) {
-		mfd->ov0_wb_buf->size = mdp_pdata->ov0_wb_size;
-		mfd->ov1_wb_buf->size = mdp_pdata->ov1_wb_size;
-		mfd->mem_hid = mdp_pdata->mem_hid;
-		mfd->avtimer_phy = mdp_pdata->avtimer_phy;
-	} else {
-		mfd->ov0_wb_buf->size = 0;
-		mfd->ov1_wb_buf->size = 0;
-		mfd->mem_hid = 0;
-		mfd->avtimer_phy = 0;
-	}
-
-	/* initialize Post Processing data*/
-	mdp_hist_lut_ini