counter_4bit.vhd

-- counter_4bit.vhd ------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--------------------------------------------------
ENTITY counter_4bit IS
	PORT (clk : IN std_logic;
		digit : OUT std_logic_vector(3 downto 0));
END ENTITY;
--------------------------------------------------
ARCHITECTURE behavior OF counter_4bit IS
BEGIN
	count: PROCESS(clk)
	variable temp: std_logic_vector(3 downto 0):= "0000";	
	BEGIN
		IF (clk'EVENT AND clk='1') THEN
			temp := std_logic_vector(unsigned(temp) + 1);
--vector to int:
--use ieee.numeric_std.all;
--...<= to_integer(unsigned(....));
--...<= to_integer(signed(....));
			IF (temp="1111") THEN temp := "0000";
			END IF;
		END IF;
		digit <= temp; 		
	END PROCESS count;
END ARCHITECTURE;
--------------------------------------------------

counter_4bit_tb.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY counter_4bit_tb IS
END counter_4bit_tb;

ARCHITECTURE stimulus OF counter_4bit_tb IS

COMPONENT counter_4bit
	PORT (clk : IN std_logic;
		  digit : OUT std_logic_vector(3 downto 0));
END COMPONENT;

SIGNAL clk_tb:   std_logic := '0';
SIGNAL digit_tb: std_logic_vector(3 DOWNTO 0);

BEGIN
	COUNTS: counter_4bit port map (clk=>clk_tb, digit=>digit_tb);
	clk_tb <= NOT clk_tb AFTER 50ns;
END stimulus;

decoder.vhd

-- NG_decoder.vhd ---------------------------
LIBRARY ieee; 
USE ieee.std_logic_1164.all;
---------------------------------------------
ENTITY decoder IS
	PORT ( ena : IN STD_LOGIC;
		   sel : IN INTEGER RANGE 0 TO 7;
			 x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ENTITY;
---------------------------------------------
ARCHITECTURE NG OF decoder IS
BEGIN
	PROCESS (ena, sel)
	BEGIN
		IF (ena='0') THEN
			x <= (OTHERS => '1');
		ELSE
			x <= (OTHERS => '1');
			x(sel) <= '0';
		END IF;
	END PROCESS;
END ARCHITECTURE;
---------------------------------------------

decoder_tb.vhd

library ieee;
use ieee.std_logic_1164.all;

ENTITY decoder_tb IS
END decoder_tb;

ARCHITECTURE stimulus OF decoder_tb IS

COMPONENT decoder
PORT ( ena: IN STD_LOGIC;
       sel: IN INTEGER RANGE 0 TO 7;
       x:   OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;

SIGNAL  ena_tb: STD_LOGIC;
SIGNAL  sel_tb: INTEGER RANGE 0 TO 7;
SIGNAL  x_tb:   STD_LOGIC_VECTOR (7 DOWNTO 0);

BEGIN

    decoder1: decoder PORT MAP (ena=>ena_tb, sel=>sel_tb, x=>x_tb);

    PROCESS      
    BEGIN
        ena_tb <= '0';
		sel_tb <=  3; WAIT FOR 100 ns;

        ena_tb <= '1';
		sel_tb <=  3; WAIT FOR 100 ns;
		
        ena_tb <= '1';
        sel_tb <=  4; WAIT FOR 100 ns;

        ena_tb <= '1';
	    sel_tb <=  5; WAIT;
    END PROCESS;    

END stimulus;

Reg_ckt03.vhd

-- mux_reg Circuits -------------------
ENTITY Reg_ckt03 IS
  PORT (clk: IN BIT;
          x: IN BIT_VECTOR(7 DOWNTO 0);
        sel: IN INTEGER RANGE 0 TO 7;
          y: OUT BIT);
END ENTITY;
----- code 3:----------------------------
ARCHITECTURE circuits OF Reg_ckt03 IS
BEGIN
    PROCESS (clk)
    BEGIN
       IF clk'EVENT AND clk='1' THEN
         y <= x(sel);
       END IF;
    END PROCESS;
END ARCHITECTURE;