Created
April 1, 2014 04:04
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Basic Gate Hspice
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| ************************************************************************ | |
| * auCdl Netlist: | |
| * | |
| * Library Name: my_lib | |
| * Top Cell Name: inv | |
| * View Name: schematic | |
| * Netlisted on: Mar 25 09:46:00 2014 | |
| ************************************************************************ | |
| .lib "~/cic018.l" TT | |
| *.BIPOLAR | |
| *.RESI = 2000 | |
| *.RESVAL | |
| *.CAPVAL | |
| *.DIOPERI | |
| *.DIOAREA | |
| *.EQUATION | |
| *.SCALE METER | |
| *.MEGA | |
| .PARAM | |
| .GLOBAL gnd! | |
| + vdd! | |
| vdd vdd! 0 1.8 | |
| vgnd gnd! 0 0 | |
| vin vin gnd! pulse(0 1.8 0 0.1n 0.1n 50n 100n) | |
| *.PIN gnd! | |
| *+ vdd! | |
| ************************************************************************ | |
| * Library Name: my_lib | |
| * Cell Name: inv | |
| * View Name: schematic | |
| ************************************************************************ | |
| .SUBCKT inv vin vout | |
| *.PININFO vin:I vout:O | |
| MM1 vout vin gnd! gnd! N_18 W=1.88u L=180n | |
| MM0 vout vin vdd! vdd! P_18 W=500n L=180n | |
| .ENDS | |
| xinv vin vout inv | |
| .op | |
| .options post | |
| .tran 0.01n 400n | |
| .end | |
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| ************************************************************************ | |
| * auCdl Netlist: | |
| * | |
| * Library Name: my_lib | |
| * Top Cell Name: xor | |
| * View Name: schematic | |
| * Netlisted on: Apr 1 10:31:51 2014 | |
| ************************************************************************ | |
| .lib "~/cic018.l" TT | |
| *.BIPOLAR | |
| *.RESI = 2000 | |
| *.RESVAL | |
| *.CAPVAL | |
| *.DIOPERI | |
| *.DIOAREA | |
| *.EQUATION | |
| *.SCALE METER | |
| *.MEGA | |
| .PARAM | |
| .GLOBAL gnd! | |
| + vdd! | |
| vdd vdd! 0 1.8 | |
| vgnd gnd! 0 0 | |
| v1 vin1 gnd! pulse(0 1.8 0 0.1n 0.1n 50n 100n) | |
| v2 vin2 gnd! pulse(0 1.8 0 0.1n 0.1n 100n 200n) | |
| *.PIN gnd! | |
| *+ vdd! | |
| ************************************************************************ | |
| * Library Name: my_lib | |
| * Cell Name: xor | |
| * View Name: schematic | |
| ************************************************************************ | |
| .SUBCKT xor A B out | |
| MM10 out net18 gnd! gnd! N_18 W=500n L=180n | |
| MM9 net18 A gnd! gnd! N_18 W=500n L=180n | |
| MM8 out B net6 gnd! N_18 W=500n L=180n | |
| MM7 net6 A gnd! gnd! N_18 W=500n L=180n | |
| MM6 net18 B gnd! gnd! N_18 W=500n L=180n | |
| MM5 out net18 net25 vdd! P_18 W=1.88u L=180n | |
| MM4 net25 B vdd! vdd! P_18 W=1.88u L=180n | |
| MM3 net41 A vdd! vdd! P_18 W=1.88u L=180n | |
| MM2 net18 B net41 vdd! P_18 W=1.88u L=180n | |
| MM1 out net18 net29 vdd! P_18 W=1.88u L=180n | |
| MM0 net29 A vdd! vdd! P_18 W=1.88u L=180n | |
| .ENDS | |
| xor1 vin1 vin2 out xor | |
| .op | |
| .options post | |
| .tran 0.01n 400n | |
| .end |
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