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February 27, 2018 15:01
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# ! [ cfg_attr ( feature = "rt" , feature ( global_asm ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( macro_reexport ) ) ] # ! [ cfg_attr ( feature = "rt" , feature ( used ) ) ] # ! [ doc = "Peripheral access API for ATSAMD21E15A microcontrollers (generated using svd2rust v0.12.0)\n\nYou can find an overview of the API [here].\n\n[here]: https://docs.rs/svd2rust/0.12.0/svd2rust/#peripheral-api" ] # ! [ allow ( private_no_mangle_statics ) ] # ! [ deny ( missing_docs ) ] # ! [ deny ( warnings ) ] # ! [ allow ( non_camel_case_types ) ] # ! [ feature ( const_fn ) ] # ! [ no_std ] | |
extern crate bare_metal; | |
extern crate cortex_m; | |
#[macro_reexport(default_handler, exception)] | |
#[cfg(feature = "rt")] | |
extern crate cortex_m_rt; | |
extern crate vcell; | |
use core::ops::Deref; | |
use core::marker::PhantomData; | |
#[doc = r" Number available in the NVIC for configuring priority"] | |
pub const NVIC_PRIO_BITS: u8 = 2; | |
pub use interrupt::Interrupt; | |
#[doc(hidden)] | |
pub mod interrupt { | |
use bare_metal::Nr; | |
#[cfg(feature = "rt")] | |
extern "C" { | |
fn DEFAULT_HANDLER(); | |
} | |
#[cfg(feature = "rt")] | |
#[allow(non_snake_case)] | |
#[no_mangle] | |
pub unsafe extern "C" fn DH_TRAMPOLINE() { | |
DEFAULT_HANDLER(); | |
} | |
#[cfg(feature = "rt")] | |
global_asm ! ( "\n.weak PM\nPM = DH_TRAMPOLINE\n.weak SYSCTRL\nSYSCTRL = DH_TRAMPOLINE\n.weak WDT\nWDT = DH_TRAMPOLINE\n.weak RTC\nRTC = DH_TRAMPOLINE\n.weak EIC\nEIC = DH_TRAMPOLINE\n.weak NVMCTRL\nNVMCTRL = DH_TRAMPOLINE\n.weak DMAC\nDMAC = DH_TRAMPOLINE\n.weak USB\nUSB = DH_TRAMPOLINE\n.weak EVSYS\nEVSYS = DH_TRAMPOLINE\n.weak SERCOM0\nSERCOM0 = DH_TRAMPOLINE\n.weak SERCOM1\nSERCOM1 = DH_TRAMPOLINE\n.weak SERCOM2\nSERCOM2 = DH_TRAMPOLINE\n.weak SERCOM3\nSERCOM3 = DH_TRAMPOLINE\n.weak TCC0\nTCC0 = DH_TRAMPOLINE\n.weak TCC1\nTCC1 = DH_TRAMPOLINE\n.weak TCC2\nTCC2 = DH_TRAMPOLINE\n.weak TC3\nTC3 = DH_TRAMPOLINE\n.weak TC4\nTC4 = DH_TRAMPOLINE\n.weak TC5\nTC5 = DH_TRAMPOLINE\n.weak ADC\nADC = DH_TRAMPOLINE\n.weak AC\nAC = DH_TRAMPOLINE\n.weak DAC\nDAC = DH_TRAMPOLINE\n.weak I2S\nI2S = DH_TRAMPOLINE" ) ; | |
#[cfg(feature = "rt")] | |
extern "C" { | |
fn PM(); | |
fn SYSCTRL(); | |
fn WDT(); | |
fn RTC(); | |
fn EIC(); | |
fn NVMCTRL(); | |
fn DMAC(); | |
fn USB(); | |
fn EVSYS(); | |
fn SERCOM0(); | |
fn SERCOM1(); | |
fn SERCOM2(); | |
fn SERCOM3(); | |
fn TCC0(); | |
fn TCC1(); | |
fn TCC2(); | |
fn TC3(); | |
fn TC4(); | |
fn TC5(); | |
fn ADC(); | |
fn AC(); | |
fn DAC(); | |
fn I2S(); | |
} | |
#[allow(private_no_mangle_statics)] | |
#[cfg(feature = "rt")] | |
#[doc(hidden)] | |
#[link_section = ".vector_table.interrupts"] | |
#[no_mangle] | |
#[used] | |
pub static INTERRUPTS: [Option<unsafe extern "C" fn()>; 28] = [ | |
Some(PM), | |
Some(SYSCTRL), | |
Some(WDT), | |
Some(RTC), | |
Some(EIC), | |
Some(NVMCTRL), | |
Some(DMAC), | |
Some(USB), | |
Some(EVSYS), | |
Some(SERCOM0), | |
Some(SERCOM1), | |
Some(SERCOM2), | |
Some(SERCOM3), | |
None, | |
None, | |
Some(TCC0), | |
Some(TCC1), | |
Some(TCC2), | |
Some(TC3), | |
Some(TC4), | |
Some(TC5), | |
None, | |
None, | |
Some(ADC), | |
Some(AC), | |
Some(DAC), | |
None, | |
Some(I2S), | |
]; | |
#[doc = r" Enumeration of all the interrupts"] | |
pub enum Interrupt { | |
#[doc = "0 - PM"] | |
PM, | |
#[doc = "1 - SYSCTRL"] | |
SYSCTRL, | |
#[doc = "2 - WDT"] | |
WDT, | |
#[doc = "3 - RTC"] | |
RTC, | |
#[doc = "4 - EIC"] | |
EIC, | |
#[doc = "5 - NVMCTRL"] | |
NVMCTRL, | |
#[doc = "6 - DMAC"] | |
DMAC, | |
#[doc = "7 - USB"] | |
USB, | |
#[doc = "8 - EVSYS"] | |
EVSYS, | |
#[doc = "9 - SERCOM0"] | |
SERCOM0, | |
#[doc = "10 - SERCOM1"] | |
SERCOM1, | |
#[doc = "11 - SERCOM2"] | |
SERCOM2, | |
#[doc = "12 - SERCOM3"] | |
SERCOM3, | |
#[doc = "15 - TCC0"] | |
TCC0, | |
#[doc = "16 - TCC1"] | |
TCC1, | |
#[doc = "17 - TCC2"] | |
TCC2, | |
#[doc = "18 - TC3"] | |
TC3, | |
#[doc = "19 - TC4"] | |
TC4, | |
#[doc = "20 - TC5"] | |
TC5, | |
#[doc = "23 - ADC"] | |
ADC, | |
#[doc = "24 - AC"] | |
AC, | |
#[doc = "25 - DAC"] | |
DAC, | |
#[doc = "27 - I2S"] | |
I2S, | |
} | |
unsafe impl Nr for Interrupt { | |
#[inline] | |
fn nr(&self) -> u8 { | |
match *self { | |
Interrupt::PM => 0, | |
Interrupt::SYSCTRL => 1, | |
Interrupt::WDT => 2, | |
Interrupt::RTC => 3, | |
Interrupt::EIC => 4, | |
Interrupt::NVMCTRL => 5, | |
Interrupt::DMAC => 6, | |
Interrupt::USB => 7, | |
Interrupt::EVSYS => 8, | |
Interrupt::SERCOM0 => 9, | |
Interrupt::SERCOM1 => 10, | |
Interrupt::SERCOM2 => 11, | |
Interrupt::SERCOM3 => 12, | |
Interrupt::TCC0 => 15, | |
Interrupt::TCC1 => 16, | |
Interrupt::TCC2 => 17, | |
Interrupt::TC3 => 18, | |
Interrupt::TC4 => 19, | |
Interrupt::TC5 => 20, | |
Interrupt::ADC => 23, | |
Interrupt::AC => 24, | |
Interrupt::DAC => 25, | |
Interrupt::I2S => 27, | |
} | |
} | |
} | |
#[cfg(feature = "rt")] | |
#[macro_export] | |
macro_rules ! interrupt { ( $ NAME : ident , $ path : path , locals : { $ ( $ lvar : ident : $ lty : ty = $ lval : expr ; ) * } ) => { # [ allow ( non_snake_case ) ] mod $ NAME { pub struct Locals { $ ( pub $ lvar : $ lty , ) * } } # [ allow ( non_snake_case ) ] # [ no_mangle ] pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ( $ lvar : $ lval , ) * } ; let f : fn ( & mut self :: $ NAME :: Locals ) = $ path ; f ( unsafe { & mut LOCALS } ) ; } } ; ( $ NAME : ident , $ path : path ) => { # [ allow ( non_snake_case ) ] # [ no_mangle ] pub extern "C" fn $ NAME ( ) { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn ( ) = $ path ; f ( ) ; } } } | |
} | |
pub use cortex_m::peripheral::Peripherals as CorePeripherals; | |
pub use cortex_m::peripheral::CPUID; | |
pub use cortex_m::peripheral::DCB; | |
pub use cortex_m::peripheral::DWT; | |
pub use cortex_m::peripheral::MPU; | |
pub use cortex_m::peripheral::NVIC; | |
pub use cortex_m::peripheral::SCB; | |
pub use cortex_m::peripheral::SYST; | |
#[doc = "Analog Comparators"] | |
pub struct AC { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for AC {} | |
impl AC { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const ac::RegisterBlock { | |
0x4200_4400 as *const _ | |
} | |
} | |
impl Deref for AC { | |
type Target = ac::RegisterBlock; | |
fn deref(&self) -> &ac::RegisterBlock { | |
unsafe { &*AC::ptr() } | |
} | |
} | |
#[doc = "Analog Comparators"] | |
pub mod ac { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control A"] | |
pub ctrla: CTRLA, | |
#[doc = "0x01 - Control B"] | |
pub ctrlb: CTRLB, | |
#[doc = "0x02 - Event Control"] | |
pub evctrl: EVCTRL, | |
#[doc = "0x04 - Interrupt Enable Clear"] | |
pub intenclr: INTENCLR, | |
#[doc = "0x05 - Interrupt Enable Set"] | |
pub intenset: INTENSET, | |
#[doc = "0x06 - Interrupt Flag Status and Clear"] | |
pub intflag: INTFLAG, | |
_reserved0: [u8; 1usize], | |
#[doc = "0x08 - Status A"] | |
pub statusa: STATUSA, | |
#[doc = "0x09 - Status B"] | |
pub statusb: STATUSB, | |
#[doc = "0x0a - Status C"] | |
pub statusc: STATUSC, | |
_reserved1: [u8; 1usize], | |
#[doc = "0x0c - Window Control"] | |
pub winctrl: WINCTRL, | |
_reserved2: [u8; 3usize], | |
#[doc = "0x10 - Comparator Control n"] | |
pub compctrl: [COMPCTRL; 2], | |
_reserved3: [u8; 8usize], | |
#[doc = "0x20 - Scaler n"] | |
pub scaler: [SCALER; 2], | |
} | |
#[doc = "Comparator Control n"] | |
pub struct COMPCTRL { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Comparator Control n"] | |
pub mod compctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::COMPCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SINGLER { | |
bits: bool, | |
} | |
impl SINGLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SPEED`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SPEEDR { | |
#[doc = "Low speed"] | |
LOW, | |
#[doc = "High speed"] | |
HIGH, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SPEEDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SPEEDR::LOW => 0, | |
SPEEDR::HIGH => 0x01, | |
SPEEDR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SPEEDR { | |
match value { | |
0 => SPEEDR::LOW, | |
1 => SPEEDR::HIGH, | |
i => SPEEDR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SPEEDR::LOW | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SPEEDR::HIGH | |
} | |
} | |
#[doc = "Possible values of the field `INTSEL`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum INTSELR { | |
#[doc = "Interrupt on comparator output toggle"] | |
TOGGLE, | |
#[doc = "Interrupt on comparator output rising"] | |
RISING, | |
#[doc = "Interrupt on comparator output falling"] | |
FALLING, | |
#[doc = "Interrupt on end of comparison (single-shot mode only)"] | |
EOC, | |
} | |
impl INTSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
INTSELR::TOGGLE => 0, | |
INTSELR::RISING => 0x01, | |
INTSELR::FALLING => 0x02, | |
INTSELR::EOC => 0x03, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> INTSELR { | |
match value { | |
0 => INTSELR::TOGGLE, | |
1 => INTSELR::RISING, | |
2 => INTSELR::FALLING, | |
3 => INTSELR::EOC, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `TOGGLE`"] | |
#[inline] | |
pub fn is_toggle(&self) -> bool { | |
*self == INTSELR::TOGGLE | |
} | |
#[doc = "Checks if the value of the field is `RISING`"] | |
#[inline] | |
pub fn is_rising(&self) -> bool { | |
*self == INTSELR::RISING | |
} | |
#[doc = "Checks if the value of the field is `FALLING`"] | |
#[inline] | |
pub fn is_falling(&self) -> bool { | |
*self == INTSELR::FALLING | |
} | |
#[doc = "Checks if the value of the field is `EOC`"] | |
#[inline] | |
pub fn is_eoc(&self) -> bool { | |
*self == INTSELR::EOC | |
} | |
} | |
#[doc = "Possible values of the field `MUXNEG`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum MUXNEGR { | |
#[doc = "I/O pin 0"] | |
PIN0, | |
#[doc = "I/O pin 1"] | |
PIN1, | |
#[doc = "I/O pin 2"] | |
PIN2, | |
#[doc = "I/O pin 3"] | |
PIN3, | |
#[doc = "Ground"] | |
GND, | |
#[doc = "VDD scaler"] | |
VSCALE, | |
#[doc = "Internal bandgap voltage"] | |
BANDGAP, | |
#[doc = "DAC output"] | |
DAC, | |
} | |
impl MUXNEGR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
MUXNEGR::PIN0 => 0, | |
MUXNEGR::PIN1 => 0x01, | |
MUXNEGR::PIN2 => 0x02, | |
MUXNEGR::PIN3 => 0x03, | |
MUXNEGR::GND => 0x04, | |
MUXNEGR::VSCALE => 0x05, | |
MUXNEGR::BANDGAP => 0x06, | |
MUXNEGR::DAC => 0x07, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> MUXNEGR { | |
match value { | |
0 => MUXNEGR::PIN0, | |
1 => MUXNEGR::PIN1, | |
2 => MUXNEGR::PIN2, | |
3 => MUXNEGR::PIN3, | |
4 => MUXNEGR::GND, | |
5 => MUXNEGR::VSCALE, | |
6 => MUXNEGR::BANDGAP, | |
7 => MUXNEGR::DAC, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `PIN0`"] | |
#[inline] | |
pub fn is_pin0(&self) -> bool { | |
*self == MUXNEGR::PIN0 | |
} | |
#[doc = "Checks if the value of the field is `PIN1`"] | |
#[inline] | |
pub fn is_pin1(&self) -> bool { | |
*self == MUXNEGR::PIN1 | |
} | |
#[doc = "Checks if the value of the field is `PIN2`"] | |
#[inline] | |
pub fn is_pin2(&self) -> bool { | |
*self == MUXNEGR::PIN2 | |
} | |
#[doc = "Checks if the value of the field is `PIN3`"] | |
#[inline] | |
pub fn is_pin3(&self) -> bool { | |
*self == MUXNEGR::PIN3 | |
} | |
#[doc = "Checks if the value of the field is `GND`"] | |
#[inline] | |
pub fn is_gnd(&self) -> bool { | |
*self == MUXNEGR::GND | |
} | |
#[doc = "Checks if the value of the field is `VSCALE`"] | |
#[inline] | |
pub fn is_vscale(&self) -> bool { | |
*self == MUXNEGR::VSCALE | |
} | |
#[doc = "Checks if the value of the field is `BANDGAP`"] | |
#[inline] | |
pub fn is_bandgap(&self) -> bool { | |
*self == MUXNEGR::BANDGAP | |
} | |
#[doc = "Checks if the value of the field is `DAC`"] | |
#[inline] | |
pub fn is_dac(&self) -> bool { | |
*self == MUXNEGR::DAC | |
} | |
} | |
#[doc = "Possible values of the field `MUXPOS`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum MUXPOSR { | |
#[doc = "I/O pin 0"] | |
PIN0, | |
#[doc = "I/O pin 1"] | |
PIN1, | |
#[doc = "I/O pin 2"] | |
PIN2, | |
#[doc = "I/O pin 3"] | |
PIN3, | |
} | |
impl MUXPOSR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
MUXPOSR::PIN0 => 0, | |
MUXPOSR::PIN1 => 0x01, | |
MUXPOSR::PIN2 => 0x02, | |
MUXPOSR::PIN3 => 0x03, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> MUXPOSR { | |
match value { | |
0 => MUXPOSR::PIN0, | |
1 => MUXPOSR::PIN1, | |
2 => MUXPOSR::PIN2, | |
3 => MUXPOSR::PIN3, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `PIN0`"] | |
#[inline] | |
pub fn is_pin0(&self) -> bool { | |
*self == MUXPOSR::PIN0 | |
} | |
#[doc = "Checks if the value of the field is `PIN1`"] | |
#[inline] | |
pub fn is_pin1(&self) -> bool { | |
*self == MUXPOSR::PIN1 | |
} | |
#[doc = "Checks if the value of the field is `PIN2`"] | |
#[inline] | |
pub fn is_pin2(&self) -> bool { | |
*self == MUXPOSR::PIN2 | |
} | |
#[doc = "Checks if the value of the field is `PIN3`"] | |
#[inline] | |
pub fn is_pin3(&self) -> bool { | |
*self == MUXPOSR::PIN3 | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWAPR { | |
bits: bool, | |
} | |
impl SWAPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `OUT`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum OUTR {# [ doc = "The output of COMPn is not routed to the COMPn I/O port" ] OFF , # [ doc = "The asynchronous output of COMPn is routed to the COMPn I/O port" ] ASYNC , # [ doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" ] SYNC , # [ doc = r" Reserved" ] _Reserved ( u8 )} | |
impl OUTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
OUTR::OFF => 0, | |
OUTR::ASYNC => 0x01, | |
OUTR::SYNC => 0x02, | |
OUTR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> OUTR { | |
match value { | |
0 => OUTR::OFF, | |
1 => OUTR::ASYNC, | |
2 => OUTR::SYNC, | |
i => OUTR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `OFF`"] | |
#[inline] | |
pub fn is_off(&self) -> bool { | |
*self == OUTR::OFF | |
} | |
#[doc = "Checks if the value of the field is `ASYNC`"] | |
#[inline] | |
pub fn is_async(&self) -> bool { | |
*self == OUTR::ASYNC | |
} | |
#[doc = "Checks if the value of the field is `SYNC`"] | |
#[inline] | |
pub fn is_sync(&self) -> bool { | |
*self == OUTR::SYNC | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct HYSTR { | |
bits: bool, | |
} | |
impl HYSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `FLEN`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum FLENR { | |
#[doc = "No filtering"] | |
OFF, | |
#[doc = "3-bit majority function (2 of 3)"] | |
MAJ3, | |
#[doc = "5-bit majority function (3 of 5)"] | |
MAJ5, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl FLENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
FLENR::OFF => 0, | |
FLENR::MAJ3 => 0x01, | |
FLENR::MAJ5 => 0x02, | |
FLENR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> FLENR { | |
match value { | |
0 => FLENR::OFF, | |
1 => FLENR::MAJ3, | |
2 => FLENR::MAJ5, | |
i => FLENR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `OFF`"] | |
#[inline] | |
pub fn is_off(&self) -> bool { | |
*self == FLENR::OFF | |
} | |
#[doc = "Checks if the value of the field is `MAJ3`"] | |
#[inline] | |
pub fn is_maj3(&self) -> bool { | |
*self == FLENR::MAJ3 | |
} | |
#[doc = "Checks if the value of the field is `MAJ5`"] | |
#[inline] | |
pub fn is_maj5(&self) -> bool { | |
*self == FLENR::MAJ5 | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SINGLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SINGLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SPEED`"] | |
pub enum SPEEDW { | |
#[doc = "Low speed"] | |
LOW, | |
#[doc = "High speed"] | |
HIGH, | |
} | |
impl SPEEDW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SPEEDW::LOW => 0, | |
SPEEDW::HIGH => 1, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SPEEDW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SPEEDW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SPEEDW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "Low speed"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SPEEDW::LOW) | |
} | |
#[doc = "High speed"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SPEEDW::HIGH) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `INTSEL`"] | |
pub enum INTSELW { | |
#[doc = "Interrupt on comparator output toggle"] | |
TOGGLE, | |
#[doc = "Interrupt on comparator output rising"] | |
RISING, | |
#[doc = "Interrupt on comparator output falling"] | |
FALLING, | |
#[doc = "Interrupt on end of comparison (single-shot mode only)"] | |
EOC, | |
} | |
impl INTSELW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
INTSELW::TOGGLE => 0, | |
INTSELW::RISING => 1, | |
INTSELW::FALLING => 2, | |
INTSELW::EOC => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _INTSELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _INTSELW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: INTSELW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "Interrupt on comparator output toggle"] | |
#[inline] | |
pub fn toggle(self) -> &'a mut W { | |
self.variant(INTSELW::TOGGLE) | |
} | |
#[doc = "Interrupt on comparator output rising"] | |
#[inline] | |
pub fn rising(self) -> &'a mut W { | |
self.variant(INTSELW::RISING) | |
} | |
#[doc = "Interrupt on comparator output falling"] | |
#[inline] | |
pub fn falling(self) -> &'a mut W { | |
self.variant(INTSELW::FALLING) | |
} | |
#[doc = "Interrupt on end of comparison (single-shot mode only)"] | |
#[inline] | |
pub fn eoc(self) -> &'a mut W { | |
self.variant(INTSELW::EOC) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `MUXNEG`"] | |
pub enum MUXNEGW { | |
#[doc = "I/O pin 0"] | |
PIN0, | |
#[doc = "I/O pin 1"] | |
PIN1, | |
#[doc = "I/O pin 2"] | |
PIN2, | |
#[doc = "I/O pin 3"] | |
PIN3, | |
#[doc = "Ground"] | |
GND, | |
#[doc = "VDD scaler"] | |
VSCALE, | |
#[doc = "Internal bandgap voltage"] | |
BANDGAP, | |
#[doc = "DAC output"] | |
DAC, | |
} | |
impl MUXNEGW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
MUXNEGW::PIN0 => 0, | |
MUXNEGW::PIN1 => 1, | |
MUXNEGW::PIN2 => 2, | |
MUXNEGW::PIN3 => 3, | |
MUXNEGW::GND => 4, | |
MUXNEGW::VSCALE => 5, | |
MUXNEGW::BANDGAP => 6, | |
MUXNEGW::DAC => 7, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _MUXNEGW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _MUXNEGW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: MUXNEGW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "I/O pin 0"] | |
#[inline] | |
pub fn pin0(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN0) | |
} | |
#[doc = "I/O pin 1"] | |
#[inline] | |
pub fn pin1(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN1) | |
} | |
#[doc = "I/O pin 2"] | |
#[inline] | |
pub fn pin2(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN2) | |
} | |
#[doc = "I/O pin 3"] | |
#[inline] | |
pub fn pin3(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN3) | |
} | |
#[doc = "Ground"] | |
#[inline] | |
pub fn gnd(self) -> &'a mut W { | |
self.variant(MUXNEGW::GND) | |
} | |
#[doc = "VDD scaler"] | |
#[inline] | |
pub fn vscale(self) -> &'a mut W { | |
self.variant(MUXNEGW::VSCALE) | |
} | |
#[doc = "Internal bandgap voltage"] | |
#[inline] | |
pub fn bandgap(self) -> &'a mut W { | |
self.variant(MUXNEGW::BANDGAP) | |
} | |
#[doc = "DAC output"] | |
#[inline] | |
pub fn dac(self) -> &'a mut W { | |
self.variant(MUXNEGW::DAC) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `MUXPOS`"] | |
pub enum MUXPOSW { | |
#[doc = "I/O pin 0"] | |
PIN0, | |
#[doc = "I/O pin 1"] | |
PIN1, | |
#[doc = "I/O pin 2"] | |
PIN2, | |
#[doc = "I/O pin 3"] | |
PIN3, | |
} | |
impl MUXPOSW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
MUXPOSW::PIN0 => 0, | |
MUXPOSW::PIN1 => 1, | |
MUXPOSW::PIN2 => 2, | |
MUXPOSW::PIN3 => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _MUXPOSW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _MUXPOSW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: MUXPOSW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "I/O pin 0"] | |
#[inline] | |
pub fn pin0(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN0) | |
} | |
#[doc = "I/O pin 1"] | |
#[inline] | |
pub fn pin1(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN1) | |
} | |
#[doc = "I/O pin 2"] | |
#[inline] | |
pub fn pin2(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN2) | |
} | |
#[doc = "I/O pin 3"] | |
#[inline] | |
pub fn pin3(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN3) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWAPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWAPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `OUT`"] | |
pub enum OUTW {# [ doc = "The output of COMPn is not routed to the COMPn I/O port" ] OFF , # [ doc = "The asynchronous output of COMPn is routed to the COMPn I/O port" ] ASYNC , # [ doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" ] SYNC} | |
impl OUTW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
OUTW::OFF => 0, | |
OUTW::ASYNC => 1, | |
OUTW::SYNC => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _OUTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _OUTW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: OUTW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "The output of COMPn is not routed to the COMPn I/O port"] | |
#[inline] | |
pub fn off(self) -> &'a mut W { | |
self.variant(OUTW::OFF) | |
} | |
#[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] | |
#[inline] | |
pub fn async(self) -> &'a mut W { | |
self.variant(OUTW::ASYNC) | |
} | |
# [ doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port" ] # [ inline ] | |
pub fn sync(self) -> &'a mut W { | |
self.variant(OUTW::SYNC) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 16; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _HYSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _HYSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 19; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `FLEN`"] | |
pub enum FLENW { | |
#[doc = "No filtering"] | |
OFF, | |
#[doc = "3-bit majority function (2 of 3)"] | |
MAJ3, | |
#[doc = "5-bit majority function (3 of 5)"] | |
MAJ5, | |
} | |
impl FLENW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
FLENW::OFF => 0, | |
FLENW::MAJ3 => 1, | |
FLENW::MAJ5 => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FLENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FLENW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: FLENW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No filtering"] | |
#[inline] | |
pub fn off(self) -> &'a mut W { | |
self.variant(FLENW::OFF) | |
} | |
#[doc = "3-bit majority function (2 of 3)"] | |
#[inline] | |
pub fn maj3(self) -> &'a mut W { | |
self.variant(FLENW::MAJ3) | |
} | |
#[doc = "5-bit majority function (3 of 5)"] | |
#[inline] | |
pub fn maj5(self) -> &'a mut W { | |
self.variant(FLENW::MAJ5) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
ENABLER { bits } | |
} | |
#[doc = "Bit 1 - Single-Shot Mode"] | |
#[inline] | |
pub fn single(&self) -> SINGLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SINGLER { bits } | |
} | |
#[doc = "Bits 2:3 - Speed Selection"] | |
#[inline] | |
pub fn speed(&self) -> SPEEDR { | |
SPEEDR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 5:6 - Interrupt Selection"] | |
#[inline] | |
pub fn intsel(&self) -> INTSELR { | |
INTSELR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 8:10 - Negative Input Mux Selection"] | |
#[inline] | |
pub fn muxneg(&self) -> MUXNEGR { | |
MUXNEGR::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 12:13 - Positive Input Mux Selection"] | |
#[inline] | |
pub fn muxpos(&self) -> MUXPOSR { | |
MUXPOSR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 15 - Swap Inputs and Invert"] | |
#[inline] | |
pub fn swap(&self) -> SWAPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWAPR { bits } | |
} | |
#[doc = "Bits 16:17 - Output"] | |
#[inline] | |
pub fn out(&self) -> OUTR { | |
OUTR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 19 - Hysteresis Enable"] | |
#[inline] | |
pub fn hyst(&self) -> HYSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 19; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
HYSTR { bits } | |
} | |
#[doc = "Bits 24:26 - Filter Length"] | |
#[inline] | |
pub fn flen(&self) -> FLENR { | |
FLENR::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
#[doc = "Bit 1 - Single-Shot Mode"] | |
#[inline] | |
pub fn single(&mut self) -> _SINGLEW { | |
_SINGLEW { w: self } | |
} | |
#[doc = "Bits 2:3 - Speed Selection"] | |
#[inline] | |
pub fn speed(&mut self) -> _SPEEDW { | |
_SPEEDW { w: self } | |
} | |
#[doc = "Bits 5:6 - Interrupt Selection"] | |
#[inline] | |
pub fn intsel(&mut self) -> _INTSELW { | |
_INTSELW { w: self } | |
} | |
#[doc = "Bits 8:10 - Negative Input Mux Selection"] | |
#[inline] | |
pub fn muxneg(&mut self) -> _MUXNEGW { | |
_MUXNEGW { w: self } | |
} | |
#[doc = "Bits 12:13 - Positive Input Mux Selection"] | |
#[inline] | |
pub fn muxpos(&mut self) -> _MUXPOSW { | |
_MUXPOSW { w: self } | |
} | |
#[doc = "Bit 15 - Swap Inputs and Invert"] | |
#[inline] | |
pub fn swap(&mut self) -> _SWAPW { | |
_SWAPW { w: self } | |
} | |
#[doc = "Bits 16:17 - Output"] | |
#[inline] | |
pub fn out(&mut self) -> _OUTW { | |
_OUTW { w: self } | |
} | |
#[doc = "Bit 19 - Hysteresis Enable"] | |
#[inline] | |
pub fn hyst(&mut self) -> _HYSTW { | |
_HYSTW { w: self } | |
} | |
#[doc = "Bits 24:26 - Filter Length"] | |
#[inline] | |
pub fn flen(&mut self) -> _FLENW { | |
_FLENW { w: self } | |
} | |
} | |
} | |
#[doc = "Control A"] | |
pub struct CTRLA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control A"] | |
pub mod ctrla { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRLA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RUNSTDBYR { | |
bits: bool, | |
} | |
impl RUNSTDBYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LPMUXR { | |
bits: bool, | |
} | |
impl LPMUXR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RUNSTDBYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RUNSTDBYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LPMUXW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LPMUXW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
ENABLER { bits } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&self) -> RUNSTDBYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RUNSTDBYR { bits } | |
} | |
#[doc = "Bit 7 - Low-Power Mux"] | |
#[inline] | |
pub fn lpmux(&self) -> LPMUXR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
LPMUXR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&mut self) -> _RUNSTDBYW { | |
_RUNSTDBYW { w: self } | |
} | |
#[doc = "Bit 7 - Low-Power Mux"] | |
#[inline] | |
pub fn lpmux(&mut self) -> _LPMUXW { | |
_LPMUXW { w: self } | |
} | |
} | |
} | |
#[doc = "Control B"] | |
pub struct CTRLB { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control B"] | |
pub mod ctrlb { | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRLB { | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _START0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _START0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _START1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _START1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Comparator 0 Start Comparison"] | |
#[inline] | |
pub fn start0(&mut self) -> _START0W { | |
_START0W { w: self } | |
} | |
#[doc = "Bit 1 - Comparator 1 Start Comparison"] | |
#[inline] | |
pub fn start1(&mut self) -> _START1W { | |
_START1W { w: self } | |
} | |
} | |
} | |
#[doc = "Event Control"] | |
pub struct EVCTRL { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Event Control"] | |
pub mod evctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::EVCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMPEO0R { | |
bits: bool, | |
} | |
impl COMPEO0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMPEO1R { | |
bits: bool, | |
} | |
impl COMPEO1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINEO0R { | |
bits: bool, | |
} | |
impl WINEO0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMPEI0R { | |
bits: bool, | |
} | |
impl COMPEI0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMPEI1R { | |
bits: bool, | |
} | |
impl COMPEI1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMPEO0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMPEO0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMPEO1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMPEO1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINEO0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINEO0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMPEI0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMPEI0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMPEI1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMPEI1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Event Output Enable"] | |
#[inline] | |
pub fn compeo0(&self) -> COMPEO0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
COMPEO0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Event Output Enable"] | |
#[inline] | |
pub fn compeo1(&self) -> COMPEO1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
COMPEO1R { bits } | |
} | |
#[doc = "Bit 4 - Window 0 Event Output Enable"] | |
#[inline] | |
pub fn wineo0(&self) -> WINEO0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
WINEO0R { bits } | |
} | |
#[doc = "Bit 8 - Comparator 0 Event Input"] | |
#[inline] | |
pub fn compei0(&self) -> COMPEI0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
COMPEI0R { bits } | |
} | |
#[doc = "Bit 9 - Comparator 1 Event Input"] | |
#[inline] | |
pub fn compei1(&self) -> COMPEI1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
COMPEI1R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Comparator 0 Event Output Enable"] | |
#[inline] | |
pub fn compeo0(&mut self) -> _COMPEO0W { | |
_COMPEO0W { w: self } | |
} | |
#[doc = "Bit 1 - Comparator 1 Event Output Enable"] | |
#[inline] | |
pub fn compeo1(&mut self) -> _COMPEO1W { | |
_COMPEO1W { w: self } | |
} | |
#[doc = "Bit 4 - Window 0 Event Output Enable"] | |
#[inline] | |
pub fn wineo0(&mut self) -> _WINEO0W { | |
_WINEO0W { w: self } | |
} | |
#[doc = "Bit 8 - Comparator 0 Event Input"] | |
#[inline] | |
pub fn compei0(&mut self) -> _COMPEI0W { | |
_COMPEI0W { w: self } | |
} | |
#[doc = "Bit 9 - Comparator 1 Event Input"] | |
#[inline] | |
pub fn compei1(&mut self) -> _COMPEI1W { | |
_COMPEI1W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub struct INTENCLR { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub mod intenclr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENCLR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP0R { | |
bits: bool, | |
} | |
impl COMP0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP1R { | |
bits: bool, | |
} | |
impl COMP1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WIN0R { | |
bits: bool, | |
} | |
impl WIN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WIN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WIN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Interrupt Enable"] | |
#[inline] | |
pub fn comp0(&self) -> COMP0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Interrupt Enable"] | |
#[inline] | |
pub fn comp1(&self) -> COMP1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP1R { bits } | |
} | |
#[doc = "Bit 4 - Window 0 Interrupt Enable"] | |
#[inline] | |
pub fn win0(&self) -> WIN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WIN0R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Comparator 0 Interrupt Enable"] | |
#[inline] | |
pub fn comp0(&mut self) -> _COMP0W { | |
_COMP0W { w: self } | |
} | |
#[doc = "Bit 1 - Comparator 1 Interrupt Enable"] | |
#[inline] | |
pub fn comp1(&mut self) -> _COMP1W { | |
_COMP1W { w: self } | |
} | |
#[doc = "Bit 4 - Window 0 Interrupt Enable"] | |
#[inline] | |
pub fn win0(&mut self) -> _WIN0W { | |
_WIN0W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub struct INTENSET { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub mod intenset { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENSET { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP0R { | |
bits: bool, | |
} | |
impl COMP0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP1R { | |
bits: bool, | |
} | |
impl COMP1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WIN0R { | |
bits: bool, | |
} | |
impl WIN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WIN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WIN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Interrupt Enable"] | |
#[inline] | |
pub fn comp0(&self) -> COMP0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Interrupt Enable"] | |
#[inline] | |
pub fn comp1(&self) -> COMP1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP1R { bits } | |
} | |
#[doc = "Bit 4 - Window 0 Interrupt Enable"] | |
#[inline] | |
pub fn win0(&self) -> WIN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WIN0R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Comparator 0 Interrupt Enable"] | |
#[inline] | |
pub fn comp0(&mut self) -> _COMP0W { | |
_COMP0W { w: self } | |
} | |
#[doc = "Bit 1 - Comparator 1 Interrupt Enable"] | |
#[inline] | |
pub fn comp1(&mut self) -> _COMP1W { | |
_COMP1W { w: self } | |
} | |
#[doc = "Bit 4 - Window 0 Interrupt Enable"] | |
#[inline] | |
pub fn win0(&mut self) -> _WIN0W { | |
_WIN0W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub struct INTFLAG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub mod intflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP0R { | |
bits: bool, | |
} | |
impl COMP0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct COMP1R { | |
bits: bool, | |
} | |
impl COMP1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WIN0R { | |
bits: bool, | |
} | |
impl WIN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _COMP1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _COMP1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WIN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WIN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0"] | |
#[inline] | |
pub fn comp0(&self) -> COMP0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1"] | |
#[inline] | |
pub fn comp1(&self) -> COMP1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
COMP1R { bits } | |
} | |
#[doc = "Bit 4 - Window 0"] | |
#[inline] | |
pub fn win0(&self) -> WIN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WIN0R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Comparator 0"] | |
#[inline] | |
pub fn comp0(&mut self) -> _COMP0W { | |
_COMP0W { w: self } | |
} | |
#[doc = "Bit 1 - Comparator 1"] | |
#[inline] | |
pub fn comp1(&mut self) -> _COMP1W { | |
_COMP1W { w: self } | |
} | |
#[doc = "Bit 4 - Window 0"] | |
#[inline] | |
pub fn win0(&mut self) -> _WIN0W { | |
_WIN0W { w: self } | |
} | |
} | |
} | |
#[doc = "Scaler n"] | |
pub struct SCALER { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Scaler n"] | |
pub mod scaler { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::SCALER { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct VALUER { | |
bits: u8, | |
} | |
impl VALUER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _VALUEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _VALUEW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:5 - Scaler Value"] | |
#[inline] | |
pub fn value(&self) -> VALUER { | |
let bits = { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}; | |
VALUER { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:5 - Scaler Value"] | |
#[inline] | |
pub fn value(&mut self) -> _VALUEW { | |
_VALUEW { w: self } | |
} | |
} | |
} | |
#[doc = "Status A"] | |
pub struct STATUSA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status A"] | |
pub mod statusa { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUSA { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STATE0R { | |
bits: bool, | |
} | |
impl STATE0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STATE1R { | |
bits: bool, | |
} | |
impl STATE1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `WSTATE0`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum WSTATE0R { | |
#[doc = "Signal is above window"] | |
ABOVE, | |
#[doc = "Signal is inside window"] | |
INSIDE, | |
#[doc = "Signal is below window"] | |
BELOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl WSTATE0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
WSTATE0R::ABOVE => 0, | |
WSTATE0R::INSIDE => 0x01, | |
WSTATE0R::BELOW => 0x02, | |
WSTATE0R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> WSTATE0R { | |
match value { | |
0 => WSTATE0R::ABOVE, | |
1 => WSTATE0R::INSIDE, | |
2 => WSTATE0R::BELOW, | |
i => WSTATE0R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `ABOVE`"] | |
#[inline] | |
pub fn is_above(&self) -> bool { | |
*self == WSTATE0R::ABOVE | |
} | |
#[doc = "Checks if the value of the field is `INSIDE`"] | |
#[inline] | |
pub fn is_inside(&self) -> bool { | |
*self == WSTATE0R::INSIDE | |
} | |
#[doc = "Checks if the value of the field is `BELOW`"] | |
#[inline] | |
pub fn is_below(&self) -> bool { | |
*self == WSTATE0R::BELOW | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Current State"] | |
#[inline] | |
pub fn state0(&self) -> STATE0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STATE0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Current State"] | |
#[inline] | |
pub fn state1(&self) -> STATE1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STATE1R { bits } | |
} | |
#[doc = "Bits 4:5 - Window 0 Current State"] | |
#[inline] | |
pub fn wstate0(&self) -> WSTATE0R { | |
WSTATE0R::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
} | |
} | |
#[doc = "Status B"] | |
pub struct STATUSB { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status B"] | |
pub mod statusb { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUSB { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct READY0R { | |
bits: bool, | |
} | |
impl READY0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct READY1R { | |
bits: bool, | |
} | |
impl READY1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCBUSYR { | |
bits: bool, | |
} | |
impl SYNCBUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Ready"] | |
#[inline] | |
pub fn ready0(&self) -> READY0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
READY0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Ready"] | |
#[inline] | |
pub fn ready1(&self) -> READY1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
READY1R { bits } | |
} | |
#[doc = "Bit 7 - Synchronization Busy"] | |
#[inline] | |
pub fn syncbusy(&self) -> SYNCBUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCBUSYR { bits } | |
} | |
} | |
} | |
#[doc = "Status C"] | |
pub struct STATUSC { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status C"] | |
pub mod statusc { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUSC { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STATE0R { | |
bits: bool, | |
} | |
impl STATE0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STATE1R { | |
bits: bool, | |
} | |
impl STATE1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `WSTATE0`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum WSTATE0R { | |
#[doc = "Signal is above window"] | |
ABOVE, | |
#[doc = "Signal is inside window"] | |
INSIDE, | |
#[doc = "Signal is below window"] | |
BELOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl WSTATE0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
WSTATE0R::ABOVE => 0, | |
WSTATE0R::INSIDE => 0x01, | |
WSTATE0R::BELOW => 0x02, | |
WSTATE0R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> WSTATE0R { | |
match value { | |
0 => WSTATE0R::ABOVE, | |
1 => WSTATE0R::INSIDE, | |
2 => WSTATE0R::BELOW, | |
i => WSTATE0R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `ABOVE`"] | |
#[inline] | |
pub fn is_above(&self) -> bool { | |
*self == WSTATE0R::ABOVE | |
} | |
#[doc = "Checks if the value of the field is `INSIDE`"] | |
#[inline] | |
pub fn is_inside(&self) -> bool { | |
*self == WSTATE0R::INSIDE | |
} | |
#[doc = "Checks if the value of the field is `BELOW`"] | |
#[inline] | |
pub fn is_below(&self) -> bool { | |
*self == WSTATE0R::BELOW | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Comparator 0 Current State"] | |
#[inline] | |
pub fn state0(&self) -> STATE0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STATE0R { bits } | |
} | |
#[doc = "Bit 1 - Comparator 1 Current State"] | |
#[inline] | |
pub fn state1(&self) -> STATE1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STATE1R { bits } | |
} | |
#[doc = "Bits 4:5 - Window 0 Current State"] | |
#[inline] | |
pub fn wstate0(&self) -> WSTATE0R { | |
WSTATE0R::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
} | |
} | |
#[doc = "Window Control"] | |
pub struct WINCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Window Control"] | |
pub mod winctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::WINCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WEN0R { | |
bits: bool, | |
} | |
impl WEN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `WINTSEL0`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum WINTSEL0R { | |
#[doc = "Interrupt on signal above window"] | |
ABOVE, | |
#[doc = "Interrupt on signal inside window"] | |
INSIDE, | |
#[doc = "Interrupt on signal below window"] | |
BELOW, | |
#[doc = "Interrupt on signal outside window"] | |
OUTSIDE, | |
} | |
impl WINTSEL0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
WINTSEL0R::ABOVE => 0, | |
WINTSEL0R::INSIDE => 0x01, | |
WINTSEL0R::BELOW => 0x02, | |
WINTSEL0R::OUTSIDE => 0x03, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> WINTSEL0R { | |
match value { | |
0 => WINTSEL0R::ABOVE, | |
1 => WINTSEL0R::INSIDE, | |
2 => WINTSEL0R::BELOW, | |
3 => WINTSEL0R::OUTSIDE, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `ABOVE`"] | |
#[inline] | |
pub fn is_above(&self) -> bool { | |
*self == WINTSEL0R::ABOVE | |
} | |
#[doc = "Checks if the value of the field is `INSIDE`"] | |
#[inline] | |
pub fn is_inside(&self) -> bool { | |
*self == WINTSEL0R::INSIDE | |
} | |
#[doc = "Checks if the value of the field is `BELOW`"] | |
#[inline] | |
pub fn is_below(&self) -> bool { | |
*self == WINTSEL0R::BELOW | |
} | |
#[doc = "Checks if the value of the field is `OUTSIDE`"] | |
#[inline] | |
pub fn is_outside(&self) -> bool { | |
*self == WINTSEL0R::OUTSIDE | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WEN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WEN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `WINTSEL0`"] | |
pub enum WINTSEL0W { | |
#[doc = "Interrupt on signal above window"] | |
ABOVE, | |
#[doc = "Interrupt on signal inside window"] | |
INSIDE, | |
#[doc = "Interrupt on signal below window"] | |
BELOW, | |
#[doc = "Interrupt on signal outside window"] | |
OUTSIDE, | |
} | |
impl WINTSEL0W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
WINTSEL0W::ABOVE => 0, | |
WINTSEL0W::INSIDE => 1, | |
WINTSEL0W::BELOW => 2, | |
WINTSEL0W::OUTSIDE => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINTSEL0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINTSEL0W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: WINTSEL0W) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "Interrupt on signal above window"] | |
#[inline] | |
pub fn above(self) -> &'a mut W { | |
self.variant(WINTSEL0W::ABOVE) | |
} | |
#[doc = "Interrupt on signal inside window"] | |
#[inline] | |
pub fn inside(self) -> &'a mut W { | |
self.variant(WINTSEL0W::INSIDE) | |
} | |
#[doc = "Interrupt on signal below window"] | |
#[inline] | |
pub fn below(self) -> &'a mut W { | |
self.variant(WINTSEL0W::BELOW) | |
} | |
#[doc = "Interrupt on signal outside window"] | |
#[inline] | |
pub fn outside(self) -> &'a mut W { | |
self.variant(WINTSEL0W::OUTSIDE) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Window 0 Mode Enable"] | |
#[inline] | |
pub fn wen0(&self) -> WEN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WEN0R { bits } | |
} | |
#[doc = "Bits 1:2 - Window 0 Interrupt Selection"] | |
#[inline] | |
pub fn wintsel0(&self) -> WINTSEL0R { | |
WINTSEL0R::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Window 0 Mode Enable"] | |
#[inline] | |
pub fn wen0(&mut self) -> _WEN0W { | |
_WEN0W { w: self } | |
} | |
#[doc = "Bits 1:2 - Window 0 Interrupt Selection"] | |
#[inline] | |
pub fn wintsel0(&mut self) -> _WINTSEL0W { | |
_WINTSEL0W { w: self } | |
} | |
} | |
} | |
} | |
#[doc = "Analog Digital Converter"] | |
pub struct ADC { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for ADC {} | |
impl ADC { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const adc::RegisterBlock { | |
0x4200_4000 as *const _ | |
} | |
} | |
impl Deref for ADC { | |
type Target = adc::RegisterBlock; | |
fn deref(&self) -> &adc::RegisterBlock { | |
unsafe { &*ADC::ptr() } | |
} | |
} | |
#[doc = "Analog Digital Converter"] | |
pub mod adc { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control A"] | |
pub ctrla: CTRLA, | |
#[doc = "0x01 - Reference Control"] | |
pub refctrl: REFCTRL, | |
#[doc = "0x02 - Average Control"] | |
pub avgctrl: AVGCTRL, | |
#[doc = "0x03 - Sampling Time Control"] | |
pub sampctrl: SAMPCTRL, | |
#[doc = "0x04 - Control B"] | |
pub ctrlb: CTRLB, | |
_reserved0: [u8; 2usize], | |
#[doc = "0x08 - Window Monitor Control"] | |
pub winctrl: WINCTRL, | |
_reserved1: [u8; 3usize], | |
#[doc = "0x0c - Software Trigger"] | |
pub swtrig: SWTRIG, | |
_reserved2: [u8; 3usize], | |
#[doc = "0x10 - Input Control"] | |
pub inputctrl: INPUTCTRL, | |
#[doc = "0x14 - Event Control"] | |
pub evctrl: EVCTRL, | |
_reserved3: [u8; 1usize], | |
#[doc = "0x16 - Interrupt Enable Clear"] | |
pub intenclr: INTENCLR, | |
#[doc = "0x17 - Interrupt Enable Set"] | |
pub intenset: INTENSET, | |
#[doc = "0x18 - Interrupt Flag Status and Clear"] | |
pub intflag: INTFLAG, | |
#[doc = "0x19 - Status"] | |
pub status: STATUS, | |
#[doc = "0x1a - Result"] | |
pub result: RESULT, | |
#[doc = "0x1c - Window Monitor Lower Threshold"] | |
pub winlt: WINLT, | |
_reserved4: [u8; 2usize], | |
#[doc = "0x20 - Window Monitor Upper Threshold"] | |
pub winut: WINUT, | |
_reserved5: [u8; 2usize], | |
#[doc = "0x24 - Gain Correction"] | |
pub gaincorr: GAINCORR, | |
#[doc = "0x26 - Offset Correction"] | |
pub offsetcorr: OFFSETCORR, | |
#[doc = "0x28 - Calibration"] | |
pub calib: CALIB, | |
#[doc = "0x2a - Debug Control"] | |
pub dbgctrl: DBGCTRL, | |
} | |
#[doc = "Average Control"] | |
pub struct AVGCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Average Control"] | |
pub mod avgctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::AVGCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `SAMPLENUM`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SAMPLENUMR { | |
#[doc = "1 sample"] | |
_1, | |
#[doc = "2 samples"] | |
_2, | |
#[doc = "4 samples"] | |
_4, | |
#[doc = "8 samples"] | |
_8, | |
#[doc = "16 samples"] | |
_16, | |
#[doc = "32 samples"] | |
_32, | |
#[doc = "64 samples"] | |
_64, | |
#[doc = "128 samples"] | |
_128, | |
#[doc = "256 samples"] | |
_256, | |
#[doc = "512 samples"] | |
_512, | |
#[doc = "1024 samples"] | |
_1024, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SAMPLENUMR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SAMPLENUMR::_1 => 0, | |
SAMPLENUMR::_2 => 0x01, | |
SAMPLENUMR::_4 => 0x02, | |
SAMPLENUMR::_8 => 0x03, | |
SAMPLENUMR::_16 => 0x04, | |
SAMPLENUMR::_32 => 0x05, | |
SAMPLENUMR::_64 => 0x06, | |
SAMPLENUMR::_128 => 0x07, | |
SAMPLENUMR::_256 => 0x08, | |
SAMPLENUMR::_512 => 0x09, | |
SAMPLENUMR::_1024 => 0x0a, | |
SAMPLENUMR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SAMPLENUMR { | |
match value { | |
0 => SAMPLENUMR::_1, | |
1 => SAMPLENUMR::_2, | |
2 => SAMPLENUMR::_4, | |
3 => SAMPLENUMR::_8, | |
4 => SAMPLENUMR::_16, | |
5 => SAMPLENUMR::_32, | |
6 => SAMPLENUMR::_64, | |
7 => SAMPLENUMR::_128, | |
8 => SAMPLENUMR::_256, | |
9 => SAMPLENUMR::_512, | |
10 => SAMPLENUMR::_1024, | |
i => SAMPLENUMR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `_1`"] | |
#[inline] | |
pub fn is_1(&self) -> bool { | |
*self == SAMPLENUMR::_1 | |
} | |
#[doc = "Checks if the value of the field is `_2`"] | |
#[inline] | |
pub fn is_2(&self) -> bool { | |
*self == SAMPLENUMR::_2 | |
} | |
#[doc = "Checks if the value of the field is `_4`"] | |
#[inline] | |
pub fn is_4(&self) -> bool { | |
*self == SAMPLENUMR::_4 | |
} | |
#[doc = "Checks if the value of the field is `_8`"] | |
#[inline] | |
pub fn is_8(&self) -> bool { | |
*self == SAMPLENUMR::_8 | |
} | |
#[doc = "Checks if the value of the field is `_16`"] | |
#[inline] | |
pub fn is_16(&self) -> bool { | |
*self == SAMPLENUMR::_16 | |
} | |
#[doc = "Checks if the value of the field is `_32`"] | |
#[inline] | |
pub fn is_32(&self) -> bool { | |
*self == SAMPLENUMR::_32 | |
} | |
#[doc = "Checks if the value of the field is `_64`"] | |
#[inline] | |
pub fn is_64(&self) -> bool { | |
*self == SAMPLENUMR::_64 | |
} | |
#[doc = "Checks if the value of the field is `_128`"] | |
#[inline] | |
pub fn is_128(&self) -> bool { | |
*self == SAMPLENUMR::_128 | |
} | |
#[doc = "Checks if the value of the field is `_256`"] | |
#[inline] | |
pub fn is_256(&self) -> bool { | |
*self == SAMPLENUMR::_256 | |
} | |
#[doc = "Checks if the value of the field is `_512`"] | |
#[inline] | |
pub fn is_512(&self) -> bool { | |
*self == SAMPLENUMR::_512 | |
} | |
#[doc = "Checks if the value of the field is `_1024`"] | |
#[inline] | |
pub fn is_1024(&self) -> bool { | |
*self == SAMPLENUMR::_1024 | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ADJRESR { | |
bits: u8, | |
} | |
impl ADJRESR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = "Values that can be written to the field `SAMPLENUM`"] | |
pub enum SAMPLENUMW { | |
#[doc = "1 sample"] | |
_1, | |
#[doc = "2 samples"] | |
_2, | |
#[doc = "4 samples"] | |
_4, | |
#[doc = "8 samples"] | |
_8, | |
#[doc = "16 samples"] | |
_16, | |
#[doc = "32 samples"] | |
_32, | |
#[doc = "64 samples"] | |
_64, | |
#[doc = "128 samples"] | |
_128, | |
#[doc = "256 samples"] | |
_256, | |
#[doc = "512 samples"] | |
_512, | |
#[doc = "1024 samples"] | |
_1024, | |
} | |
impl SAMPLENUMW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SAMPLENUMW::_1 => 0, | |
SAMPLENUMW::_2 => 1, | |
SAMPLENUMW::_4 => 2, | |
SAMPLENUMW::_8 => 3, | |
SAMPLENUMW::_16 => 4, | |
SAMPLENUMW::_32 => 5, | |
SAMPLENUMW::_64 => 6, | |
SAMPLENUMW::_128 => 7, | |
SAMPLENUMW::_256 => 8, | |
SAMPLENUMW::_512 => 9, | |
SAMPLENUMW::_1024 => 10, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SAMPLENUMW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SAMPLENUMW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SAMPLENUMW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "1 sample"] | |
#[inline] | |
pub fn _1(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_1) | |
} | |
#[doc = "2 samples"] | |
#[inline] | |
pub fn _2(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_2) | |
} | |
#[doc = "4 samples"] | |
#[inline] | |
pub fn _4(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_4) | |
} | |
#[doc = "8 samples"] | |
#[inline] | |
pub fn _8(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_8) | |
} | |
#[doc = "16 samples"] | |
#[inline] | |
pub fn _16(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_16) | |
} | |
#[doc = "32 samples"] | |
#[inline] | |
pub fn _32(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_32) | |
} | |
#[doc = "64 samples"] | |
#[inline] | |
pub fn _64(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_64) | |
} | |
#[doc = "128 samples"] | |
#[inline] | |
pub fn _128(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_128) | |
} | |
#[doc = "256 samples"] | |
#[inline] | |
pub fn _256(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_256) | |
} | |
#[doc = "512 samples"] | |
#[inline] | |
pub fn _512(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_512) | |
} | |
#[doc = "1024 samples"] | |
#[inline] | |
pub fn _1024(self) -> &'a mut W { | |
self.variant(SAMPLENUMW::_1024) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ADJRESW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ADJRESW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Number of Samples to be Collected"] | |
#[inline] | |
pub fn samplenum(&self) -> SAMPLENUMR { | |
SAMPLENUMR::_from({ | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
#[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] | |
#[inline] | |
pub fn adjres(&self) -> ADJRESR { | |
let bits = { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}; | |
ADJRESR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Number of Samples to be Collected"] | |
#[inline] | |
pub fn samplenum(&mut self) -> _SAMPLENUMW { | |
_SAMPLENUMW { w: self } | |
} | |
#[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] | |
#[inline] | |
pub fn adjres(&mut self) -> _ADJRESW { | |
_ADJRESW { w: self } | |
} | |
} | |
} | |
#[doc = "Calibration"] | |
pub struct CALIB { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Calibration"] | |
pub mod calib { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::CALIB { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LINEARITY_CALR { | |
bits: u8, | |
} | |
impl LINEARITY_CALR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BIAS_CALR { | |
bits: u8, | |
} | |
impl BIAS_CALR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LINEARITY_CALW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LINEARITY_CALW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _BIAS_CALW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _BIAS_CALW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Linearity Calibration Value"] | |
#[inline] | |
pub fn linearity_cal(&self) -> LINEARITY_CALR { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}; | |
LINEARITY_CALR { bits } | |
} | |
#[doc = "Bits 8:10 - Bias Calibration Value"] | |
#[inline] | |
pub fn bias_cal(&self) -> BIAS_CALR { | |
let bits = { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}; | |
BIAS_CALR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:7 - Linearity Calibration Value"] | |
#[inline] | |
pub fn linearity_cal(&mut self) -> _LINEARITY_CALW { | |
_LINEARITY_CALW { w: self } | |
} | |
#[doc = "Bits 8:10 - Bias Calibration Value"] | |
#[inline] | |
pub fn bias_cal(&mut self) -> _BIAS_CALW { | |
_BIAS_CALW { w: self } | |
} | |
} | |
} | |
#[doc = "Control A"] | |
pub struct CTRLA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control A"] | |
pub mod ctrla { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRLA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWRSTR { | |
bits: bool, | |
} | |
impl SWRSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RUNSTDBYR { | |
bits: bool, | |
} | |
impl RUNSTDBYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RUNSTDBYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RUNSTDBYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&self) -> SWRSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SWRSTR { bits } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
ENABLER { bits } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&self) -> RUNSTDBYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RUNSTDBYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&mut self) -> _RUNSTDBYW { | |
_RUNSTDBYW { w: self } | |
} | |
} | |
} | |
#[doc = "Control B"] | |
pub struct CTRLB { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Control B"] | |
pub mod ctrlb { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::CTRLB { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DIFFMODER { | |
bits: bool, | |
} | |
impl DIFFMODER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LEFTADJR { | |
bits: bool, | |
} | |
impl LEFTADJR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FREERUNR { | |
bits: bool, | |
} | |
impl FREERUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CORRENR { | |
bits: bool, | |
} | |
impl CORRENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `RESSEL`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum RESSELR { | |
#[doc = "12-bit result"] | |
_12BIT, | |
#[doc = "For averaging mode output"] | |
_16BIT, | |
#[doc = "10-bit result"] | |
_10BIT, | |
#[doc = "8-bit result"] | |
_8BIT, | |
} | |
impl RESSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
RESSELR::_12BIT => 0, | |
RESSELR::_16BIT => 0x01, | |
RESSELR::_10BIT => 0x02, | |
RESSELR::_8BIT => 0x03, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> RESSELR { | |
match value { | |
0 => RESSELR::_12BIT, | |
1 => RESSELR::_16BIT, | |
2 => RESSELR::_10BIT, | |
3 => RESSELR::_8BIT, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `_12BIT`"] | |
#[inline] | |
pub fn is_12bit(&self) -> bool { | |
*self == RESSELR::_12BIT | |
} | |
#[doc = "Checks if the value of the field is `_16BIT`"] | |
#[inline] | |
pub fn is_16bit(&self) -> bool { | |
*self == RESSELR::_16BIT | |
} | |
#[doc = "Checks if the value of the field is `_10BIT`"] | |
#[inline] | |
pub fn is_10bit(&self) -> bool { | |
*self == RESSELR::_10BIT | |
} | |
#[doc = "Checks if the value of the field is `_8BIT`"] | |
#[inline] | |
pub fn is_8bit(&self) -> bool { | |
*self == RESSELR::_8BIT | |
} | |
} | |
#[doc = "Possible values of the field `PRESCALER`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum PRESCALERR { | |
#[doc = "Peripheral clock divided by 4"] | |
DIV4, | |
#[doc = "Peripheral clock divided by 8"] | |
DIV8, | |
#[doc = "Peripheral clock divided by 16"] | |
DIV16, | |
#[doc = "Peripheral clock divided by 32"] | |
DIV32, | |
#[doc = "Peripheral clock divided by 64"] | |
DIV64, | |
#[doc = "Peripheral clock divided by 128"] | |
DIV128, | |
#[doc = "Peripheral clock divided by 256"] | |
DIV256, | |
#[doc = "Peripheral clock divided by 512"] | |
DIV512, | |
} | |
impl PRESCALERR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
PRESCALERR::DIV4 => 0, | |
PRESCALERR::DIV8 => 0x01, | |
PRESCALERR::DIV16 => 0x02, | |
PRESCALERR::DIV32 => 0x03, | |
PRESCALERR::DIV64 => 0x04, | |
PRESCALERR::DIV128 => 0x05, | |
PRESCALERR::DIV256 => 0x06, | |
PRESCALERR::DIV512 => 0x07, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> PRESCALERR { | |
match value { | |
0 => PRESCALERR::DIV4, | |
1 => PRESCALERR::DIV8, | |
2 => PRESCALERR::DIV16, | |
3 => PRESCALERR::DIV32, | |
4 => PRESCALERR::DIV64, | |
5 => PRESCALERR::DIV128, | |
6 => PRESCALERR::DIV256, | |
7 => PRESCALERR::DIV512, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `DIV4`"] | |
#[inline] | |
pub fn is_div4(&self) -> bool { | |
*self == PRESCALERR::DIV4 | |
} | |
#[doc = "Checks if the value of the field is `DIV8`"] | |
#[inline] | |
pub fn is_div8(&self) -> bool { | |
*self == PRESCALERR::DIV8 | |
} | |
#[doc = "Checks if the value of the field is `DIV16`"] | |
#[inline] | |
pub fn is_div16(&self) -> bool { | |
*self == PRESCALERR::DIV16 | |
} | |
#[doc = "Checks if the value of the field is `DIV32`"] | |
#[inline] | |
pub fn is_div32(&self) -> bool { | |
*self == PRESCALERR::DIV32 | |
} | |
#[doc = "Checks if the value of the field is `DIV64`"] | |
#[inline] | |
pub fn is_div64(&self) -> bool { | |
*self == PRESCALERR::DIV64 | |
} | |
#[doc = "Checks if the value of the field is `DIV128`"] | |
#[inline] | |
pub fn is_div128(&self) -> bool { | |
*self == PRESCALERR::DIV128 | |
} | |
#[doc = "Checks if the value of the field is `DIV256`"] | |
#[inline] | |
pub fn is_div256(&self) -> bool { | |
*self == PRESCALERR::DIV256 | |
} | |
#[doc = "Checks if the value of the field is `DIV512`"] | |
#[inline] | |
pub fn is_div512(&self) -> bool { | |
*self == PRESCALERR::DIV512 | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DIFFMODEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DIFFMODEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LEFTADJW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LEFTADJW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FREERUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FREERUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CORRENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CORRENW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `RESSEL`"] | |
pub enum RESSELW { | |
#[doc = "12-bit result"] | |
_12BIT, | |
#[doc = "For averaging mode output"] | |
_16BIT, | |
#[doc = "10-bit result"] | |
_10BIT, | |
#[doc = "8-bit result"] | |
_8BIT, | |
} | |
impl RESSELW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
RESSELW::_12BIT => 0, | |
RESSELW::_16BIT => 1, | |
RESSELW::_10BIT => 2, | |
RESSELW::_8BIT => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RESSELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RESSELW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: RESSELW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "12-bit result"] | |
#[inline] | |
pub fn _12bit(self) -> &'a mut W { | |
self.variant(RESSELW::_12BIT) | |
} | |
#[doc = "For averaging mode output"] | |
#[inline] | |
pub fn _16bit(self) -> &'a mut W { | |
self.variant(RESSELW::_16BIT) | |
} | |
#[doc = "10-bit result"] | |
#[inline] | |
pub fn _10bit(self) -> &'a mut W { | |
self.variant(RESSELW::_10BIT) | |
} | |
#[doc = "8-bit result"] | |
#[inline] | |
pub fn _8bit(self) -> &'a mut W { | |
self.variant(RESSELW::_8BIT) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `PRESCALER`"] | |
pub enum PRESCALERW { | |
#[doc = "Peripheral clock divided by 4"] | |
DIV4, | |
#[doc = "Peripheral clock divided by 8"] | |
DIV8, | |
#[doc = "Peripheral clock divided by 16"] | |
DIV16, | |
#[doc = "Peripheral clock divided by 32"] | |
DIV32, | |
#[doc = "Peripheral clock divided by 64"] | |
DIV64, | |
#[doc = "Peripheral clock divided by 128"] | |
DIV128, | |
#[doc = "Peripheral clock divided by 256"] | |
DIV256, | |
#[doc = "Peripheral clock divided by 512"] | |
DIV512, | |
} | |
impl PRESCALERW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
PRESCALERW::DIV4 => 0, | |
PRESCALERW::DIV8 => 1, | |
PRESCALERW::DIV16 => 2, | |
PRESCALERW::DIV32 => 3, | |
PRESCALERW::DIV64 => 4, | |
PRESCALERW::DIV128 => 5, | |
PRESCALERW::DIV256 => 6, | |
PRESCALERW::DIV512 => 7, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _PRESCALERW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _PRESCALERW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: PRESCALERW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "Peripheral clock divided by 4"] | |
#[inline] | |
pub fn div4(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV4) | |
} | |
#[doc = "Peripheral clock divided by 8"] | |
#[inline] | |
pub fn div8(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV8) | |
} | |
#[doc = "Peripheral clock divided by 16"] | |
#[inline] | |
pub fn div16(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV16) | |
} | |
#[doc = "Peripheral clock divided by 32"] | |
#[inline] | |
pub fn div32(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV32) | |
} | |
#[doc = "Peripheral clock divided by 64"] | |
#[inline] | |
pub fn div64(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV64) | |
} | |
#[doc = "Peripheral clock divided by 128"] | |
#[inline] | |
pub fn div128(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV128) | |
} | |
#[doc = "Peripheral clock divided by 256"] | |
#[inline] | |
pub fn div256(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV256) | |
} | |
#[doc = "Peripheral clock divided by 512"] | |
#[inline] | |
pub fn div512(self) -> &'a mut W { | |
self.variant(PRESCALERW::DIV512) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Differential Mode"] | |
#[inline] | |
pub fn diffmode(&self) -> DIFFMODER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
DIFFMODER { bits } | |
} | |
#[doc = "Bit 1 - Left-Adjusted Result"] | |
#[inline] | |
pub fn leftadj(&self) -> LEFTADJR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
LEFTADJR { bits } | |
} | |
#[doc = "Bit 2 - Free Running Mode"] | |
#[inline] | |
pub fn freerun(&self) -> FREERUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
FREERUNR { bits } | |
} | |
#[doc = "Bit 3 - Digital Correction Logic Enabled"] | |
#[inline] | |
pub fn corren(&self) -> CORRENR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
CORRENR { bits } | |
} | |
#[doc = "Bits 4:5 - Conversion Result Resolution"] | |
#[inline] | |
pub fn ressel(&self) -> RESSELR { | |
RESSELR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}) | |
} | |
#[doc = "Bits 8:10 - Prescaler Configuration"] | |
#[inline] | |
pub fn prescaler(&self) -> PRESCALERR { | |
PRESCALERR::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Differential Mode"] | |
#[inline] | |
pub fn diffmode(&mut self) -> _DIFFMODEW { | |
_DIFFMODEW { w: self } | |
} | |
#[doc = "Bit 1 - Left-Adjusted Result"] | |
#[inline] | |
pub fn leftadj(&mut self) -> _LEFTADJW { | |
_LEFTADJW { w: self } | |
} | |
#[doc = "Bit 2 - Free Running Mode"] | |
#[inline] | |
pub fn freerun(&mut self) -> _FREERUNW { | |
_FREERUNW { w: self } | |
} | |
#[doc = "Bit 3 - Digital Correction Logic Enabled"] | |
#[inline] | |
pub fn corren(&mut self) -> _CORRENW { | |
_CORRENW { w: self } | |
} | |
#[doc = "Bits 4:5 - Conversion Result Resolution"] | |
#[inline] | |
pub fn ressel(&mut self) -> _RESSELW { | |
_RESSELW { w: self } | |
} | |
#[doc = "Bits 8:10 - Prescaler Configuration"] | |
#[inline] | |
pub fn prescaler(&mut self) -> _PRESCALERW { | |
_PRESCALERW { w: self } | |
} | |
} | |
} | |
#[doc = "Debug Control"] | |
pub struct DBGCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Debug Control"] | |
pub mod dbgctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::DBGCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DBGRUNR { | |
bits: bool, | |
} | |
impl DBGRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DBGRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DBGRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Debug Run"] | |
#[inline] | |
pub fn dbgrun(&self) -> DBGRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DBGRUNR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Debug Run"] | |
#[inline] | |
pub fn dbgrun(&mut self) -> _DBGRUNW { | |
_DBGRUNW { w: self } | |
} | |
} | |
} | |
#[doc = "Event Control"] | |
pub struct EVCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Event Control"] | |
pub mod evctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::EVCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STARTEIR { | |
bits: bool, | |
} | |
impl STARTEIR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCEIR { | |
bits: bool, | |
} | |
impl SYNCEIR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RESRDYEOR { | |
bits: bool, | |
} | |
impl RESRDYEOR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINMONEOR { | |
bits: bool, | |
} | |
impl WINMONEOR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _STARTEIW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _STARTEIW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCEIW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCEIW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RESRDYEOW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RESRDYEOW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINMONEOW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINMONEOW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Start Conversion Event In"] | |
#[inline] | |
pub fn startei(&self) -> STARTEIR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STARTEIR { bits } | |
} | |
#[doc = "Bit 1 - Synchronization Event In"] | |
#[inline] | |
pub fn syncei(&self) -> SYNCEIR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCEIR { bits } | |
} | |
#[doc = "Bit 4 - Result Ready Event Out"] | |
#[inline] | |
pub fn resrdyeo(&self) -> RESRDYEOR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RESRDYEOR { bits } | |
} | |
#[doc = "Bit 5 - Window Monitor Event Out"] | |
#[inline] | |
pub fn winmoneo(&self) -> WINMONEOR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WINMONEOR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Start Conversion Event In"] | |
#[inline] | |
pub fn startei(&mut self) -> _STARTEIW { | |
_STARTEIW { w: self } | |
} | |
#[doc = "Bit 1 - Synchronization Event In"] | |
#[inline] | |
pub fn syncei(&mut self) -> _SYNCEIW { | |
_SYNCEIW { w: self } | |
} | |
#[doc = "Bit 4 - Result Ready Event Out"] | |
#[inline] | |
pub fn resrdyeo(&mut self) -> _RESRDYEOW { | |
_RESRDYEOW { w: self } | |
} | |
#[doc = "Bit 5 - Window Monitor Event Out"] | |
#[inline] | |
pub fn winmoneo(&mut self) -> _WINMONEOW { | |
_WINMONEOW { w: self } | |
} | |
} | |
} | |
#[doc = "Gain Correction"] | |
pub struct GAINCORR { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Gain Correction"] | |
pub mod gaincorr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::GAINCORR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct GAINCORRR { | |
bits: u16, | |
} | |
impl GAINCORRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _GAINCORRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _GAINCORRW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0x0fff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:11 - Gain Correction Value"] | |
#[inline] | |
pub fn gaincorr(&self) -> GAINCORRR { | |
let bits = { | |
const MASK: u16 = 0x0fff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
GAINCORRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:11 - Gain Correction Value"] | |
#[inline] | |
pub fn gaincorr(&mut self) -> _GAINCORRW { | |
_GAINCORRW { w: self } | |
} | |
} | |
} | |
#[doc = "Input Control"] | |
pub struct INPUTCTRL { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Input Control"] | |
pub mod inputctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::INPUTCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `MUXPOS`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum MUXPOSR { | |
#[doc = "ADC AIN0 Pin"] | |
PIN0, | |
#[doc = "ADC AIN1 Pin"] | |
PIN1, | |
#[doc = "ADC AIN2 Pin"] | |
PIN2, | |
#[doc = "ADC AIN3 Pin"] | |
PIN3, | |
#[doc = "ADC AIN4 Pin"] | |
PIN4, | |
#[doc = "ADC AIN5 Pin"] | |
PIN5, | |
#[doc = "ADC AIN6 Pin"] | |
PIN6, | |
#[doc = "ADC AIN7 Pin"] | |
PIN7, | |
#[doc = "ADC AIN8 Pin"] | |
PIN8, | |
#[doc = "ADC AIN9 Pin"] | |
PIN9, | |
#[doc = "ADC AIN10 Pin"] | |
PIN10, | |
#[doc = "ADC AIN11 Pin"] | |
PIN11, | |
#[doc = "ADC AIN12 Pin"] | |
PIN12, | |
#[doc = "ADC AIN13 Pin"] | |
PIN13, | |
#[doc = "ADC AIN14 Pin"] | |
PIN14, | |
#[doc = "ADC AIN15 Pin"] | |
PIN15, | |
#[doc = "ADC AIN16 Pin"] | |
PIN16, | |
#[doc = "ADC AIN17 Pin"] | |
PIN17, | |
#[doc = "ADC AIN18 Pin"] | |
PIN18, | |
#[doc = "ADC AIN19 Pin"] | |
PIN19, | |
#[doc = "Temperature Reference"] | |
TEMP, | |
#[doc = "Bandgap Voltage"] | |
BANDGAP, | |
#[doc = "1/4 Scaled Core Supply"] | |
SCALEDCOREVCC, | |
#[doc = "1/4 Scaled I/O Supply"] | |
SCALEDIOVCC, | |
#[doc = "DAC Output"] | |
DAC, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl MUXPOSR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
MUXPOSR::PIN0 => 0, | |
MUXPOSR::PIN1 => 0x01, | |
MUXPOSR::PIN2 => 0x02, | |
MUXPOSR::PIN3 => 0x03, | |
MUXPOSR::PIN4 => 0x04, | |
MUXPOSR::PIN5 => 0x05, | |
MUXPOSR::PIN6 => 0x06, | |
MUXPOSR::PIN7 => 0x07, | |
MUXPOSR::PIN8 => 0x08, | |
MUXPOSR::PIN9 => 0x09, | |
MUXPOSR::PIN10 => 0x0a, | |
MUXPOSR::PIN11 => 0x0b, | |
MUXPOSR::PIN12 => 0x0c, | |
MUXPOSR::PIN13 => 0x0d, | |
MUXPOSR::PIN14 => 0x0e, | |
MUXPOSR::PIN15 => 0x0f, | |
MUXPOSR::PIN16 => 0x10, | |
MUXPOSR::PIN17 => 0x11, | |
MUXPOSR::PIN18 => 0x12, | |
MUXPOSR::PIN19 => 0x13, | |
MUXPOSR::TEMP => 0x18, | |
MUXPOSR::BANDGAP => 0x19, | |
MUXPOSR::SCALEDCOREVCC => 0x1a, | |
MUXPOSR::SCALEDIOVCC => 0x1b, | |
MUXPOSR::DAC => 0x1c, | |
MUXPOSR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> MUXPOSR { | |
match value { | |
0 => MUXPOSR::PIN0, | |
1 => MUXPOSR::PIN1, | |
2 => MUXPOSR::PIN2, | |
3 => MUXPOSR::PIN3, | |
4 => MUXPOSR::PIN4, | |
5 => MUXPOSR::PIN5, | |
6 => MUXPOSR::PIN6, | |
7 => MUXPOSR::PIN7, | |
8 => MUXPOSR::PIN8, | |
9 => MUXPOSR::PIN9, | |
10 => MUXPOSR::PIN10, | |
11 => MUXPOSR::PIN11, | |
12 => MUXPOSR::PIN12, | |
13 => MUXPOSR::PIN13, | |
14 => MUXPOSR::PIN14, | |
15 => MUXPOSR::PIN15, | |
16 => MUXPOSR::PIN16, | |
17 => MUXPOSR::PIN17, | |
18 => MUXPOSR::PIN18, | |
19 => MUXPOSR::PIN19, | |
24 => MUXPOSR::TEMP, | |
25 => MUXPOSR::BANDGAP, | |
26 => MUXPOSR::SCALEDCOREVCC, | |
27 => MUXPOSR::SCALEDIOVCC, | |
28 => MUXPOSR::DAC, | |
i => MUXPOSR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `PIN0`"] | |
#[inline] | |
pub fn is_pin0(&self) -> bool { | |
*self == MUXPOSR::PIN0 | |
} | |
#[doc = "Checks if the value of the field is `PIN1`"] | |
#[inline] | |
pub fn is_pin1(&self) -> bool { | |
*self == MUXPOSR::PIN1 | |
} | |
#[doc = "Checks if the value of the field is `PIN2`"] | |
#[inline] | |
pub fn is_pin2(&self) -> bool { | |
*self == MUXPOSR::PIN2 | |
} | |
#[doc = "Checks if the value of the field is `PIN3`"] | |
#[inline] | |
pub fn is_pin3(&self) -> bool { | |
*self == MUXPOSR::PIN3 | |
} | |
#[doc = "Checks if the value of the field is `PIN4`"] | |
#[inline] | |
pub fn is_pin4(&self) -> bool { | |
*self == MUXPOSR::PIN4 | |
} | |
#[doc = "Checks if the value of the field is `PIN5`"] | |
#[inline] | |
pub fn is_pin5(&self) -> bool { | |
*self == MUXPOSR::PIN5 | |
} | |
#[doc = "Checks if the value of the field is `PIN6`"] | |
#[inline] | |
pub fn is_pin6(&self) -> bool { | |
*self == MUXPOSR::PIN6 | |
} | |
#[doc = "Checks if the value of the field is `PIN7`"] | |
#[inline] | |
pub fn is_pin7(&self) -> bool { | |
*self == MUXPOSR::PIN7 | |
} | |
#[doc = "Checks if the value of the field is `PIN8`"] | |
#[inline] | |
pub fn is_pin8(&self) -> bool { | |
*self == MUXPOSR::PIN8 | |
} | |
#[doc = "Checks if the value of the field is `PIN9`"] | |
#[inline] | |
pub fn is_pin9(&self) -> bool { | |
*self == MUXPOSR::PIN9 | |
} | |
#[doc = "Checks if the value of the field is `PIN10`"] | |
#[inline] | |
pub fn is_pin10(&self) -> bool { | |
*self == MUXPOSR::PIN10 | |
} | |
#[doc = "Checks if the value of the field is `PIN11`"] | |
#[inline] | |
pub fn is_pin11(&self) -> bool { | |
*self == MUXPOSR::PIN11 | |
} | |
#[doc = "Checks if the value of the field is `PIN12`"] | |
#[inline] | |
pub fn is_pin12(&self) -> bool { | |
*self == MUXPOSR::PIN12 | |
} | |
#[doc = "Checks if the value of the field is `PIN13`"] | |
#[inline] | |
pub fn is_pin13(&self) -> bool { | |
*self == MUXPOSR::PIN13 | |
} | |
#[doc = "Checks if the value of the field is `PIN14`"] | |
#[inline] | |
pub fn is_pin14(&self) -> bool { | |
*self == MUXPOSR::PIN14 | |
} | |
#[doc = "Checks if the value of the field is `PIN15`"] | |
#[inline] | |
pub fn is_pin15(&self) -> bool { | |
*self == MUXPOSR::PIN15 | |
} | |
#[doc = "Checks if the value of the field is `PIN16`"] | |
#[inline] | |
pub fn is_pin16(&self) -> bool { | |
*self == MUXPOSR::PIN16 | |
} | |
#[doc = "Checks if the value of the field is `PIN17`"] | |
#[inline] | |
pub fn is_pin17(&self) -> bool { | |
*self == MUXPOSR::PIN17 | |
} | |
#[doc = "Checks if the value of the field is `PIN18`"] | |
#[inline] | |
pub fn is_pin18(&self) -> bool { | |
*self == MUXPOSR::PIN18 | |
} | |
#[doc = "Checks if the value of the field is `PIN19`"] | |
#[inline] | |
pub fn is_pin19(&self) -> bool { | |
*self == MUXPOSR::PIN19 | |
} | |
#[doc = "Checks if the value of the field is `TEMP`"] | |
#[inline] | |
pub fn is_temp(&self) -> bool { | |
*self == MUXPOSR::TEMP | |
} | |
#[doc = "Checks if the value of the field is `BANDGAP`"] | |
#[inline] | |
pub fn is_bandgap(&self) -> bool { | |
*self == MUXPOSR::BANDGAP | |
} | |
#[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] | |
#[inline] | |
pub fn is_scaledcorevcc(&self) -> bool { | |
*self == MUXPOSR::SCALEDCOREVCC | |
} | |
#[doc = "Checks if the value of the field is `SCALEDIOVCC`"] | |
#[inline] | |
pub fn is_scalediovcc(&self) -> bool { | |
*self == MUXPOSR::SCALEDIOVCC | |
} | |
#[doc = "Checks if the value of the field is `DAC`"] | |
#[inline] | |
pub fn is_dac(&self) -> bool { | |
*self == MUXPOSR::DAC | |
} | |
} | |
#[doc = "Possible values of the field `MUXNEG`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum MUXNEGR { | |
#[doc = "ADC AIN0 Pin"] | |
PIN0, | |
#[doc = "ADC AIN1 Pin"] | |
PIN1, | |
#[doc = "ADC AIN2 Pin"] | |
PIN2, | |
#[doc = "ADC AIN3 Pin"] | |
PIN3, | |
#[doc = "ADC AIN4 Pin"] | |
PIN4, | |
#[doc = "ADC AIN5 Pin"] | |
PIN5, | |
#[doc = "ADC AIN6 Pin"] | |
PIN6, | |
#[doc = "ADC AIN7 Pin"] | |
PIN7, | |
#[doc = "Internal Ground"] | |
GND, | |
#[doc = "I/O Ground"] | |
IOGND, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl MUXNEGR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
MUXNEGR::PIN0 => 0, | |
MUXNEGR::PIN1 => 0x01, | |
MUXNEGR::PIN2 => 0x02, | |
MUXNEGR::PIN3 => 0x03, | |
MUXNEGR::PIN4 => 0x04, | |
MUXNEGR::PIN5 => 0x05, | |
MUXNEGR::PIN6 => 0x06, | |
MUXNEGR::PIN7 => 0x07, | |
MUXNEGR::GND => 0x18, | |
MUXNEGR::IOGND => 0x19, | |
MUXNEGR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> MUXNEGR { | |
match value { | |
0 => MUXNEGR::PIN0, | |
1 => MUXNEGR::PIN1, | |
2 => MUXNEGR::PIN2, | |
3 => MUXNEGR::PIN3, | |
4 => MUXNEGR::PIN4, | |
5 => MUXNEGR::PIN5, | |
6 => MUXNEGR::PIN6, | |
7 => MUXNEGR::PIN7, | |
24 => MUXNEGR::GND, | |
25 => MUXNEGR::IOGND, | |
i => MUXNEGR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `PIN0`"] | |
#[inline] | |
pub fn is_pin0(&self) -> bool { | |
*self == MUXNEGR::PIN0 | |
} | |
#[doc = "Checks if the value of the field is `PIN1`"] | |
#[inline] | |
pub fn is_pin1(&self) -> bool { | |
*self == MUXNEGR::PIN1 | |
} | |
#[doc = "Checks if the value of the field is `PIN2`"] | |
#[inline] | |
pub fn is_pin2(&self) -> bool { | |
*self == MUXNEGR::PIN2 | |
} | |
#[doc = "Checks if the value of the field is `PIN3`"] | |
#[inline] | |
pub fn is_pin3(&self) -> bool { | |
*self == MUXNEGR::PIN3 | |
} | |
#[doc = "Checks if the value of the field is `PIN4`"] | |
#[inline] | |
pub fn is_pin4(&self) -> bool { | |
*self == MUXNEGR::PIN4 | |
} | |
#[doc = "Checks if the value of the field is `PIN5`"] | |
#[inline] | |
pub fn is_pin5(&self) -> bool { | |
*self == MUXNEGR::PIN5 | |
} | |
#[doc = "Checks if the value of the field is `PIN6`"] | |
#[inline] | |
pub fn is_pin6(&self) -> bool { | |
*self == MUXNEGR::PIN6 | |
} | |
#[doc = "Checks if the value of the field is `PIN7`"] | |
#[inline] | |
pub fn is_pin7(&self) -> bool { | |
*self == MUXNEGR::PIN7 | |
} | |
#[doc = "Checks if the value of the field is `GND`"] | |
#[inline] | |
pub fn is_gnd(&self) -> bool { | |
*self == MUXNEGR::GND | |
} | |
#[doc = "Checks if the value of the field is `IOGND`"] | |
#[inline] | |
pub fn is_iognd(&self) -> bool { | |
*self == MUXNEGR::IOGND | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct INPUTSCANR { | |
bits: u8, | |
} | |
impl INPUTSCANR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct INPUTOFFSETR { | |
bits: u8, | |
} | |
impl INPUTOFFSETR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = "Possible values of the field `GAIN`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum GAINR { | |
#[doc = "1x"] | |
_1X, | |
#[doc = "2x"] | |
_2X, | |
#[doc = "4x"] | |
_4X, | |
#[doc = "8x"] | |
_8X, | |
#[doc = "16x"] | |
_16X, | |
#[doc = "1/2x"] | |
DIV2, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl GAINR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
GAINR::_1X => 0, | |
GAINR::_2X => 0x01, | |
GAINR::_4X => 0x02, | |
GAINR::_8X => 0x03, | |
GAINR::_16X => 0x04, | |
GAINR::DIV2 => 0x0f, | |
GAINR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> GAINR { | |
match value { | |
0 => GAINR::_1X, | |
1 => GAINR::_2X, | |
2 => GAINR::_4X, | |
3 => GAINR::_8X, | |
4 => GAINR::_16X, | |
15 => GAINR::DIV2, | |
i => GAINR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `_1X`"] | |
#[inline] | |
pub fn is_1x(&self) -> bool { | |
*self == GAINR::_1X | |
} | |
#[doc = "Checks if the value of the field is `_2X`"] | |
#[inline] | |
pub fn is_2x(&self) -> bool { | |
*self == GAINR::_2X | |
} | |
#[doc = "Checks if the value of the field is `_4X`"] | |
#[inline] | |
pub fn is_4x(&self) -> bool { | |
*self == GAINR::_4X | |
} | |
#[doc = "Checks if the value of the field is `_8X`"] | |
#[inline] | |
pub fn is_8x(&self) -> bool { | |
*self == GAINR::_8X | |
} | |
#[doc = "Checks if the value of the field is `_16X`"] | |
#[inline] | |
pub fn is_16x(&self) -> bool { | |
*self == GAINR::_16X | |
} | |
#[doc = "Checks if the value of the field is `DIV2`"] | |
#[inline] | |
pub fn is_div2(&self) -> bool { | |
*self == GAINR::DIV2 | |
} | |
} | |
#[doc = "Values that can be written to the field `MUXPOS`"] | |
pub enum MUXPOSW { | |
#[doc = "ADC AIN0 Pin"] | |
PIN0, | |
#[doc = "ADC AIN1 Pin"] | |
PIN1, | |
#[doc = "ADC AIN2 Pin"] | |
PIN2, | |
#[doc = "ADC AIN3 Pin"] | |
PIN3, | |
#[doc = "ADC AIN4 Pin"] | |
PIN4, | |
#[doc = "ADC AIN5 Pin"] | |
PIN5, | |
#[doc = "ADC AIN6 Pin"] | |
PIN6, | |
#[doc = "ADC AIN7 Pin"] | |
PIN7, | |
#[doc = "ADC AIN8 Pin"] | |
PIN8, | |
#[doc = "ADC AIN9 Pin"] | |
PIN9, | |
#[doc = "ADC AIN10 Pin"] | |
PIN10, | |
#[doc = "ADC AIN11 Pin"] | |
PIN11, | |
#[doc = "ADC AIN12 Pin"] | |
PIN12, | |
#[doc = "ADC AIN13 Pin"] | |
PIN13, | |
#[doc = "ADC AIN14 Pin"] | |
PIN14, | |
#[doc = "ADC AIN15 Pin"] | |
PIN15, | |
#[doc = "ADC AIN16 Pin"] | |
PIN16, | |
#[doc = "ADC AIN17 Pin"] | |
PIN17, | |
#[doc = "ADC AIN18 Pin"] | |
PIN18, | |
#[doc = "ADC AIN19 Pin"] | |
PIN19, | |
#[doc = "Temperature Reference"] | |
TEMP, | |
#[doc = "Bandgap Voltage"] | |
BANDGAP, | |
#[doc = "1/4 Scaled Core Supply"] | |
SCALEDCOREVCC, | |
#[doc = "1/4 Scaled I/O Supply"] | |
SCALEDIOVCC, | |
#[doc = "DAC Output"] | |
DAC, | |
} | |
impl MUXPOSW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
MUXPOSW::PIN0 => 0, | |
MUXPOSW::PIN1 => 1, | |
MUXPOSW::PIN2 => 2, | |
MUXPOSW::PIN3 => 3, | |
MUXPOSW::PIN4 => 4, | |
MUXPOSW::PIN5 => 5, | |
MUXPOSW::PIN6 => 6, | |
MUXPOSW::PIN7 => 7, | |
MUXPOSW::PIN8 => 8, | |
MUXPOSW::PIN9 => 9, | |
MUXPOSW::PIN10 => 10, | |
MUXPOSW::PIN11 => 11, | |
MUXPOSW::PIN12 => 12, | |
MUXPOSW::PIN13 => 13, | |
MUXPOSW::PIN14 => 14, | |
MUXPOSW::PIN15 => 15, | |
MUXPOSW::PIN16 => 16, | |
MUXPOSW::PIN17 => 17, | |
MUXPOSW::PIN18 => 18, | |
MUXPOSW::PIN19 => 19, | |
MUXPOSW::TEMP => 24, | |
MUXPOSW::BANDGAP => 25, | |
MUXPOSW::SCALEDCOREVCC => 26, | |
MUXPOSW::SCALEDIOVCC => 27, | |
MUXPOSW::DAC => 28, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _MUXPOSW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _MUXPOSW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: MUXPOSW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "ADC AIN0 Pin"] | |
#[inline] | |
pub fn pin0(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN0) | |
} | |
#[doc = "ADC AIN1 Pin"] | |
#[inline] | |
pub fn pin1(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN1) | |
} | |
#[doc = "ADC AIN2 Pin"] | |
#[inline] | |
pub fn pin2(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN2) | |
} | |
#[doc = "ADC AIN3 Pin"] | |
#[inline] | |
pub fn pin3(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN3) | |
} | |
#[doc = "ADC AIN4 Pin"] | |
#[inline] | |
pub fn pin4(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN4) | |
} | |
#[doc = "ADC AIN5 Pin"] | |
#[inline] | |
pub fn pin5(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN5) | |
} | |
#[doc = "ADC AIN6 Pin"] | |
#[inline] | |
pub fn pin6(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN6) | |
} | |
#[doc = "ADC AIN7 Pin"] | |
#[inline] | |
pub fn pin7(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN7) | |
} | |
#[doc = "ADC AIN8 Pin"] | |
#[inline] | |
pub fn pin8(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN8) | |
} | |
#[doc = "ADC AIN9 Pin"] | |
#[inline] | |
pub fn pin9(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN9) | |
} | |
#[doc = "ADC AIN10 Pin"] | |
#[inline] | |
pub fn pin10(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN10) | |
} | |
#[doc = "ADC AIN11 Pin"] | |
#[inline] | |
pub fn pin11(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN11) | |
} | |
#[doc = "ADC AIN12 Pin"] | |
#[inline] | |
pub fn pin12(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN12) | |
} | |
#[doc = "ADC AIN13 Pin"] | |
#[inline] | |
pub fn pin13(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN13) | |
} | |
#[doc = "ADC AIN14 Pin"] | |
#[inline] | |
pub fn pin14(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN14) | |
} | |
#[doc = "ADC AIN15 Pin"] | |
#[inline] | |
pub fn pin15(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN15) | |
} | |
#[doc = "ADC AIN16 Pin"] | |
#[inline] | |
pub fn pin16(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN16) | |
} | |
#[doc = "ADC AIN17 Pin"] | |
#[inline] | |
pub fn pin17(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN17) | |
} | |
#[doc = "ADC AIN18 Pin"] | |
#[inline] | |
pub fn pin18(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN18) | |
} | |
#[doc = "ADC AIN19 Pin"] | |
#[inline] | |
pub fn pin19(self) -> &'a mut W { | |
self.variant(MUXPOSW::PIN19) | |
} | |
#[doc = "Temperature Reference"] | |
#[inline] | |
pub fn temp(self) -> &'a mut W { | |
self.variant(MUXPOSW::TEMP) | |
} | |
#[doc = "Bandgap Voltage"] | |
#[inline] | |
pub fn bandgap(self) -> &'a mut W { | |
self.variant(MUXPOSW::BANDGAP) | |
} | |
#[doc = "1/4 Scaled Core Supply"] | |
#[inline] | |
pub fn scaledcorevcc(self) -> &'a mut W { | |
self.variant(MUXPOSW::SCALEDCOREVCC) | |
} | |
#[doc = "1/4 Scaled I/O Supply"] | |
#[inline] | |
pub fn scalediovcc(self) -> &'a mut W { | |
self.variant(MUXPOSW::SCALEDIOVCC) | |
} | |
#[doc = "DAC Output"] | |
#[inline] | |
pub fn dac(self) -> &'a mut W { | |
self.variant(MUXPOSW::DAC) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `MUXNEG`"] | |
pub enum MUXNEGW { | |
#[doc = "ADC AIN0 Pin"] | |
PIN0, | |
#[doc = "ADC AIN1 Pin"] | |
PIN1, | |
#[doc = "ADC AIN2 Pin"] | |
PIN2, | |
#[doc = "ADC AIN3 Pin"] | |
PIN3, | |
#[doc = "ADC AIN4 Pin"] | |
PIN4, | |
#[doc = "ADC AIN5 Pin"] | |
PIN5, | |
#[doc = "ADC AIN6 Pin"] | |
PIN6, | |
#[doc = "ADC AIN7 Pin"] | |
PIN7, | |
#[doc = "Internal Ground"] | |
GND, | |
#[doc = "I/O Ground"] | |
IOGND, | |
} | |
impl MUXNEGW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
MUXNEGW::PIN0 => 0, | |
MUXNEGW::PIN1 => 1, | |
MUXNEGW::PIN2 => 2, | |
MUXNEGW::PIN3 => 3, | |
MUXNEGW::PIN4 => 4, | |
MUXNEGW::PIN5 => 5, | |
MUXNEGW::PIN6 => 6, | |
MUXNEGW::PIN7 => 7, | |
MUXNEGW::GND => 24, | |
MUXNEGW::IOGND => 25, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _MUXNEGW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _MUXNEGW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: MUXNEGW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "ADC AIN0 Pin"] | |
#[inline] | |
pub fn pin0(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN0) | |
} | |
#[doc = "ADC AIN1 Pin"] | |
#[inline] | |
pub fn pin1(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN1) | |
} | |
#[doc = "ADC AIN2 Pin"] | |
#[inline] | |
pub fn pin2(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN2) | |
} | |
#[doc = "ADC AIN3 Pin"] | |
#[inline] | |
pub fn pin3(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN3) | |
} | |
#[doc = "ADC AIN4 Pin"] | |
#[inline] | |
pub fn pin4(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN4) | |
} | |
#[doc = "ADC AIN5 Pin"] | |
#[inline] | |
pub fn pin5(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN5) | |
} | |
#[doc = "ADC AIN6 Pin"] | |
#[inline] | |
pub fn pin6(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN6) | |
} | |
#[doc = "ADC AIN7 Pin"] | |
#[inline] | |
pub fn pin7(self) -> &'a mut W { | |
self.variant(MUXNEGW::PIN7) | |
} | |
#[doc = "Internal Ground"] | |
#[inline] | |
pub fn gnd(self) -> &'a mut W { | |
self.variant(MUXNEGW::GND) | |
} | |
#[doc = "I/O Ground"] | |
#[inline] | |
pub fn iognd(self) -> &'a mut W { | |
self.variant(MUXNEGW::IOGND) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _INPUTSCANW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _INPUTSCANW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 16; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _INPUTOFFSETW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _INPUTOFFSETW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 20; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `GAIN`"] | |
pub enum GAINW { | |
#[doc = "1x"] | |
_1X, | |
#[doc = "2x"] | |
_2X, | |
#[doc = "4x"] | |
_4X, | |
#[doc = "8x"] | |
_8X, | |
#[doc = "16x"] | |
_16X, | |
#[doc = "1/2x"] | |
DIV2, | |
} | |
impl GAINW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
GAINW::_1X => 0, | |
GAINW::_2X => 1, | |
GAINW::_4X => 2, | |
GAINW::_8X => 3, | |
GAINW::_16X => 4, | |
GAINW::DIV2 => 15, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _GAINW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _GAINW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: GAINW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "1x"] | |
#[inline] | |
pub fn _1x(self) -> &'a mut W { | |
self.variant(GAINW::_1X) | |
} | |
#[doc = "2x"] | |
#[inline] | |
pub fn _2x(self) -> &'a mut W { | |
self.variant(GAINW::_2X) | |
} | |
#[doc = "4x"] | |
#[inline] | |
pub fn _4x(self) -> &'a mut W { | |
self.variant(GAINW::_4X) | |
} | |
#[doc = "8x"] | |
#[inline] | |
pub fn _8x(self) -> &'a mut W { | |
self.variant(GAINW::_8X) | |
} | |
#[doc = "16x"] | |
#[inline] | |
pub fn _16x(self) -> &'a mut W { | |
self.variant(GAINW::_16X) | |
} | |
#[doc = "1/2x"] | |
#[inline] | |
pub fn div2(self) -> &'a mut W { | |
self.variant(GAINW::DIV2) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:4 - Positive Mux Input Selection"] | |
#[inline] | |
pub fn muxpos(&self) -> MUXPOSR { | |
MUXPOSR::_from({ | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 8:12 - Negative Mux Input Selection"] | |
#[inline] | |
pub fn muxneg(&self) -> MUXNEGR { | |
MUXNEGR::_from({ | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] | |
#[inline] | |
pub fn inputscan(&self) -> INPUTSCANR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
INPUTSCANR { bits } | |
} | |
#[doc = "Bits 20:23 - Positive Mux Setting Offset"] | |
#[inline] | |
pub fn inputoffset(&self) -> INPUTOFFSETR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 20; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
INPUTOFFSETR { bits } | |
} | |
#[doc = "Bits 24:27 - Gain Factor Selection"] | |
#[inline] | |
pub fn gain(&self) -> GAINR { | |
GAINR::_from({ | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:4 - Positive Mux Input Selection"] | |
#[inline] | |
pub fn muxpos(&mut self) -> _MUXPOSW { | |
_MUXPOSW { w: self } | |
} | |
#[doc = "Bits 8:12 - Negative Mux Input Selection"] | |
#[inline] | |
pub fn muxneg(&mut self) -> _MUXNEGW { | |
_MUXNEGW { w: self } | |
} | |
#[doc = "Bits 16:19 - Number of Input Channels Included in Scan"] | |
#[inline] | |
pub fn inputscan(&mut self) -> _INPUTSCANW { | |
_INPUTSCANW { w: self } | |
} | |
#[doc = "Bits 20:23 - Positive Mux Setting Offset"] | |
#[inline] | |
pub fn inputoffset(&mut self) -> _INPUTOFFSETW { | |
_INPUTOFFSETW { w: self } | |
} | |
#[doc = "Bits 24:27 - Gain Factor Selection"] | |
#[inline] | |
pub fn gain(&mut self) -> _GAINW { | |
_GAINW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub struct INTENCLR { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub mod intenclr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENCLR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RESRDYR { | |
bits: bool, | |
} | |
impl RESRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct OVERRUNR { | |
bits: bool, | |
} | |
impl OVERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINMONR { | |
bits: bool, | |
} | |
impl WINMONR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RESRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RESRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _OVERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _OVERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINMONW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINMONW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Result Ready Interrupt Enable"] | |
#[inline] | |
pub fn resrdy(&self) -> RESRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RESRDYR { bits } | |
} | |
#[doc = "Bit 1 - Overrun Interrupt Enable"] | |
#[inline] | |
pub fn overrun(&self) -> OVERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
OVERRUNR { bits } | |
} | |
#[doc = "Bit 2 - Window Monitor Interrupt Enable"] | |
#[inline] | |
pub fn winmon(&self) -> WINMONR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WINMONR { bits } | |
} | |
#[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Result Ready Interrupt Enable"] | |
#[inline] | |
pub fn resrdy(&mut self) -> _RESRDYW { | |
_RESRDYW { w: self } | |
} | |
#[doc = "Bit 1 - Overrun Interrupt Enable"] | |
#[inline] | |
pub fn overrun(&mut self) -> _OVERRUNW { | |
_OVERRUNW { w: self } | |
} | |
#[doc = "Bit 2 - Window Monitor Interrupt Enable"] | |
#[inline] | |
pub fn winmon(&mut self) -> _WINMONW { | |
_WINMONW { w: self } | |
} | |
#[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub struct INTENSET { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub mod intenset { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENSET { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RESRDYR { | |
bits: bool, | |
} | |
impl RESRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct OVERRUNR { | |
bits: bool, | |
} | |
impl OVERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINMONR { | |
bits: bool, | |
} | |
impl WINMONR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RESRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RESRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _OVERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _OVERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINMONW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINMONW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Result Ready Interrupt Enable"] | |
#[inline] | |
pub fn resrdy(&self) -> RESRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RESRDYR { bits } | |
} | |
#[doc = "Bit 1 - Overrun Interrupt Enable"] | |
#[inline] | |
pub fn overrun(&self) -> OVERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
OVERRUNR { bits } | |
} | |
#[doc = "Bit 2 - Window Monitor Interrupt Enable"] | |
#[inline] | |
pub fn winmon(&self) -> WINMONR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WINMONR { bits } | |
} | |
#[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Result Ready Interrupt Enable"] | |
#[inline] | |
pub fn resrdy(&mut self) -> _RESRDYW { | |
_RESRDYW { w: self } | |
} | |
#[doc = "Bit 1 - Overrun Interrupt Enable"] | |
#[inline] | |
pub fn overrun(&mut self) -> _OVERRUNW { | |
_OVERRUNW { w: self } | |
} | |
#[doc = "Bit 2 - Window Monitor Interrupt Enable"] | |
#[inline] | |
pub fn winmon(&mut self) -> _WINMONW { | |
_WINMONW { w: self } | |
} | |
#[doc = "Bit 3 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub struct INTFLAG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub mod intflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RESRDYR { | |
bits: bool, | |
} | |
impl RESRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct OVERRUNR { | |
bits: bool, | |
} | |
impl OVERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINMONR { | |
bits: bool, | |
} | |
impl WINMONR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RESRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RESRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _OVERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _OVERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINMONW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINMONW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Result Ready"] | |
#[inline] | |
pub fn resrdy(&self) -> RESRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RESRDYR { bits } | |
} | |
#[doc = "Bit 1 - Overrun"] | |
#[inline] | |
pub fn overrun(&self) -> OVERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
OVERRUNR { bits } | |
} | |
#[doc = "Bit 2 - Window Monitor"] | |
#[inline] | |
pub fn winmon(&self) -> WINMONR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
WINMONR { bits } | |
} | |
#[doc = "Bit 3 - Synchronization Ready"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Result Ready"] | |
#[inline] | |
pub fn resrdy(&mut self) -> _RESRDYW { | |
_RESRDYW { w: self } | |
} | |
#[doc = "Bit 1 - Overrun"] | |
#[inline] | |
pub fn overrun(&mut self) -> _OVERRUNW { | |
_OVERRUNW { w: self } | |
} | |
#[doc = "Bit 2 - Window Monitor"] | |
#[inline] | |
pub fn winmon(&mut self) -> _WINMONW { | |
_WINMONW { w: self } | |
} | |
#[doc = "Bit 3 - Synchronization Ready"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Offset Correction"] | |
pub struct OFFSETCORR { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Offset Correction"] | |
pub mod offsetcorr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::OFFSETCORR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct OFFSETCORRR { | |
bits: u16, | |
} | |
impl OFFSETCORRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _OFFSETCORRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _OFFSETCORRW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0x0fff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:11 - Offset Correction Value"] | |
#[inline] | |
pub fn offsetcorr(&self) -> OFFSETCORRR { | |
let bits = { | |
const MASK: u16 = 0x0fff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
OFFSETCORRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:11 - Offset Correction Value"] | |
#[inline] | |
pub fn offsetcorr(&mut self) -> _OFFSETCORRW { | |
_OFFSETCORRW { w: self } | |
} | |
} | |
} | |
#[doc = "Reference Control"] | |
pub struct REFCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Reference Control"] | |
pub mod refctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::REFCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `REFSEL`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum REFSELR { | |
#[doc = "1.0V voltage reference"] | |
INT1V, | |
#[doc = "1/1.48 VDDANA"] | |
INTVCC0, | |
#[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] | |
INTVCC1, | |
#[doc = "External reference"] | |
AREFA, | |
#[doc = "External reference"] | |
AREFB, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl REFSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
REFSELR::INT1V => 0, | |
REFSELR::INTVCC0 => 0x01, | |
REFSELR::INTVCC1 => 0x02, | |
REFSELR::AREFA => 0x03, | |
REFSELR::AREFB => 0x04, | |
REFSELR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> REFSELR { | |
match value { | |
0 => REFSELR::INT1V, | |
1 => REFSELR::INTVCC0, | |
2 => REFSELR::INTVCC1, | |
3 => REFSELR::AREFA, | |
4 => REFSELR::AREFB, | |
i => REFSELR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `INT1V`"] | |
#[inline] | |
pub fn is_int1v(&self) -> bool { | |
*self == REFSELR::INT1V | |
} | |
#[doc = "Checks if the value of the field is `INTVCC0`"] | |
#[inline] | |
pub fn is_intvcc0(&self) -> bool { | |
*self == REFSELR::INTVCC0 | |
} | |
#[doc = "Checks if the value of the field is `INTVCC1`"] | |
#[inline] | |
pub fn is_intvcc1(&self) -> bool { | |
*self == REFSELR::INTVCC1 | |
} | |
#[doc = "Checks if the value of the field is `AREFA`"] | |
#[inline] | |
pub fn is_arefa(&self) -> bool { | |
*self == REFSELR::AREFA | |
} | |
#[doc = "Checks if the value of the field is `AREFB`"] | |
#[inline] | |
pub fn is_arefb(&self) -> bool { | |
*self == REFSELR::AREFB | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct REFCOMPR { | |
bits: bool, | |
} | |
impl REFCOMPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Values that can be written to the field `REFSEL`"] | |
pub enum REFSELW { | |
#[doc = "1.0V voltage reference"] | |
INT1V, | |
#[doc = "1/1.48 VDDANA"] | |
INTVCC0, | |
#[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] | |
INTVCC1, | |
#[doc = "External reference"] | |
AREFA, | |
#[doc = "External reference"] | |
AREFB, | |
} | |
impl REFSELW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
REFSELW::INT1V => 0, | |
REFSELW::INTVCC0 => 1, | |
REFSELW::INTVCC1 => 2, | |
REFSELW::AREFA => 3, | |
REFSELW::AREFB => 4, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _REFSELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _REFSELW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: REFSELW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "1.0V voltage reference"] | |
#[inline] | |
pub fn int1v(self) -> &'a mut W { | |
self.variant(REFSELW::INT1V) | |
} | |
#[doc = "1/1.48 VDDANA"] | |
#[inline] | |
pub fn intvcc0(self) -> &'a mut W { | |
self.variant(REFSELW::INTVCC0) | |
} | |
#[doc = "1/2 VDDANA (only for VDDANA > 2.0V)"] | |
#[inline] | |
pub fn intvcc1(self) -> &'a mut W { | |
self.variant(REFSELW::INTVCC1) | |
} | |
#[doc = "External reference"] | |
#[inline] | |
pub fn arefa(self) -> &'a mut W { | |
self.variant(REFSELW::AREFA) | |
} | |
#[doc = "External reference"] | |
#[inline] | |
pub fn arefb(self) -> &'a mut W { | |
self.variant(REFSELW::AREFB) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _REFCOMPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _REFCOMPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Reference Selection"] | |
#[inline] | |
pub fn refsel(&self) -> REFSELR { | |
REFSELR::_from({ | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
#[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] | |
#[inline] | |
pub fn refcomp(&self) -> REFCOMPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
REFCOMPR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Reference Selection"] | |
#[inline] | |
pub fn refsel(&mut self) -> _REFSELW { | |
_REFSELW { w: self } | |
} | |
#[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] | |
#[inline] | |
pub fn refcomp(&mut self) -> _REFCOMPW { | |
_REFCOMPW { w: self } | |
} | |
} | |
} | |
#[doc = "Result"] | |
pub struct RESULT { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Result"] | |
pub mod result { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
impl super::RESULT { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RESULTR { | |
bits: u16, | |
} | |
impl RESULTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:15 - Result Conversion Value"] | |
#[inline] | |
pub fn result(&self) -> RESULTR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
RESULTR { bits } | |
} | |
} | |
} | |
#[doc = "Sampling Time Control"] | |
pub struct SAMPCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Sampling Time Control"] | |
pub mod sampctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::SAMPCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SAMPLENR { | |
bits: u8, | |
} | |
impl SAMPLENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SAMPLENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SAMPLENW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:5 - Sampling Time Length"] | |
#[inline] | |
pub fn samplen(&self) -> SAMPLENR { | |
let bits = { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}; | |
SAMPLENR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:5 - Sampling Time Length"] | |
#[inline] | |
pub fn samplen(&mut self) -> _SAMPLENW { | |
_SAMPLENW { w: self } | |
} | |
} | |
} | |
#[doc = "Status"] | |
pub struct STATUS { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status"] | |
pub mod status { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUS { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCBUSYR { | |
bits: bool, | |
} | |
impl SYNCBUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 7 - Synchronization Busy"] | |
#[inline] | |
pub fn syncbusy(&self) -> SYNCBUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCBUSYR { bits } | |
} | |
} | |
} | |
#[doc = "Software Trigger"] | |
pub struct SWTRIG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Software Trigger"] | |
pub mod swtrig { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::SWTRIG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FLUSHR { | |
bits: bool, | |
} | |
impl FLUSHR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STARTR { | |
bits: bool, | |
} | |
impl STARTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FLUSHW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FLUSHW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _STARTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _STARTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - ADC Conversion Flush"] | |
#[inline] | |
pub fn flush(&self) -> FLUSHR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
FLUSHR { bits } | |
} | |
#[doc = "Bit 1 - ADC Start Conversion"] | |
#[inline] | |
pub fn start(&self) -> STARTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STARTR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - ADC Conversion Flush"] | |
#[inline] | |
pub fn flush(&mut self) -> _FLUSHW { | |
_FLUSHW { w: self } | |
} | |
#[doc = "Bit 1 - ADC Start Conversion"] | |
#[inline] | |
pub fn start(&mut self) -> _STARTW { | |
_STARTW { w: self } | |
} | |
} | |
} | |
#[doc = "Window Monitor Control"] | |
pub struct WINCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Window Monitor Control"] | |
pub mod winctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::WINCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `WINMODE`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum WINMODER { | |
#[doc = "No window mode (default)"] | |
DISABLE, | |
#[doc = "Mode 1: RESULT > WINLT"] | |
MODE1, | |
#[doc = "Mode 2: RESULT < WINUT"] | |
MODE2, | |
#[doc = "Mode 3: WINLT < RESULT < WINUT"] | |
MODE3, | |
#[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] | |
MODE4, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl WINMODER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
WINMODER::DISABLE => 0, | |
WINMODER::MODE1 => 0x01, | |
WINMODER::MODE2 => 0x02, | |
WINMODER::MODE3 => 0x03, | |
WINMODER::MODE4 => 0x04, | |
WINMODER::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> WINMODER { | |
match value { | |
0 => WINMODER::DISABLE, | |
1 => WINMODER::MODE1, | |
2 => WINMODER::MODE2, | |
3 => WINMODER::MODE3, | |
4 => WINMODER::MODE4, | |
i => WINMODER::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `DISABLE`"] | |
#[inline] | |
pub fn is_disable(&self) -> bool { | |
*self == WINMODER::DISABLE | |
} | |
#[doc = "Checks if the value of the field is `MODE1`"] | |
#[inline] | |
pub fn is_mode1(&self) -> bool { | |
*self == WINMODER::MODE1 | |
} | |
#[doc = "Checks if the value of the field is `MODE2`"] | |
#[inline] | |
pub fn is_mode2(&self) -> bool { | |
*self == WINMODER::MODE2 | |
} | |
#[doc = "Checks if the value of the field is `MODE3`"] | |
#[inline] | |
pub fn is_mode3(&self) -> bool { | |
*self == WINMODER::MODE3 | |
} | |
#[doc = "Checks if the value of the field is `MODE4`"] | |
#[inline] | |
pub fn is_mode4(&self) -> bool { | |
*self == WINMODER::MODE4 | |
} | |
} | |
#[doc = "Values that can be written to the field `WINMODE`"] | |
pub enum WINMODEW { | |
#[doc = "No window mode (default)"] | |
DISABLE, | |
#[doc = "Mode 1: RESULT > WINLT"] | |
MODE1, | |
#[doc = "Mode 2: RESULT < WINUT"] | |
MODE2, | |
#[doc = "Mode 3: WINLT < RESULT < WINUT"] | |
MODE3, | |
#[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] | |
MODE4, | |
} | |
impl WINMODEW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
WINMODEW::DISABLE => 0, | |
WINMODEW::MODE1 => 1, | |
WINMODEW::MODE2 => 2, | |
WINMODEW::MODE3 => 3, | |
WINMODEW::MODE4 => 4, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINMODEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINMODEW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: WINMODEW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No window mode (default)"] | |
#[inline] | |
pub fn disable(self) -> &'a mut W { | |
self.variant(WINMODEW::DISABLE) | |
} | |
#[doc = "Mode 1: RESULT > WINLT"] | |
#[inline] | |
pub fn mode1(self) -> &'a mut W { | |
self.variant(WINMODEW::MODE1) | |
} | |
#[doc = "Mode 2: RESULT < WINUT"] | |
#[inline] | |
pub fn mode2(self) -> &'a mut W { | |
self.variant(WINMODEW::MODE2) | |
} | |
#[doc = "Mode 3: WINLT < RESULT < WINUT"] | |
#[inline] | |
pub fn mode3(self) -> &'a mut W { | |
self.variant(WINMODEW::MODE3) | |
} | |
#[doc = "Mode 4: !(WINLT < RESULT < WINUT)"] | |
#[inline] | |
pub fn mode4(self) -> &'a mut W { | |
self.variant(WINMODEW::MODE4) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:2 - Window Monitor Mode"] | |
#[inline] | |
pub fn winmode(&self) -> WINMODER { | |
WINMODER::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:2 - Window Monitor Mode"] | |
#[inline] | |
pub fn winmode(&mut self) -> _WINMODEW { | |
_WINMODEW { w: self } | |
} | |
} | |
} | |
#[doc = "Window Monitor Lower Threshold"] | |
pub struct WINLT { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Window Monitor Lower Threshold"] | |
pub mod winlt { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::WINLT { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINLTR { | |
bits: u16, | |
} | |
impl WINLTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINLTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINLTW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:15 - Window Lower Threshold"] | |
#[inline] | |
pub fn winlt(&self) -> WINLTR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
WINLTR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:15 - Window Lower Threshold"] | |
#[inline] | |
pub fn winlt(&mut self) -> _WINLTW { | |
_WINLTW { w: self } | |
} | |
} | |
} | |
#[doc = "Window Monitor Upper Threshold"] | |
pub struct WINUT { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Window Monitor Upper Threshold"] | |
pub mod winut { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::WINUT { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WINUTR { | |
bits: u16, | |
} | |
impl WINUTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WINUTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WINUTW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:15 - Window Upper Threshold"] | |
#[inline] | |
pub fn winut(&self) -> WINUTR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
WINUTR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:15 - Window Upper Threshold"] | |
#[inline] | |
pub fn winut(&mut self) -> _WINUTW { | |
_WINUTW { w: self } | |
} | |
} | |
} | |
} | |
#[doc = "Digital Analog Converter"] | |
pub struct DAC { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for DAC {} | |
impl DAC { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const dac::RegisterBlock { | |
0x4200_4800 as *const _ | |
} | |
} | |
impl Deref for DAC { | |
type Target = dac::RegisterBlock; | |
fn deref(&self) -> &dac::RegisterBlock { | |
unsafe { &*DAC::ptr() } | |
} | |
} | |
#[doc = "Digital Analog Converter"] | |
pub mod dac { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control A"] | |
pub ctrla: CTRLA, | |
#[doc = "0x01 - Control B"] | |
pub ctrlb: CTRLB, | |
#[doc = "0x02 - Event Control"] | |
pub evctrl: EVCTRL, | |
_reserved0: [u8; 1usize], | |
#[doc = "0x04 - Interrupt Enable Clear"] | |
pub intenclr: INTENCLR, | |
#[doc = "0x05 - Interrupt Enable Set"] | |
pub intenset: INTENSET, | |
#[doc = "0x06 - Interrupt Flag Status and Clear"] | |
pub intflag: INTFLAG, | |
#[doc = "0x07 - Status"] | |
pub status: STATUS, | |
#[doc = "0x08 - Data"] | |
pub data: DATA, | |
_reserved1: [u8; 2usize], | |
#[doc = "0x0c - Data Buffer"] | |
pub databuf: DATABUF, | |
} | |
#[doc = "Control A"] | |
pub struct CTRLA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control A"] | |
pub mod ctrla { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRLA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWRSTR { | |
bits: bool, | |
} | |
impl SWRSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RUNSTDBYR { | |
bits: bool, | |
} | |
impl RUNSTDBYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RUNSTDBYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RUNSTDBYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&self) -> SWRSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SWRSTR { bits } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
ENABLER { bits } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&self) -> RUNSTDBYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
RUNSTDBYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
#[doc = "Bit 2 - Run in Standby"] | |
#[inline] | |
pub fn runstdby(&mut self) -> _RUNSTDBYW { | |
_RUNSTDBYW { w: self } | |
} | |
} | |
} | |
#[doc = "Control B"] | |
pub struct CTRLB { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control B"] | |
pub mod ctrlb { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRLB { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EOENR { | |
bits: bool, | |
} | |
impl EOENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct IOENR { | |
bits: bool, | |
} | |
impl IOENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LEFTADJR { | |
bits: bool, | |
} | |
impl LEFTADJR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct VPDR { | |
bits: bool, | |
} | |
impl VPDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BDWPR { | |
bits: bool, | |
} | |
impl BDWPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `REFSEL`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum REFSELR { | |
#[doc = "Internal 1.0V reference"] | |
INT1V, | |
#[doc = "AVCC"] | |
AVCC, | |
#[doc = "External reference"] | |
VREFP, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl REFSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
REFSELR::INT1V => 0, | |
REFSELR::AVCC => 0x01, | |
REFSELR::VREFP => 0x02, | |
REFSELR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> REFSELR { | |
match value { | |
0 => REFSELR::INT1V, | |
1 => REFSELR::AVCC, | |
2 => REFSELR::VREFP, | |
i => REFSELR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `INT1V`"] | |
#[inline] | |
pub fn is_int1v(&self) -> bool { | |
*self == REFSELR::INT1V | |
} | |
#[doc = "Checks if the value of the field is `AVCC`"] | |
#[inline] | |
pub fn is_avcc(&self) -> bool { | |
*self == REFSELR::AVCC | |
} | |
#[doc = "Checks if the value of the field is `VREFP`"] | |
#[inline] | |
pub fn is_vrefp(&self) -> bool { | |
*self == REFSELR::VREFP | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EOENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EOENW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _IOENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _IOENW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LEFTADJW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LEFTADJW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _VPDW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _VPDW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _BDWPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _BDWPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `REFSEL`"] | |
pub enum REFSELW { | |
#[doc = "Internal 1.0V reference"] | |
INT1V, | |
#[doc = "AVCC"] | |
AVCC, | |
#[doc = "External reference"] | |
VREFP, | |
} | |
impl REFSELW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
REFSELW::INT1V => 0, | |
REFSELW::AVCC => 1, | |
REFSELW::VREFP => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _REFSELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _REFSELW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: REFSELW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "Internal 1.0V reference"] | |
#[inline] | |
pub fn int1v(self) -> &'a mut W { | |
self.variant(REFSELW::INT1V) | |
} | |
#[doc = "AVCC"] | |
#[inline] | |
pub fn avcc(self) -> &'a mut W { | |
self.variant(REFSELW::AVCC) | |
} | |
#[doc = "External reference"] | |
#[inline] | |
pub fn vrefp(self) -> &'a mut W { | |
self.variant(REFSELW::VREFP) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Output Enable"] | |
#[inline] | |
pub fn eoen(&self) -> EOENR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
EOENR { bits } | |
} | |
#[doc = "Bit 1 - Internal Output Enable"] | |
#[inline] | |
pub fn ioen(&self) -> IOENR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
IOENR { bits } | |
} | |
#[doc = "Bit 2 - Left Adjusted Data"] | |
#[inline] | |
pub fn leftadj(&self) -> LEFTADJR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
LEFTADJR { bits } | |
} | |
#[doc = "Bit 3 - Voltage Pump Disable"] | |
#[inline] | |
pub fn vpd(&self) -> VPDR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
VPDR { bits } | |
} | |
#[doc = "Bit 4 - Bypass DATABUF Write Protection"] | |
#[inline] | |
pub fn bdwp(&self) -> BDWPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
BDWPR { bits } | |
} | |
#[doc = "Bits 6:7 - Reference Selection"] | |
#[inline] | |
pub fn refsel(&self) -> REFSELR { | |
REFSELR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Output Enable"] | |
#[inline] | |
pub fn eoen(&mut self) -> _EOENW { | |
_EOENW { w: self } | |
} | |
#[doc = "Bit 1 - Internal Output Enable"] | |
#[inline] | |
pub fn ioen(&mut self) -> _IOENW { | |
_IOENW { w: self } | |
} | |
#[doc = "Bit 2 - Left Adjusted Data"] | |
#[inline] | |
pub fn leftadj(&mut self) -> _LEFTADJW { | |
_LEFTADJW { w: self } | |
} | |
#[doc = "Bit 3 - Voltage Pump Disable"] | |
#[inline] | |
pub fn vpd(&mut self) -> _VPDW { | |
_VPDW { w: self } | |
} | |
#[doc = "Bit 4 - Bypass DATABUF Write Protection"] | |
#[inline] | |
pub fn bdwp(&mut self) -> _BDWPW { | |
_BDWPW { w: self } | |
} | |
#[doc = "Bits 6:7 - Reference Selection"] | |
#[inline] | |
pub fn refsel(&mut self) -> _REFSELW { | |
_REFSELW { w: self } | |
} | |
} | |
} | |
#[doc = "Data"] | |
pub struct DATA { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Data"] | |
pub mod data { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::DATA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DATAR { | |
bits: u16, | |
} | |
impl DATAR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DATAW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DATAW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:15 - Data value to be converted"] | |
#[inline] | |
pub fn data(&self) -> DATAR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
DATAR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:15 - Data value to be converted"] | |
#[inline] | |
pub fn data(&mut self) -> _DATAW { | |
_DATAW { w: self } | |
} | |
} | |
} | |
#[doc = "Data Buffer"] | |
pub struct DATABUF { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Data Buffer"] | |
pub mod databuf { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::DATABUF { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DATABUFR { | |
bits: u16, | |
} | |
impl DATABUFR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DATABUFW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DATABUFW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u16) -> &'a mut W { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:15 - Data Buffer"] | |
#[inline] | |
pub fn databuf(&self) -> DATABUFR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u16 | |
}; | |
DATABUFR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:15 - Data Buffer"] | |
#[inline] | |
pub fn databuf(&mut self) -> _DATABUFW { | |
_DATABUFW { w: self } | |
} | |
} | |
} | |
#[doc = "Event Control"] | |
pub struct EVCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Event Control"] | |
pub mod evctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::EVCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct STARTEIR { | |
bits: bool, | |
} | |
impl STARTEIR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EMPTYEOR { | |
bits: bool, | |
} | |
impl EMPTYEOR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _STARTEIW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _STARTEIW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EMPTYEOW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EMPTYEOW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Start Conversion Event Input"] | |
#[inline] | |
pub fn startei(&self) -> STARTEIR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
STARTEIR { bits } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Event Output"] | |
#[inline] | |
pub fn emptyeo(&self) -> EMPTYEOR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
EMPTYEOR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Start Conversion Event Input"] | |
#[inline] | |
pub fn startei(&mut self) -> _STARTEIW { | |
_STARTEIW { w: self } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Event Output"] | |
#[inline] | |
pub fn emptyeo(&mut self) -> _EMPTYEOW { | |
_EMPTYEOW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub struct INTENCLR { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub mod intenclr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENCLR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct UNDERRUNR { | |
bits: bool, | |
} | |
impl UNDERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EMPTYR { | |
bits: bool, | |
} | |
impl EMPTYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _UNDERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _UNDERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EMPTYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EMPTYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Underrun Interrupt Enable"] | |
#[inline] | |
pub fn underrun(&self) -> UNDERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
UNDERRUNR { bits } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] | |
#[inline] | |
pub fn empty(&self) -> EMPTYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
EMPTYR { bits } | |
} | |
#[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Underrun Interrupt Enable"] | |
#[inline] | |
pub fn underrun(&mut self) -> _UNDERRUNW { | |
_UNDERRUNW { w: self } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] | |
#[inline] | |
pub fn empty(&mut self) -> _EMPTYW { | |
_EMPTYW { w: self } | |
} | |
#[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub struct INTENSET { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub mod intenset { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTENSET { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct UNDERRUNR { | |
bits: bool, | |
} | |
impl UNDERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EMPTYR { | |
bits: bool, | |
} | |
impl EMPTYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _UNDERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _UNDERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EMPTYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EMPTYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Underrun Interrupt Enable"] | |
#[inline] | |
pub fn underrun(&self) -> UNDERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
UNDERRUNR { bits } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] | |
#[inline] | |
pub fn empty(&self) -> EMPTYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
EMPTYR { bits } | |
} | |
#[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Underrun Interrupt Enable"] | |
#[inline] | |
pub fn underrun(&mut self) -> _UNDERRUNW { | |
_UNDERRUNW { w: self } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty Interrupt Enable"] | |
#[inline] | |
pub fn empty(&mut self) -> _EMPTYW { | |
_EMPTYW { w: self } | |
} | |
#[doc = "Bit 2 - Synchronization Ready Interrupt Enable"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub struct INTFLAG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub mod intflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::INTFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct UNDERRUNR { | |
bits: bool, | |
} | |
impl UNDERRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EMPTYR { | |
bits: bool, | |
} | |
impl EMPTYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCRDYR { | |
bits: bool, | |
} | |
impl SYNCRDYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _UNDERRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _UNDERRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EMPTYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EMPTYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SYNCRDYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SYNCRDYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Underrun"] | |
#[inline] | |
pub fn underrun(&self) -> UNDERRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
UNDERRUNR { bits } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty"] | |
#[inline] | |
pub fn empty(&self) -> EMPTYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
EMPTYR { bits } | |
} | |
#[doc = "Bit 2 - Synchronization Ready"] | |
#[inline] | |
pub fn syncrdy(&self) -> SYNCRDYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCRDYR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Underrun"] | |
#[inline] | |
pub fn underrun(&mut self) -> _UNDERRUNW { | |
_UNDERRUNW { w: self } | |
} | |
#[doc = "Bit 1 - Data Buffer Empty"] | |
#[inline] | |
pub fn empty(&mut self) -> _EMPTYW { | |
_EMPTYW { w: self } | |
} | |
#[doc = "Bit 2 - Synchronization Ready"] | |
#[inline] | |
pub fn syncrdy(&mut self) -> _SYNCRDYW { | |
_SYNCRDYW { w: self } | |
} | |
} | |
} | |
#[doc = "Status"] | |
pub struct STATUS { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status"] | |
pub mod status { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUS { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCBUSYR { | |
bits: bool, | |
} | |
impl SYNCBUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 7 - Synchronization Busy Status"] | |
#[inline] | |
pub fn syncbusy(&self) -> SYNCBUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCBUSYR { bits } | |
} | |
} | |
} | |
} | |
#[doc = "Direct Memory Access Controller"] | |
pub struct DMAC { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for DMAC {} | |
impl DMAC { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const dmac::RegisterBlock { | |
0x4100_4800 as *const _ | |
} | |
} | |
impl Deref for DMAC { | |
type Target = dmac::RegisterBlock; | |
fn deref(&self) -> &dmac::RegisterBlock { | |
unsafe { &*DMAC::ptr() } | |
} | |
} | |
#[doc = "Direct Memory Access Controller"] | |
pub mod dmac { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control"] | |
pub ctrl: CTRL, | |
#[doc = "0x02 - CRC Control"] | |
pub crcctrl: CRCCTRL, | |
#[doc = "0x04 - CRC Data Input"] | |
pub crcdatain: CRCDATAIN, | |
#[doc = "0x08 - CRC Checksum"] | |
pub crcchksum: CRCCHKSUM, | |
#[doc = "0x0c - CRC Status"] | |
pub crcstatus: CRCSTATUS, | |
#[doc = "0x0d - Debug Control"] | |
pub dbgctrl: DBGCTRL, | |
_reserved0: [u8; 2usize], | |
#[doc = "0x10 - Software Trigger Control"] | |
pub swtrigctrl: SWTRIGCTRL, | |
#[doc = "0x14 - Priority Control 0"] | |
pub prictrl0: PRICTRL0, | |
_reserved1: [u8; 8usize], | |
#[doc = "0x20 - Interrupt Pending"] | |
pub intpend: INTPEND, | |
_reserved2: [u8; 2usize], | |
#[doc = "0x24 - Interrupt Status"] | |
pub intstatus: INTSTATUS, | |
#[doc = "0x28 - Busy Channels"] | |
pub busych: BUSYCH, | |
#[doc = "0x2c - Pending Channels"] | |
pub pendch: PENDCH, | |
#[doc = "0x30 - Active Channel and Levels"] | |
pub active: ACTIVE, | |
#[doc = "0x34 - Descriptor Memory Section Base Address"] | |
pub baseaddr: BASEADDR, | |
#[doc = "0x38 - Write-Back Memory Section Base Address"] | |
pub wrbaddr: WRBADDR, | |
_reserved3: [u8; 3usize], | |
#[doc = "0x3f - Channel ID"] | |
pub chid: CHID, | |
#[doc = "0x40 - Channel Control A"] | |
pub chctrla: CHCTRLA, | |
_reserved4: [u8; 3usize], | |
#[doc = "0x44 - Channel Control B"] | |
pub chctrlb: CHCTRLB, | |
_reserved5: [u8; 4usize], | |
#[doc = "0x4c - Channel Interrupt Enable Clear"] | |
pub chintenclr: CHINTENCLR, | |
#[doc = "0x4d - Channel Interrupt Enable Set"] | |
pub chintenset: CHINTENSET, | |
#[doc = "0x4e - Channel Interrupt Flag Status and Clear"] | |
pub chintflag: CHINTFLAG, | |
#[doc = "0x4f - Channel Status"] | |
pub chstatus: CHSTATUS, | |
} | |
#[doc = "Active Channel and Levels"] | |
pub struct ACTIVE { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Active Channel and Levels"] | |
pub mod active { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::ACTIVE { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEX0R { | |
bits: bool, | |
} | |
impl LVLEX0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEX1R { | |
bits: bool, | |
} | |
impl LVLEX1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEX2R { | |
bits: bool, | |
} | |
impl LVLEX2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEX3R { | |
bits: bool, | |
} | |
impl LVLEX3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct IDR { | |
bits: u8, | |
} | |
impl IDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ABUSYR { | |
bits: bool, | |
} | |
impl ABUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BTCNTR { | |
bits: u16, | |
} | |
impl BTCNTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] | |
#[inline] | |
pub fn lvlex0(&self) -> LVLEX0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
LVLEX0R { bits } | |
} | |
#[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] | |
#[inline] | |
pub fn lvlex1(&self) -> LVLEX1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
LVLEX1R { bits } | |
} | |
#[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] | |
#[inline] | |
pub fn lvlex2(&self) -> LVLEX2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
LVLEX2R { bits } | |
} | |
#[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] | |
#[inline] | |
pub fn lvlex3(&self) -> LVLEX3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
LVLEX3R { bits } | |
} | |
#[doc = "Bits 8:12 - Active Channel ID"] | |
#[inline] | |
pub fn id(&self) -> IDR { | |
let bits = { | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
IDR { bits } | |
} | |
#[doc = "Bit 15 - Active Channel Busy"] | |
#[inline] | |
pub fn abusy(&self) -> ABUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
ABUSYR { bits } | |
} | |
#[doc = "Bits 16:31 - Active Channel Block Transfer Count"] | |
#[inline] | |
pub fn btcnt(&self) -> BTCNTR { | |
let bits = { | |
const MASK: u16 = 0xffff; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u16 | |
}; | |
BTCNTR { bits } | |
} | |
} | |
} | |
#[doc = "Descriptor Memory Section Base Address"] | |
pub struct BASEADDR { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Descriptor Memory Section Base Address"] | |
pub mod baseaddr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::BASEADDR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BASEADDRR { | |
bits: u32, | |
} | |
impl BASEADDRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _BASEADDRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _BASEADDRW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - Descriptor Memory Base Address"] | |
#[inline] | |
pub fn baseaddr(&self) -> BASEADDRR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
BASEADDRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - Descriptor Memory Base Address"] | |
#[inline] | |
pub fn baseaddr(&mut self) -> _BASEADDRW { | |
_BASEADDRW { w: self } | |
} | |
} | |
} | |
#[doc = "Busy Channels"] | |
pub struct BUSYCH { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Busy Channels"] | |
pub mod busych { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::BUSYCH { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH0R { | |
bits: bool, | |
} | |
impl BUSYCH0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH1R { | |
bits: bool, | |
} | |
impl BUSYCH1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH2R { | |
bits: bool, | |
} | |
impl BUSYCH2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH3R { | |
bits: bool, | |
} | |
impl BUSYCH3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH4R { | |
bits: bool, | |
} | |
impl BUSYCH4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH5R { | |
bits: bool, | |
} | |
impl BUSYCH5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH6R { | |
bits: bool, | |
} | |
impl BUSYCH6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH7R { | |
bits: bool, | |
} | |
impl BUSYCH7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH8R { | |
bits: bool, | |
} | |
impl BUSYCH8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH9R { | |
bits: bool, | |
} | |
impl BUSYCH9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH10R { | |
bits: bool, | |
} | |
impl BUSYCH10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYCH11R { | |
bits: bool, | |
} | |
impl BUSYCH11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Busy Channel 0"] | |
#[inline] | |
pub fn busych0(&self) -> BUSYCH0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH0R { bits } | |
} | |
#[doc = "Bit 1 - Busy Channel 1"] | |
#[inline] | |
pub fn busych1(&self) -> BUSYCH1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH1R { bits } | |
} | |
#[doc = "Bit 2 - Busy Channel 2"] | |
#[inline] | |
pub fn busych2(&self) -> BUSYCH2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH2R { bits } | |
} | |
#[doc = "Bit 3 - Busy Channel 3"] | |
#[inline] | |
pub fn busych3(&self) -> BUSYCH3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH3R { bits } | |
} | |
#[doc = "Bit 4 - Busy Channel 4"] | |
#[inline] | |
pub fn busych4(&self) -> BUSYCH4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH4R { bits } | |
} | |
#[doc = "Bit 5 - Busy Channel 5"] | |
#[inline] | |
pub fn busych5(&self) -> BUSYCH5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH5R { bits } | |
} | |
#[doc = "Bit 6 - Busy Channel 6"] | |
#[inline] | |
pub fn busych6(&self) -> BUSYCH6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH6R { bits } | |
} | |
#[doc = "Bit 7 - Busy Channel 7"] | |
#[inline] | |
pub fn busych7(&self) -> BUSYCH7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH7R { bits } | |
} | |
#[doc = "Bit 8 - Busy Channel 8"] | |
#[inline] | |
pub fn busych8(&self) -> BUSYCH8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH8R { bits } | |
} | |
#[doc = "Bit 9 - Busy Channel 9"] | |
#[inline] | |
pub fn busych9(&self) -> BUSYCH9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH9R { bits } | |
} | |
#[doc = "Bit 10 - Busy Channel 10"] | |
#[inline] | |
pub fn busych10(&self) -> BUSYCH10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH10R { bits } | |
} | |
#[doc = "Bit 11 - Busy Channel 11"] | |
#[inline] | |
pub fn busych11(&self) -> BUSYCH11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
BUSYCH11R { bits } | |
} | |
} | |
} | |
#[doc = "Channel Control A"] | |
pub struct CHCTRLA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel Control A"] | |
pub mod chctrla { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CHCTRLA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWRSTR { | |
bits: bool, | |
} | |
impl SWRSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Channel Software Reset"] | |
#[inline] | |
pub fn swrst(&self) -> SWRSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SWRSTR { bits } | |
} | |
#[doc = "Bit 1 - Channel Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
ENABLER { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Channel Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - Channel Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel Control B"] | |
pub struct CHCTRLB { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Channel Control B"] | |
pub mod chctrlb { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::CHCTRLB { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `EVACT`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum EVACTR { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "Transfer and periodic transfer trigger"] | |
TRIG, | |
#[doc = "Conditional transfer trigger"] | |
CTRIG, | |
#[doc = "Conditional block transfer"] | |
CBLOCK, | |
#[doc = "Channel suspend operation"] | |
SUSPEND, | |
#[doc = "Channel resume operation"] | |
RESUME, | |
#[doc = "Skip next block suspend action"] | |
SSKIP, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl EVACTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
EVACTR::NOACT => 0, | |
EVACTR::TRIG => 0x01, | |
EVACTR::CTRIG => 0x02, | |
EVACTR::CBLOCK => 0x03, | |
EVACTR::SUSPEND => 0x04, | |
EVACTR::RESUME => 0x05, | |
EVACTR::SSKIP => 0x06, | |
EVACTR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> EVACTR { | |
match value { | |
0 => EVACTR::NOACT, | |
1 => EVACTR::TRIG, | |
2 => EVACTR::CTRIG, | |
3 => EVACTR::CBLOCK, | |
4 => EVACTR::SUSPEND, | |
5 => EVACTR::RESUME, | |
6 => EVACTR::SSKIP, | |
i => EVACTR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NOACT`"] | |
#[inline] | |
pub fn is_noact(&self) -> bool { | |
*self == EVACTR::NOACT | |
} | |
#[doc = "Checks if the value of the field is `TRIG`"] | |
#[inline] | |
pub fn is_trig(&self) -> bool { | |
*self == EVACTR::TRIG | |
} | |
#[doc = "Checks if the value of the field is `CTRIG`"] | |
#[inline] | |
pub fn is_ctrig(&self) -> bool { | |
*self == EVACTR::CTRIG | |
} | |
#[doc = "Checks if the value of the field is `CBLOCK`"] | |
#[inline] | |
pub fn is_cblock(&self) -> bool { | |
*self == EVACTR::CBLOCK | |
} | |
#[doc = "Checks if the value of the field is `SUSPEND`"] | |
#[inline] | |
pub fn is_suspend(&self) -> bool { | |
*self == EVACTR::SUSPEND | |
} | |
#[doc = "Checks if the value of the field is `RESUME`"] | |
#[inline] | |
pub fn is_resume(&self) -> bool { | |
*self == EVACTR::RESUME | |
} | |
#[doc = "Checks if the value of the field is `SSKIP`"] | |
#[inline] | |
pub fn is_sskip(&self) -> bool { | |
*self == EVACTR::SSKIP | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EVIER { | |
bits: bool, | |
} | |
impl EVIER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EVOER { | |
bits: bool, | |
} | |
impl EVOER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLR { | |
bits: u8, | |
} | |
impl LVLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = "Possible values of the field `TRIGSRC`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum TRIGSRCR { | |
#[doc = "Only software/event triggers"] | |
DISABLE, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl TRIGSRCR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
TRIGSRCR::DISABLE => 0, | |
TRIGSRCR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> TRIGSRCR { | |
match value { | |
0 => TRIGSRCR::DISABLE, | |
i => TRIGSRCR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `DISABLE`"] | |
#[inline] | |
pub fn is_disable(&self) -> bool { | |
*self == TRIGSRCR::DISABLE | |
} | |
} | |
#[doc = "Possible values of the field `TRIGACT`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum TRIGACTR { | |
#[doc = "One trigger required for each block transfer"] | |
BLOCK, | |
#[doc = "One trigger required for each beat transfer"] | |
BEAT, | |
#[doc = "One trigger required for each transaction"] | |
TRANSACTION, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl TRIGACTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
TRIGACTR::BLOCK => 0, | |
TRIGACTR::BEAT => 0x02, | |
TRIGACTR::TRANSACTION => 0x03, | |
TRIGACTR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> TRIGACTR { | |
match value { | |
0 => TRIGACTR::BLOCK, | |
2 => TRIGACTR::BEAT, | |
3 => TRIGACTR::TRANSACTION, | |
i => TRIGACTR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `BLOCK`"] | |
#[inline] | |
pub fn is_block(&self) -> bool { | |
*self == TRIGACTR::BLOCK | |
} | |
#[doc = "Checks if the value of the field is `BEAT`"] | |
#[inline] | |
pub fn is_beat(&self) -> bool { | |
*self == TRIGACTR::BEAT | |
} | |
#[doc = "Checks if the value of the field is `TRANSACTION`"] | |
#[inline] | |
pub fn is_transaction(&self) -> bool { | |
*self == TRIGACTR::TRANSACTION | |
} | |
} | |
#[doc = "Possible values of the field `CMD`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum CMDR { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "Channel suspend operation"] | |
SUSPEND, | |
#[doc = "Channel resume operation"] | |
RESUME, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl CMDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
CMDR::NOACT => 0, | |
CMDR::SUSPEND => 0x01, | |
CMDR::RESUME => 0x02, | |
CMDR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> CMDR { | |
match value { | |
0 => CMDR::NOACT, | |
1 => CMDR::SUSPEND, | |
2 => CMDR::RESUME, | |
i => CMDR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NOACT`"] | |
#[inline] | |
pub fn is_noact(&self) -> bool { | |
*self == CMDR::NOACT | |
} | |
#[doc = "Checks if the value of the field is `SUSPEND`"] | |
#[inline] | |
pub fn is_suspend(&self) -> bool { | |
*self == CMDR::SUSPEND | |
} | |
#[doc = "Checks if the value of the field is `RESUME`"] | |
#[inline] | |
pub fn is_resume(&self) -> bool { | |
*self == CMDR::RESUME | |
} | |
} | |
#[doc = "Values that can be written to the field `EVACT`"] | |
pub enum EVACTW { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "Transfer and periodic transfer trigger"] | |
TRIG, | |
#[doc = "Conditional transfer trigger"] | |
CTRIG, | |
#[doc = "Conditional block transfer"] | |
CBLOCK, | |
#[doc = "Channel suspend operation"] | |
SUSPEND, | |
#[doc = "Channel resume operation"] | |
RESUME, | |
#[doc = "Skip next block suspend action"] | |
SSKIP, | |
} | |
impl EVACTW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
EVACTW::NOACT => 0, | |
EVACTW::TRIG => 1, | |
EVACTW::CTRIG => 2, | |
EVACTW::CBLOCK => 3, | |
EVACTW::SUSPEND => 4, | |
EVACTW::RESUME => 5, | |
EVACTW::SSKIP => 6, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EVACTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EVACTW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: EVACTW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No action"] | |
#[inline] | |
pub fn noact(self) -> &'a mut W { | |
self.variant(EVACTW::NOACT) | |
} | |
#[doc = "Transfer and periodic transfer trigger"] | |
#[inline] | |
pub fn trig(self) -> &'a mut W { | |
self.variant(EVACTW::TRIG) | |
} | |
#[doc = "Conditional transfer trigger"] | |
#[inline] | |
pub fn ctrig(self) -> &'a mut W { | |
self.variant(EVACTW::CTRIG) | |
} | |
#[doc = "Conditional block transfer"] | |
#[inline] | |
pub fn cblock(self) -> &'a mut W { | |
self.variant(EVACTW::CBLOCK) | |
} | |
#[doc = "Channel suspend operation"] | |
#[inline] | |
pub fn suspend(self) -> &'a mut W { | |
self.variant(EVACTW::SUSPEND) | |
} | |
#[doc = "Channel resume operation"] | |
#[inline] | |
pub fn resume(self) -> &'a mut W { | |
self.variant(EVACTW::RESUME) | |
} | |
#[doc = "Skip next block suspend action"] | |
#[inline] | |
pub fn sskip(self) -> &'a mut W { | |
self.variant(EVACTW::SSKIP) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EVIEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EVIEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EVOEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EVOEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `TRIGSRC`"] | |
pub enum TRIGSRCW { | |
#[doc = "Only software/event triggers"] | |
DISABLE, | |
} | |
impl TRIGSRCW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
TRIGSRCW::DISABLE => 0, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TRIGSRCW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TRIGSRCW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: TRIGSRCW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "Only software/event triggers"] | |
#[inline] | |
pub fn disable(self) -> &'a mut W { | |
self.variant(TRIGSRCW::DISABLE) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `TRIGACT`"] | |
pub enum TRIGACTW { | |
#[doc = "One trigger required for each block transfer"] | |
BLOCK, | |
#[doc = "One trigger required for each beat transfer"] | |
BEAT, | |
#[doc = "One trigger required for each transaction"] | |
TRANSACTION, | |
} | |
impl TRIGACTW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
TRIGACTW::BLOCK => 0, | |
TRIGACTW::BEAT => 2, | |
TRIGACTW::TRANSACTION => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TRIGACTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TRIGACTW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: TRIGACTW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "One trigger required for each block transfer"] | |
#[inline] | |
pub fn block(self) -> &'a mut W { | |
self.variant(TRIGACTW::BLOCK) | |
} | |
#[doc = "One trigger required for each beat transfer"] | |
#[inline] | |
pub fn beat(self) -> &'a mut W { | |
self.variant(TRIGACTW::BEAT) | |
} | |
#[doc = "One trigger required for each transaction"] | |
#[inline] | |
pub fn transaction(self) -> &'a mut W { | |
self.variant(TRIGACTW::TRANSACTION) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 22; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `CMD`"] | |
pub enum CMDW { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "Channel suspend operation"] | |
SUSPEND, | |
#[doc = "Channel resume operation"] | |
RESUME, | |
} | |
impl CMDW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
CMDW::NOACT => 0, | |
CMDW::SUSPEND => 1, | |
CMDW::RESUME => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CMDW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CMDW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: CMDW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No action"] | |
#[inline] | |
pub fn noact(self) -> &'a mut W { | |
self.variant(CMDW::NOACT) | |
} | |
#[doc = "Channel suspend operation"] | |
#[inline] | |
pub fn suspend(self) -> &'a mut W { | |
self.variant(CMDW::SUSPEND) | |
} | |
#[doc = "Channel resume operation"] | |
#[inline] | |
pub fn resume(self) -> &'a mut W { | |
self.variant(CMDW::RESUME) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:2 - Event Input Action"] | |
#[inline] | |
pub fn evact(&self) -> EVACTR { | |
EVACTR::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 3 - Channel Event Input Enable"] | |
#[inline] | |
pub fn evie(&self) -> EVIER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EVIER { bits } | |
} | |
#[doc = "Bit 4 - Channel Event Output Enable"] | |
#[inline] | |
pub fn evoe(&self) -> EVOER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EVOER { bits } | |
} | |
#[doc = "Bits 5:6 - Channel Arbitration Level"] | |
#[inline] | |
pub fn lvl(&self) -> LVLR { | |
let bits = { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
LVLR { bits } | |
} | |
#[doc = "Bits 8:13 - Peripheral Trigger Source"] | |
#[inline] | |
pub fn trigsrc(&self) -> TRIGSRCR { | |
TRIGSRCR::_from({ | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 22:23 - Trigger Action"] | |
#[inline] | |
pub fn trigact(&self) -> TRIGACTR { | |
TRIGACTR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 22; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 24:25 - Software Command"] | |
#[inline] | |
pub fn cmd(&self) -> CMDR { | |
CMDR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:2 - Event Input Action"] | |
#[inline] | |
pub fn evact(&mut self) -> _EVACTW { | |
_EVACTW { w: self } | |
} | |
#[doc = "Bit 3 - Channel Event Input Enable"] | |
#[inline] | |
pub fn evie(&mut self) -> _EVIEW { | |
_EVIEW { w: self } | |
} | |
#[doc = "Bit 4 - Channel Event Output Enable"] | |
#[inline] | |
pub fn evoe(&mut self) -> _EVOEW { | |
_EVOEW { w: self } | |
} | |
#[doc = "Bits 5:6 - Channel Arbitration Level"] | |
#[inline] | |
pub fn lvl(&mut self) -> _LVLW { | |
_LVLW { w: self } | |
} | |
#[doc = "Bits 8:13 - Peripheral Trigger Source"] | |
#[inline] | |
pub fn trigsrc(&mut self) -> _TRIGSRCW { | |
_TRIGSRCW { w: self } | |
} | |
#[doc = "Bits 22:23 - Trigger Action"] | |
#[inline] | |
pub fn trigact(&mut self) -> _TRIGACTW { | |
_TRIGACTW { w: self } | |
} | |
#[doc = "Bits 24:25 - Software Command"] | |
#[inline] | |
pub fn cmd(&mut self) -> _CMDW { | |
_CMDW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel ID"] | |
pub struct CHID { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel ID"] | |
pub mod chid { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CHID { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct IDR { | |
bits: u8, | |
} | |
impl IDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _IDW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _IDW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Channel ID"] | |
#[inline] | |
pub fn id(&self) -> IDR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}; | |
IDR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Channel ID"] | |
#[inline] | |
pub fn id(&mut self) -> _IDW { | |
_IDW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel Interrupt Enable Clear"] | |
pub struct CHINTENCLR { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel Interrupt Enable Clear"] | |
pub mod chintenclr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CHINTENCLR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TERRR { | |
bits: bool, | |
} | |
impl TERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TCMPLR { | |
bits: bool, | |
} | |
impl TCMPLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SUSPR { | |
bits: bool, | |
} | |
impl SUSPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TCMPLW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TCMPLW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SUSPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SUSPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Transfer Error Interrupt Enable"] | |
#[inline] | |
pub fn terr(&self) -> TERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TERRR { bits } | |
} | |
#[doc = "Bit 1 - Transfer Complete Interrupt Enable"] | |
#[inline] | |
pub fn tcmpl(&self) -> TCMPLR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TCMPLR { bits } | |
} | |
#[doc = "Bit 2 - Channel Suspend Interrupt Enable"] | |
#[inline] | |
pub fn susp(&self) -> SUSPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SUSPR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Transfer Error Interrupt Enable"] | |
#[inline] | |
pub fn terr(&mut self) -> _TERRW { | |
_TERRW { w: self } | |
} | |
#[doc = "Bit 1 - Transfer Complete Interrupt Enable"] | |
#[inline] | |
pub fn tcmpl(&mut self) -> _TCMPLW { | |
_TCMPLW { w: self } | |
} | |
#[doc = "Bit 2 - Channel Suspend Interrupt Enable"] | |
#[inline] | |
pub fn susp(&mut self) -> _SUSPW { | |
_SUSPW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel Interrupt Enable Set"] | |
pub struct CHINTENSET { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel Interrupt Enable Set"] | |
pub mod chintenset { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CHINTENSET { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TERRR { | |
bits: bool, | |
} | |
impl TERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TCMPLR { | |
bits: bool, | |
} | |
impl TCMPLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SUSPR { | |
bits: bool, | |
} | |
impl SUSPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TCMPLW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TCMPLW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SUSPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SUSPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Transfer Error Interrupt Enable"] | |
#[inline] | |
pub fn terr(&self) -> TERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TERRR { bits } | |
} | |
#[doc = "Bit 1 - Transfer Complete Interrupt Enable"] | |
#[inline] | |
pub fn tcmpl(&self) -> TCMPLR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TCMPLR { bits } | |
} | |
#[doc = "Bit 2 - Channel Suspend Interrupt Enable"] | |
#[inline] | |
pub fn susp(&self) -> SUSPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SUSPR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Transfer Error Interrupt Enable"] | |
#[inline] | |
pub fn terr(&mut self) -> _TERRW { | |
_TERRW { w: self } | |
} | |
#[doc = "Bit 1 - Transfer Complete Interrupt Enable"] | |
#[inline] | |
pub fn tcmpl(&mut self) -> _TCMPLW { | |
_TCMPLW { w: self } | |
} | |
#[doc = "Bit 2 - Channel Suspend Interrupt Enable"] | |
#[inline] | |
pub fn susp(&mut self) -> _SUSPW { | |
_SUSPW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel Interrupt Flag Status and Clear"] | |
pub struct CHINTFLAG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel Interrupt Flag Status and Clear"] | |
pub mod chintflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CHINTFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TERRR { | |
bits: bool, | |
} | |
impl TERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TCMPLR { | |
bits: bool, | |
} | |
impl TCMPLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SUSPR { | |
bits: bool, | |
} | |
impl SUSPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TCMPLW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TCMPLW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SUSPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SUSPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Transfer Error"] | |
#[inline] | |
pub fn terr(&self) -> TERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TERRR { bits } | |
} | |
#[doc = "Bit 1 - Transfer Complete"] | |
#[inline] | |
pub fn tcmpl(&self) -> TCMPLR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
TCMPLR { bits } | |
} | |
#[doc = "Bit 2 - Channel Suspend"] | |
#[inline] | |
pub fn susp(&self) -> SUSPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SUSPR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Transfer Error"] | |
#[inline] | |
pub fn terr(&mut self) -> _TERRW { | |
_TERRW { w: self } | |
} | |
#[doc = "Bit 1 - Transfer Complete"] | |
#[inline] | |
pub fn tcmpl(&mut self) -> _TCMPLW { | |
_TCMPLW { w: self } | |
} | |
#[doc = "Bit 2 - Channel Suspend"] | |
#[inline] | |
pub fn susp(&mut self) -> _SUSPW { | |
_SUSPW { w: self } | |
} | |
} | |
} | |
#[doc = "Channel Status"] | |
pub struct CHSTATUS { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Channel Status"] | |
pub mod chstatus { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::CHSTATUS { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDR { | |
bits: bool, | |
} | |
impl PENDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYR { | |
bits: bool, | |
} | |
impl BUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FERRR { | |
bits: bool, | |
} | |
impl FERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Channel Pending"] | |
#[inline] | |
pub fn pend(&self) -> PENDR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
PENDR { bits } | |
} | |
#[doc = "Bit 1 - Channel Busy"] | |
#[inline] | |
pub fn busy(&self) -> BUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
BUSYR { bits } | |
} | |
#[doc = "Bit 2 - Fetch Error"] | |
#[inline] | |
pub fn ferr(&self) -> FERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
FERRR { bits } | |
} | |
} | |
} | |
#[doc = "CRC Checksum"] | |
pub struct CRCCHKSUM { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "CRC Checksum"] | |
pub mod crcchksum { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::CRCCHKSUM { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRCCHKSUMR { | |
bits: u32, | |
} | |
impl CRCCHKSUMR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCCHKSUMW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCCHKSUMW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - CRC Checksum"] | |
#[inline] | |
pub fn crcchksum(&self) -> CRCCHKSUMR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
CRCCHKSUMR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - CRC Checksum"] | |
#[inline] | |
pub fn crcchksum(&mut self) -> _CRCCHKSUMW { | |
_CRCCHKSUMW { w: self } | |
} | |
} | |
} | |
#[doc = "CRC Control"] | |
pub struct CRCCTRL { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "CRC Control"] | |
pub mod crcctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::CRCCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `CRCBEATSIZE`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum CRCBEATSIZER { | |
#[doc = "Byte bus access"] | |
BYTE, | |
#[doc = "Half-word bus access"] | |
HWORD, | |
#[doc = "Word bus access"] | |
WORD, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl CRCBEATSIZER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
CRCBEATSIZER::BYTE => 0, | |
CRCBEATSIZER::HWORD => 0x01, | |
CRCBEATSIZER::WORD => 0x02, | |
CRCBEATSIZER::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> CRCBEATSIZER { | |
match value { | |
0 => CRCBEATSIZER::BYTE, | |
1 => CRCBEATSIZER::HWORD, | |
2 => CRCBEATSIZER::WORD, | |
i => CRCBEATSIZER::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `BYTE`"] | |
#[inline] | |
pub fn is_byte(&self) -> bool { | |
*self == CRCBEATSIZER::BYTE | |
} | |
#[doc = "Checks if the value of the field is `HWORD`"] | |
#[inline] | |
pub fn is_hword(&self) -> bool { | |
*self == CRCBEATSIZER::HWORD | |
} | |
#[doc = "Checks if the value of the field is `WORD`"] | |
#[inline] | |
pub fn is_word(&self) -> bool { | |
*self == CRCBEATSIZER::WORD | |
} | |
} | |
#[doc = "Possible values of the field `CRCPOLY`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum CRCPOLYR { | |
#[doc = "CRC-16 (CRC-CCITT)"] | |
CRC16, | |
#[doc = "CRC32 (IEEE 802.3)"] | |
CRC32, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl CRCPOLYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
CRCPOLYR::CRC16 => 0, | |
CRCPOLYR::CRC32 => 0x01, | |
CRCPOLYR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> CRCPOLYR { | |
match value { | |
0 => CRCPOLYR::CRC16, | |
1 => CRCPOLYR::CRC32, | |
i => CRCPOLYR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `CRC16`"] | |
#[inline] | |
pub fn is_crc16(&self) -> bool { | |
*self == CRCPOLYR::CRC16 | |
} | |
#[doc = "Checks if the value of the field is `CRC32`"] | |
#[inline] | |
pub fn is_crc32(&self) -> bool { | |
*self == CRCPOLYR::CRC32 | |
} | |
} | |
#[doc = "Possible values of the field `CRCSRC`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum CRCSRCR { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "I/O interface"] | |
IO, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl CRCSRCR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
CRCSRCR::NOACT => 0, | |
CRCSRCR::IO => 0x01, | |
CRCSRCR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> CRCSRCR { | |
match value { | |
0 => CRCSRCR::NOACT, | |
1 => CRCSRCR::IO, | |
i => CRCSRCR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NOACT`"] | |
#[inline] | |
pub fn is_noact(&self) -> bool { | |
*self == CRCSRCR::NOACT | |
} | |
#[doc = "Checks if the value of the field is `IO`"] | |
#[inline] | |
pub fn is_io(&self) -> bool { | |
*self == CRCSRCR::IO | |
} | |
} | |
#[doc = "Values that can be written to the field `CRCBEATSIZE`"] | |
pub enum CRCBEATSIZEW { | |
#[doc = "Byte bus access"] | |
BYTE, | |
#[doc = "Half-word bus access"] | |
HWORD, | |
#[doc = "Word bus access"] | |
WORD, | |
} | |
impl CRCBEATSIZEW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
CRCBEATSIZEW::BYTE => 0, | |
CRCBEATSIZEW::HWORD => 1, | |
CRCBEATSIZEW::WORD => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCBEATSIZEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCBEATSIZEW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: CRCBEATSIZEW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "Byte bus access"] | |
#[inline] | |
pub fn byte(self) -> &'a mut W { | |
self.variant(CRCBEATSIZEW::BYTE) | |
} | |
#[doc = "Half-word bus access"] | |
#[inline] | |
pub fn hword(self) -> &'a mut W { | |
self.variant(CRCBEATSIZEW::HWORD) | |
} | |
#[doc = "Word bus access"] | |
#[inline] | |
pub fn word(self) -> &'a mut W { | |
self.variant(CRCBEATSIZEW::WORD) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `CRCPOLY`"] | |
pub enum CRCPOLYW { | |
#[doc = "CRC-16 (CRC-CCITT)"] | |
CRC16, | |
#[doc = "CRC32 (IEEE 802.3)"] | |
CRC32, | |
} | |
impl CRCPOLYW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
CRCPOLYW::CRC16 => 0, | |
CRCPOLYW::CRC32 => 1, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCPOLYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCPOLYW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: CRCPOLYW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "CRC-16 (CRC-CCITT)"] | |
#[inline] | |
pub fn crc16(self) -> &'a mut W { | |
self.variant(CRCPOLYW::CRC16) | |
} | |
#[doc = "CRC32 (IEEE 802.3)"] | |
#[inline] | |
pub fn crc32(self) -> &'a mut W { | |
self.variant(CRCPOLYW::CRC32) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `CRCSRC`"] | |
pub enum CRCSRCW { | |
#[doc = "No action"] | |
NOACT, | |
#[doc = "I/O interface"] | |
IO, | |
} | |
impl CRCSRCW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
CRCSRCW::NOACT => 0, | |
CRCSRCW::IO => 1, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCSRCW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCSRCW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: CRCSRCW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No action"] | |
#[inline] | |
pub fn noact(self) -> &'a mut W { | |
self.variant(CRCSRCW::NOACT) | |
} | |
#[doc = "I/O interface"] | |
#[inline] | |
pub fn io(self) -> &'a mut W { | |
self.variant(CRCSRCW::IO) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:1 - CRC Beat Size"] | |
#[inline] | |
pub fn crcbeatsize(&self) -> CRCBEATSIZER { | |
CRCBEATSIZER::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}) | |
} | |
#[doc = "Bits 2:3 - CRC Polynomial Type"] | |
#[inline] | |
pub fn crcpoly(&self) -> CRCPOLYR { | |
CRCPOLYR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}) | |
} | |
#[doc = "Bits 8:13 - CRC Input Source"] | |
#[inline] | |
pub fn crcsrc(&self) -> CRCSRCR { | |
CRCSRCR::_from({ | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:1 - CRC Beat Size"] | |
#[inline] | |
pub fn crcbeatsize(&mut self) -> _CRCBEATSIZEW { | |
_CRCBEATSIZEW { w: self } | |
} | |
#[doc = "Bits 2:3 - CRC Polynomial Type"] | |
#[inline] | |
pub fn crcpoly(&mut self) -> _CRCPOLYW { | |
_CRCPOLYW { w: self } | |
} | |
#[doc = "Bits 8:13 - CRC Input Source"] | |
#[inline] | |
pub fn crcsrc(&mut self) -> _CRCSRCW { | |
_CRCSRCW { w: self } | |
} | |
} | |
} | |
#[doc = "CRC Data Input"] | |
pub struct CRCDATAIN { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "CRC Data Input"] | |
pub mod crcdatain { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::CRCDATAIN { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRCDATAINR { | |
bits: u32, | |
} | |
impl CRCDATAINR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCDATAINW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCDATAINW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - CRC Data Input"] | |
#[inline] | |
pub fn crcdatain(&self) -> CRCDATAINR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
CRCDATAINR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - CRC Data Input"] | |
#[inline] | |
pub fn crcdatain(&mut self) -> _CRCDATAINW { | |
_CRCDATAINW { w: self } | |
} | |
} | |
} | |
#[doc = "CRC Status"] | |
pub struct CRCSTATUS { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "CRC Status"] | |
pub mod crcstatus { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CRCSTATUS { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRCBUSYR { | |
bits: bool, | |
} | |
impl CRCBUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRCZEROR { | |
bits: bool, | |
} | |
impl CRCZEROR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCBUSYW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCBUSYW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - CRC Module Busy"] | |
#[inline] | |
pub fn crcbusy(&self) -> CRCBUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
CRCBUSYR { bits } | |
} | |
#[doc = "Bit 1 - CRC Zero"] | |
#[inline] | |
pub fn crczero(&self) -> CRCZEROR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
CRCZEROR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - CRC Module Busy"] | |
#[inline] | |
pub fn crcbusy(&mut self) -> _CRCBUSYW { | |
_CRCBUSYW { w: self } | |
} | |
} | |
} | |
#[doc = "Control"] | |
pub struct CTRL { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Control"] | |
pub mod ctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::CTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWRSTR { | |
bits: bool, | |
} | |
impl SWRSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DMAENABLER { | |
bits: bool, | |
} | |
impl DMAENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRCENABLER { | |
bits: bool, | |
} | |
impl CRCENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEN0R { | |
bits: bool, | |
} | |
impl LVLEN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEN1R { | |
bits: bool, | |
} | |
impl LVLEN1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEN2R { | |
bits: bool, | |
} | |
impl LVLEN2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLEN3R { | |
bits: bool, | |
} | |
impl LVLEN3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DMAENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DMAENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLEN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLEN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLEN1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLEN1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLEN2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLEN2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLEN3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLEN3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&self) -> SWRSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
SWRSTR { bits } | |
} | |
#[doc = "Bit 1 - DMA Enable"] | |
#[inline] | |
pub fn dmaenable(&self) -> DMAENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
DMAENABLER { bits } | |
} | |
#[doc = "Bit 2 - CRC Enable"] | |
#[inline] | |
pub fn crcenable(&self) -> CRCENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
CRCENABLER { bits } | |
} | |
#[doc = "Bit 8 - Priority Level 0 Enable"] | |
#[inline] | |
pub fn lvlen0(&self) -> LVLEN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
LVLEN0R { bits } | |
} | |
#[doc = "Bit 9 - Priority Level 1 Enable"] | |
#[inline] | |
pub fn lvlen1(&self) -> LVLEN1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
LVLEN1R { bits } | |
} | |
#[doc = "Bit 10 - Priority Level 2 Enable"] | |
#[inline] | |
pub fn lvlen2(&self) -> LVLEN2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
LVLEN2R { bits } | |
} | |
#[doc = "Bit 11 - Priority Level 3 Enable"] | |
#[inline] | |
pub fn lvlen3(&self) -> LVLEN3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
LVLEN3R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - DMA Enable"] | |
#[inline] | |
pub fn dmaenable(&mut self) -> _DMAENABLEW { | |
_DMAENABLEW { w: self } | |
} | |
#[doc = "Bit 2 - CRC Enable"] | |
#[inline] | |
pub fn crcenable(&mut self) -> _CRCENABLEW { | |
_CRCENABLEW { w: self } | |
} | |
#[doc = "Bit 8 - Priority Level 0 Enable"] | |
#[inline] | |
pub fn lvlen0(&mut self) -> _LVLEN0W { | |
_LVLEN0W { w: self } | |
} | |
#[doc = "Bit 9 - Priority Level 1 Enable"] | |
#[inline] | |
pub fn lvlen1(&mut self) -> _LVLEN1W { | |
_LVLEN1W { w: self } | |
} | |
#[doc = "Bit 10 - Priority Level 2 Enable"] | |
#[inline] | |
pub fn lvlen2(&mut self) -> _LVLEN2W { | |
_LVLEN2W { w: self } | |
} | |
#[doc = "Bit 11 - Priority Level 3 Enable"] | |
#[inline] | |
pub fn lvlen3(&mut self) -> _LVLEN3W { | |
_LVLEN3W { w: self } | |
} | |
} | |
} | |
#[doc = "Debug Control"] | |
pub struct DBGCTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Debug Control"] | |
pub mod dbgctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::DBGCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DBGRUNR { | |
bits: bool, | |
} | |
impl DBGRUNR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DBGRUNW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DBGRUNW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Debug Run"] | |
#[inline] | |
pub fn dbgrun(&self) -> DBGRUNR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DBGRUNR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Debug Run"] | |
#[inline] | |
pub fn dbgrun(&mut self) -> _DBGRUNW { | |
_DBGRUNW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Pending"] | |
pub struct INTPEND { | |
register: VolatileCell<u16>, | |
} | |
#[doc = "Interrupt Pending"] | |
pub mod intpend { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u16, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u16, | |
} | |
impl super::INTPEND { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct IDR { | |
bits: u8, | |
} | |
impl IDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TERRR { | |
bits: bool, | |
} | |
impl TERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct TCMPLR { | |
bits: bool, | |
} | |
impl TCMPLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SUSPR { | |
bits: bool, | |
} | |
impl SUSPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FERRR { | |
bits: bool, | |
} | |
impl FERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BUSYR { | |
bits: bool, | |
} | |
impl BUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDR { | |
bits: bool, | |
} | |
impl PENDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _IDW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _IDW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _TCMPLW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _TCMPLW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SUSPW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SUSPW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u16) << OFFSET); | |
self.w.bits |= ((value & MASK) as u16) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u16 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Channel ID"] | |
#[inline] | |
pub fn id(&self) -> IDR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u16) as u8 | |
}; | |
IDR { bits } | |
} | |
#[doc = "Bit 8 - Transfer Error"] | |
#[inline] | |
pub fn terr(&self) -> TERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
TERRR { bits } | |
} | |
#[doc = "Bit 9 - Transfer Complete"] | |
#[inline] | |
pub fn tcmpl(&self) -> TCMPLR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
TCMPLR { bits } | |
} | |
#[doc = "Bit 10 - Channel Suspend"] | |
#[inline] | |
pub fn susp(&self) -> SUSPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
SUSPR { bits } | |
} | |
#[doc = "Bit 13 - Fetch Error"] | |
#[inline] | |
pub fn ferr(&self) -> FERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
FERRR { bits } | |
} | |
#[doc = "Bit 14 - Busy"] | |
#[inline] | |
pub fn busy(&self) -> BUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
BUSYR { bits } | |
} | |
#[doc = "Bit 15 - Pending"] | |
#[inline] | |
pub fn pend(&self) -> PENDR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u16) != 0 | |
}; | |
PENDR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Channel ID"] | |
#[inline] | |
pub fn id(&mut self) -> _IDW { | |
_IDW { w: self } | |
} | |
#[doc = "Bit 8 - Transfer Error"] | |
#[inline] | |
pub fn terr(&mut self) -> _TERRW { | |
_TERRW { w: self } | |
} | |
#[doc = "Bit 9 - Transfer Complete"] | |
#[inline] | |
pub fn tcmpl(&mut self) -> _TCMPLW { | |
_TCMPLW { w: self } | |
} | |
#[doc = "Bit 10 - Channel Suspend"] | |
#[inline] | |
pub fn susp(&mut self) -> _SUSPW { | |
_SUSPW { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Status"] | |
pub struct INTSTATUS { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Interrupt Status"] | |
pub mod intstatus { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::INTSTATUS { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT0R { | |
bits: bool, | |
} | |
impl CHINT0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT1R { | |
bits: bool, | |
} | |
impl CHINT1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT2R { | |
bits: bool, | |
} | |
impl CHINT2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT3R { | |
bits: bool, | |
} | |
impl CHINT3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT4R { | |
bits: bool, | |
} | |
impl CHINT4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT5R { | |
bits: bool, | |
} | |
impl CHINT5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT6R { | |
bits: bool, | |
} | |
impl CHINT6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT7R { | |
bits: bool, | |
} | |
impl CHINT7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT8R { | |
bits: bool, | |
} | |
impl CHINT8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT9R { | |
bits: bool, | |
} | |
impl CHINT9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT10R { | |
bits: bool, | |
} | |
impl CHINT10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHINT11R { | |
bits: bool, | |
} | |
impl CHINT11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Channel 0 Pending Interrupt"] | |
#[inline] | |
pub fn chint0(&self) -> CHINT0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT0R { bits } | |
} | |
#[doc = "Bit 1 - Channel 1 Pending Interrupt"] | |
#[inline] | |
pub fn chint1(&self) -> CHINT1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT1R { bits } | |
} | |
#[doc = "Bit 2 - Channel 2 Pending Interrupt"] | |
#[inline] | |
pub fn chint2(&self) -> CHINT2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT2R { bits } | |
} | |
#[doc = "Bit 3 - Channel 3 Pending Interrupt"] | |
#[inline] | |
pub fn chint3(&self) -> CHINT3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT3R { bits } | |
} | |
#[doc = "Bit 4 - Channel 4 Pending Interrupt"] | |
#[inline] | |
pub fn chint4(&self) -> CHINT4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT4R { bits } | |
} | |
#[doc = "Bit 5 - Channel 5 Pending Interrupt"] | |
#[inline] | |
pub fn chint5(&self) -> CHINT5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT5R { bits } | |
} | |
#[doc = "Bit 6 - Channel 6 Pending Interrupt"] | |
#[inline] | |
pub fn chint6(&self) -> CHINT6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT6R { bits } | |
} | |
#[doc = "Bit 7 - Channel 7 Pending Interrupt"] | |
#[inline] | |
pub fn chint7(&self) -> CHINT7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT7R { bits } | |
} | |
#[doc = "Bit 8 - Channel 8 Pending Interrupt"] | |
#[inline] | |
pub fn chint8(&self) -> CHINT8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT8R { bits } | |
} | |
#[doc = "Bit 9 - Channel 9 Pending Interrupt"] | |
#[inline] | |
pub fn chint9(&self) -> CHINT9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT9R { bits } | |
} | |
#[doc = "Bit 10 - Channel 10 Pending Interrupt"] | |
#[inline] | |
pub fn chint10(&self) -> CHINT10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT10R { bits } | |
} | |
#[doc = "Bit 11 - Channel 11 Pending Interrupt"] | |
#[inline] | |
pub fn chint11(&self) -> CHINT11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
CHINT11R { bits } | |
} | |
} | |
} | |
#[doc = "Pending Channels"] | |
pub struct PENDCH { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Pending Channels"] | |
pub mod pendch { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PENDCH { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH0R { | |
bits: bool, | |
} | |
impl PENDCH0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH1R { | |
bits: bool, | |
} | |
impl PENDCH1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH2R { | |
bits: bool, | |
} | |
impl PENDCH2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH3R { | |
bits: bool, | |
} | |
impl PENDCH3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH4R { | |
bits: bool, | |
} | |
impl PENDCH4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH5R { | |
bits: bool, | |
} | |
impl PENDCH5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH6R { | |
bits: bool, | |
} | |
impl PENDCH6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH7R { | |
bits: bool, | |
} | |
impl PENDCH7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH8R { | |
bits: bool, | |
} | |
impl PENDCH8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH9R { | |
bits: bool, | |
} | |
impl PENDCH9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH10R { | |
bits: bool, | |
} | |
impl PENDCH10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PENDCH11R { | |
bits: bool, | |
} | |
impl PENDCH11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Pending Channel 0"] | |
#[inline] | |
pub fn pendch0(&self) -> PENDCH0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH0R { bits } | |
} | |
#[doc = "Bit 1 - Pending Channel 1"] | |
#[inline] | |
pub fn pendch1(&self) -> PENDCH1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH1R { bits } | |
} | |
#[doc = "Bit 2 - Pending Channel 2"] | |
#[inline] | |
pub fn pendch2(&self) -> PENDCH2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH2R { bits } | |
} | |
#[doc = "Bit 3 - Pending Channel 3"] | |
#[inline] | |
pub fn pendch3(&self) -> PENDCH3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH3R { bits } | |
} | |
#[doc = "Bit 4 - Pending Channel 4"] | |
#[inline] | |
pub fn pendch4(&self) -> PENDCH4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH4R { bits } | |
} | |
#[doc = "Bit 5 - Pending Channel 5"] | |
#[inline] | |
pub fn pendch5(&self) -> PENDCH5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH5R { bits } | |
} | |
#[doc = "Bit 6 - Pending Channel 6"] | |
#[inline] | |
pub fn pendch6(&self) -> PENDCH6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH6R { bits } | |
} | |
#[doc = "Bit 7 - Pending Channel 7"] | |
#[inline] | |
pub fn pendch7(&self) -> PENDCH7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH7R { bits } | |
} | |
#[doc = "Bit 8 - Pending Channel 8"] | |
#[inline] | |
pub fn pendch8(&self) -> PENDCH8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH8R { bits } | |
} | |
#[doc = "Bit 9 - Pending Channel 9"] | |
#[inline] | |
pub fn pendch9(&self) -> PENDCH9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH9R { bits } | |
} | |
#[doc = "Bit 10 - Pending Channel 10"] | |
#[inline] | |
pub fn pendch10(&self) -> PENDCH10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH10R { bits } | |
} | |
#[doc = "Bit 11 - Pending Channel 11"] | |
#[inline] | |
pub fn pendch11(&self) -> PENDCH11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
PENDCH11R { bits } | |
} | |
} | |
} | |
#[doc = "Priority Control 0"] | |
pub struct PRICTRL0 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Priority Control 0"] | |
pub mod prictrl0 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::PRICTRL0 { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLPRI0R { | |
bits: u8, | |
} | |
impl LVLPRI0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RRLVLEN0R { | |
bits: bool, | |
} | |
impl RRLVLEN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLPRI1R { | |
bits: u8, | |
} | |
impl LVLPRI1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RRLVLEN1R { | |
bits: bool, | |
} | |
impl RRLVLEN1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLPRI2R { | |
bits: u8, | |
} | |
impl LVLPRI2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RRLVLEN2R { | |
bits: bool, | |
} | |
impl RRLVLEN2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LVLPRI3R { | |
bits: u8, | |
} | |
impl LVLPRI3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct RRLVLEN3R { | |
bits: bool, | |
} | |
impl RRLVLEN3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLPRI0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLPRI0W<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RRLVLEN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RRLVLEN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLPRI1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLPRI1W<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RRLVLEN1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RRLVLEN1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLPRI2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLPRI2W<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 16; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RRLVLEN2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RRLVLEN2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 23; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LVLPRI3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LVLPRI3W<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _RRLVLEN3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _RRLVLEN3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 31; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Level 0 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri0(&self) -> LVLPRI0R { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
LVLPRI0R { bits } | |
} | |
#[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen0(&self) -> RRLVLEN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
RRLVLEN0R { bits } | |
} | |
#[doc = "Bits 8:11 - Level 1 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri1(&self) -> LVLPRI1R { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
LVLPRI1R { bits } | |
} | |
#[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen1(&self) -> RRLVLEN1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
RRLVLEN1R { bits } | |
} | |
#[doc = "Bits 16:19 - Level 2 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri2(&self) -> LVLPRI2R { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
LVLPRI2R { bits } | |
} | |
#[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen2(&self) -> RRLVLEN2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 23; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
RRLVLEN2R { bits } | |
} | |
#[doc = "Bits 24:27 - Level 3 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri3(&self) -> LVLPRI3R { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
LVLPRI3R { bits } | |
} | |
#[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen3(&self) -> RRLVLEN3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 31; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
RRLVLEN3R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Level 0 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri0(&mut self) -> _LVLPRI0W { | |
_LVLPRI0W { w: self } | |
} | |
#[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen0(&mut self) -> _RRLVLEN0W { | |
_RRLVLEN0W { w: self } | |
} | |
#[doc = "Bits 8:11 - Level 1 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri1(&mut self) -> _LVLPRI1W { | |
_LVLPRI1W { w: self } | |
} | |
#[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen1(&mut self) -> _RRLVLEN1W { | |
_RRLVLEN1W { w: self } | |
} | |
#[doc = "Bits 16:19 - Level 2 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri2(&mut self) -> _LVLPRI2W { | |
_LVLPRI2W { w: self } | |
} | |
#[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen2(&mut self) -> _RRLVLEN2W { | |
_RRLVLEN2W { w: self } | |
} | |
#[doc = "Bits 24:27 - Level 3 Channel Priority Number"] | |
#[inline] | |
pub fn lvlpri3(&mut self) -> _LVLPRI3W { | |
_LVLPRI3W { w: self } | |
} | |
#[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] | |
#[inline] | |
pub fn rrlvlen3(&mut self) -> _RRLVLEN3W { | |
_RRLVLEN3W { w: self } | |
} | |
} | |
} | |
#[doc = "Software Trigger Control"] | |
pub struct SWTRIGCTRL { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Software Trigger Control"] | |
pub mod swtrigctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::SWTRIGCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG0R { | |
bits: bool, | |
} | |
impl SWTRIG0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG1R { | |
bits: bool, | |
} | |
impl SWTRIG1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG2R { | |
bits: bool, | |
} | |
impl SWTRIG2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG3R { | |
bits: bool, | |
} | |
impl SWTRIG3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG4R { | |
bits: bool, | |
} | |
impl SWTRIG4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG5R { | |
bits: bool, | |
} | |
impl SWTRIG5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG6R { | |
bits: bool, | |
} | |
impl SWTRIG6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG7R { | |
bits: bool, | |
} | |
impl SWTRIG7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG8R { | |
bits: bool, | |
} | |
impl SWTRIG8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG9R { | |
bits: bool, | |
} | |
impl SWTRIG9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG10R { | |
bits: bool, | |
} | |
impl SWTRIG10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWTRIG11R { | |
bits: bool, | |
} | |
impl SWTRIG11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWTRIG11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWTRIG11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Channel 0 Software Trigger"] | |
#[inline] | |
pub fn swtrig0(&self) -> SWTRIG0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG0R { bits } | |
} | |
#[doc = "Bit 1 - Channel 1 Software Trigger"] | |
#[inline] | |
pub fn swtrig1(&self) -> SWTRIG1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG1R { bits } | |
} | |
#[doc = "Bit 2 - Channel 2 Software Trigger"] | |
#[inline] | |
pub fn swtrig2(&self) -> SWTRIG2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG2R { bits } | |
} | |
#[doc = "Bit 3 - Channel 3 Software Trigger"] | |
#[inline] | |
pub fn swtrig3(&self) -> SWTRIG3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG3R { bits } | |
} | |
#[doc = "Bit 4 - Channel 4 Software Trigger"] | |
#[inline] | |
pub fn swtrig4(&self) -> SWTRIG4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG4R { bits } | |
} | |
#[doc = "Bit 5 - Channel 5 Software Trigger"] | |
#[inline] | |
pub fn swtrig5(&self) -> SWTRIG5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG5R { bits } | |
} | |
#[doc = "Bit 6 - Channel 6 Software Trigger"] | |
#[inline] | |
pub fn swtrig6(&self) -> SWTRIG6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG6R { bits } | |
} | |
#[doc = "Bit 7 - Channel 7 Software Trigger"] | |
#[inline] | |
pub fn swtrig7(&self) -> SWTRIG7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG7R { bits } | |
} | |
#[doc = "Bit 8 - Channel 8 Software Trigger"] | |
#[inline] | |
pub fn swtrig8(&self) -> SWTRIG8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG8R { bits } | |
} | |
#[doc = "Bit 9 - Channel 9 Software Trigger"] | |
#[inline] | |
pub fn swtrig9(&self) -> SWTRIG9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG9R { bits } | |
} | |
#[doc = "Bit 10 - Channel 10 Software Trigger"] | |
#[inline] | |
pub fn swtrig10(&self) -> SWTRIG10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG10R { bits } | |
} | |
#[doc = "Bit 11 - Channel 11 Software Trigger"] | |
#[inline] | |
pub fn swtrig11(&self) -> SWTRIG11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWTRIG11R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Channel 0 Software Trigger"] | |
#[inline] | |
pub fn swtrig0(&mut self) -> _SWTRIG0W { | |
_SWTRIG0W { w: self } | |
} | |
#[doc = "Bit 1 - Channel 1 Software Trigger"] | |
#[inline] | |
pub fn swtrig1(&mut self) -> _SWTRIG1W { | |
_SWTRIG1W { w: self } | |
} | |
#[doc = "Bit 2 - Channel 2 Software Trigger"] | |
#[inline] | |
pub fn swtrig2(&mut self) -> _SWTRIG2W { | |
_SWTRIG2W { w: self } | |
} | |
#[doc = "Bit 3 - Channel 3 Software Trigger"] | |
#[inline] | |
pub fn swtrig3(&mut self) -> _SWTRIG3W { | |
_SWTRIG3W { w: self } | |
} | |
#[doc = "Bit 4 - Channel 4 Software Trigger"] | |
#[inline] | |
pub fn swtrig4(&mut self) -> _SWTRIG4W { | |
_SWTRIG4W { w: self } | |
} | |
#[doc = "Bit 5 - Channel 5 Software Trigger"] | |
#[inline] | |
pub fn swtrig5(&mut self) -> _SWTRIG5W { | |
_SWTRIG5W { w: self } | |
} | |
#[doc = "Bit 6 - Channel 6 Software Trigger"] | |
#[inline] | |
pub fn swtrig6(&mut self) -> _SWTRIG6W { | |
_SWTRIG6W { w: self } | |
} | |
#[doc = "Bit 7 - Channel 7 Software Trigger"] | |
#[inline] | |
pub fn swtrig7(&mut self) -> _SWTRIG7W { | |
_SWTRIG7W { w: self } | |
} | |
#[doc = "Bit 8 - Channel 8 Software Trigger"] | |
#[inline] | |
pub fn swtrig8(&mut self) -> _SWTRIG8W { | |
_SWTRIG8W { w: self } | |
} | |
#[doc = "Bit 9 - Channel 9 Software Trigger"] | |
#[inline] | |
pub fn swtrig9(&mut self) -> _SWTRIG9W { | |
_SWTRIG9W { w: self } | |
} | |
#[doc = "Bit 10 - Channel 10 Software Trigger"] | |
#[inline] | |
pub fn swtrig10(&mut self) -> _SWTRIG10W { | |
_SWTRIG10W { w: self } | |
} | |
#[doc = "Bit 11 - Channel 11 Software Trigger"] | |
#[inline] | |
pub fn swtrig11(&mut self) -> _SWTRIG11W { | |
_SWTRIG11W { w: self } | |
} | |
} | |
} | |
#[doc = "Write-Back Memory Section Base Address"] | |
pub struct WRBADDR { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Write-Back Memory Section Base Address"] | |
pub mod wrbaddr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::WRBADDR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WRBADDRR { | |
bits: u32, | |
} | |
impl WRBADDRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WRBADDRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WRBADDRW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - Write-Back Memory Base Address"] | |
#[inline] | |
pub fn wrbaddr(&self) -> WRBADDRR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
WRBADDRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - Write-Back Memory Base Address"] | |
#[inline] | |
pub fn wrbaddr(&mut self) -> _WRBADDRW { | |
_WRBADDRW { w: self } | |
} | |
} | |
} | |
} | |
#[doc = "Device Service Unit"] | |
pub struct DSU { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for DSU {} | |
impl DSU { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const dsu::RegisterBlock { | |
0x4100_2000 as *const _ | |
} | |
} | |
impl Deref for DSU { | |
type Target = dsu::RegisterBlock; | |
fn deref(&self) -> &dsu::RegisterBlock { | |
unsafe { &*DSU::ptr() } | |
} | |
} | |
#[doc = "Device Service Unit"] | |
pub mod dsu { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control"] | |
pub ctrl: CTRL, | |
#[doc = "0x01 - Status A"] | |
pub statusa: STATUSA, | |
#[doc = "0x02 - Status B"] | |
pub statusb: STATUSB, | |
_reserved0: [u8; 1usize], | |
#[doc = "0x04 - Address"] | |
pub addr: ADDR, | |
#[doc = "0x08 - Length"] | |
pub length: LENGTH, | |
#[doc = "0x0c - Data"] | |
pub data: DATA, | |
#[doc = "0x10 - Debug Communication Channel n"] | |
pub dcc: [DCC; 2], | |
#[doc = "0x18 - Device Identification"] | |
pub did: DID, | |
_reserved1: [u8; 4068usize], | |
#[doc = "0x1000 - Coresight ROM Table Entry n"] | |
pub entry: [ENTRY; 2], | |
#[doc = "0x1008 - Coresight ROM Table End"] | |
pub end: END, | |
_reserved2: [u8; 4032usize], | |
#[doc = "0x1fcc - Coresight ROM Table Memory Type"] | |
pub memtype: MEMTYPE, | |
#[doc = "0x1fd0 - Peripheral Identification 4"] | |
pub pid4: PID4, | |
_reserved3: [u8; 12usize], | |
#[doc = "0x1fe0 - Peripheral Identification 0"] | |
pub pid0: PID0, | |
#[doc = "0x1fe4 - Peripheral Identification 1"] | |
pub pid1: PID1, | |
#[doc = "0x1fe8 - Peripheral Identification 2"] | |
pub pid2: PID2, | |
#[doc = "0x1fec - Peripheral Identification 3"] | |
pub pid3: PID3, | |
#[doc = "0x1ff0 - Component Identification 0"] | |
pub cid0: CID0, | |
#[doc = "0x1ff4 - Component Identification 1"] | |
pub cid1: CID1, | |
#[doc = "0x1ff8 - Component Identification 2"] | |
pub cid2: CID2, | |
#[doc = "0x1ffc - Component Identification 3"] | |
pub cid3: CID3, | |
} | |
#[doc = "Address"] | |
pub struct ADDR { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Address"] | |
pub mod addr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::ADDR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ADDRR { | |
bits: u32, | |
} | |
impl ADDRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ADDRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ADDRW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0x3fff_ffff; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 2:31 - Address"] | |
#[inline] | |
pub fn addr(&self) -> ADDRR { | |
let bits = { | |
const MASK: u32 = 0x3fff_ffff; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
ADDRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 2:31 - Address"] | |
#[inline] | |
pub fn addr(&mut self) -> _ADDRW { | |
_ADDRW { w: self } | |
} | |
} | |
} | |
#[doc = "Component Identification 0"] | |
pub struct CID0 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Component Identification 0"] | |
pub mod cid0 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::CID0 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PREAMBLEB0R { | |
bits: u8, | |
} | |
impl PREAMBLEB0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Preamble Byte 0"] | |
#[inline] | |
pub fn preambleb0(&self) -> PREAMBLEB0R { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PREAMBLEB0R { bits } | |
} | |
} | |
} | |
#[doc = "Component Identification 1"] | |
pub struct CID1 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Component Identification 1"] | |
pub mod cid1 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::CID1 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PREAMBLER { | |
bits: u8, | |
} | |
impl PREAMBLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CCLASSR { | |
bits: u8, | |
} | |
impl CCLASSR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Preamble"] | |
#[inline] | |
pub fn preamble(&self) -> PREAMBLER { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PREAMBLER { bits } | |
} | |
#[doc = "Bits 4:7 - Component Class"] | |
#[inline] | |
pub fn cclass(&self) -> CCLASSR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
CCLASSR { bits } | |
} | |
} | |
} | |
#[doc = "Component Identification 2"] | |
pub struct CID2 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Component Identification 2"] | |
pub mod cid2 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::CID2 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PREAMBLEB2R { | |
bits: u8, | |
} | |
impl PREAMBLEB2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Preamble Byte 2"] | |
#[inline] | |
pub fn preambleb2(&self) -> PREAMBLEB2R { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PREAMBLEB2R { bits } | |
} | |
} | |
} | |
#[doc = "Component Identification 3"] | |
pub struct CID3 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Component Identification 3"] | |
pub mod cid3 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::CID3 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PREAMBLEB3R { | |
bits: u8, | |
} | |
impl PREAMBLEB3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Preamble Byte 3"] | |
#[inline] | |
pub fn preambleb3(&self) -> PREAMBLEB3R { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PREAMBLEB3R { bits } | |
} | |
} | |
} | |
#[doc = "Control"] | |
pub struct CTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control"] | |
pub mod ctrl { | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRL { | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRCW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRCW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _MBISTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _MBISTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 2 - 32-bit Cyclic Redundancy Check"] | |
#[inline] | |
pub fn crc(&mut self) -> _CRCW { | |
_CRCW { w: self } | |
} | |
#[doc = "Bit 3 - Memory Built-In Self-Test"] | |
#[inline] | |
pub fn mbist(&mut self) -> _MBISTW { | |
_MBISTW { w: self } | |
} | |
#[doc = "Bit 4 - Chip Erase"] | |
#[inline] | |
pub fn ce(&mut self) -> _CEW { | |
_CEW { w: self } | |
} | |
} | |
} | |
#[doc = "Data"] | |
pub struct DATA { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Data"] | |
pub mod data { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::DATA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DATAR { | |
bits: u32, | |
} | |
impl DATAR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DATAW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DATAW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - Data"] | |
#[inline] | |
pub fn data(&self) -> DATAR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
DATAR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - Data"] | |
#[inline] | |
pub fn data(&mut self) -> _DATAW { | |
_DATAW { w: self } | |
} | |
} | |
} | |
#[doc = "Debug Communication Channel n"] | |
pub struct DCC { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Debug Communication Channel n"] | |
pub mod dcc { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::DCC { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DATAR { | |
bits: u32, | |
} | |
impl DATAR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DATAW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DATAW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - Data"] | |
#[inline] | |
pub fn data(&self) -> DATAR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
DATAR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:31 - Data"] | |
#[inline] | |
pub fn data(&mut self) -> _DATAW { | |
_DATAW { w: self } | |
} | |
} | |
} | |
#[doc = "Device Identification"] | |
pub struct DID { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Device Identification"] | |
pub mod did { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::DID { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DEVSELR { | |
bits: u8, | |
} | |
impl DEVSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct REVISIONR { | |
bits: u8, | |
} | |
impl REVISIONR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DIER { | |
bits: u8, | |
} | |
impl DIER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SERIESR { | |
bits: u8, | |
} | |
impl SERIESR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FAMILYR { | |
bits: u8, | |
} | |
impl FAMILYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PROCESSORR { | |
bits: u8, | |
} | |
impl PROCESSORR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Device Select"] | |
#[inline] | |
pub fn devsel(&self) -> DEVSELR { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
DEVSELR { bits } | |
} | |
#[doc = "Bits 8:11 - Revision"] | |
#[inline] | |
pub fn revision(&self) -> REVISIONR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
REVISIONR { bits } | |
} | |
#[doc = "Bits 12:15 - Die Identification"] | |
#[inline] | |
pub fn die(&self) -> DIER { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
DIER { bits } | |
} | |
#[doc = "Bits 16:21 - Product Series"] | |
#[inline] | |
pub fn series(&self) -> SERIESR { | |
let bits = { | |
const MASK: u8 = 0x3f; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
SERIESR { bits } | |
} | |
#[doc = "Bits 23:27 - Product Family"] | |
#[inline] | |
pub fn family(&self) -> FAMILYR { | |
let bits = { | |
const MASK: u8 = 0x1f; | |
const OFFSET: u8 = 23; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
FAMILYR { bits } | |
} | |
#[doc = "Bits 28:31 - Processor"] | |
#[inline] | |
pub fn processor(&self) -> PROCESSORR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 28; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PROCESSORR { bits } | |
} | |
} | |
} | |
#[doc = "Coresight ROM Table End"] | |
pub struct END { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Coresight ROM Table End"] | |
pub mod end { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::END { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENDR { | |
bits: u32, | |
} | |
impl ENDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:31 - End Marker"] | |
#[inline] | |
pub fn end(&self) -> ENDR { | |
let bits = { | |
const MASK: u32 = 0xffff_ffff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
ENDR { bits } | |
} | |
} | |
} | |
#[doc = "Coresight ROM Table Entry n"] | |
pub struct ENTRY { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Coresight ROM Table Entry n"] | |
pub mod entry { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::ENTRY { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EPRESR { | |
bits: bool, | |
} | |
impl EPRESR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FMTR { | |
bits: bool, | |
} | |
impl FMTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ADDOFFR { | |
bits: u32, | |
} | |
impl ADDOFFR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Entry Present"] | |
#[inline] | |
pub fn epres(&self) -> EPRESR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EPRESR { bits } | |
} | |
#[doc = "Bit 1 - Format"] | |
#[inline] | |
pub fn fmt(&self) -> FMTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FMTR { bits } | |
} | |
#[doc = "Bits 12:31 - Address Offset"] | |
#[inline] | |
pub fn addoff(&self) -> ADDOFFR { | |
let bits = { | |
const MASK: u32 = 0x000f_ffff; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
ADDOFFR { bits } | |
} | |
} | |
} | |
#[doc = "Length"] | |
pub struct LENGTH { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Length"] | |
pub mod length { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::LENGTH { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct LENGTHR { | |
bits: u32, | |
} | |
impl LENGTHR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _LENGTHW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _LENGTHW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u32) -> &'a mut W { | |
const MASK: u32 = 0x3fff_ffff; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 2:31 - Length"] | |
#[inline] | |
pub fn length(&self) -> LENGTHR { | |
let bits = { | |
const MASK: u32 = 0x3fff_ffff; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) as u32 | |
}; | |
LENGTHR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 2:31 - Length"] | |
#[inline] | |
pub fn length(&mut self) -> _LENGTHW { | |
_LENGTHW { w: self } | |
} | |
} | |
} | |
#[doc = "Coresight ROM Table Memory Type"] | |
pub struct MEMTYPE { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Coresight ROM Table Memory Type"] | |
pub mod memtype { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::MEMTYPE { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SMEMPR { | |
bits: bool, | |
} | |
impl SMEMPR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - System Memory Present"] | |
#[inline] | |
pub fn smemp(&self) -> SMEMPR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SMEMPR { bits } | |
} | |
} | |
} | |
#[doc = "Peripheral Identification 0"] | |
pub struct PID0 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Peripheral Identification 0"] | |
pub mod pid0 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PID0 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PARTNBLR { | |
bits: u8, | |
} | |
impl PARTNBLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:7 - Part Number Low"] | |
#[inline] | |
pub fn partnbl(&self) -> PARTNBLR { | |
let bits = { | |
const MASK: u8 = 0xff; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PARTNBLR { bits } | |
} | |
} | |
} | |
#[doc = "Peripheral Identification 1"] | |
pub struct PID1 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Peripheral Identification 1"] | |
pub mod pid1 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PID1 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PARTNBHR { | |
bits: u8, | |
} | |
impl PARTNBHR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct JEPIDCLR { | |
bits: u8, | |
} | |
impl JEPIDCLR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Part Number High"] | |
#[inline] | |
pub fn partnbh(&self) -> PARTNBHR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
PARTNBHR { bits } | |
} | |
#[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] | |
#[inline] | |
pub fn jepidcl(&self) -> JEPIDCLR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
JEPIDCLR { bits } | |
} | |
} | |
} | |
#[doc = "Peripheral Identification 2"] | |
pub struct PID2 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Peripheral Identification 2"] | |
pub mod pid2 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PID2 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct JEPIDCHR { | |
bits: u8, | |
} | |
impl JEPIDCHR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct JEPUR { | |
bits: bool, | |
} | |
impl JEPUR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct REVISIONR { | |
bits: u8, | |
} | |
impl REVISIONR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:2 - JEP-106 Identity Code High"] | |
#[inline] | |
pub fn jepidch(&self) -> JEPIDCHR { | |
let bits = { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
JEPIDCHR { bits } | |
} | |
#[doc = "Bit 3 - JEP-106 Identity Code is used"] | |
#[inline] | |
pub fn jepu(&self) -> JEPUR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
JEPUR { bits } | |
} | |
#[doc = "Bits 4:7 - Revision Number"] | |
#[inline] | |
pub fn revision(&self) -> REVISIONR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
REVISIONR { bits } | |
} | |
} | |
} | |
#[doc = "Peripheral Identification 3"] | |
pub struct PID3 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Peripheral Identification 3"] | |
pub mod pid3 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PID3 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CUSMODR { | |
bits: u8, | |
} | |
impl CUSMODR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct REVANDR { | |
bits: u8, | |
} | |
impl REVANDR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - ARM CUSMOD"] | |
#[inline] | |
pub fn cusmod(&self) -> CUSMODR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
CUSMODR { bits } | |
} | |
#[doc = "Bits 4:7 - Revision Number"] | |
#[inline] | |
pub fn revand(&self) -> REVANDR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
REVANDR { bits } | |
} | |
} | |
} | |
#[doc = "Peripheral Identification 4"] | |
pub struct PID4 { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Peripheral Identification 4"] | |
pub mod pid4 { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
impl super::PID4 { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct JEPCCR { | |
bits: u8, | |
} | |
impl JEPCCR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FKBCR { | |
bits: u8, | |
} | |
impl FKBCR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - JEP-106 Continuation Code"] | |
#[inline] | |
pub fn jepcc(&self) -> JEPCCR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
JEPCCR { bits } | |
} | |
#[doc = "Bits 4:7 - 4KB Count"] | |
#[inline] | |
pub fn fkbc(&self) -> FKBCR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
FKBCR { bits } | |
} | |
} | |
} | |
#[doc = "Status A"] | |
pub struct STATUSA { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status A"] | |
pub mod statusa { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::STATUSA { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DONER { | |
bits: bool, | |
} | |
impl DONER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CRSTEXTR { | |
bits: bool, | |
} | |
impl CRSTEXTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct BERRR { | |
bits: bool, | |
} | |
impl BERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FAILR { | |
bits: bool, | |
} | |
impl FAILR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PERRR { | |
bits: bool, | |
} | |
impl PERRR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _DONEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _DONEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CRSTEXTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CRSTEXTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _BERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _BERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FAILW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FAILW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _PERRW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _PERRW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Done"] | |
#[inline] | |
pub fn done(&self) -> DONER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DONER { bits } | |
} | |
#[doc = "Bit 1 - CPU Reset Phase Extension"] | |
#[inline] | |
pub fn crstext(&self) -> CRSTEXTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
CRSTEXTR { bits } | |
} | |
#[doc = "Bit 2 - Bus Error"] | |
#[inline] | |
pub fn berr(&self) -> BERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
BERRR { bits } | |
} | |
#[doc = "Bit 3 - Failure"] | |
#[inline] | |
pub fn fail(&self) -> FAILR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
FAILR { bits } | |
} | |
#[doc = "Bit 4 - Protection Error"] | |
#[inline] | |
pub fn perr(&self) -> PERRR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
PERRR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Done"] | |
#[inline] | |
pub fn done(&mut self) -> _DONEW { | |
_DONEW { w: self } | |
} | |
#[doc = "Bit 1 - CPU Reset Phase Extension"] | |
#[inline] | |
pub fn crstext(&mut self) -> _CRSTEXTW { | |
_CRSTEXTW { w: self } | |
} | |
#[doc = "Bit 2 - Bus Error"] | |
#[inline] | |
pub fn berr(&mut self) -> _BERRW { | |
_BERRW { w: self } | |
} | |
#[doc = "Bit 3 - Failure"] | |
#[inline] | |
pub fn fail(&mut self) -> _FAILW { | |
_FAILW { w: self } | |
} | |
#[doc = "Bit 4 - Protection Error"] | |
#[inline] | |
pub fn perr(&mut self) -> _PERRW { | |
_PERRW { w: self } | |
} | |
} | |
} | |
#[doc = "Status B"] | |
pub struct STATUSB { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status B"] | |
pub mod statusb { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUSB { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct PROTR { | |
bits: bool, | |
} | |
impl PROTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DBGPRESR { | |
bits: bool, | |
} | |
impl DBGPRESR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DCCD0R { | |
bits: bool, | |
} | |
impl DCCD0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct DCCD1R { | |
bits: bool, | |
} | |
impl DCCD1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct HPER { | |
bits: bool, | |
} | |
impl HPER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Protected"] | |
#[inline] | |
pub fn prot(&self) -> PROTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
PROTR { bits } | |
} | |
#[doc = "Bit 1 - Debugger Present"] | |
#[inline] | |
pub fn dbgpres(&self) -> DBGPRESR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DBGPRESR { bits } | |
} | |
#[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] | |
#[inline] | |
pub fn dccd0(&self) -> DCCD0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DCCD0R { bits } | |
} | |
#[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] | |
#[inline] | |
pub fn dccd1(&self) -> DCCD1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
DCCD1R { bits } | |
} | |
#[doc = "Bit 4 - Hot-Plugging Enable"] | |
#[inline] | |
pub fn hpe(&self) -> HPER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
HPER { bits } | |
} | |
} | |
} | |
} | |
#[doc = "External Interrupt Controller"] | |
pub struct EIC { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for EIC {} | |
impl EIC { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const eic::RegisterBlock { | |
0x4000_1800 as *const _ | |
} | |
} | |
impl Deref for EIC { | |
type Target = eic::RegisterBlock; | |
fn deref(&self) -> &eic::RegisterBlock { | |
unsafe { &*EIC::ptr() } | |
} | |
} | |
#[doc = "External Interrupt Controller"] | |
pub mod eic { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control"] | |
pub ctrl: CTRL, | |
#[doc = "0x01 - Status"] | |
pub status: STATUS, | |
#[doc = "0x02 - Non-Maskable Interrupt Control"] | |
pub nmictrl: NMICTRL, | |
#[doc = "0x03 - Non-Maskable Interrupt Flag Status and Clear"] | |
pub nmiflag: NMIFLAG, | |
#[doc = "0x04 - Event Control"] | |
pub evctrl: EVCTRL, | |
#[doc = "0x08 - Interrupt Enable Clear"] | |
pub intenclr: INTENCLR, | |
#[doc = "0x0c - Interrupt Enable Set"] | |
pub intenset: INTENSET, | |
#[doc = "0x10 - Interrupt Flag Status and Clear"] | |
pub intflag: INTFLAG, | |
#[doc = "0x14 - Wake-Up Enable"] | |
pub wakeup: WAKEUP, | |
#[doc = "0x18 - Configuration n"] | |
pub config: [CONFIG; 2], | |
} | |
#[doc = "Configuration n"] | |
pub struct CONFIG { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Configuration n"] | |
pub mod config { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::CONFIG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `SENSE0`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE0R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising-edge detection"] | |
RISE, | |
#[doc = "Falling-edge detection"] | |
FALL, | |
#[doc = "Both-edges detection"] | |
BOTH, | |
#[doc = "High-level detection"] | |
HIGH, | |
#[doc = "Low-level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE0R::NONE => 0, | |
SENSE0R::RISE => 0x01, | |
SENSE0R::FALL => 0x02, | |
SENSE0R::BOTH => 0x03, | |
SENSE0R::HIGH => 0x04, | |
SENSE0R::LOW => 0x05, | |
SENSE0R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE0R { | |
match value { | |
0 => SENSE0R::NONE, | |
1 => SENSE0R::RISE, | |
2 => SENSE0R::FALL, | |
3 => SENSE0R::BOTH, | |
4 => SENSE0R::HIGH, | |
5 => SENSE0R::LOW, | |
i => SENSE0R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE0R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE0R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE0R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE0R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE0R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE0R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN0R { | |
bits: bool, | |
} | |
impl FILTEN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE1`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE1R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE1R::NONE => 0, | |
SENSE1R::RISE => 0x01, | |
SENSE1R::FALL => 0x02, | |
SENSE1R::BOTH => 0x03, | |
SENSE1R::HIGH => 0x04, | |
SENSE1R::LOW => 0x05, | |
SENSE1R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE1R { | |
match value { | |
0 => SENSE1R::NONE, | |
1 => SENSE1R::RISE, | |
2 => SENSE1R::FALL, | |
3 => SENSE1R::BOTH, | |
4 => SENSE1R::HIGH, | |
5 => SENSE1R::LOW, | |
i => SENSE1R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE1R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE1R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE1R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE1R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE1R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE1R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN1R { | |
bits: bool, | |
} | |
impl FILTEN1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE2`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE2R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE2R::NONE => 0, | |
SENSE2R::RISE => 0x01, | |
SENSE2R::FALL => 0x02, | |
SENSE2R::BOTH => 0x03, | |
SENSE2R::HIGH => 0x04, | |
SENSE2R::LOW => 0x05, | |
SENSE2R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE2R { | |
match value { | |
0 => SENSE2R::NONE, | |
1 => SENSE2R::RISE, | |
2 => SENSE2R::FALL, | |
3 => SENSE2R::BOTH, | |
4 => SENSE2R::HIGH, | |
5 => SENSE2R::LOW, | |
i => SENSE2R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE2R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE2R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE2R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE2R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE2R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE2R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN2R { | |
bits: bool, | |
} | |
impl FILTEN2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE3`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE3R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE3R::NONE => 0, | |
SENSE3R::RISE => 0x01, | |
SENSE3R::FALL => 0x02, | |
SENSE3R::BOTH => 0x03, | |
SENSE3R::HIGH => 0x04, | |
SENSE3R::LOW => 0x05, | |
SENSE3R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE3R { | |
match value { | |
0 => SENSE3R::NONE, | |
1 => SENSE3R::RISE, | |
2 => SENSE3R::FALL, | |
3 => SENSE3R::BOTH, | |
4 => SENSE3R::HIGH, | |
5 => SENSE3R::LOW, | |
i => SENSE3R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE3R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE3R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE3R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE3R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE3R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE3R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN3R { | |
bits: bool, | |
} | |
impl FILTEN3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE4`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE4R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE4R::NONE => 0, | |
SENSE4R::RISE => 0x01, | |
SENSE4R::FALL => 0x02, | |
SENSE4R::BOTH => 0x03, | |
SENSE4R::HIGH => 0x04, | |
SENSE4R::LOW => 0x05, | |
SENSE4R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE4R { | |
match value { | |
0 => SENSE4R::NONE, | |
1 => SENSE4R::RISE, | |
2 => SENSE4R::FALL, | |
3 => SENSE4R::BOTH, | |
4 => SENSE4R::HIGH, | |
5 => SENSE4R::LOW, | |
i => SENSE4R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE4R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE4R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE4R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE4R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE4R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE4R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN4R { | |
bits: bool, | |
} | |
impl FILTEN4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE5`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE5R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE5R::NONE => 0, | |
SENSE5R::RISE => 0x01, | |
SENSE5R::FALL => 0x02, | |
SENSE5R::BOTH => 0x03, | |
SENSE5R::HIGH => 0x04, | |
SENSE5R::LOW => 0x05, | |
SENSE5R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE5R { | |
match value { | |
0 => SENSE5R::NONE, | |
1 => SENSE5R::RISE, | |
2 => SENSE5R::FALL, | |
3 => SENSE5R::BOTH, | |
4 => SENSE5R::HIGH, | |
5 => SENSE5R::LOW, | |
i => SENSE5R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE5R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE5R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE5R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE5R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE5R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE5R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN5R { | |
bits: bool, | |
} | |
impl FILTEN5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE6`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE6R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE6R::NONE => 0, | |
SENSE6R::RISE => 0x01, | |
SENSE6R::FALL => 0x02, | |
SENSE6R::BOTH => 0x03, | |
SENSE6R::HIGH => 0x04, | |
SENSE6R::LOW => 0x05, | |
SENSE6R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE6R { | |
match value { | |
0 => SENSE6R::NONE, | |
1 => SENSE6R::RISE, | |
2 => SENSE6R::FALL, | |
3 => SENSE6R::BOTH, | |
4 => SENSE6R::HIGH, | |
5 => SENSE6R::LOW, | |
i => SENSE6R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE6R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE6R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE6R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE6R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE6R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE6R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN6R { | |
bits: bool, | |
} | |
impl FILTEN6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Possible values of the field `SENSE7`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum SENSE7R { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl SENSE7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
SENSE7R::NONE => 0, | |
SENSE7R::RISE => 0x01, | |
SENSE7R::FALL => 0x02, | |
SENSE7R::BOTH => 0x03, | |
SENSE7R::HIGH => 0x04, | |
SENSE7R::LOW => 0x05, | |
SENSE7R::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> SENSE7R { | |
match value { | |
0 => SENSE7R::NONE, | |
1 => SENSE7R::RISE, | |
2 => SENSE7R::FALL, | |
3 => SENSE7R::BOTH, | |
4 => SENSE7R::HIGH, | |
5 => SENSE7R::LOW, | |
i => SENSE7R::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == SENSE7R::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == SENSE7R::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == SENSE7R::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == SENSE7R::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == SENSE7R::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == SENSE7R::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct FILTEN7R { | |
bits: bool, | |
} | |
impl FILTEN7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE0`"] | |
pub enum SENSE0W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising-edge detection"] | |
RISE, | |
#[doc = "Falling-edge detection"] | |
FALL, | |
#[doc = "Both-edges detection"] | |
BOTH, | |
#[doc = "High-level detection"] | |
HIGH, | |
#[doc = "Low-level detection"] | |
LOW, | |
} | |
impl SENSE0W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE0W::NONE => 0, | |
SENSE0W::RISE => 1, | |
SENSE0W::FALL => 2, | |
SENSE0W::BOTH => 3, | |
SENSE0W::HIGH => 4, | |
SENSE0W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE0W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE0W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE0W::NONE) | |
} | |
#[doc = "Rising-edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE0W::RISE) | |
} | |
#[doc = "Falling-edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE0W::FALL) | |
} | |
#[doc = "Both-edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE0W::BOTH) | |
} | |
#[doc = "High-level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE0W::HIGH) | |
} | |
#[doc = "Low-level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE0W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE1`"] | |
pub enum SENSE1W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE1W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE1W::NONE => 0, | |
SENSE1W::RISE => 1, | |
SENSE1W::FALL => 2, | |
SENSE1W::BOTH => 3, | |
SENSE1W::HIGH => 4, | |
SENSE1W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE1W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE1W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE1W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE1W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE1W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE1W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE1W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE1W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE2`"] | |
pub enum SENSE2W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE2W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE2W::NONE => 0, | |
SENSE2W::RISE => 1, | |
SENSE2W::FALL => 2, | |
SENSE2W::BOTH => 3, | |
SENSE2W::HIGH => 4, | |
SENSE2W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE2W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE2W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE2W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE2W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE2W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE2W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE2W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE2W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE3`"] | |
pub enum SENSE3W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE3W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE3W::NONE => 0, | |
SENSE3W::RISE => 1, | |
SENSE3W::FALL => 2, | |
SENSE3W::BOTH => 3, | |
SENSE3W::HIGH => 4, | |
SENSE3W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE3W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE3W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE3W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE3W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE3W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE3W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE3W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE3W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE4`"] | |
pub enum SENSE4W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE4W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE4W::NONE => 0, | |
SENSE4W::RISE => 1, | |
SENSE4W::FALL => 2, | |
SENSE4W::BOTH => 3, | |
SENSE4W::HIGH => 4, | |
SENSE4W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE4W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE4W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE4W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE4W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE4W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE4W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE4W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE4W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 16; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 19; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE5`"] | |
pub enum SENSE5W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE5W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE5W::NONE => 0, | |
SENSE5W::RISE => 1, | |
SENSE5W::FALL => 2, | |
SENSE5W::BOTH => 3, | |
SENSE5W::HIGH => 4, | |
SENSE5W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE5W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE5W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE5W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE5W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE5W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE5W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE5W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE5W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 20; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 23; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE6`"] | |
pub enum SENSE6W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE6W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE6W::NONE => 0, | |
SENSE6W::RISE => 1, | |
SENSE6W::FALL => 2, | |
SENSE6W::BOTH => 3, | |
SENSE6W::HIGH => 4, | |
SENSE6W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE6W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE6W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE6W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE6W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE6W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE6W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE6W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE6W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 27; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `SENSE7`"] | |
pub enum SENSE7W { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising edge detection"] | |
RISE, | |
#[doc = "Falling edge detection"] | |
FALL, | |
#[doc = "Both edges detection"] | |
BOTH, | |
#[doc = "High level detection"] | |
HIGH, | |
#[doc = "Low level detection"] | |
LOW, | |
} | |
impl SENSE7W { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
SENSE7W::NONE => 0, | |
SENSE7W::RISE => 1, | |
SENSE7W::FALL => 2, | |
SENSE7W::BOTH => 3, | |
SENSE7W::HIGH => 4, | |
SENSE7W::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SENSE7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SENSE7W<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: SENSE7W) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(SENSE7W::NONE) | |
} | |
#[doc = "Rising edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(SENSE7W::RISE) | |
} | |
#[doc = "Falling edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(SENSE7W::FALL) | |
} | |
#[doc = "Both edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(SENSE7W::BOTH) | |
} | |
#[doc = "High level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(SENSE7W::HIGH) | |
} | |
#[doc = "Low level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(SENSE7W::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 28; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _FILTEN7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _FILTEN7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 31; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:2 - Input Sense n Configuration"] | |
#[inline] | |
pub fn sense0(&self) -> SENSE0R { | |
SENSE0R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 3 - Filter n Enable"] | |
#[inline] | |
pub fn filten0(&self) -> FILTEN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN0R { bits } | |
} | |
#[doc = "Bits 4:6 - Input Sense 1 Configuration"] | |
#[inline] | |
pub fn sense1(&self) -> SENSE1R { | |
SENSE1R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 7 - Filter 1 Enable"] | |
#[inline] | |
pub fn filten1(&self) -> FILTEN1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN1R { bits } | |
} | |
#[doc = "Bits 8:10 - Input Sense 2 Configuration"] | |
#[inline] | |
pub fn sense2(&self) -> SENSE2R { | |
SENSE2R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 11 - Filter 2 Enable"] | |
#[inline] | |
pub fn filten2(&self) -> FILTEN2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN2R { bits } | |
} | |
#[doc = "Bits 12:14 - Input Sense 3 Configuration"] | |
#[inline] | |
pub fn sense3(&self) -> SENSE3R { | |
SENSE3R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 15 - Filter 3 Enable"] | |
#[inline] | |
pub fn filten3(&self) -> FILTEN3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN3R { bits } | |
} | |
#[doc = "Bits 16:18 - Input Sense 4 Configuration"] | |
#[inline] | |
pub fn sense4(&self) -> SENSE4R { | |
SENSE4R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 19 - Filter 4 Enable"] | |
#[inline] | |
pub fn filten4(&self) -> FILTEN4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 19; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN4R { bits } | |
} | |
#[doc = "Bits 20:22 - Input Sense 5 Configuration"] | |
#[inline] | |
pub fn sense5(&self) -> SENSE5R { | |
SENSE5R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 20; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 23 - Filter 5 Enable"] | |
#[inline] | |
pub fn filten5(&self) -> FILTEN5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 23; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN5R { bits } | |
} | |
#[doc = "Bits 24:26 - Input Sense 6 Configuration"] | |
#[inline] | |
pub fn sense6(&self) -> SENSE6R { | |
SENSE6R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 27 - Filter 6 Enable"] | |
#[inline] | |
pub fn filten6(&self) -> FILTEN6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 27; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN6R { bits } | |
} | |
#[doc = "Bits 28:30 - Input Sense 7 Configuration"] | |
#[inline] | |
pub fn sense7(&self) -> SENSE7R { | |
SENSE7R::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 28; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bit 31 - Filter 7 Enable"] | |
#[inline] | |
pub fn filten7(&self) -> FILTEN7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 31; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
FILTEN7R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:2 - Input Sense n Configuration"] | |
#[inline] | |
pub fn sense0(&mut self) -> _SENSE0W { | |
_SENSE0W { w: self } | |
} | |
#[doc = "Bit 3 - Filter n Enable"] | |
#[inline] | |
pub fn filten0(&mut self) -> _FILTEN0W { | |
_FILTEN0W { w: self } | |
} | |
#[doc = "Bits 4:6 - Input Sense 1 Configuration"] | |
#[inline] | |
pub fn sense1(&mut self) -> _SENSE1W { | |
_SENSE1W { w: self } | |
} | |
#[doc = "Bit 7 - Filter 1 Enable"] | |
#[inline] | |
pub fn filten1(&mut self) -> _FILTEN1W { | |
_FILTEN1W { w: self } | |
} | |
#[doc = "Bits 8:10 - Input Sense 2 Configuration"] | |
#[inline] | |
pub fn sense2(&mut self) -> _SENSE2W { | |
_SENSE2W { w: self } | |
} | |
#[doc = "Bit 11 - Filter 2 Enable"] | |
#[inline] | |
pub fn filten2(&mut self) -> _FILTEN2W { | |
_FILTEN2W { w: self } | |
} | |
#[doc = "Bits 12:14 - Input Sense 3 Configuration"] | |
#[inline] | |
pub fn sense3(&mut self) -> _SENSE3W { | |
_SENSE3W { w: self } | |
} | |
#[doc = "Bit 15 - Filter 3 Enable"] | |
#[inline] | |
pub fn filten3(&mut self) -> _FILTEN3W { | |
_FILTEN3W { w: self } | |
} | |
#[doc = "Bits 16:18 - Input Sense 4 Configuration"] | |
#[inline] | |
pub fn sense4(&mut self) -> _SENSE4W { | |
_SENSE4W { w: self } | |
} | |
#[doc = "Bit 19 - Filter 4 Enable"] | |
#[inline] | |
pub fn filten4(&mut self) -> _FILTEN4W { | |
_FILTEN4W { w: self } | |
} | |
#[doc = "Bits 20:22 - Input Sense 5 Configuration"] | |
#[inline] | |
pub fn sense5(&mut self) -> _SENSE5W { | |
_SENSE5W { w: self } | |
} | |
#[doc = "Bit 23 - Filter 5 Enable"] | |
#[inline] | |
pub fn filten5(&mut self) -> _FILTEN5W { | |
_FILTEN5W { w: self } | |
} | |
#[doc = "Bits 24:26 - Input Sense 6 Configuration"] | |
#[inline] | |
pub fn sense6(&mut self) -> _SENSE6W { | |
_SENSE6W { w: self } | |
} | |
#[doc = "Bit 27 - Filter 6 Enable"] | |
#[inline] | |
pub fn filten6(&mut self) -> _FILTEN6W { | |
_FILTEN6W { w: self } | |
} | |
#[doc = "Bits 28:30 - Input Sense 7 Configuration"] | |
#[inline] | |
pub fn sense7(&mut self) -> _SENSE7W { | |
_SENSE7W { w: self } | |
} | |
#[doc = "Bit 31 - Filter 7 Enable"] | |
#[inline] | |
pub fn filten7(&mut self) -> _FILTEN7W { | |
_FILTEN7W { w: self } | |
} | |
} | |
} | |
#[doc = "Control"] | |
pub struct CTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Control"] | |
pub mod ctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::CTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWRSTR { | |
bits: bool, | |
} | |
impl SWRSTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct ENABLER { | |
bits: bool, | |
} | |
impl ENABLER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWRSTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWRSTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _ENABLEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _ENABLEW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&self) -> SWRSTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SWRSTR { bits } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&self) -> ENABLER { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
ENABLER { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Software Reset"] | |
#[inline] | |
pub fn swrst(&mut self) -> _SWRSTW { | |
_SWRSTW { w: self } | |
} | |
#[doc = "Bit 1 - Enable"] | |
#[inline] | |
pub fn enable(&mut self) -> _ENABLEW { | |
_ENABLEW { w: self } | |
} | |
} | |
} | |
#[doc = "Event Control"] | |
pub struct EVCTRL { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Event Control"] | |
pub mod evctrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::EVCTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO0R { | |
bits: bool, | |
} | |
impl EXTINTEO0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO1R { | |
bits: bool, | |
} | |
impl EXTINTEO1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO2R { | |
bits: bool, | |
} | |
impl EXTINTEO2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO3R { | |
bits: bool, | |
} | |
impl EXTINTEO3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO4R { | |
bits: bool, | |
} | |
impl EXTINTEO4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO5R { | |
bits: bool, | |
} | |
impl EXTINTEO5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO6R { | |
bits: bool, | |
} | |
impl EXTINTEO6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO7R { | |
bits: bool, | |
} | |
impl EXTINTEO7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO8R { | |
bits: bool, | |
} | |
impl EXTINTEO8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO9R { | |
bits: bool, | |
} | |
impl EXTINTEO9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO10R { | |
bits: bool, | |
} | |
impl EXTINTEO10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO11R { | |
bits: bool, | |
} | |
impl EXTINTEO11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO12R { | |
bits: bool, | |
} | |
impl EXTINTEO12R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO13R { | |
bits: bool, | |
} | |
impl EXTINTEO13R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO14R { | |
bits: bool, | |
} | |
impl EXTINTEO14R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINTEO15R { | |
bits: bool, | |
} | |
impl EXTINTEO15R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO12W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO12W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO13W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO13W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO14W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO14W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINTEO15W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINTEO15W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] | |
#[inline] | |
pub fn extinteo0(&self) -> EXTINTEO0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO0R { bits } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] | |
#[inline] | |
pub fn extinteo1(&self) -> EXTINTEO1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO1R { bits } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] | |
#[inline] | |
pub fn extinteo2(&self) -> EXTINTEO2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO2R { bits } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] | |
#[inline] | |
pub fn extinteo3(&self) -> EXTINTEO3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO3R { bits } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] | |
#[inline] | |
pub fn extinteo4(&self) -> EXTINTEO4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO4R { bits } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] | |
#[inline] | |
pub fn extinteo5(&self) -> EXTINTEO5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO5R { bits } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] | |
#[inline] | |
pub fn extinteo6(&self) -> EXTINTEO6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO6R { bits } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] | |
#[inline] | |
pub fn extinteo7(&self) -> EXTINTEO7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO7R { bits } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] | |
#[inline] | |
pub fn extinteo8(&self) -> EXTINTEO8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO8R { bits } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] | |
#[inline] | |
pub fn extinteo9(&self) -> EXTINTEO9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO9R { bits } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] | |
#[inline] | |
pub fn extinteo10(&self) -> EXTINTEO10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO10R { bits } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] | |
#[inline] | |
pub fn extinteo11(&self) -> EXTINTEO11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO11R { bits } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] | |
#[inline] | |
pub fn extinteo12(&self) -> EXTINTEO12R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO12R { bits } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] | |
#[inline] | |
pub fn extinteo13(&self) -> EXTINTEO13R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO13R { bits } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] | |
#[inline] | |
pub fn extinteo14(&self) -> EXTINTEO14R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO14R { bits } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] | |
#[inline] | |
pub fn extinteo15(&self) -> EXTINTEO15R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINTEO15R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Event Output Enable"] | |
#[inline] | |
pub fn extinteo0(&mut self) -> _EXTINTEO0W { | |
_EXTINTEO0W { w: self } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Event Output Enable"] | |
#[inline] | |
pub fn extinteo1(&mut self) -> _EXTINTEO1W { | |
_EXTINTEO1W { w: self } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Event Output Enable"] | |
#[inline] | |
pub fn extinteo2(&mut self) -> _EXTINTEO2W { | |
_EXTINTEO2W { w: self } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Event Output Enable"] | |
#[inline] | |
pub fn extinteo3(&mut self) -> _EXTINTEO3W { | |
_EXTINTEO3W { w: self } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Event Output Enable"] | |
#[inline] | |
pub fn extinteo4(&mut self) -> _EXTINTEO4W { | |
_EXTINTEO4W { w: self } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Event Output Enable"] | |
#[inline] | |
pub fn extinteo5(&mut self) -> _EXTINTEO5W { | |
_EXTINTEO5W { w: self } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Event Output Enable"] | |
#[inline] | |
pub fn extinteo6(&mut self) -> _EXTINTEO6W { | |
_EXTINTEO6W { w: self } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Event Output Enable"] | |
#[inline] | |
pub fn extinteo7(&mut self) -> _EXTINTEO7W { | |
_EXTINTEO7W { w: self } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Event Output Enable"] | |
#[inline] | |
pub fn extinteo8(&mut self) -> _EXTINTEO8W { | |
_EXTINTEO8W { w: self } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Event Output Enable"] | |
#[inline] | |
pub fn extinteo9(&mut self) -> _EXTINTEO9W { | |
_EXTINTEO9W { w: self } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Event Output Enable"] | |
#[inline] | |
pub fn extinteo10(&mut self) -> _EXTINTEO10W { | |
_EXTINTEO10W { w: self } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Event Output Enable"] | |
#[inline] | |
pub fn extinteo11(&mut self) -> _EXTINTEO11W { | |
_EXTINTEO11W { w: self } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Event Output Enable"] | |
#[inline] | |
pub fn extinteo12(&mut self) -> _EXTINTEO12W { | |
_EXTINTEO12W { w: self } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Event Output Enable"] | |
#[inline] | |
pub fn extinteo13(&mut self) -> _EXTINTEO13W { | |
_EXTINTEO13W { w: self } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Event Output Enable"] | |
#[inline] | |
pub fn extinteo14(&mut self) -> _EXTINTEO14W { | |
_EXTINTEO14W { w: self } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Event Output Enable"] | |
#[inline] | |
pub fn extinteo15(&mut self) -> _EXTINTEO15W { | |
_EXTINTEO15W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub struct INTENCLR { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Interrupt Enable Clear"] | |
pub mod intenclr { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::INTENCLR { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT0R { | |
bits: bool, | |
} | |
impl EXTINT0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT1R { | |
bits: bool, | |
} | |
impl EXTINT1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT2R { | |
bits: bool, | |
} | |
impl EXTINT2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT3R { | |
bits: bool, | |
} | |
impl EXTINT3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT4R { | |
bits: bool, | |
} | |
impl EXTINT4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT5R { | |
bits: bool, | |
} | |
impl EXTINT5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT6R { | |
bits: bool, | |
} | |
impl EXTINT6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT7R { | |
bits: bool, | |
} | |
impl EXTINT7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT8R { | |
bits: bool, | |
} | |
impl EXTINT8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT9R { | |
bits: bool, | |
} | |
impl EXTINT9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT10R { | |
bits: bool, | |
} | |
impl EXTINT10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT11R { | |
bits: bool, | |
} | |
impl EXTINT11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT12R { | |
bits: bool, | |
} | |
impl EXTINT12R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT13R { | |
bits: bool, | |
} | |
impl EXTINT13R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT14R { | |
bits: bool, | |
} | |
impl EXTINT14R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT15R { | |
bits: bool, | |
} | |
impl EXTINT15R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT12W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT12W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT13W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT13W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT14W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT14W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT15W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT15W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Enable"] | |
#[inline] | |
pub fn extint0(&self) -> EXTINT0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT0R { bits } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Enable"] | |
#[inline] | |
pub fn extint1(&self) -> EXTINT1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT1R { bits } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Enable"] | |
#[inline] | |
pub fn extint2(&self) -> EXTINT2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT2R { bits } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Enable"] | |
#[inline] | |
pub fn extint3(&self) -> EXTINT3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT3R { bits } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Enable"] | |
#[inline] | |
pub fn extint4(&self) -> EXTINT4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT4R { bits } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Enable"] | |
#[inline] | |
pub fn extint5(&self) -> EXTINT5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT5R { bits } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Enable"] | |
#[inline] | |
pub fn extint6(&self) -> EXTINT6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT6R { bits } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Enable"] | |
#[inline] | |
pub fn extint7(&self) -> EXTINT7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT7R { bits } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Enable"] | |
#[inline] | |
pub fn extint8(&self) -> EXTINT8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT8R { bits } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Enable"] | |
#[inline] | |
pub fn extint9(&self) -> EXTINT9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT9R { bits } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Enable"] | |
#[inline] | |
pub fn extint10(&self) -> EXTINT10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT10R { bits } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Enable"] | |
#[inline] | |
pub fn extint11(&self) -> EXTINT11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT11R { bits } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Enable"] | |
#[inline] | |
pub fn extint12(&self) -> EXTINT12R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT12R { bits } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Enable"] | |
#[inline] | |
pub fn extint13(&self) -> EXTINT13R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT13R { bits } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Enable"] | |
#[inline] | |
pub fn extint14(&self) -> EXTINT14R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT14R { bits } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Enable"] | |
#[inline] | |
pub fn extint15(&self) -> EXTINT15R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT15R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Enable"] | |
#[inline] | |
pub fn extint0(&mut self) -> _EXTINT0W { | |
_EXTINT0W { w: self } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Enable"] | |
#[inline] | |
pub fn extint1(&mut self) -> _EXTINT1W { | |
_EXTINT1W { w: self } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Enable"] | |
#[inline] | |
pub fn extint2(&mut self) -> _EXTINT2W { | |
_EXTINT2W { w: self } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Enable"] | |
#[inline] | |
pub fn extint3(&mut self) -> _EXTINT3W { | |
_EXTINT3W { w: self } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Enable"] | |
#[inline] | |
pub fn extint4(&mut self) -> _EXTINT4W { | |
_EXTINT4W { w: self } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Enable"] | |
#[inline] | |
pub fn extint5(&mut self) -> _EXTINT5W { | |
_EXTINT5W { w: self } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Enable"] | |
#[inline] | |
pub fn extint6(&mut self) -> _EXTINT6W { | |
_EXTINT6W { w: self } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Enable"] | |
#[inline] | |
pub fn extint7(&mut self) -> _EXTINT7W { | |
_EXTINT7W { w: self } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Enable"] | |
#[inline] | |
pub fn extint8(&mut self) -> _EXTINT8W { | |
_EXTINT8W { w: self } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Enable"] | |
#[inline] | |
pub fn extint9(&mut self) -> _EXTINT9W { | |
_EXTINT9W { w: self } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Enable"] | |
#[inline] | |
pub fn extint10(&mut self) -> _EXTINT10W { | |
_EXTINT10W { w: self } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Enable"] | |
#[inline] | |
pub fn extint11(&mut self) -> _EXTINT11W { | |
_EXTINT11W { w: self } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Enable"] | |
#[inline] | |
pub fn extint12(&mut self) -> _EXTINT12W { | |
_EXTINT12W { w: self } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Enable"] | |
#[inline] | |
pub fn extint13(&mut self) -> _EXTINT13W { | |
_EXTINT13W { w: self } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Enable"] | |
#[inline] | |
pub fn extint14(&mut self) -> _EXTINT14W { | |
_EXTINT14W { w: self } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Enable"] | |
#[inline] | |
pub fn extint15(&mut self) -> _EXTINT15W { | |
_EXTINT15W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub struct INTENSET { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Interrupt Enable Set"] | |
pub mod intenset { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::INTENSET { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT0R { | |
bits: bool, | |
} | |
impl EXTINT0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT1R { | |
bits: bool, | |
} | |
impl EXTINT1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT2R { | |
bits: bool, | |
} | |
impl EXTINT2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT3R { | |
bits: bool, | |
} | |
impl EXTINT3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT4R { | |
bits: bool, | |
} | |
impl EXTINT4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT5R { | |
bits: bool, | |
} | |
impl EXTINT5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT6R { | |
bits: bool, | |
} | |
impl EXTINT6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT7R { | |
bits: bool, | |
} | |
impl EXTINT7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT8R { | |
bits: bool, | |
} | |
impl EXTINT8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT9R { | |
bits: bool, | |
} | |
impl EXTINT9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT10R { | |
bits: bool, | |
} | |
impl EXTINT10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT11R { | |
bits: bool, | |
} | |
impl EXTINT11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT12R { | |
bits: bool, | |
} | |
impl EXTINT12R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT13R { | |
bits: bool, | |
} | |
impl EXTINT13R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT14R { | |
bits: bool, | |
} | |
impl EXTINT14R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT15R { | |
bits: bool, | |
} | |
impl EXTINT15R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT12W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT12W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT13W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT13W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT14W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT14W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT15W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT15W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Enable"] | |
#[inline] | |
pub fn extint0(&self) -> EXTINT0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT0R { bits } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Enable"] | |
#[inline] | |
pub fn extint1(&self) -> EXTINT1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT1R { bits } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Enable"] | |
#[inline] | |
pub fn extint2(&self) -> EXTINT2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT2R { bits } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Enable"] | |
#[inline] | |
pub fn extint3(&self) -> EXTINT3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT3R { bits } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Enable"] | |
#[inline] | |
pub fn extint4(&self) -> EXTINT4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT4R { bits } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Enable"] | |
#[inline] | |
pub fn extint5(&self) -> EXTINT5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT5R { bits } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Enable"] | |
#[inline] | |
pub fn extint6(&self) -> EXTINT6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT6R { bits } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Enable"] | |
#[inline] | |
pub fn extint7(&self) -> EXTINT7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT7R { bits } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Enable"] | |
#[inline] | |
pub fn extint8(&self) -> EXTINT8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT8R { bits } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Enable"] | |
#[inline] | |
pub fn extint9(&self) -> EXTINT9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT9R { bits } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Enable"] | |
#[inline] | |
pub fn extint10(&self) -> EXTINT10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT10R { bits } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Enable"] | |
#[inline] | |
pub fn extint11(&self) -> EXTINT11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT11R { bits } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Enable"] | |
#[inline] | |
pub fn extint12(&self) -> EXTINT12R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT12R { bits } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Enable"] | |
#[inline] | |
pub fn extint13(&self) -> EXTINT13R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT13R { bits } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Enable"] | |
#[inline] | |
pub fn extint14(&self) -> EXTINT14R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT14R { bits } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Enable"] | |
#[inline] | |
pub fn extint15(&self) -> EXTINT15R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT15R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Enable"] | |
#[inline] | |
pub fn extint0(&mut self) -> _EXTINT0W { | |
_EXTINT0W { w: self } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Enable"] | |
#[inline] | |
pub fn extint1(&mut self) -> _EXTINT1W { | |
_EXTINT1W { w: self } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Enable"] | |
#[inline] | |
pub fn extint2(&mut self) -> _EXTINT2W { | |
_EXTINT2W { w: self } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Enable"] | |
#[inline] | |
pub fn extint3(&mut self) -> _EXTINT3W { | |
_EXTINT3W { w: self } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Enable"] | |
#[inline] | |
pub fn extint4(&mut self) -> _EXTINT4W { | |
_EXTINT4W { w: self } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Enable"] | |
#[inline] | |
pub fn extint5(&mut self) -> _EXTINT5W { | |
_EXTINT5W { w: self } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Enable"] | |
#[inline] | |
pub fn extint6(&mut self) -> _EXTINT6W { | |
_EXTINT6W { w: self } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Enable"] | |
#[inline] | |
pub fn extint7(&mut self) -> _EXTINT7W { | |
_EXTINT7W { w: self } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Enable"] | |
#[inline] | |
pub fn extint8(&mut self) -> _EXTINT8W { | |
_EXTINT8W { w: self } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Enable"] | |
#[inline] | |
pub fn extint9(&mut self) -> _EXTINT9W { | |
_EXTINT9W { w: self } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Enable"] | |
#[inline] | |
pub fn extint10(&mut self) -> _EXTINT10W { | |
_EXTINT10W { w: self } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Enable"] | |
#[inline] | |
pub fn extint11(&mut self) -> _EXTINT11W { | |
_EXTINT11W { w: self } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Enable"] | |
#[inline] | |
pub fn extint12(&mut self) -> _EXTINT12W { | |
_EXTINT12W { w: self } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Enable"] | |
#[inline] | |
pub fn extint13(&mut self) -> _EXTINT13W { | |
_EXTINT13W { w: self } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Enable"] | |
#[inline] | |
pub fn extint14(&mut self) -> _EXTINT14W { | |
_EXTINT14W { w: self } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Enable"] | |
#[inline] | |
pub fn extint15(&mut self) -> _EXTINT15W { | |
_EXTINT15W { w: self } | |
} | |
} | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub struct INTFLAG { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Interrupt Flag Status and Clear"] | |
pub mod intflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::INTFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT0R { | |
bits: bool, | |
} | |
impl EXTINT0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT1R { | |
bits: bool, | |
} | |
impl EXTINT1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT2R { | |
bits: bool, | |
} | |
impl EXTINT2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT3R { | |
bits: bool, | |
} | |
impl EXTINT3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT4R { | |
bits: bool, | |
} | |
impl EXTINT4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT5R { | |
bits: bool, | |
} | |
impl EXTINT5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT6R { | |
bits: bool, | |
} | |
impl EXTINT6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT7R { | |
bits: bool, | |
} | |
impl EXTINT7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT8R { | |
bits: bool, | |
} | |
impl EXTINT8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT9R { | |
bits: bool, | |
} | |
impl EXTINT9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT10R { | |
bits: bool, | |
} | |
impl EXTINT10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT11R { | |
bits: bool, | |
} | |
impl EXTINT11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT12R { | |
bits: bool, | |
} | |
impl EXTINT12R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT13R { | |
bits: bool, | |
} | |
impl EXTINT13R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT14R { | |
bits: bool, | |
} | |
impl EXTINT14R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EXTINT15R { | |
bits: bool, | |
} | |
impl EXTINT15R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT12W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT12W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT13W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT13W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT14W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT14W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EXTINT15W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EXTINT15W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Interrupt 0"] | |
#[inline] | |
pub fn extint0(&self) -> EXTINT0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT0R { bits } | |
} | |
#[doc = "Bit 1 - External Interrupt 1"] | |
#[inline] | |
pub fn extint1(&self) -> EXTINT1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT1R { bits } | |
} | |
#[doc = "Bit 2 - External Interrupt 2"] | |
#[inline] | |
pub fn extint2(&self) -> EXTINT2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT2R { bits } | |
} | |
#[doc = "Bit 3 - External Interrupt 3"] | |
#[inline] | |
pub fn extint3(&self) -> EXTINT3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT3R { bits } | |
} | |
#[doc = "Bit 4 - External Interrupt 4"] | |
#[inline] | |
pub fn extint4(&self) -> EXTINT4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT4R { bits } | |
} | |
#[doc = "Bit 5 - External Interrupt 5"] | |
#[inline] | |
pub fn extint5(&self) -> EXTINT5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT5R { bits } | |
} | |
#[doc = "Bit 6 - External Interrupt 6"] | |
#[inline] | |
pub fn extint6(&self) -> EXTINT6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT6R { bits } | |
} | |
#[doc = "Bit 7 - External Interrupt 7"] | |
#[inline] | |
pub fn extint7(&self) -> EXTINT7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT7R { bits } | |
} | |
#[doc = "Bit 8 - External Interrupt 8"] | |
#[inline] | |
pub fn extint8(&self) -> EXTINT8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT8R { bits } | |
} | |
#[doc = "Bit 9 - External Interrupt 9"] | |
#[inline] | |
pub fn extint9(&self) -> EXTINT9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT9R { bits } | |
} | |
#[doc = "Bit 10 - External Interrupt 10"] | |
#[inline] | |
pub fn extint10(&self) -> EXTINT10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT10R { bits } | |
} | |
#[doc = "Bit 11 - External Interrupt 11"] | |
#[inline] | |
pub fn extint11(&self) -> EXTINT11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT11R { bits } | |
} | |
#[doc = "Bit 12 - External Interrupt 12"] | |
#[inline] | |
pub fn extint12(&self) -> EXTINT12R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT12R { bits } | |
} | |
#[doc = "Bit 13 - External Interrupt 13"] | |
#[inline] | |
pub fn extint13(&self) -> EXTINT13R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT13R { bits } | |
} | |
#[doc = "Bit 14 - External Interrupt 14"] | |
#[inline] | |
pub fn extint14(&self) -> EXTINT14R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT14R { bits } | |
} | |
#[doc = "Bit 15 - External Interrupt 15"] | |
#[inline] | |
pub fn extint15(&self) -> EXTINT15R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
EXTINT15R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Interrupt 0"] | |
#[inline] | |
pub fn extint0(&mut self) -> _EXTINT0W { | |
_EXTINT0W { w: self } | |
} | |
#[doc = "Bit 1 - External Interrupt 1"] | |
#[inline] | |
pub fn extint1(&mut self) -> _EXTINT1W { | |
_EXTINT1W { w: self } | |
} | |
#[doc = "Bit 2 - External Interrupt 2"] | |
#[inline] | |
pub fn extint2(&mut self) -> _EXTINT2W { | |
_EXTINT2W { w: self } | |
} | |
#[doc = "Bit 3 - External Interrupt 3"] | |
#[inline] | |
pub fn extint3(&mut self) -> _EXTINT3W { | |
_EXTINT3W { w: self } | |
} | |
#[doc = "Bit 4 - External Interrupt 4"] | |
#[inline] | |
pub fn extint4(&mut self) -> _EXTINT4W { | |
_EXTINT4W { w: self } | |
} | |
#[doc = "Bit 5 - External Interrupt 5"] | |
#[inline] | |
pub fn extint5(&mut self) -> _EXTINT5W { | |
_EXTINT5W { w: self } | |
} | |
#[doc = "Bit 6 - External Interrupt 6"] | |
#[inline] | |
pub fn extint6(&mut self) -> _EXTINT6W { | |
_EXTINT6W { w: self } | |
} | |
#[doc = "Bit 7 - External Interrupt 7"] | |
#[inline] | |
pub fn extint7(&mut self) -> _EXTINT7W { | |
_EXTINT7W { w: self } | |
} | |
#[doc = "Bit 8 - External Interrupt 8"] | |
#[inline] | |
pub fn extint8(&mut self) -> _EXTINT8W { | |
_EXTINT8W { w: self } | |
} | |
#[doc = "Bit 9 - External Interrupt 9"] | |
#[inline] | |
pub fn extint9(&mut self) -> _EXTINT9W { | |
_EXTINT9W { w: self } | |
} | |
#[doc = "Bit 10 - External Interrupt 10"] | |
#[inline] | |
pub fn extint10(&mut self) -> _EXTINT10W { | |
_EXTINT10W { w: self } | |
} | |
#[doc = "Bit 11 - External Interrupt 11"] | |
#[inline] | |
pub fn extint11(&mut self) -> _EXTINT11W { | |
_EXTINT11W { w: self } | |
} | |
#[doc = "Bit 12 - External Interrupt 12"] | |
#[inline] | |
pub fn extint12(&mut self) -> _EXTINT12W { | |
_EXTINT12W { w: self } | |
} | |
#[doc = "Bit 13 - External Interrupt 13"] | |
#[inline] | |
pub fn extint13(&mut self) -> _EXTINT13W { | |
_EXTINT13W { w: self } | |
} | |
#[doc = "Bit 14 - External Interrupt 14"] | |
#[inline] | |
pub fn extint14(&mut self) -> _EXTINT14W { | |
_EXTINT14W { w: self } | |
} | |
#[doc = "Bit 15 - External Interrupt 15"] | |
#[inline] | |
pub fn extint15(&mut self) -> _EXTINT15W { | |
_EXTINT15W { w: self } | |
} | |
} | |
} | |
#[doc = "Non-Maskable Interrupt Control"] | |
pub struct NMICTRL { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Non-Maskable Interrupt Control"] | |
pub mod nmictrl { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::NMICTRL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = "Possible values of the field `NMISENSE`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum NMISENSER { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising-edge detection"] | |
RISE, | |
#[doc = "Falling-edge detection"] | |
FALL, | |
#[doc = "Both-edges detection"] | |
BOTH, | |
#[doc = "High-level detection"] | |
HIGH, | |
#[doc = "Low-level detection"] | |
LOW, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl NMISENSER { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
NMISENSER::NONE => 0, | |
NMISENSER::RISE => 0x01, | |
NMISENSER::FALL => 0x02, | |
NMISENSER::BOTH => 0x03, | |
NMISENSER::HIGH => 0x04, | |
NMISENSER::LOW => 0x05, | |
NMISENSER::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> NMISENSER { | |
match value { | |
0 => NMISENSER::NONE, | |
1 => NMISENSER::RISE, | |
2 => NMISENSER::FALL, | |
3 => NMISENSER::BOTH, | |
4 => NMISENSER::HIGH, | |
5 => NMISENSER::LOW, | |
i => NMISENSER::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NONE`"] | |
#[inline] | |
pub fn is_none(&self) -> bool { | |
*self == NMISENSER::NONE | |
} | |
#[doc = "Checks if the value of the field is `RISE`"] | |
#[inline] | |
pub fn is_rise(&self) -> bool { | |
*self == NMISENSER::RISE | |
} | |
#[doc = "Checks if the value of the field is `FALL`"] | |
#[inline] | |
pub fn is_fall(&self) -> bool { | |
*self == NMISENSER::FALL | |
} | |
#[doc = "Checks if the value of the field is `BOTH`"] | |
#[inline] | |
pub fn is_both(&self) -> bool { | |
*self == NMISENSER::BOTH | |
} | |
#[doc = "Checks if the value of the field is `HIGH`"] | |
#[inline] | |
pub fn is_high(&self) -> bool { | |
*self == NMISENSER::HIGH | |
} | |
#[doc = "Checks if the value of the field is `LOW`"] | |
#[inline] | |
pub fn is_low(&self) -> bool { | |
*self == NMISENSER::LOW | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct NMIFILTENR { | |
bits: bool, | |
} | |
impl NMIFILTENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = "Values that can be written to the field `NMISENSE`"] | |
pub enum NMISENSEW { | |
#[doc = "No detection"] | |
NONE, | |
#[doc = "Rising-edge detection"] | |
RISE, | |
#[doc = "Falling-edge detection"] | |
FALL, | |
#[doc = "Both-edges detection"] | |
BOTH, | |
#[doc = "High-level detection"] | |
HIGH, | |
#[doc = "Low-level detection"] | |
LOW, | |
} | |
impl NMISENSEW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
NMISENSEW::NONE => 0, | |
NMISENSEW::RISE => 1, | |
NMISENSEW::FALL => 2, | |
NMISENSEW::BOTH => 3, | |
NMISENSEW::HIGH => 4, | |
NMISENSEW::LOW => 5, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _NMISENSEW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _NMISENSEW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: NMISENSEW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "No detection"] | |
#[inline] | |
pub fn none(self) -> &'a mut W { | |
self.variant(NMISENSEW::NONE) | |
} | |
#[doc = "Rising-edge detection"] | |
#[inline] | |
pub fn rise(self) -> &'a mut W { | |
self.variant(NMISENSEW::RISE) | |
} | |
#[doc = "Falling-edge detection"] | |
#[inline] | |
pub fn fall(self) -> &'a mut W { | |
self.variant(NMISENSEW::FALL) | |
} | |
#[doc = "Both-edges detection"] | |
#[inline] | |
pub fn both(self) -> &'a mut W { | |
self.variant(NMISENSEW::BOTH) | |
} | |
#[doc = "High-level detection"] | |
#[inline] | |
pub fn high(self) -> &'a mut W { | |
self.variant(NMISENSEW::HIGH) | |
} | |
#[doc = "Low-level detection"] | |
#[inline] | |
pub fn low(self) -> &'a mut W { | |
self.variant(NMISENSEW::LOW) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _NMIFILTENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _NMIFILTENW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] | |
#[inline] | |
pub fn nmisense(&self) -> NMISENSER { | |
NMISENSER::_from({ | |
const MASK: u8 = 0x07; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) as u8 | |
}) | |
} | |
#[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] | |
#[inline] | |
pub fn nmifilten(&self) -> NMIFILTENR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
NMIFILTENR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:2 - Non-Maskable Interrupt Sense"] | |
#[inline] | |
pub fn nmisense(&mut self) -> _NMISENSEW { | |
_NMISENSEW { w: self } | |
} | |
#[doc = "Bit 3 - Non-Maskable Interrupt Filter Enable"] | |
#[inline] | |
pub fn nmifilten(&mut self) -> _NMIFILTENW { | |
_NMIFILTENW { w: self } | |
} | |
} | |
} | |
#[doc = "Non-Maskable Interrupt Flag Status and Clear"] | |
pub struct NMIFLAG { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Non-Maskable Interrupt Flag Status and Clear"] | |
pub mod nmiflag { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u8, | |
} | |
impl super::NMIFLAG { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct NMIR { | |
bits: bool, | |
} | |
impl NMIR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _NMIW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _NMIW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u8) << OFFSET); | |
self.w.bits |= ((value & MASK) as u8) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 0 - Non-Maskable Interrupt"] | |
#[inline] | |
pub fn nmi(&self) -> NMIR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
NMIR { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - Non-Maskable Interrupt"] | |
#[inline] | |
pub fn nmi(&mut self) -> _NMIW { | |
_NMIW { w: self } | |
} | |
} | |
} | |
#[doc = "Status"] | |
pub struct STATUS { | |
register: VolatileCell<u8>, | |
} | |
#[doc = "Status"] | |
pub mod status { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u8, | |
} | |
impl super::STATUS { | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SYNCBUSYR { | |
bits: bool, | |
} | |
impl SYNCBUSYR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
#[doc = "Bit 7 - Synchronization Busy"] | |
#[inline] | |
pub fn syncbusy(&self) -> SYNCBUSYR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u8) != 0 | |
}; | |
SYNCBUSYR { bits } | |
} | |
} | |
} | |
#[doc = "Wake-Up Enable"] | |
pub struct WAKEUP { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Wake-Up Enable"] | |
pub mod wakeup { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::WAKEUP { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN0R { | |
bits: bool, | |
} | |
impl WAKEUPEN0R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN1R { | |
bits: bool, | |
} | |
impl WAKEUPEN1R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN2R { | |
bits: bool, | |
} | |
impl WAKEUPEN2R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN3R { | |
bits: bool, | |
} | |
impl WAKEUPEN3R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN4R { | |
bits: bool, | |
} | |
impl WAKEUPEN4R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN5R { | |
bits: bool, | |
} | |
impl WAKEUPEN5R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN6R { | |
bits: bool, | |
} | |
impl WAKEUPEN6R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN7R { | |
bits: bool, | |
} | |
impl WAKEUPEN7R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN8R { | |
bits: bool, | |
} | |
impl WAKEUPEN8R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN9R { | |
bits: bool, | |
} | |
impl WAKEUPEN9R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN10R { | |
bits: bool, | |
} | |
impl WAKEUPEN10R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN11R { | |
bits: bool, | |
} | |
impl WAKEUPEN11R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN12R { | |
bits: bool, | |
} | |
impl WAKEUPEN12R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN13R { | |
bits: bool, | |
} | |
impl WAKEUPEN13R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN14R { | |
bits: bool, | |
} | |
impl WAKEUPEN14R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct WAKEUPEN15R { | |
bits: bool, | |
} | |
impl WAKEUPEN15R { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN0W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN0W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN1W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN1W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN2W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN2W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN3W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN3W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN4W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN4W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN5W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN5W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN6W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN6W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN7W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN7W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN8W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN8W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN9W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN9W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN10W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN10W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN11W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN11W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN12W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN12W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN13W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN13W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN14W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN14W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _WAKEUPEN15W<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _WAKEUPEN15W<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen0(&self) -> WAKEUPEN0R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN0R { bits } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen1(&self) -> WAKEUPEN1R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 1; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN1R { bits } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen2(&self) -> WAKEUPEN2R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 2; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN2R { bits } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen3(&self) -> WAKEUPEN3R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 3; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN3R { bits } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen4(&self) -> WAKEUPEN4R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 4; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN4R { bits } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen5(&self) -> WAKEUPEN5R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 5; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN5R { bits } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen6(&self) -> WAKEUPEN6R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 6; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN6R { bits } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen7(&self) -> WAKEUPEN7R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 7; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN7R { bits } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen8(&self) -> WAKEUPEN8R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN8R { bits } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen9(&self) -> WAKEUPEN9R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 9; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN9R { bits } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen10(&self) -> WAKEUPEN10R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 10; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN10R { bits } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen11(&self) -> WAKEUPEN11R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 11; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN11R { bits } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen12(&self) -> WAKEUPEN12R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 12; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN12R { bits } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen13(&self) -> WAKEUPEN13R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 13; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN13R { bits } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen14(&self) -> WAKEUPEN14R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 14; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN14R { bits } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen15(&self) -> WAKEUPEN15R { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 15; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
WAKEUPEN15R { bits } | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bit 0 - External Interrupt 0 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen0(&mut self) -> _WAKEUPEN0W { | |
_WAKEUPEN0W { w: self } | |
} | |
#[doc = "Bit 1 - External Interrupt 1 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen1(&mut self) -> _WAKEUPEN1W { | |
_WAKEUPEN1W { w: self } | |
} | |
#[doc = "Bit 2 - External Interrupt 2 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen2(&mut self) -> _WAKEUPEN2W { | |
_WAKEUPEN2W { w: self } | |
} | |
#[doc = "Bit 3 - External Interrupt 3 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen3(&mut self) -> _WAKEUPEN3W { | |
_WAKEUPEN3W { w: self } | |
} | |
#[doc = "Bit 4 - External Interrupt 4 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen4(&mut self) -> _WAKEUPEN4W { | |
_WAKEUPEN4W { w: self } | |
} | |
#[doc = "Bit 5 - External Interrupt 5 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen5(&mut self) -> _WAKEUPEN5W { | |
_WAKEUPEN5W { w: self } | |
} | |
#[doc = "Bit 6 - External Interrupt 6 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen6(&mut self) -> _WAKEUPEN6W { | |
_WAKEUPEN6W { w: self } | |
} | |
#[doc = "Bit 7 - External Interrupt 7 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen7(&mut self) -> _WAKEUPEN7W { | |
_WAKEUPEN7W { w: self } | |
} | |
#[doc = "Bit 8 - External Interrupt 8 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen8(&mut self) -> _WAKEUPEN8W { | |
_WAKEUPEN8W { w: self } | |
} | |
#[doc = "Bit 9 - External Interrupt 9 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen9(&mut self) -> _WAKEUPEN9W { | |
_WAKEUPEN9W { w: self } | |
} | |
#[doc = "Bit 10 - External Interrupt 10 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen10(&mut self) -> _WAKEUPEN10W { | |
_WAKEUPEN10W { w: self } | |
} | |
#[doc = "Bit 11 - External Interrupt 11 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen11(&mut self) -> _WAKEUPEN11W { | |
_WAKEUPEN11W { w: self } | |
} | |
#[doc = "Bit 12 - External Interrupt 12 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen12(&mut self) -> _WAKEUPEN12W { | |
_WAKEUPEN12W { w: self } | |
} | |
#[doc = "Bit 13 - External Interrupt 13 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen13(&mut self) -> _WAKEUPEN13W { | |
_WAKEUPEN13W { w: self } | |
} | |
#[doc = "Bit 14 - External Interrupt 14 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen14(&mut self) -> _WAKEUPEN14W { | |
_WAKEUPEN14W { w: self } | |
} | |
#[doc = "Bit 15 - External Interrupt 15 Wake-up Enable"] | |
#[inline] | |
pub fn wakeupen15(&mut self) -> _WAKEUPEN15W { | |
_WAKEUPEN15W { w: self } | |
} | |
} | |
} | |
} | |
#[doc = "Event System Interface"] | |
pub struct EVSYS { | |
_marker: PhantomData<*const ()>, | |
} | |
unsafe impl Send for EVSYS {} | |
impl EVSYS { | |
#[doc = r" Returns a pointer to the register block"] | |
pub fn ptr() -> *const evsys::RegisterBlock { | |
0x4200_0400 as *const _ | |
} | |
} | |
impl Deref for EVSYS { | |
type Target = evsys::RegisterBlock; | |
fn deref(&self) -> &evsys::RegisterBlock { | |
unsafe { &*EVSYS::ptr() } | |
} | |
} | |
#[doc = "Event System Interface"] | |
pub mod evsys { | |
use vcell::VolatileCell; | |
#[doc = r" Register block"] | |
#[repr(C)] | |
pub struct RegisterBlock { | |
#[doc = "0x00 - Control"] | |
pub ctrl: CTRL, | |
_reserved0: [u8; 3usize], | |
#[doc = "0x04 - Channel"] | |
pub channel: CHANNEL, | |
#[doc = "0x08 - User Multiplexer"] | |
pub user: USER, | |
_reserved1: [u8; 2usize], | |
#[doc = "0x0c - Channel Status"] | |
pub chstatus: CHSTATUS, | |
#[doc = "0x10 - Interrupt Enable Clear"] | |
pub intenclr: INTENCLR, | |
#[doc = "0x14 - Interrupt Enable Set"] | |
pub intenset: INTENSET, | |
#[doc = "0x18 - Interrupt Flag Status and Clear"] | |
pub intflag: INTFLAG, | |
} | |
#[doc = "Channel"] | |
pub struct CHANNEL { | |
register: VolatileCell<u32>, | |
} | |
#[doc = "Channel"] | |
pub mod channel { | |
#[doc = r" Value read from the register"] | |
pub struct R { | |
bits: u32, | |
} | |
#[doc = r" Value to write to the register"] | |
pub struct W { | |
bits: u32, | |
} | |
impl super::CHANNEL { | |
#[doc = r" Modifies the contents of the register"] | |
#[inline] | |
pub fn modify<F>(&self, f: F) | |
where | |
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, | |
{ | |
let bits = self.register.get(); | |
let r = R { bits: bits }; | |
let mut w = W { bits: bits }; | |
f(&r, &mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Reads the contents of the register"] | |
#[inline] | |
pub fn read(&self) -> R { | |
R { | |
bits: self.register.get(), | |
} | |
} | |
#[doc = r" Writes to the register"] | |
#[inline] | |
pub fn write<F>(&self, f: F) | |
where | |
F: FnOnce(&mut W) -> &mut W, | |
{ | |
let mut w = W::reset_value(); | |
f(&mut w); | |
self.register.set(w.bits); | |
} | |
#[doc = r" Writes the reset value to the register"] | |
#[inline] | |
pub fn reset(&self) { | |
self.write(|w| w) | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct CHANNELR { | |
bits: u8, | |
} | |
impl CHANNELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct SWEVTR { | |
bits: bool, | |
} | |
impl SWEVTR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bit(&self) -> bool { | |
self.bits | |
} | |
#[doc = r" Returns `true` if the bit is clear (0)"] | |
#[inline] | |
pub fn bit_is_clear(&self) -> bool { | |
!self.bit() | |
} | |
#[doc = r" Returns `true` if the bit is set (1)"] | |
#[inline] | |
pub fn bit_is_set(&self) -> bool { | |
self.bit() | |
} | |
} | |
#[doc = r" Value of the field"] | |
pub struct EVGENR { | |
bits: u8, | |
} | |
impl EVGENR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
self.bits | |
} | |
} | |
#[doc = "Possible values of the field `PATH`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum PATHR { | |
#[doc = "Synchronous path"] | |
SYNCHRONOUS, | |
#[doc = "Resynchronized path"] | |
RESYNCHRONIZED, | |
#[doc = "Asynchronous path"] | |
ASYNCHRONOUS, | |
#[doc = r" Reserved"] | |
_Reserved(u8), | |
} | |
impl PATHR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
PATHR::SYNCHRONOUS => 0, | |
PATHR::RESYNCHRONIZED => 0x01, | |
PATHR::ASYNCHRONOUS => 0x02, | |
PATHR::_Reserved(bits) => bits, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> PATHR { | |
match value { | |
0 => PATHR::SYNCHRONOUS, | |
1 => PATHR::RESYNCHRONIZED, | |
2 => PATHR::ASYNCHRONOUS, | |
i => PATHR::_Reserved(i), | |
} | |
} | |
#[doc = "Checks if the value of the field is `SYNCHRONOUS`"] | |
#[inline] | |
pub fn is_synchronous(&self) -> bool { | |
*self == PATHR::SYNCHRONOUS | |
} | |
#[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] | |
#[inline] | |
pub fn is_resynchronized(&self) -> bool { | |
*self == PATHR::RESYNCHRONIZED | |
} | |
#[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] | |
#[inline] | |
pub fn is_asynchronous(&self) -> bool { | |
*self == PATHR::ASYNCHRONOUS | |
} | |
} | |
#[doc = "Possible values of the field `EDGSEL`"] | |
#[derive(Clone, Copy, Debug, PartialEq)] | |
pub enum EDGSELR {# [ doc = "No event output when using the resynchronized or synchronous path" ] NO_EVT_OUTPUT , # [ doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" ] RISING_EDGE , # [ doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" ] FALLING_EDGE , # [ doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" ] BOTH_EDGES} | |
impl EDGSELR { | |
#[doc = r" Value of the field as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u8 { | |
match *self { | |
EDGSELR::NO_EVT_OUTPUT => 0, | |
EDGSELR::RISING_EDGE => 0x01, | |
EDGSELR::FALLING_EDGE => 0x02, | |
EDGSELR::BOTH_EDGES => 0x03, | |
} | |
} | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _from(value: u8) -> EDGSELR { | |
match value { | |
0 => EDGSELR::NO_EVT_OUTPUT, | |
1 => EDGSELR::RISING_EDGE, | |
2 => EDGSELR::FALLING_EDGE, | |
3 => EDGSELR::BOTH_EDGES, | |
_ => unreachable!(), | |
} | |
} | |
#[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] | |
#[inline] | |
pub fn is_no_evt_output(&self) -> bool { | |
*self == EDGSELR::NO_EVT_OUTPUT | |
} | |
#[doc = "Checks if the value of the field is `RISING_EDGE`"] | |
#[inline] | |
pub fn is_rising_edge(&self) -> bool { | |
*self == EDGSELR::RISING_EDGE | |
} | |
#[doc = "Checks if the value of the field is `FALLING_EDGE`"] | |
#[inline] | |
pub fn is_falling_edge(&self) -> bool { | |
*self == EDGSELR::FALLING_EDGE | |
} | |
#[doc = "Checks if the value of the field is `BOTH_EDGES`"] | |
#[inline] | |
pub fn is_both_edges(&self) -> bool { | |
*self == EDGSELR::BOTH_EDGES | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _CHANNELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _CHANNELW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _SWEVTW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _SWEVTW<'a> { | |
#[doc = r" Sets the field bit"] | |
pub fn set_bit(self) -> &'a mut W { | |
self.bit(true) | |
} | |
#[doc = r" Clears the field bit"] | |
pub fn clear_bit(self) -> &'a mut W { | |
self.bit(false) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bit(self, value: bool) -> &'a mut W { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EVGENW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EVGENW<'a> { | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x7f; | |
const OFFSET: u8 = 16; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `PATH`"] | |
pub enum PATHW { | |
#[doc = "Synchronous path"] | |
SYNCHRONOUS, | |
#[doc = "Resynchronized path"] | |
RESYNCHRONIZED, | |
#[doc = "Asynchronous path"] | |
ASYNCHRONOUS, | |
} | |
impl PATHW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
PATHW::SYNCHRONOUS => 0, | |
PATHW::RESYNCHRONIZED => 1, | |
PATHW::ASYNCHRONOUS => 2, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _PATHW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _PATHW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: PATHW) -> &'a mut W { | |
unsafe { self.bits(variant._bits()) } | |
} | |
#[doc = "Synchronous path"] | |
#[inline] | |
pub fn synchronous(self) -> &'a mut W { | |
self.variant(PATHW::SYNCHRONOUS) | |
} | |
#[doc = "Resynchronized path"] | |
#[inline] | |
pub fn resynchronized(self) -> &'a mut W { | |
self.variant(PATHW::RESYNCHRONIZED) | |
} | |
#[doc = "Asynchronous path"] | |
#[inline] | |
pub fn asynchronous(self) -> &'a mut W { | |
self.variant(PATHW::ASYNCHRONOUS) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub unsafe fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 24; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
#[doc = "Values that can be written to the field `EDGSEL`"] | |
pub enum EDGSELW {# [ doc = "No event output when using the resynchronized or synchronous path" ] NO_EVT_OUTPUT , # [ doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" ] RISING_EDGE , # [ doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" ] FALLING_EDGE , # [ doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" ] BOTH_EDGES} | |
impl EDGSELW { | |
#[allow(missing_docs)] | |
#[doc(hidden)] | |
#[inline] | |
pub fn _bits(&self) -> u8 { | |
match *self { | |
EDGSELW::NO_EVT_OUTPUT => 0, | |
EDGSELW::RISING_EDGE => 1, | |
EDGSELW::FALLING_EDGE => 2, | |
EDGSELW::BOTH_EDGES => 3, | |
} | |
} | |
} | |
#[doc = r" Proxy"] | |
pub struct _EDGSELW<'a> { | |
w: &'a mut W, | |
} | |
impl<'a> _EDGSELW<'a> { | |
#[doc = r" Writes `variant` to the field"] | |
#[inline] | |
pub fn variant(self, variant: EDGSELW) -> &'a mut W { | |
{ | |
self.bits(variant._bits()) | |
} | |
} | |
#[doc = "No event output when using the resynchronized or synchronous path"] | |
#[inline] | |
pub fn no_evt_output(self) -> &'a mut W { | |
self.variant(EDGSELW::NO_EVT_OUTPUT) | |
} | |
# [ doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path" ] # [ inline ] | |
pub fn rising_edge(self) -> &'a mut W { | |
self.variant(EDGSELW::RISING_EDGE) | |
} | |
# [ doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path" ] # [ inline ] | |
pub fn falling_edge(self) -> &'a mut W { | |
self.variant(EDGSELW::FALLING_EDGE) | |
} | |
# [ doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path" ] # [ inline ] | |
pub fn both_edges(self) -> &'a mut W { | |
self.variant(EDGSELW::BOTH_EDGES) | |
} | |
#[doc = r" Writes raw bits to the field"] | |
#[inline] | |
pub fn bits(self, value: u8) -> &'a mut W { | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 26; | |
self.w.bits &= !((MASK as u32) << OFFSET); | |
self.w.bits |= ((value & MASK) as u32) << OFFSET; | |
self.w | |
} | |
} | |
impl R { | |
#[doc = r" Value of the register as raw bits"] | |
#[inline] | |
pub fn bits(&self) -> u32 { | |
self.bits | |
} | |
#[doc = "Bits 0:3 - Channel Selection"] | |
#[inline] | |
pub fn channel(&self) -> CHANNELR { | |
let bits = { | |
const MASK: u8 = 0x0f; | |
const OFFSET: u8 = 0; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
CHANNELR { bits } | |
} | |
#[doc = "Bit 8 - Software Event"] | |
#[inline] | |
pub fn swevt(&self) -> SWEVTR { | |
let bits = { | |
const MASK: bool = true; | |
const OFFSET: u8 = 8; | |
((self.bits >> OFFSET) & MASK as u32) != 0 | |
}; | |
SWEVTR { bits } | |
} | |
#[doc = "Bits 16:22 - Event Generator Selection"] | |
#[inline] | |
pub fn evgen(&self) -> EVGENR { | |
let bits = { | |
const MASK: u8 = 0x7f; | |
const OFFSET: u8 = 16; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}; | |
EVGENR { bits } | |
} | |
#[doc = "Bits 24:25 - Path Selection"] | |
#[inline] | |
pub fn path(&self) -> PATHR { | |
PATHR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 24; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
#[doc = "Bits 26:27 - Edge Detection Selection"] | |
#[inline] | |
pub fn edgsel(&self) -> EDGSELR { | |
EDGSELR::_from({ | |
const MASK: u8 = 0x03; | |
const OFFSET: u8 = 26; | |
((self.bits >> OFFSET) & MASK as u32) as u8 | |
}) | |
} | |
} | |
impl W { | |
#[doc = r" Reset value of the register"] | |
#[inline] | |
pub fn reset_value() -> W { | |
W { bits: 0 } | |
} | |
#[doc = r" Writes raw bits to the register"] | |
#[inline] | |
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { | |
self.bits = bits; | |
self | |
} | |
#[doc = "Bits 0:3 - Channel Selection"] | |
#[inline] | |
pub fn channel(&mut self) -> _CHANNELW { | |
_CHANNELW { w: self } | |
} | |
#[doc = "Bit 8 - Software Event"] | |
#[inline] | |
pub fn swevt(&mut self) -> _SWEVTW { | |
_SWEVTW { w: self } | |
} | |
#[doc = "Bits 16:22 - Event Generator Selection"] | |
#[inline] | |
pub fn evgen(&mut self) -> _EVGENW { | |
_EVGENW { w: self |
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