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jannson/qemu_ecos3.0.patch

Created March 12, 2014 03:51
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更新eCos代码，以让eCos能运行在qemu mips上，并能进行网卡通信。
Raw
qemu_ecos3.0.patch
Index: packages/kernel/v3_0/src/intr/intr.cxx
===================================================================
--- packages/kernel/v3_0/src/intr/intr.cxx (revision 12)
+++ packages/kernel/v3_0/src/intr/intr.cxx (revision 24)
@@ -680,6 +680,10 @@
CYG_INTERRUPT_STATE old_ints;
HAL_DISABLE_INTERRUPTS(old_ints);
+ if (vector >= CYGNUM_HAL_INTERRUPT_CTRL1_BASE)
+ {
+ int noused = HAL_GALILEO_GETREG(0xc34);/*update by gan*/
+ }
HAL_INTERRUPT_MASK( vector );
HAL_RESTORE_INTERRUPTS(old_ints);
Index: packages/infra/v3_0/src/diag.cxx
===================================================================
--- packages/infra/v3_0/src/diag.cxx (revision 12)
+++ packages/infra/v3_0/src/diag.cxx (revision 24)
@@ -20,8 +20,8 @@
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
+// along with eCos; if not, write to the Free Software Foundation, Inc.,
// You should have received a copy of the GNU General Public License
-// along with eCos; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
// As a special exception, if other files instantiate templates or use
@@ -116,11 +116,21 @@
{
}
+static void my_putc(char c, void** param)
+{
+ volatile unsigned char* r = (volatile unsigned char*)(0xb00003f8+5);
+ volatile unsigned char* w = (volatile unsigned char*)(0xb00003f8);
+
+ while(*r == 0);
+ *w = c;
+}
+
//
// This routine is used to send characters during 'printf()' functions.
// It can be replaced by providing a replacement via diag_init_putc().
//
-static void (*_putc)(char c, void **param) = _diag_write_char;
+/*static void (*_putc)(char c, void **param) = _diag_write_char;*/
+static void (*_putc)(char c, void **param) = my_putc;
void
diag_init_putc(void (*putc)(char c, void **param))
Index: packages/devs/eth/amd/pcnet/v3_0/src/amd_pcnet.h
===================================================================
--- packages/devs/eth/amd/pcnet/v3_0/src/amd_pcnet.h (revision 12)
+++ packages/devs/eth/amd/pcnet/v3_0/src/amd_pcnet.h (revision 24)
@@ -66,10 +66,10 @@
// 2 for added data IO output: get_reg, put_reg
// 4 for packet allocation/free output
// 8 for only startup status, so we can tell we're installed OK
-#define DEBUG 0x0
+#define DEBUG 0x4
#if DEBUG & 1
-#define DEBUG_FUNCTION() do { os_printf("%s\n", __FUNCTION__); } while (0)
+#define DEBUG_FUNCTION() do { diag_printf(" %d %s \n", __LINE__, __FUNCTION__); } while (0)
#else
#define DEBUG_FUNCTION() do {} while(0)
#endif
Index: packages/devs/eth/amd/pcnet/v3_0/src/if_pcnet.c
===================================================================
--- packages/devs/eth/amd/pcnet/v3_0/src/if_pcnet.c (revision 12)
+++ packages/devs/eth/amd/pcnet/v3_0/src/if_pcnet.c (revision 24)
@@ -899,13 +899,14 @@
DEBUG_FUNCTION();
stat = get_reg(sc, PCNET_ANR_PHYSTAT);
+ return 1;/* added by gan */
if ((stat & PCNET_ANR_PHYSTAT_LINK) == 0) {
return 0; // Link not connected
}
return (0 == cpd->txbusy);
}
-
+#define DEBUG 1
//
// This routine is called to send data to the hardware.
static void
@@ -1145,9 +1146,9 @@
#if DEBUG & 1
int i;
for (i = 0; i < cpd->rx_ring_cnt; i++) {
- rxd = cpd->rx_ring + i*PCNET_RD_SIZE;
rstat = _SU32(rxd, PCNET_RD_PTR);
+ rxd = cpd->rx_ring + i*PCNET_RD_SIZE;
if (!(rstat & PCNET_RD_PTR_OWN)) {
int i;
cyg_uint32 rstat;
@@ -1229,13 +1230,25 @@
// may come in pieces, using a scatter-gather list. This allows for more
// efficient processing in the upper layers of the stack.
//
+static void print_buf(unsigned char *buf, int len)
+{
+ int i;
+ for(i = 0; i < len; i++)
+ {
+ printf("%02x ", buf[i]);
+ if((i+1) % 32 == 0)
+ {
+ printf("\n");
+ }
+ }
+}
static void
pcnet_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
{
struct pcnet_priv_data *cpd =
(struct pcnet_priv_data *)sc->driver_private;
- int i, mlen=0, plen;
- cyg_uint8 *data, *rxd, *buf;
+ int i, mlen=0, plen, tmp_len;
+ cyg_uint8 *data, *rxd, *buf, *tmp_buf;
DEBUG_FUNCTION();
@@ -1245,7 +1258,8 @@
INCR_STAT( rx_deliver );
plen = _SU16(rxd, PCNET_RD_MLEN);
-
+ tmp_buf = buf;
+ tmp_len = plen;
for (i = 0; i < sg_len; i++) {
data = (cyg_uint8*)sg_list[i].buf;
mlen = sg_list[i].len;
@@ -1261,6 +1275,10 @@
}
}
}
+
+ {
+ print_buf(tmp_buf, tmp_len);
+ }
}
static void
Index: packages/hal/mips/malta/v3_0/include/platform.inc
===================================================================
--- packages/hal/mips/malta/v3_0/include/platform.inc (revision 12)
+++ packages/hal/mips/malta/v3_0/include/platform.inc (revision 24)
@@ -61,6 +61,52 @@
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_io.h>
+ .macro hal_vectors_init
+ # If we don~t play nice with a ROM monitor, copy the required
+ # vectors into the proper location.
+ la t0,0x80000000 # dest addr
+ la t1,utlb_vector # source addr
+ la t3,utlb_vector_end # end dest addr
+1:
+ lw v0,0(t1) # get word
+ addi t1,t1,4
+ sw v0,0(t0) # write word
+ addi t0,t0,4
+ bne t1,t3,1b
+ nop
+
+ la t0,0x80000180 # dest addr
+ la t1,other_vector # source addr
+ la t3,other_vector_end # end dest addr
+1:
+ lw v0,0(t1) # get word
+ addi t1,t1,4
+ sw v0,0(t0) # write word
+ addi t0,t0,4
+ bne t1,t3,1b
+ nop
+ #if 0
+ .set mips3 # Set ISA to MIPS 3 to allow cache insns
+ # Now clear the region in the caches
+ la t0,0x80000000 # dest addr
+ ori t1,t0,0x200 # source addr
+1: cache 0x01,0(t0) # Flush word from data cache
+ cache 0x01,1(t0)
+ cache 0x01,2(t0)
+ cache 0x01,3(t0)
+ nop
+ cache 0x00,0(t0) # Invalidate icache for word
+ cache 0x00,1(t0)
+ cache 0x00,2(t0)
+ cache 0x00,3(t0)
+ nop
+ addi t0,t0,0x20
+ bne t0,t1,1b
+ nop
+ .set mips0 # reset ISA to default
+ #endif
+ .endm
+
#------------------------------------------------------------------------------
# Additional bits for status register.
# We set the IM[0] bit to accept all interrupts.
Index: packages/hal/mips/malta/v3_0/include/plf_io.h
===================================================================
--- packages/hal/mips/malta/v3_0/include/plf_io.h (revision 12)
+++ packages/hal/mips/malta/v3_0/include/plf_io.h (revision 24)
@@ -72,14 +72,14 @@
/* Malta Memory Definitions */
#define HAL_MALTA_RAM_BASE 0x00000000
-#define HAL_MALTA_PCI_MEM0_BASE 0x08000000
-#define HAL_MALTA_PCI_MEM0_SIZE 0x08000000 // 128 MB
-#define HAL_MALTA_PCI_MEM1_BASE 0x10000000
-#define HAL_MALTA_PCI_MEM1_SIZE 0x08000000 // 128 MB
+#define HAL_MALTA_PCI_MEM0_BASE 0x12000000 //0x08000000
+#define HAL_MALTA_PCI_MEM0_SIZE 0x1000000 //0x08000000 // 128 MB
+#define HAL_MALTA_PCI_MEM1_BASE 0x13000000 //0x10000000
+#define HAL_MALTA_PCI_MEM1_SIZE 0x1000000 //0x08000000 // 128 MB
-#define HAL_MALTA_PCI_IO_BASE 0x18000000
-#define HAL_MALTA_PCI_IO_SIZE 0x03d00000 // 62 MB
-#define HAL_MALTA_CONTROLLER_BASE 0x1BE00000
+#define HAL_MALTA_PCI_IO_BASE 0x10000000 //0x18000000
+#define HAL_MALTA_PCI_IO_SIZE 0x1000000 //0x03d00000 // 62 MB
+#define HAL_MALTA_CONTROLLER_BASE 0x14000000 //0x1BE00000
#define HAL_MALTA_CONTROLLER_BASE_ISD_CONFIG (HAL_MALTA_CONTROLLER_BASE >> 21)
#define HAL_MALTA_FLASH_BASE 0x1E000000
#define HAL_MALTA_FLASH_SIZE SZ_4M
@@ -149,7 +149,8 @@
#define HAL_MALTA_BRKRES_DEFAULT_VALUE 0xA
// PIIX4 registers
-#define HAL_PIIX4_REGISTER_BASE 0xb8000000
+/* #define HAL_PIIX4_REGISTER_BASE 0xb8000000*/
+#define HAL_PIIX4_REGISTER_BASE 0xb0000000
// PIIX4 interrupt controller stuff
#define HAL_PIIX4_MASTER_ICW1 HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0020)
Index: packages/hal/mips/malta/v3_0/src/ser16c550c.c
===================================================================
--- packages/hal/mips/malta/v3_0/src/ser16c550c.c (revision 12)
+++ packages/hal/mips/malta/v3_0/src/ser16c550c.c (revision 24)
@@ -63,8 +63,10 @@
// Define the serial registers. The Malta board is equipped with a 16550C
// serial chip.
#define MALTA_SER_CLOCK 1843200
-#define MALTA_SER_16550_BASE_A 0xb80003f8
-#define MALTA_SER_16550_BASE_B 0xb80002f8
+/*#define MALTA_SER_16550_BASE_A 0xb80003f8
+#define MALTA_SER_16550_BASE_B 0xb80002f8*/
+#define MALTA_SER_16550_BASE_A 0xb00003f8
+#define MALTA_SER_16550_BASE_B 0xb00002f8
#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
Index: packages/hal/mips/malta/v3_0/src/plf_misc.c
===================================================================
--- packages/hal/mips/malta/v3_0/src/plf_misc.c (revision 12)
+++ packages/hal/mips/malta/v3_0/src/plf_misc.c (revision 24)
@@ -171,15 +171,19 @@
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_ICW4, HAL_PIIX4_ICW4_UPMODE);
// Mask all sources
- HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1,
- 0xff & ~(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE)));
+ HAL_WRITE_UINT8(HAL_PIIX4_MASTER_OCW1, 0xff);
+ /*0xff & ~(1<<(CYGNUM_HAL_INTERRUPT_CASCADE-CYGNUM_HAL_INTERRUPT_CTRL1_BASE)));*/
HAL_WRITE_UINT8(HAL_PIIX4_SLAVE_OCW1, 0xff);
// Set PCI interrupt routing and set those interrupts to level
// sense as per 4.1.10 page 59 in 82371AB doc.
- v = ( (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 0
+ /*v = ( (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 0
|(CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 8
|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 16
+ |(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 24); modified by gan*/
+ v = ( (CYGNUM_HAL_INTERRUPT_PCI_AB-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 0
+ |(CYGNUM_HAL_INTERRUPT_11-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 8
+ |(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 16
|(CYGNUM_HAL_INTERRUPT_PCI_CD-CYGNUM_HAL_INTERRUPT_EXTERNAL_BASE) << 24);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(_PIIX4_PCI_ID,0),
CYG_PCI_CFG_PIIX4_PIRQR, v);
@@ -217,6 +221,15 @@
}
+static void pci_pcnet_write_bar(cyg_pci_device_id devid)
+{
+ cyg_uint8 bus = CYG_PCI_DEV_GET_BUS(devid);
+ cyg_uint8 devfn = CYG_PCI_DEV_GET_DEVFN(devid);
+
+ cyg_pcihw_write_config_uint16(bus, devfn, CYG_PCI_CFG_COMMAND, 0x3);
+ cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_BASE, 0x1000);
+ cyg_pcihw_write_config_uint32(bus, devfn, CYG_PCI_CFG_BAR_BASE + 4, 0x12002000);
+}
// One-time PCI initialization.
void cyg_hal_plf_pci_init(void)
@@ -229,6 +242,8 @@
static int initialized = 0;
if (initialized) return;
initialized = 1;
+
+ pci_pcnet_write_bar(0x5800);
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
Index: packages/hal/mips/arch/v3_0/src/vectors.S
===================================================================
--- packages/hal/mips/arch/v3_0/src/vectors.S (revision 12)
+++ packages/hal/mips/arch/v3_0/src/vectors.S (revision 24)
@@ -230,12 +230,23 @@
jal initialize_stub
nop
#endif
+#if 0
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
.extern hal_ctrlc_isr_init
jal hal_ctrlc_isr_init
nop
#endif
-
+#endif
+#if 0
+ mfc0 v0,status
+ la v1,0xFFFFFFF9
+ and v0,v0,v1 # clear EXL and ERL bits
+ ori v0,v0,0x0001 # set IE bit
+ mtc0 v0,status
+ nop
+ nop
+ nop
+#endif
# Call cyg_start
.extern cyg_start
Index: packages/hal/mips/mips32/v3_0/include/variant.inc
===================================================================
--- packages/hal/mips/mips32/v3_0/include/variant.inc (revision 12)
+++ packages/hal/mips/mips32/v3_0/include/variant.inc (revision 24)
@@ -112,6 +112,7 @@
# RAM and NOT using a ROM monitor, initialize the VSR table.
.macro hal_mon_init
+ hal_vectors_init
# Set default exception VSR for all vectors
ori a0,zero,16 # CYGNUM_HAL_VSR_COUNT
la a1,__default_exception_vsr
@@ -146,6 +147,7 @@
# the rest are left to the ROM for now...
.macro hal_mon_init
+ hal_vectors_init
la a0,__default_interrupt_vsr
la a3,hal_vsr_table
sw a0,0(a3)
Index: packages/io/pci/v3_0/src/pci.c
===================================================================
--- packages/io/pci/v3_0/src/pci.c (revision 12)
+++ packages/io/pci/v3_0/src/pci.c (revision 24)
@@ -681,16 +681,17 @@
ret = false;
if ((flags & CYG_PCI_CFG_BAR_SPACE_MASK) == CYG_PCI_CFG_BAR_SPACE_MEM){
- ret |= cyg_pci_allocate_memory(dev_info, bar,
- &cyg_pci_memory_base);
+ /*ret |= cyg_pci_allocate_memory(dev_info, bar,
+ &cyg_pci_memory_base);*/
// If this is a 64bit memory region, skip the next bar
// since it will contain the top 32 bits.
if (flags & CYG_PRI_CFG_BAR_MEM_TYPE_64)
bar++;
} else
- ret |= cyg_pci_allocate_io(dev_info, bar, &cyg_pci_io_base);
+ /*ret |= cyg_pci_allocate_io(dev_info, bar, &cyg_pci_io_base);*/
+ ret = 1;/* added by weishenggan */
if (!ret)
return ret;
}
Index: packages/NEWS
===================================================================
--- packages/NEWS (revision 12)
+++ packages/NEWS (revision 24)
@@ -35,7 +35,7 @@
* Improved varient support for the AT91
* Support for the Ethenet device on the NETARM devices.
* Added support for the AT91 based PhyCore.
-* Added support for Exys XSEngine (PXA255) based system.
+* Added support for Exys XSEngine (PXA255) based system.test
* Port of ezXML parser added.
* Port to the Keil MCB2100, Olimex P2106 and Olimex LPC-MT by Jani Monoses
* Generic support for the lpc2xxx, hal, serial and watchdog by Jani Monoses
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