The GNU Build tools

Makefile.depend

MAKEDEPEND=makedepend

# Since our sources are nothing more than our objects, which the .o changed to .c, we use this rule:
SRCS=$(OBJS:.o=.c)

depend:
        $(MAKEDEPEND) -Y $(SRCS)

Makefile.generic

# We use "gcc" as our compiler
CC=gcc

# "gcc" is also our linker
LD=gcc

# There are the flags for "gcc"
CFLAGS=-g -Wall

# THere are no linker flags we specify
LDFLAGS=

# These are the objects we need to create
OBJS=hello.o

# This is the main binary
PROG=hello

# This is our install program
INSTALL=install

# This is the path where we need to install our program
INSTALL_PATH=/usr/local/bin

# This is the default target. It only depends on the main program
all: $(PROG)

# Main binary depends on our objects. After the objects are
# created, link them into the main binary
$(PROG): $(OBJS)
        $(LD) $(LDFLAGS) $(OBJS) -o $(PROG)

# This rule will be triggered when we need to convert a .c file into a .o file
# The $< stands for the .c file, the $@ for the .o file.
.c.o:
        $(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@

install: $(PROG)
        $(INSTALL) -m 0755 $(PROG) $(INSTALL_PATH)

# This target will cleanup everything so we can start from scratch again
clean:
        $(RM) *.o $(PROG)

.PHONY: install clean

Makefile.simple

# This default rule will compile hello into a binary
all:
        gcc -o hello hello.c

# This rule will install the binary into /usr/local/bin with the correct more. Note that we
# need to be root to do this.
install:
        install -m 0755 hello /usr/local/bin