I'm trying to design a circuit that will allow a button to trigger only for a single clock pulse. This was my first attempt, using 2 D flip-flops (using Logisim for now):
The button provides the rising edge which loads high into the first flipflop, and Q1 goes high, then second picks this up on the next clock pulse and Q2 will go high. Q2 going high triggers an async reset on the first flipflop, making Q2 go low on the next pulse.
First question - is this sensible? Perhaps there's a much easier way? (if so, ignore the next question :)
Second question - I had a go at designing a real circuit for this but there's a problem. On quad D flipflop ICs the async reset is shared between all flipflops on the chip, so my reset mechanism won't work here (the second flipflop would immediately be reset when Q2 goes high). So I came up with this hack:
By adding a 3rd D flipflop to delay the reset by a cycle I can ensure that the single pulse has had time to propagate to the "Playback" module. It just seems really... kludgy :)
This turned out to be a case of missing terminology - what I in fact needed was a positive edge trigger, which can be easily implemented with a few logic gates:
