6502 testbench

cpu_tb.v

module cpu_tb;

reg clk;
reg reset;
reg irq;
reg nmi;
reg rdy;

wire [15:0] addr;
wire [7:0] cpu_do;
wire [7:0] cpu_di;
wire we;

// 6502 CPU

cpu cpu0 (
	.clk(clk), 
	.reset(reset), 
	.AB(addr), 
	.DI(cpu_di), 
	.DO(cpu_do), 
	.WE(we), 
	.IRQ(irq), 
	.NMI(nmi), 
	.RDY(rdy)
);

// Low 2K of RAM $0000-$07FF
wire ramlo_cs = addr[15:11] == 5'h0;
ram #(.ADDR_WIDTH(11)) ramlo (
	.clk(clk), 
	.addr(addr[10:0]), 
	.data_in(cpu_do), 
	.data_out(cpu_di), 
	.cs(ramlo_cs), 
	.we(we)
);	

wire ramhi_cs = addr[15:12] == 4'hF;
// High 4K of RAM $F000-$FFFF
ram #(.ADDR_WIDTH(12), .INIT_FILE("ram.hex")) ramhi (
	.clk(clk), 
	.addr(addr[11:0]), 
	.data_in(cpu_do), 
	.data_out(cpu_di), 
	.cs(ramhi_cs), 
	.we(we)
);	

initial 
begin
	// Initialize Inputs
	irq = 0;
	nmi = 0;
	rdy = 1;
	clk = 0;
	reset = 1;
	repeat(4) #10 clk = ~clk;
	reset = 0;
	forever #10 clk = ~clk;
	$finish;
end      

endmodule