Created
March 16, 2016 13:48
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from myhdl import block, delay, always_seq, instance, intbv, Signal, StopSimulation | |
@block | |
def inc(clk, rst, en, count): | |
@always_seq(clk.posedge, rst) | |
def logic(): | |
if en: | |
count.next = count + 1 | |
return logic | |
@block | |
def test_inc(backend='myhdl'): | |
clk = Clock() | |
rst = Reset(async=False) | |
en = Signal(False) | |
count = Signal(intbv()[8:]) | |
dut = inc(clk, rst, en, count) | |
#backend defaults to myhdl in config_sim | |
dut.config_sim(backend, trace=True) | |
@instance | |
def stim(): | |
for i in range(20): | |
en.next = randbits(1) | |
raise StopSimulation | |
@instance | |
def mon(): | |
while True: | |
yield clk.posedge | |
yield delay(1) | |
print(rst, en, count) | |
#If the function was not decorated with @run, | |
#run(clk.gen(), rst.pulse(), dut, stim, mon) would do the trick. | |
return clk.gen(), rst.pulse(5), dut, stim, mon | |
#run with myhdl | |
test_inc().run_sim() | |
#run with icarus | |
test_inc('icarus').run_sim() |
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