Intel CPU 286/386/486

intel-cpu.md

Variant	Year	Clock (MHz)	Bus (MHz)	Mult.	FPU	L1 Cache	Pipeline	MMU	Reg Width	Addr Bus	Data Bus	Process	Transistors	Voltage	Notes
80286	1982	6, 8, 10, 12.5	= clock	1x	None (ext. 80287)	None	~3-stage prefetch	Segmentation only	16-bit	24-bit	16-bit	1.5 µm	134K	5V
386DX	1985	16, 20, 25, 33	= clock	1x	None (ext. 80387)	None	Prefetch, not pipelined	Seg + paging	32-bit	32-bit	32-bit	1.5→1 µm	275K	5V	Full 32-bit debut
386SX	1988	16, 20, 25, 33	= clock	1x	None (ext. 80387SX)	None	Same as 386DX	Seg + paging	32-bit	24-bit	16-bit	1→0.8 µm	275K	5V	Cost-reduced; narrow external bus
486DX	1989	25, 33, 50	= clock	1x	Integrated	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	1→0.8 µm	1.2M	5V	50 MHz variant unreliable on many boards
386SL	1990	20, 25	= clock	1x	None	None	Same as 386DX	Seg + paging	32-bit	24-bit	16-bit	1 µm	~855K	3.3/5V	First SMM; laptop power management
486SX	1991	16, 20, 25, 33	= clock	1x	Disabled	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.8 µm	1.2M	5V	Same die as DX, FPU fused off
486DX2	1992	40, 50, 66	20, 25, 33	2x	Integrated	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.8 µm	1.2M	5V (3.3V later)	The iconic DOOM chip
486SL	1992	20, 25, 33	= clock	1x	Integrated	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.8 µm	1.4M	3.3/5V	Laptop variant with enhanced sleep
486SL-NM	1992	20, 25	= clock	1x	Disabled	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.8 µm	~1.4M	3.3/5V	"No Math" laptop variant
486SX2	1994	50	25	2x	Disabled	8 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.8 µm	1.2M	5V	Rare budget part
486DX4	1994	75, 100	25, 33	3x	Integrated	16 KB unified	5-stage	Seg + paging	32-bit	32-bit	32-bit	0.6 µm	1.6M	3.3V	Named "DX4" not "DX3" for marketing; doubled L1