| Published in Image Processing On Line on 2021–10–15. | |
| Submitted on 2021–05–05, accepted on 2021–08–24. | |
| ISSN 2105–1232 c 2021 IPOL & the authors CC–BY–NC–SA | |
| This article is available online with supplementary materials, | |
| software, datasets and online demo at | |
| https://doi.org/10.5201/ipol.2021.355 | |
| 2015/06/16 v0.5.1 IPOL article class | |
| Image Forgeries Detection through Mosaic Analysis: the |
| /* -*- C++ -*- | |
| * File: dht_nn_cl.h | |
| * Copyright 2026 Anton Petrusevich | |
| * | |
| * OpenCL infrastructure for DHT-NN demosaicing GPU inference. | |
| * Fused kernel: gather patch + forward pass. | |
| * Architecture (patch_r, hidden sizes) determined at runtime from the network. | |
| * Kernel source is generated dynamically with the correct #defines. | |
| * One work-item per pixel. | |
| * |
| /* -*- C++ -*- | |
| * File: dht_nn_network.h | |
| * Copyright 2026 Anton Petrusevich | |
| * | |
| * Neural network for DHT demosaicing direction refinement. | |
| * Architecture: input_size -> N hidden layers (LeakyReLU α=0.01) -> 3 (softmax H/V + sigmoid S) | |
| * Input: (2*patch_r+1)^2 patch x 16 features/pixel | |
| * Output: logit(HOR), logit(VER) [softmax], logit(sharpness) [sigmoid] | |
| * | |
| * Patch radius, number and sizes of hidden layers are runtime-configurable. |
| /* -*- C++ -*- | |
| * File: dht_nn_demosaic.cpp | |
| * Copyright 2026 Anton Petrusevich | |
| * Created: Tue Feb 10, 2026 | |
| * | |
| * This code is licensed under one of two licenses as you choose: | |
| * | |
| * 1. GNU LESSER GENERAL PUBLIC LICENSE version 2.1 | |
| * (See file LICENSE.LGPL provided in LibRaw distribution archive for | |
| * details). |
| #include "driver/gpio.h" | |
| #include <Arduino.h> | |
| #include <SPI.h> | |
| enum | |
| { | |
| PN5180_RST = GPIO_NUM_12, | |
| PN5180_SCK = GPIO_NUM_18, | |
| PN5180_MOSI = GPIO_NUM_23, | |
| PN5180_MISO = GPIO_NUM_19, |
| #include "driver/gpio.h" | |
| #include "driver/spi_master.h" | |
| #include "esp_chip_info.h" | |
| #include "esp_flash.h" | |
| #include "esp_heap_caps.h" | |
| #include "esp_log.h" | |
| #include "esp_rom_sys.h" | |
| #include "esp_system.h" | |
| #include "esp_timer.h" | |
| #include "freertos/FreeRTOS.h" |
| #!/usr/bin/perl | |
| use strict; | |
| use warnings; | |
| use Benchmark qw(cmpthese); | |
| use Config; | |
| use Inline C => Config => OPTIMIZE => " -O3 -march=native"; | |
| use Inline C => <<'END_OF_C_CODE'; | |
| SV* ret_c(SV* sv) { |
jef-sure
this is esp32-c3 mcu. OutpuEnablePin is pulled up with 10kohm resistor. why after reset during mcu initialisation for short time there's 0 on that pin?
GitHub Copilot
This behavior is expected on ESP32-C3 (and most ESP32 chips) due to the default state of GPIOs during reset and boot:
GPIOs are configured as inputs by default after reset. If you have a 10k pull-up resistor on OutputEnablePin (GPIO0), the pin should be high when floating.
| #include "spi_shiftout.h" | |
| #include "driver/gpio.h" | |
| #include "esp_log.h" | |
| #include <stdlib.h> | |
| #include <string.h> | |
| static const char *TAG = "spi_shiftout"; | |
| spi_shiftout_t *spi_shiftout_init(int32_t frequency, gpio_num_t data_pin, gpio_num_t clock_pin, gpio_num_t latch_pin, | |
| gpio_num_t output_enable_pin, spi_host_device_t host, uint8_t shift_out_length) |
| from itertools import permutations | |
| perm = permutations([*range(0,10)], 7) | |
| f, u, s, b, a, l, c = [1,2,3,4,5,6,7] | |
| def fp(): | |
| return f + b == c or (u + a > 9 and f + b + 1 == c) or (s+l > 9 and u + a + 1> 9 and f + b + 1 == c) | |
| def up(): | |
| return ((s+l+1) % 10) == u and (u + a + 1) % 10 == l |