arbit3jesper.vhd

library ieee ;
  use ieee.std_logic_1164.all ;
  use ieee.numeric_std.all ;

entity arbit3 is
  port (
    reset : in std_logic;  
    r : in std_logic_vector(2 downto 0) ;
    g : out std_logic_vector(2 downto 0)
  ) ;
end entity ; -- arbit3

architecture arch of arbit3 is
  type state is (s0,s1,s2,s3);
  signal g_inner : state;

begin
worker : process( reset, r, g_inner )
begin
  if reset='1' and reset'event then
    g_inner <= s0;
  else
    case(g_inner) is
      when s0 =>
        if r(2)='1' then
          g_inner <= s3;
        elsif r(1)='1' then
          g_inner <= s2;
        elsif r(0)='1' then
          g_inner <= s1;
        end if;
      when s1 =>
        if r(0)='0' then
          g_inner <= s0;
        end if;
      when s2 =>
        if r(1)='0' then
          g_inner <= s0;
        end if;
      when s3 =>
        if r(2)='0' then
          g_inner <= s0;
        end if ;
    end case ;
  end if ;
end process ; -- worker
g <=  "000" when g_inner=s0 else
      "001" when g_inner=s1 else
      "010" when g_inner=s2 else
      "100" when g_inner=s3 else "000";
end architecture ; -- arch