Skip to content

Instantly share code, notes, and snippets.

@jevinskie

jevinskie/lm32-decode.c

Created June 4, 2025 22:02
Show Gist options
  • Save jevinskie/149684e723cc341e9cdcf729be93201b to your computer and use it in GitHub Desktop.
Save jevinskie/149684e723cc341e9cdcf729be93201b to your computer and use it in GitHub Desktop.
Download ZIP
lm32 QEMU decodetree
Raw
lm32-decode.c
/* This file is autogenerated by scripts/decodetree.py. */
typedef struct {
int rX;
int csr;
} arg_cr;
typedef struct {
int imm;
} arg_i;
typedef struct {
int rX;
} arg_r;
typedef struct {
} arg_raise;
typedef struct {
int rX;
int imm;
} arg_ri;
typedef struct {
int rX;
int rY;
} arg_rr;
typedef struct {
int rX;
int rY;
int imm;
} arg_rri;
typedef struct {
int rX;
int rY;
int rZ;
} arg_rrr;
typedef struct {
int rX;
int rY;
} arg_sext;
typedef arg_rri arg_srui;
static bool trans_srui(DisasContext *ctx, arg_srui *a);
typedef arg_rri arg_nori;
static bool trans_nori(DisasContext *ctx, arg_nori *a);
typedef arg_rri arg_muli;
static bool trans_muli(DisasContext *ctx, arg_muli *a);
typedef arg_rri arg_sri;
static bool trans_sri(DisasContext *ctx, arg_sri *a);
typedef arg_rri arg_addi;
static bool trans_addi(DisasContext *ctx, arg_addi *a);
typedef arg_rri arg_ori;
static bool trans_ori(DisasContext *ctx, arg_ori *a);
typedef arg_rri arg_sli;
static bool trans_sli(DisasContext *ctx, arg_sli *a);
typedef arg_rri arg_xori;
static bool trans_xori(DisasContext *ctx, arg_xori *a);
typedef arg_rri arg_andi;
static bool trans_andi(DisasContext *ctx, arg_andi *a);
typedef arg_rri arg_xnori;
static bool trans_xnori(DisasContext *ctx, arg_xnori *a);
typedef arg_rri arg_andhi;
static bool trans_andhi(DisasContext *ctx, arg_andhi *a);
typedef arg_rri arg_orhi;
static bool trans_orhi(DisasContext *ctx, arg_orhi *a);
typedef arg_rri arg_sh;
static bool trans_sh(DisasContext *ctx, arg_sh *a);
typedef arg_rri arg_lb;
static bool trans_lb(DisasContext *ctx, arg_lb *a);
typedef arg_rri arg_lh;
static bool trans_lh(DisasContext *ctx, arg_lh *a);
typedef arg_rri arg_lw;
static bool trans_lw(DisasContext *ctx, arg_lw *a);
typedef arg_rri arg_lhu;
static bool trans_lhu(DisasContext *ctx, arg_lhu *a);
typedef arg_rri arg_sb;
static bool trans_sb(DisasContext *ctx, arg_sb *a);
typedef arg_rri arg_lbu;
static bool trans_lbu(DisasContext *ctx, arg_lbu *a);
typedef arg_rri arg_sw;
static bool trans_sw(DisasContext *ctx, arg_sw *a);
typedef arg_rri arg_be;
static bool trans_be(DisasContext *ctx, arg_be *a);
typedef arg_rri arg_bg;
static bool trans_bg(DisasContext *ctx, arg_bg *a);
typedef arg_rri arg_bge;
static bool trans_bge(DisasContext *ctx, arg_bge *a);
typedef arg_rri arg_bgeu;
static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a);
typedef arg_rri arg_bgu;
static bool trans_bgu(DisasContext *ctx, arg_bgu *a);
typedef arg_rri arg_bne;
static bool trans_bne(DisasContext *ctx, arg_bne *a);
typedef arg_rri arg_cmpei;
static bool trans_cmpei(DisasContext *ctx, arg_cmpei *a);
typedef arg_rri arg_cmpgi;
static bool trans_cmpgi(DisasContext *ctx, arg_cmpgi *a);
typedef arg_rri arg_cmpgei;
static bool trans_cmpgei(DisasContext *ctx, arg_cmpgei *a);
typedef arg_rri arg_cmpgeui;
static bool trans_cmpgeui(DisasContext *ctx, arg_cmpgeui *a);
typedef arg_rri arg_cmpgui;
static bool trans_cmpgui(DisasContext *ctx, arg_cmpgui *a);
typedef arg_rri arg_cmpnei;
static bool trans_cmpnei(DisasContext *ctx, arg_cmpnei *a);
typedef arg_rrr arg_sru;
static bool trans_sru(DisasContext *ctx, arg_sru *a);
typedef arg_rrr arg_nor;
static bool trans_nor(DisasContext *ctx, arg_nor *a);
typedef arg_rrr arg_mul;
static bool trans_mul(DisasContext *ctx, arg_mul *a);
typedef arg_rrr arg_divu;
static bool trans_divu(DisasContext *ctx, arg_divu *a);
typedef arg_rrr arg_sr;
static bool trans_sr(DisasContext *ctx, arg_sr *a);
typedef arg_rrr arg_xor;
static bool trans_xor(DisasContext *ctx, arg_xor *a);
typedef arg_rrr arg_div;
static bool trans_div(DisasContext *ctx, arg_div *a);
typedef arg_rrr arg_and;
static bool trans_and(DisasContext *ctx, arg_and *a);
typedef arg_rrr arg_xnor;
static bool trans_xnor(DisasContext *ctx, arg_xnor *a);
typedef arg_rrr arg_add;
static bool trans_add(DisasContext *ctx, arg_add *a);
typedef arg_rrr arg_or;
static bool trans_or(DisasContext *ctx, arg_or *a);
typedef arg_rrr arg_sl;
static bool trans_sl(DisasContext *ctx, arg_sl *a);
typedef arg_rrr arg_modu;
static bool trans_modu(DisasContext *ctx, arg_modu *a);
typedef arg_rrr arg_sub;
static bool trans_sub(DisasContext *ctx, arg_sub *a);
typedef arg_rrr arg_mod;
static bool trans_mod(DisasContext *ctx, arg_mod *a);
typedef arg_rrr arg_cmpe;
static bool trans_cmpe(DisasContext *ctx, arg_cmpe *a);
typedef arg_rrr arg_cmpg;
static bool trans_cmpg(DisasContext *ctx, arg_cmpg *a);
typedef arg_rrr arg_cmpge;
static bool trans_cmpge(DisasContext *ctx, arg_cmpge *a);
typedef arg_rrr arg_cmpgeu;
static bool trans_cmpgeu(DisasContext *ctx, arg_cmpgeu *a);
typedef arg_rrr arg_cmpgu;
static bool trans_cmpgu(DisasContext *ctx, arg_cmpgu *a);
typedef arg_rrr arg_cmpne;
static bool trans_cmpne(DisasContext *ctx, arg_cmpne *a);
typedef arg_cr arg_rcsr;
static bool trans_rcsr(DisasContext *ctx, arg_rcsr *a);
typedef arg_cr arg_wcsr;
static bool trans_wcsr(DisasContext *ctx, arg_wcsr *a);
typedef arg_raise arg_break;
static bool trans_break(DisasContext *ctx, arg_break *a);
typedef arg_raise arg_scall;
static bool trans_scall(DisasContext *ctx, arg_scall *a);
typedef arg_sext arg_sextb;
static bool trans_sextb(DisasContext *ctx, arg_sextb *a);
typedef arg_sext arg_sexth;
static bool trans_sexth(DisasContext *ctx, arg_sexth *a);
typedef arg_raise arg_bret;
static bool trans_bret(DisasContext *ctx, arg_bret *a);
typedef arg_raise arg_eret;
static bool trans_eret(DisasContext *ctx, arg_eret *a);
typedef arg_r arg_b;
static bool trans_b(DisasContext *ctx, arg_b *a);
typedef arg_r arg_call;
static bool trans_call(DisasContext *ctx, arg_call *a);
typedef arg_i arg_bi;
static bool trans_bi(DisasContext *ctx, arg_bi *a);
typedef arg_i arg_calli;
static bool trans_calli(DisasContext *ctx, arg_calli *a);
static void decode_extract_CALLBR(DisasContext *ctx, arg_r *a, uint32_t insn)
{
a->rX = extract32(insn, 21, 5);
}
static void decode_extract_CR(DisasContext *ctx, arg_cr *a, uint32_t insn)
{
a->csr = extract32(insn, 21, 5);
a->rX = extract32(insn, 16, 5);
}
static void decode_extract_I(DisasContext *ctx, arg_i *a, uint32_t insn)
{
a->imm = sextract32(insn, 0, 26);
}
static void decode_extract_RAISE(DisasContext *ctx, arg_raise *a, uint32_t insn)
{
}
static void decode_extract_RI(DisasContext *ctx, arg_rri *a, uint32_t insn)
{
a->rX = extract32(insn, 21, 5);
a->rY = extract32(insn, 16, 5);
a->imm = sextract32(insn, 0, 16);
}
static void decode_extract_RI5(DisasContext *ctx, arg_rri *a, uint32_t insn)
{
a->rX = extract32(insn, 21, 5);
a->rY = extract32(insn, 16, 5);
a->imm = extract32(insn, 0, 5);
}
static void decode_extract_RR(DisasContext *ctx, arg_rrr *a, uint32_t insn)
{
a->rZ = extract32(insn, 11, 5);
a->rX = extract32(insn, 21, 5);
a->rY = extract32(insn, 16, 5);
}
static void decode_extract_SEXT(DisasContext *ctx, arg_sext *a, uint32_t insn)
{
a->rX = extract32(insn, 21, 5);
a->rY = extract32(insn, 11, 5);
}
static bool decode(DisasContext *ctx, uint32_t insn)
{
union {
arg_cr f_cr;
arg_i f_i;
arg_r f_r;
arg_raise f_raise;
arg_ri f_ri;
arg_rr f_rr;
arg_rri f_rri;
arg_rrr f_rrr;
arg_sext f_sext;
} u;
switch ((insn >> 26) & 0x3f) {
case 0x0:
/* 000000.. ........ ........ ........ */
decode_extract_RI5(ctx, &u.f_rri, insn);
switch ((insn >> 5) & 0x7ff) {
case 0x0:
/* 000000.. ........ 00000000 000..... */
/* target/lm32/insns.decode:61 */
if (trans_srui(ctx, &u.f_rri)) return true;
break;
}
break;
case 0x1:
/* 000001.. ........ ........ ........ */
/* target/lm32/insns.decode:62 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_nori(ctx, &u.f_rri)) return true;
break;
case 0x2:
/* 000010.. ........ ........ ........ */
/* target/lm32/insns.decode:63 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_muli(ctx, &u.f_rri)) return true;
break;
case 0x3:
/* 000011.. ........ ........ ........ */
/* target/lm32/insns.decode:83 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_sh(ctx, &u.f_rri)) return true;
break;
case 0x4:
/* 000100.. ........ ........ ........ */
/* target/lm32/insns.decode:84 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_lb(ctx, &u.f_rri)) return true;
break;
case 0x5:
/* 000101.. ........ ........ ........ */
decode_extract_RI5(ctx, &u.f_rri, insn);
switch ((insn >> 5) & 0x7ff) {
case 0x0:
/* 000101.. ........ 00000000 000..... */
/* target/lm32/insns.decode:64 */
if (trans_sri(ctx, &u.f_rri)) return true;
break;
}
break;
case 0x6:
/* 000110.. ........ ........ ........ */
/* target/lm32/insns.decode:68 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_xori(ctx, &u.f_rri)) return true;
break;
case 0x7:
/* 000111.. ........ ........ ........ */
/* target/lm32/insns.decode:85 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_lh(ctx, &u.f_rri)) return true;
break;
case 0x8:
/* 001000.. ........ ........ ........ */
/* target/lm32/insns.decode:69 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_andi(ctx, &u.f_rri)) return true;
break;
case 0x9:
/* 001001.. ........ ........ ........ */
/* target/lm32/insns.decode:70 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_xnori(ctx, &u.f_rri)) return true;
break;
case 0xa:
/* 001010.. ........ ........ ........ */
/* target/lm32/insns.decode:86 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_lw(ctx, &u.f_rri)) return true;
break;
case 0xb:
/* 001011.. ........ ........ ........ */
/* target/lm32/insns.decode:87 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_lhu(ctx, &u.f_rri)) return true;
break;
case 0xc:
/* 001100.. ........ ........ ........ */
/* target/lm32/insns.decode:88 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_sb(ctx, &u.f_rri)) return true;
break;
case 0xd:
/* 001101.. ........ ........ ........ */
/* target/lm32/insns.decode:65 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_addi(ctx, &u.f_rri)) return true;
break;
case 0xe:
/* 001110.. ........ ........ ........ */
/* target/lm32/insns.decode:66 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_ori(ctx, &u.f_rri)) return true;
break;
case 0xf:
/* 001111.. ........ ........ ........ */
decode_extract_RI5(ctx, &u.f_rri, insn);
switch ((insn >> 5) & 0x7ff) {
case 0x0:
/* 001111.. ........ 00000000 000..... */
/* target/lm32/insns.decode:67 */
if (trans_sli(ctx, &u.f_rri)) return true;
break;
}
break;
case 0x10:
/* 010000.. ........ ........ ........ */
/* target/lm32/insns.decode:89 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_lbu(ctx, &u.f_rri)) return true;
break;
case 0x11:
/* 010001.. ........ ........ ........ */
/* target/lm32/insns.decode:94 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_be(ctx, &u.f_rri)) return true;
break;
case 0x12:
/* 010010.. ........ ........ ........ */
/* target/lm32/insns.decode:95 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_bg(ctx, &u.f_rri)) return true;
break;
case 0x13:
/* 010011.. ........ ........ ........ */
/* target/lm32/insns.decode:96 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_bge(ctx, &u.f_rri)) return true;
break;
case 0x14:
/* 010100.. ........ ........ ........ */
/* target/lm32/insns.decode:97 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_bgeu(ctx, &u.f_rri)) return true;
break;
case 0x15:
/* 010101.. ........ ........ ........ */
/* target/lm32/insns.decode:98 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_bgu(ctx, &u.f_rri)) return true;
break;
case 0x16:
/* 010110.. ........ ........ ........ */
/* target/lm32/insns.decode:90 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_sw(ctx, &u.f_rri)) return true;
break;
case 0x17:
/* 010111.. ........ ........ ........ */
/* target/lm32/insns.decode:99 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_bne(ctx, &u.f_rri)) return true;
break;
case 0x18:
/* 011000.. ........ ........ ........ */
/* target/lm32/insns.decode:71 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_andhi(ctx, &u.f_rri)) return true;
break;
case 0x19:
/* 011001.. ........ ........ ........ */
/* target/lm32/insns.decode:102 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpei(ctx, &u.f_rri)) return true;
break;
case 0x1a:
/* 011010.. ........ ........ ........ */
/* target/lm32/insns.decode:103 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpgi(ctx, &u.f_rri)) return true;
break;
case 0x1b:
/* 011011.. ........ ........ ........ */
/* target/lm32/insns.decode:104 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpgei(ctx, &u.f_rri)) return true;
break;
case 0x1c:
/* 011100.. ........ ........ ........ */
/* target/lm32/insns.decode:105 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpgeui(ctx, &u.f_rri)) return true;
break;
case 0x1d:
/* 011101.. ........ ........ ........ */
/* target/lm32/insns.decode:106 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpgui(ctx, &u.f_rri)) return true;
break;
case 0x1e:
/* 011110.. ........ ........ ........ */
/* target/lm32/insns.decode:72 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_orhi(ctx, &u.f_rri)) return true;
break;
case 0x1f:
/* 011111.. ........ ........ ........ */
/* target/lm32/insns.decode:107 */
decode_extract_RI(ctx, &u.f_rri, insn);
if (trans_cmpnei(ctx, &u.f_rri)) return true;
break;
case 0x20:
/* 100000.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100000.. ........ .....000 00000000 */
/* target/lm32/insns.decode:110 */
if (trans_sru(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x21:
/* 100001.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100001.. ........ .....000 00000000 */
/* target/lm32/insns.decode:111 */
if (trans_nor(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x22:
/* 100010.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100010.. ........ .....000 00000000 */
/* target/lm32/insns.decode:112 */
if (trans_mul(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x23:
/* 100011.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100011.. ........ .....000 00000000 */
/* target/lm32/insns.decode:113 */
if (trans_divu(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x24:
/* 100100.. ........ ........ ........ */
decode_extract_CR(ctx, &u.f_cr, insn);
switch (insn & 0x0000ffff) {
case 0x00000000:
/* 100100.. ........ 00000000 00000000 */
/* target/lm32/insns.decode:135 */
if (trans_rcsr(ctx, &u.f_cr)) return true;
break;
}
break;
case 0x25:
/* 100101.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100101.. ........ .....000 00000000 */
/* target/lm32/insns.decode:114 */
if (trans_sr(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x26:
/* 100110.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100110.. ........ .....000 00000000 */
/* target/lm32/insns.decode:115 */
if (trans_xor(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x27:
/* 100111.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 100111.. ........ .....000 00000000 */
/* target/lm32/insns.decode:116 */
if (trans_div(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x28:
/* 101000.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 101000.. ........ .....000 00000000 */
/* target/lm32/insns.decode:117 */
if (trans_and(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x29:
/* 101001.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 101001.. ........ .....000 00000000 */
/* target/lm32/insns.decode:118 */
if (trans_xnor(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x2b:
/* 101011.. ........ ........ ........ */
decode_extract_RAISE(ctx, &u.f_raise, insn);
switch (insn & 0x03ffffff) {
case 0x00000002:
/* 10101100 00000000 00000000 00000010 */
/* target/lm32/insns.decode:139 */
if (trans_break(ctx, &u.f_raise)) return true;
break;
case 0x00000007:
/* 10101100 00000000 00000000 00000111 */
/* target/lm32/insns.decode:140 */
if (trans_scall(ctx, &u.f_raise)) return true;
break;
}
break;
case 0x2c:
/* 101100.. ........ ........ ........ */
decode_extract_SEXT(ctx, &u.f_sext, insn);
switch (insn & 0x001f07ff) {
case 0x00000000:
/* 101100.. ...00000 .....000 00000000 */
/* target/lm32/insns.decode:141 */
if (trans_sextb(ctx, &u.f_sext)) return true;
break;
}
break;
case 0x2d:
/* 101101.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 101101.. ........ .....000 00000000 */
/* target/lm32/insns.decode:119 */
if (trans_add(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x2e:
/* 101110.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 101110.. ........ .....000 00000000 */
/* target/lm32/insns.decode:120 */
if (trans_or(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x2f:
/* 101111.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 101111.. ........ .....000 00000000 */
/* target/lm32/insns.decode:121 */
if (trans_sl(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x30:
/* 110000.. ........ ........ ........ */
switch (insn & 0x001fffff) {
case 0x00000000:
/* 110000.. ...00000 00000000 00000000 */
if ((insn & 0x03c00000) == 0x03c00000) {
/* 11000011 11.00000 00000000 00000000 */
decode_extract_RAISE(ctx, &u.f_raise, insn);
switch ((insn >> 21) & 0x1) {
case 0x0:
/* 11000011 11000000 00000000 00000000 */
/* target/lm32/insns.decode:150 */
if (trans_eret(ctx, &u.f_raise)) return true;
break;
case 0x1:
/* 11000011 11100000 00000000 00000000 */
/* target/lm32/insns.decode:149 */
if (trans_bret(ctx, &u.f_raise)) return true;
break;
}
}
/* target/lm32/insns.decode:152 */
decode_extract_CALLBR(ctx, &u.f_r, insn);
if (trans_b(ctx, &u.f_r)) return true;
break;
}
break;
case 0x31:
/* 110001.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 110001.. ........ .....000 00000000 */
/* target/lm32/insns.decode:122 */
if (trans_modu(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x32:
/* 110010.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 110010.. ........ .....000 00000000 */
/* target/lm32/insns.decode:123 */
if (trans_sub(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x34:
/* 110100.. ........ ........ ........ */
decode_extract_CR(ctx, &u.f_cr, insn);
switch (insn & 0x0000ffff) {
case 0x00000000:
/* 110100.. ........ 00000000 00000000 */
/* target/lm32/insns.decode:136 */
if (trans_wcsr(ctx, &u.f_cr)) return true;
break;
}
break;
case 0x35:
/* 110101.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 110101.. ........ .....000 00000000 */
/* target/lm32/insns.decode:124 */
if (trans_mod(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x36:
/* 110110.. ........ ........ ........ */
decode_extract_CALLBR(ctx, &u.f_r, insn);
switch (insn & 0x001fffff) {
case 0x00000000:
/* 110110.. ...00000 00000000 00000000 */
/* target/lm32/insns.decode:154 */
if (trans_call(ctx, &u.f_r)) return true;
break;
}
break;
case 0x37:
/* 110111.. ........ ........ ........ */
decode_extract_SEXT(ctx, &u.f_sext, insn);
switch (insn & 0x001f07ff) {
case 0x00000000:
/* 110111.. ...00000 .....000 00000000 */
/* target/lm32/insns.decode:142 */
if (trans_sexth(ctx, &u.f_sext)) return true;
break;
}
break;
case 0x38:
/* 111000.. ........ ........ ........ */
/* target/lm32/insns.decode:157 */
decode_extract_I(ctx, &u.f_i, insn);
if (trans_bi(ctx, &u.f_i)) return true;
break;
case 0x39:
/* 111001.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111001.. ........ .....000 00000000 */
/* target/lm32/insns.decode:127 */
if (trans_cmpe(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x3a:
/* 111010.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111010.. ........ .....000 00000000 */
/* target/lm32/insns.decode:128 */
if (trans_cmpg(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x3b:
/* 111011.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111011.. ........ .....000 00000000 */
/* target/lm32/insns.decode:129 */
if (trans_cmpge(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x3c:
/* 111100.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111100.. ........ .....000 00000000 */
/* target/lm32/insns.decode:130 */
if (trans_cmpgeu(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x3d:
/* 111101.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111101.. ........ .....000 00000000 */
/* target/lm32/insns.decode:131 */
if (trans_cmpgu(ctx, &u.f_rrr)) return true;
break;
}
break;
case 0x3e:
/* 111110.. ........ ........ ........ */
/* target/lm32/insns.decode:158 */
decode_extract_I(ctx, &u.f_i, insn);
if (trans_calli(ctx, &u.f_i)) return true;
break;
case 0x3f:
/* 111111.. ........ ........ ........ */
decode_extract_RR(ctx, &u.f_rrr, insn);
switch (insn & 0x000007ff) {
case 0x00000000:
/* 111111.. ........ .....000 00000000 */
/* target/lm32/insns.decode:132 */
if (trans_cmpne(ctx, &u.f_rrr)) return true;
break;
}
break;
}
return false;
}
Raw
lm32.decode
# Based on LatticeMico32 Processor Reference Manual version 3.9
# Field definitions
%imm26 0:s26
%imm16 0:s16
%imm5 0:5
%rX 21:5
%rY 16:5
%rZ 11:5
%csr 21:5
# %rimm3 0:3
# Argument sets
&rri rX rY imm
&rrr rX rY rZ
&ri rX imm
&rr rX rY
&r rX
&i imm
&cr rX csr
# &load rX rY imm
# &store rX rY imm
&sext rX rY
&raise
# Formats
@RI 0..... ..... ..... ................ &rri rX=%rX rY=%rY imm=%imm16
@RR 1..... ..... ..... ..... 00000000000 &rrr rX=%rX rY=%rY rZ=%rZ
@CR 1..... ..... ..... 0000000000000000 &cr rX=%rY csr=%csr
@I 1..... .......................... &i imm=%imm26
@RI5 0..... ..... ..... 00000000000 ..... &rri rX=%rX rY=%rY imm=%imm5
@RAISE 101011 00000 00000 0000000000000 ... &raise
@SEXT 1..... ..... 00000 ..... 00000000000 &sext rX=%rX rY=%rZ
@CALLBR 110..0 ..... 00000 00000 00000000000 &r rX=%rX
# Load/Store formats (special arg sets for stronger typing if wanted)
# @LOAD 0..... ..... ..... ................ &load rX=%rX rY=%rY imm=%imm16
# @STORE 0..... ..... ..... ................ &store rX=%rX rY=%rY imm=%imm16
# Arithmetic & Logic - Immediate forms
srui .00000 ..... ..... ........... ..... @RI5
nori .00001 ..... ..... ................ @RI
muli .00010 ..... ..... ................ @RI
sri .00101 ..... ..... ........... ..... @RI5
addi .01101 ..... ..... ................ @RI
ori .01110 ..... ..... ................ @RI
sli .01111 ..... ..... ........... ..... @RI5
xori .00110 ..... ..... ................ @RI
andi .01000 ..... ..... ................ @RI
xnori .01001 ..... ..... ................ @RI
andhi .11000 ..... ..... ................ @RI
orhi .11110 ..... ..... ................ @RI
# Memory operations
# sh .00011 ..... ..... ................ @STORE
# lb .00100 ..... ..... ................ @LOAD
# lh .00111 ..... ..... ................ @LOAD
# lw .01010 ..... ..... ................ @LOAD
# lhu .01011 ..... ..... ................ @LOAD
# sb .01100 ..... ..... ................ @STORE
# lbu .10000 ..... ..... ................ @LOAD
# sw .10110 ..... ..... ................ @STORE
sh .00011 ..... ..... ................ @RI
lb .00100 ..... ..... ................ @RI
lh .00111 ..... ..... ................ @RI
lw .01010 ..... ..... ................ @RI
lhu .01011 ..... ..... ................ @RI
sb .01100 ..... ..... ................ @RI
lbu .10000 ..... ..... ................ @RI
sw .10110 ..... ..... ................ @RI
# Conditional Branches
be .10001 ..... ..... ................ @RI
bg .10010 ..... ..... ................ @RI
bge .10011 ..... ..... ................ @RI
bgeu .10100 ..... ..... ................ @RI
bgu .10101 ..... ..... ................ @RI
bne .10111 ..... ..... ................ @RI
# Compare immediate
cmpei .11001 ..... ..... ................ @RI
cmpgi .11010 ..... ..... ................ @RI
cmpgei .11011 ..... ..... ................ @RI
cmpgeui .11100 ..... ..... ................ @RI
cmpgui .11101 ..... ..... ................ @RI
cmpnei .11111 ..... ..... ................ @RI
# Arithmetic & Logic - Register forms
sru .00000 ..... ..... ..... ........... @RR
nor .00001 ..... ..... ..... ........... @RR
mul .00010 ..... ..... ..... ........... @RR
divu .00011 ..... ..... ..... ........... @RR
sr .00101 ..... ..... ..... ........... @RR
xor .00110 ..... ..... ..... ........... @RR
div .00111 ..... ..... ..... ........... @RR
and .01000 ..... ..... ..... ........... @RR
xnor .01001 ..... ..... ..... ........... @RR
add .01101 ..... ..... ..... ........... @RR
or .01110 ..... ..... ..... ........... @RR
sl .01111 ..... ..... ..... ........... @RR
modu .10001 ..... ..... ..... ........... @RR
sub .10010 ..... ..... ..... ........... @RR
mod .10101 ..... ..... ..... ........... @RR
# Compare register
cmpe .11001 ..... ..... ..... ........... @RR
cmpg .11010 ..... ..... ..... ........... @RR
cmpge .11011 ..... ..... ..... ........... @RR
cmpgeu .11100 ..... ..... ..... ........... @RR
cmpgu .11101 ..... ..... ..... ........... @RR
cmpne .11111 ..... ..... ..... ........... @RR
# Control/Status Register operations
rcsr .00100 ..... ..... ................ @CR
wcsr .10100 ..... ..... ................ @CR
# Special instructions
break ...... ..... ..... ............. 010 @RAISE
scall ...... ..... ..... ............. 111 @RAISE
sextb .01100 ..... ..... ................ @SEXT
sexth .10111 ..... ..... ................ @SEXT
#sextb 101100 ..... ..... 00000 00000000000 &rr rX=%rX rY=%rY
#sexth 110111 ..... ..... 00000 00000000000 &rr rX=%rX rY=%rY
# Branch/Call register forms
{
[
bret 11000011111000000000000000000000
eret 11000011110000000000000000000000
]
b ...00. .......................... @CALLBR
}
call ...11. .......................... @CALLBR
# Branch/Call immediate forms
bi .11000 .......................... @I
calli .11110 .......................... @I
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment