Split verilog modules with their module name as file name

vsplit.pl

#!/usr/bin/perl -w

use Verilog::EditFiles;
use Getopt::Long qw( :config posix_default bundling no_ignore_case );

my $outdir = '';
my $infile = '';
GetOptions ('o=s' => \$outdir, 'i=s' => \$infile);
my $split = Verilog::EditFiles->new(
    outdir => $outdir,
    translate_synthesis => 0,
    lint_header => undef,
    celldefine => 1,
);
$split->read_and_split($infile);
$split->write_files();