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Baby Iguana Yosys
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baby_iguana.pickle.sv
// Compiled by morty-0.9.0 / 2023-03-16 10:49:40.527983167 +01:00
// Copyright 2019 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
module tc_clk_and2 (
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i & clk1_i;
endmodule
module tc_clk_buffer (
input logic clk_i,
output logic clk_o
);
assign clk_o = clk_i;
endmodule
// Description: Behavioral model of an integrated clock-gating cell (ICG)
module tc_clk_gating #(
/// This paramaeter is a hint for tool/technology specific mappings of this
/// tech_cell. It indicates wether this particular clk gate instance is
/// required for functional correctness or just instantiated for power
/// savings. If IS_FUNCTIONAL == 0, technology specific mappings might
/// replace this cell with a feedthrough connection without any gating.
parameter bit IS_FUNCTIONAL = 1'b1
)(
input logic clk_i,
input logic en_i,
input logic test_en_i,
output logic clk_o
);
logic clk_en;
always_latch begin
if (clk_i == 1'b0) clk_en <= en_i | test_en_i;
end
assign clk_o = clk_i & clk_en;
endmodule
module tc_clk_inverter (
input logic clk_i,
output logic clk_o
);
assign clk_o = ~clk_i;
endmodule
// Warning: Typical clock mux cells of a technologies std cell library ARE NOT
// GLITCH FREE!! The only difference to a regular multiplexer cell is that they
// feature balanced rise- and fall-times. In other words: SWITCHING FROM ONE
// CLOCK TO THE OTHER CAN INTRODUCE GLITCHES. ALSO, GLITCHES ON THE SELECT LINE
// DIRECTLY TRANSLATE TO GLITCHES ON THE OUTPUT CLOCK!! This cell is only
// intended to be used for quasi-static switching between clocks when one of the
// clocks is anyway inactive or if the downstream logic remains gated or in
// reset state during the transition phase. If you need dynamic switching
// between arbitrary input clocks without introducing glitches, have a look at
// the clk_mux_glitch_free cell in the pulp-platform/common_cells repository.
module tc_clk_mux2 (
input logic clk0_i,
input logic clk1_i,
input logic clk_sel_i,
output logic clk_o
);
assign clk_o = (clk_sel_i) ? clk1_i : clk0_i;
endmodule
module tc_clk_xor2 (
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i ^ clk1_i;
endmodule
module tc_clk_or2 (
input logic clk0_i,
input logic clk1_i,
output logic clk_o
);
assign clk_o = clk0_i | clk1_i;
endmodule
module tc_clk_delay #(
parameter int unsigned Delay = 300ps
) (
input logic in_i,
output logic out_o
);
// pragma translate_off
// pragma translate_on
endmodule
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Author: Florian Zaruba <[email protected]>
module fifo_v3 #(
parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
parameter type dtype = logic [DATA_WIDTH-1:0],
// DO NOT OVERWRITE THIS PARAMETER
parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i, // flush the queue
input logic testmode_i, // test_mode to bypass clock gating
// status flags
output logic full_o, // queue is full
output logic empty_o, // queue is empty
output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer
// as long as the queue is not full we can push new data
input dtype data_i, // data to push into the queue
input logic push_i, // data is valid and can be pushed to the queue
// as long as the queue is not empty we can pop new elements
output dtype data_o, // output data
input logic pop_i // pop head from queue
);
// local parameter
// FIFO depth - handle the case of pass-through, synthesizer will do constant propagation
localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1;
// clock gating control
logic gate_clock;
// pointer to the read and write section of the queue
logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q;
// keep a counter to keep track of the current queue status
// this integer will be truncated by the synthesis tool
logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q;
// actual memory
dtype [FifoDepth - 1:0] mem_n, mem_q;
assign usage_o = status_cnt_q[ADDR_DEPTH-1:0];
if (DEPTH == 0) begin : gen_pass_through
assign empty_o = ~push_i;
assign full_o = ~pop_i;
end else begin : gen_fifo
assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]);
assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i);
end
// status flags
// read and write queue logic
always_comb begin : read_write_comb
// default assignment
read_pointer_n = read_pointer_q;
write_pointer_n = write_pointer_q;
status_cnt_n = status_cnt_q;
data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
mem_n = mem_q;
gate_clock = 1'b1;
// push a new element to the queue
if (push_i && ~full_o) begin
// push the data onto the queue
mem_n[write_pointer_q] = data_i;
// un-gate the clock, we want to write something
gate_clock = 1'b0;
// increment the write counter
if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1)
write_pointer_n = '0;
else
write_pointer_n = write_pointer_q + 1;
// increment the overall counter
status_cnt_n = status_cnt_q + 1;
end
if (pop_i && ~empty_o) begin
// read from the queue is a default assignment
// but increment the read pointer...
if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1)
read_pointer_n = '0;
else
read_pointer_n = read_pointer_q + 1;
// ... and decrement the overall count
status_cnt_n = status_cnt_q - 1;
end
// keep the count pointer stable if we push and pop at the same time
if (push_i && pop_i && ~full_o && ~empty_o)
status_cnt_n = status_cnt_q;
// FIFO is in pass through mode -> do not change the pointers
if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
data_o = data_i;
if (pop_i) begin
status_cnt_n = status_cnt_q;
read_pointer_n = read_pointer_q;
write_pointer_n = write_pointer_q;
end
end
end
// sequential process
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
read_pointer_q <= '0;
write_pointer_q <= '0;
status_cnt_q <= '0;
end else begin
if (flush_i) begin
read_pointer_q <= '0;
write_pointer_q <= '0;
status_cnt_q <= '0;
end else begin
read_pointer_q <= read_pointer_n;
write_pointer_q <= write_pointer_n;
status_cnt_q <= status_cnt_n;
end
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
mem_q <= '0;
end else if (!gate_clock) begin
mem_q <= mem_n;
end
end
// pragma translate_off
// pragma translate_on
endmodule // fifo_v3
// Copyright 2021 ETH Zurich and University of Bologna.
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// A register with handshakes that completely cuts any combinational paths
/// between the input and output. This spill register can be flushed.
module spill_register_flushable #(
parameter type T = logic,
parameter bit Bypass = 1'b0 // make this spill register transparent
) (
input logic clk_i ,
input logic rst_ni ,
input logic valid_i ,
input logic flush_i ,
output logic ready_o ,
input T data_i ,
output logic valid_o ,
input logic ready_i ,
output T data_o
);
if (Bypass) begin : gen_bypass
assign valid_o = valid_i;
assign ready_o = ready_i;
assign data_o = data_i;
end else begin : gen_spill_reg
// The A register.
T a_data_q;
logic a_full_q;
logic a_fill, a_drain;
always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_data
if (!rst_ni)
a_data_q <= '0;
else if (a_fill)
a_data_q <= data_i;
end
always_ff @(posedge clk_i or negedge rst_ni) begin : ps_a_full
if (!rst_ni)
a_full_q <= 0;
else if (a_fill || a_drain)
a_full_q <= a_fill;
end
// The B register.
T b_data_q;
logic b_full_q;
logic b_fill, b_drain;
always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_data
if (!rst_ni)
b_data_q <= '0;
else if (b_fill)
b_data_q <= a_data_q;
end
always_ff @(posedge clk_i or negedge rst_ni) begin : ps_b_full
if (!rst_ni)
b_full_q <= 0;
else if (b_fill || b_drain)
b_full_q <= b_fill;
end
// Fill the A register when the A or B register is empty. Drain the A register
// whenever it is full and being filled, or if a flush is requested.
assign a_fill = valid_i && ready_o && (!flush_i);
assign a_drain = (a_full_q && !b_full_q) || flush_i;
// Fill the B register whenever the A register is drained, but the downstream
// circuit is not ready. Drain the B register whenever it is full and the
// downstream circuit is ready, or if a flush is requested.
assign b_fill = a_drain && (!ready_i) && (!flush_i);
assign b_drain = (b_full_q && ready_i) || flush_i;
// We can accept input as long as register B is not full.
// Note: flush_i and valid_i must not be high at the same time,
// otherwise an invalid handshake may occur
assign ready_o = !a_full_q || !b_full_q;
// The unit provides output as long as one of the registers is filled.
assign valid_o = a_full_q | b_full_q;
// We empty the spill register before the slice register.
assign data_o = b_full_q ? b_data_q : a_data_q;
// pragma translate_off
// pragma translate_on
end
endmodule
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Antonio Pullini <[email protected]>
module sync #(
parameter int unsigned STAGES = 2,
parameter bit ResetValue = 1'b0
) (
input logic clk_i,
input logic rst_ni,
input logic serial_i,
output logic serial_o
);
(* dont_touch = "true" *)
(* async_reg = "true" *)
logic [STAGES-1:0] reg_q;
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
reg_q <= {STAGES{ResetValue}};
end else begin
reg_q <= {reg_q[STAGES-2:0], serial_i};
end
end
assign serial_o = reg_q[STAGES-1];
endmodule
//-----------------------------------------------------------------------------
// Copyright (C) 2022 ETH Zurich, University of Bologna
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// SPDX-License-Identifier: SHL-0.51
//-----------------------------------------------------------------------------
//
// Author: Manuel Eggimann <[email protected]>
//
// Contains common defintions for the CDC Clear Synchronization Circuitry
package cdc_reset_ctrlr_pkg;
typedef enum logic[1:0] {
CLEAR_PHASE_IDLE,
CLEAR_PHASE_ISOLATE,
CLEAR_PHASE_CLEAR,
CLEAR_PHASE_POST_CLEAR
} clear_seq_phase_e;
endpackage : cdc_reset_ctrlr_pkg
// Copyright 2018 ETH Zurich and University of Bologna.
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Manuel Eggimann <[email protected]>
/// A 4-phase clock domain crossing. While this is less efficient than a 2-phase
/// CDC, it doesn't suffer from the same issues during one sided resets since
/// the IDLE state doesn't alternate with every transaction.
///
/// Parameters: T - The type of the data to transmit through the CDC.
///
/// Decoupled - If decoupled is disabled, the 4phase cdc will not consume the
/// src item until the handshake with the other side is completed. This
/// increases the latency of the first transaction but has no effect on
/// throughput. However, critical paths might be slightly longer. Use this mode
/// if you want to ensure that there are no in-flight transactions within the
/// CDC.
///
/// SEND_RESET_MSG - If send reset msg is enabled, the 4phase cdc starts sending
/// the RESET_MSG within its' asynchronous reset state. This can be usefull if
/// we need to transmit a message to the other side of the CDC immediately
/// during an async reset even if there is no clock available. This mode is
/// required for proper functionality of the cdc_reset_ctrlr module.
///
/// CONSTRAINT: Requires max_delay of min_period(src_clk_i, dst_clk_i) through
/// the paths async_req, async_ack, async_data.
/* verilator lint_off DECLFILENAME */
module cdc_4phase #(
parameter type T = logic,
parameter bit DECOUPLED = 1'b1,
parameter bit SEND_RESET_MSG = 1'b0,
parameter T RESET_MSG = T'('0)
)(
input logic src_rst_ni,
input logic src_clk_i,
input T src_data_i,
input logic src_valid_i,
output logic src_ready_o,
input logic dst_rst_ni,
input logic dst_clk_i,
output T dst_data_o,
output logic dst_valid_o,
input logic dst_ready_i
);
// Asynchronous handshake signals.
(* dont_touch = "true" *) logic async_req;
(* dont_touch = "true" *) logic async_ack;
(* dont_touch = "true" *) T async_data;
// The sender in the source domain.
cdc_4phase_src #(
.T(T),
.DECOUPLED(DECOUPLED),
.SEND_RESET_MSG(SEND_RESET_MSG),
.RESET_MSG(RESET_MSG)
) i_src (
.rst_ni ( src_rst_ni ),
.clk_i ( src_clk_i ),
.data_i ( src_data_i ),
.valid_i ( src_valid_i ),
.ready_o ( src_ready_o ),
.async_req_o ( async_req ),
.async_ack_i ( async_ack ),
.async_data_o ( async_data )
);
// The receiver in the destination domain.
cdc_4phase_dst #(.T(T), .DECOUPLED(DECOUPLED)) i_dst (
.rst_ni ( dst_rst_ni ),
.clk_i ( dst_clk_i ),
.data_o ( dst_data_o ),
.valid_o ( dst_valid_o ),
.ready_i ( dst_ready_i ),
.async_req_i ( async_req ),
.async_ack_o ( async_ack ),
.async_data_i ( async_data )
);
endmodule
/// Half of the 4-phase clock domain crossing located in the source domain.
module cdc_4phase_src #(
parameter type T = logic,
parameter int unsigned SYNC_STAGES = 2,
parameter bit DECOUPLED = 1'b1,
parameter bit SEND_RESET_MSG = 1'b0,
parameter T RESET_MSG = T'('0)
)(
input logic rst_ni,
input logic clk_i,
input T data_i,
input logic valid_i,
output logic ready_o,
output logic async_req_o,
input logic async_ack_i,
output T async_data_o
);
(* dont_touch = "true" *)
logic req_src_d, req_src_q;
(* dont_touch = "true" *)
T data_src_d, data_src_q;
(* dont_touch = "true" *)
logic ack_synced;
typedef enum logic[1:0] {IDLE, WAIT_ACK_ASSERT, WAIT_ACK_DEASSERT} state_e;
state_e state_d, state_q;
// Synchronize the async ACK
sync #(
.STAGES(SYNC_STAGES)
) i_sync(
.clk_i,
.rst_ni,
.serial_i( async_ack_i ),
.serial_o( ack_synced )
);
// FSM for the 4-phase handshake
always_comb begin
state_d = state_q;
req_src_d = 1'b0;
data_src_d = data_src_q;
ready_o = 1'b0;
case (state_q)
IDLE: begin
// If decoupling is disabled, defer assertion of ready until the
// handshake with the dst is completed
if (DECOUPLED) begin
ready_o = 1'b1;
end else begin
ready_o = 1'b0;
end
// Sample a new item when the valid signal is asserted.
if (valid_i) begin
data_src_d = data_i;
req_src_d = 1'b1;
state_d = WAIT_ACK_ASSERT;
end
end
WAIT_ACK_ASSERT: begin
req_src_d = 1'b1;
if (ack_synced == 1'b1) begin
req_src_d = 1'b0;
state_d = WAIT_ACK_DEASSERT;
end
end
WAIT_ACK_DEASSERT: begin
if (ack_synced == 1'b0) begin
state_d = IDLE;
if (!DECOUPLED) begin
ready_o = 1'b1;
end
end
end
default: begin
state_d = IDLE;
end
endcase
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
end
// Sample the data and the request signal to filter combinational glitches
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
if (SEND_RESET_MSG) begin
req_src_q <= 1'b1;
data_src_q <= RESET_MSG;
end else begin
req_src_q <= 1'b0;
data_src_q <= T'('0);
end
end else begin
req_src_q <= req_src_d;
data_src_q <= data_src_d;
end
end
// Async output assignments.
assign async_req_o = req_src_q;
assign async_data_o = data_src_q;
endmodule
/// Half of the 4-phase clock domain crossing located in the destination
/// domain.
module cdc_4phase_dst #(
parameter type T = logic,
parameter int unsigned SYNC_STAGES = 2,
parameter bit DECOUPLED = 1
)(
input logic rst_ni,
input logic clk_i,
output T data_o,
output logic valid_o,
input logic ready_i,
input logic async_req_i,
output logic async_ack_o,
input T async_data_i
);
(* dont_touch = "true" *)
logic ack_dst_d, ack_dst_q;
(* dont_touch = "true" *)
logic req_synced;
logic data_valid;
logic output_ready;
typedef enum logic[1:0] {IDLE, WAIT_DOWNSTREAM_ACK, WAIT_REQ_DEASSERT} state_e;
state_e state_d, state_q;
//Synchronize the request
sync #(
.STAGES(SYNC_STAGES)
) i_sync(
.clk_i,
.rst_ni,
.serial_i( async_req_i ),
.serial_o( req_synced )
);
// FSM for the 4-phase handshake
always_comb begin
state_d = state_q;
data_valid = 1'b0;
ack_dst_d = 1'b0;
case (state_q)
IDLE: begin
// Sample the data upon a new request and transition to the next state
if (req_synced == 1'b1) begin
data_valid = 1'b1;
if (output_ready == 1'b1) begin
state_d = WAIT_REQ_DEASSERT;
end else begin
state_d = WAIT_DOWNSTREAM_ACK;
end
end
end
WAIT_DOWNSTREAM_ACK: begin
data_valid = 1'b1;
if (output_ready == 1'b1) begin
state_d = WAIT_REQ_DEASSERT;
ack_dst_d = 1'b1;
end
end
WAIT_REQ_DEASSERT: begin
ack_dst_d = 1'b1;
if (req_synced == 1'b0) begin
ack_dst_d = 1'b0;
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
end
// Filter glitches on ack signal before sending it through the asynchronous channel
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
ack_dst_q <= 1'b0;
end else begin
ack_dst_q <= ack_dst_d;
end
end
if (DECOUPLED) begin : gen_decoupled
// Decouple the output from the asynchronous data bus without introducing
// additional latency by inserting a spill register
spill_register #(
.T(T),
.Bypass(1'b0)
) i_spill_register (
.clk_i,
.rst_ni,
.valid_i(data_valid),
.ready_o(output_ready),
.data_i(async_data_i),
.valid_o,
.ready_i,
.data_o
);
end else begin : gen_not_decoupled
assign valid_o = data_valid;
assign output_ready = ready_i;
assign data_o = async_data_i;
end
// Output assignments.
assign async_ack_o = ack_dst_q;
endmodule
/* verilator lint_on DECLFILENAME */
// Copyright 2018 ETH Zurich and University of Bologna.
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]>
/// Wrapper around the flushable spill register to maintain back-ward
/// compatibility.
module spill_register #(
parameter type T = logic,
parameter bit Bypass = 1'b0 // make this spill register transparent
) (
input logic clk_i ,
input logic rst_ni ,
input logic valid_i ,
output logic ready_o ,
input T data_i ,
output logic valid_o ,
input logic ready_i ,
output T data_o
);
spill_register_flushable #(
.T(T),
.Bypass(Bypass)
) spill_register_flushable_i (
.clk_i,
.rst_ni,
.valid_i,
.flush_i(1'b0),
.ready_o,
.data_i,
.valid_o,
.ready_i,
.data_o
);
endmodule
//-----------------------------------------------------------------------------
// Title : CDC Clear Signaling Synchronization
// -----------------------------------------------------------------------------
// File : cdc_clear_propagator.sv Author : Manuel Eggimann
// <[email protected]> Created : 22.12.2021
// -----------------------------------------------------------------------------
// Description :
//
// This module is mainly used internally to synchronize the clear requests
// between both sides of a CDC module. It aims to solve the problem of
// initiating a CDC clear, reset one-sidedly without running into
// reset-domain-crossing issues and breaking CDC protocol assumption.
//
// Problem Formulation:
//
// CDC implementations usually face the issue that one side of the CDC must not
// be cleared without clearing the other side. E.g. clearing the write-pointer
// without clearing the read-pointer in a gray-counting CDC FIFO results in an
// invalid fill-state an may cause spurious transactions of invalid data to be
// propagated accross the CDC. A similar effect is caused in 2-phase CDC
// implementations.
//
// A naive mitigation technique would be to reset both domains asynchronously
// with the same reset signal. This will cause intra-clock domain RDC issues
// since the asynchronous clear event (assertion of the reset signal) might
// happen close to the active edge of the CDC's periphery and thus might induce
// metastability. A better, but still flawed approach would be to naively
// synchronize assertion AND deassertion (the usual rst sync only synchronize
// deassertion) of the resets into the respective other domain. However, this
// might cause the classic issue of fast-to-slow clock domain crossing where the
// clear signal is not asserted long enough to be captured by the receiving
// side. The common mitigation strategy is to use a feedback acknowledge signal
// to handshake the reset request into the other domain. One even more peculiar
// corner case this approach might suffer is the scenario where the synchronized
// clear signal arrives at the other side of the CDC within or even worse after
// the same clock cylce that the other domain crossing signals (e.g. read/write
// pointers) are cleared. In this scenario, multiple signals change within the
// same clock cycle and due to metastability we cannot be sure, that the other
// side of the CDC sees the reset assertion before the first bits of e.g. the
// write/read pointer start to switch to their reset state. Care must also be
// taken to handle the corner cases where both sides are reset simultaneously or
// the case where one side leaves reset earlier than the other.
//
// How this Module Works
//
// This module has two interfaces, the 'a' side and the 'b' side. Each side can
// be triggered using the a/b_clear_i signal or (optionally) by the asynchronous
// a/b_rst_ni. Once e.g. 'a' is triggered it will initiate a clear sequence that
// first asserts an 'a_isolate_o' signal, waits until the external circuitry
// acknowledges isolation using the 'a_isolate_ack_i'. Then the module asserts
// the 'a_clear_o' signals before some cycles later, the isolate signal is
// deasserted. This sequence ensures that no transactions can arrive to the CDC
// while the state is cleared. Now the important part is, that those four phases
// (asser isolate, assert clear, deassert clear, deassert isolate) are mirrored
// on the other side ('b') in lock-step. The cdc_reset_ctrlr module uses a
// dedicated 4-phase handshaking CDC to transmit the current phase of the clear
// sequence to the other domain. We use a 4-phase rather than a 2-phase CDC to
// avoid the issues of one-sided async reset that might trigger spurious
// transactions. Furthermore, the 4-phase CDC within this module is operated in
// a special mode: DECOUPLED=0 ensures that there are no in-flight transactions.
// The src side only consumes the item once the destination side acknowledged
// the receiption. This property is required to transition through the phases in
// lock-step. Furthermore, (SEND_RESET_MSG=1) will cause the src side of the
// 4-phase CDC to immediately initiate the isolation phase in the dst domain
// upon asynchronous reset regardless how long the async reset stays asserted or
// whether the source clock is gated. Both sides of this module independently
// generate the sequence signals as an initiator (triggered by the clear_i or
// rst_ni signal) or receiver (trigerred for the other side). The or-ed version
// of initiator and receiver are used to generate the actual a/b_isolate_o and
// a/b_clear_o signal. That way, it doesn't matter wheter both sides
// simulatenously trigger a clear sequence, proper sequencing is still
// guaranteed.
//
// The time it takes to complete an entire clear sequence can be bounded as follows:
//
// t_clear <= 20*T+16*SYNC_STAGES*T, with T=max(T_a, T_b) (clock periods of src and dst)
//
// How to Use the Module
//
// Instantiate the module within your CDC and connect a/b_clk_i, the
// asyncrhonous a/b_rst_ni and the synchronous a/b_clear_i signals. The 'a' and
// 'b' port are entirely symetric so it doesn't matter whether you connect src
// to 'a' or 'b'. If you enable support for async reset
// (CLEAR_ON_ASYNC_RESET==1), parametrize the number of synchronization stages
// (for metastability resolution) to be strictly less than the latency of the
// CDC. E.g. if your CDC uses 3 (the minimum) sync stages, parametrize this
// module with SYNC_STAGES < 2! Your CDC must implement a src/dst_clear_i port
// that SYNCHRONOUSLY clears all FFs on the respective side. Connect the CDC's
// src/dst_clear ports to this module's a/b_clear_o port. Once the a/b_isolate_o
// signal is asserted, the respective CDC side (src/dst) must be isolated from
// the outside world (i.e. must no longer accept any transaction on the src side
// and cease presenting or even withdrawing data on the dst side). Once your CDC
// side is isolated (depending on protocol this might take several cycles),
// assert the a/b_isolate_ack_i signal.
//
// -----------------------------------------------------------------------------
// Copyright (C) 2021 ETH Zurich, University of Bologna Copyright and related
// rights are licensed under the Solderpad Hardware License, Version 0.51 (the
// "License"); you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law or
// agreed to in writing, software, hardware and materials distributed under this
// License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS
// OF ANY KIND, either express or implied. See the License for the specific
// language governing permissions and limitations under the License.
// SPDX-License-Identifier: SHL-0.51
// -----------------------------------------------------------------------------
module cdc_reset_ctrlr
import cdc_reset_ctrlr_pkg::*;
#(
/// The number of synchronization stages to use for the
/// clear signal request/acknowledge. Must be less than the
/// number of sync stages used in the CDC.
parameter int unsigned SYNC_STAGES = 2,
/// Whether an asynchronous reset shall cause a clear
/// request to be sent to the other side.
parameter logic CLEAR_ON_ASYNC_RESET = 1'b1
)(
// Side A (both sides are symmetric)
input logic a_clk_i,
input logic a_rst_ni,
input logic a_clear_i,
output logic a_clear_o,
input logic a_clear_ack_i,
output logic a_isolate_o,
input logic a_isolate_ack_i,
// Side B (both sides are symmetric)
input logic b_clk_i,
input logic b_rst_ni,
input logic b_clear_i,
output logic b_clear_o,
input logic b_clear_ack_i,
output logic b_isolate_o,
input logic b_isolate_ack_i
);
(* dont_touch = "true" *)
logic async_a2b_req, async_b2a_ack;
(* dont_touch = "true" *)
clear_seq_phase_e async_a2b_next_phase;
(* dont_touch = "true" *)
logic async_b2a_req, async_a2b_ack;
(* dont_touch = "true" *)
clear_seq_phase_e async_b2a_next_phase;
cdc_reset_ctrlr_half #(
.SYNC_STAGES ( SYNC_STAGES ),
.CLEAR_ON_ASYNC_RESET ( CLEAR_ON_ASYNC_RESET )
) i_cdc_reset_ctrlr_half_a (
.clk_i ( a_clk_i ),
.rst_ni ( a_rst_ni ),
.clear_i ( a_clear_i ),
.clear_o ( a_clear_o ),
.clear_ack_i ( a_clear_ack_i ),
.isolate_o ( a_isolate_o ),
.isolate_ack_i ( a_isolate_ack_i ),
(* async *) .async_next_phase_o ( async_a2b_next_phase ),
(* async *) .async_req_o ( async_a2b_req ),
(* async *) .async_ack_i ( async_b2a_ack ),
(* async *) .async_next_phase_i ( async_b2a_next_phase ),
(* async *) .async_req_i ( async_b2a_req ),
(* async *) .async_ack_o ( async_a2b_ack )
);
cdc_reset_ctrlr_half #(
.SYNC_STAGES ( SYNC_STAGES ),
.CLEAR_ON_ASYNC_RESET ( CLEAR_ON_ASYNC_RESET )
) i_cdc_reset_ctrlr_half_b (
.clk_i ( b_clk_i ),
.rst_ni ( b_rst_ni ),
.clear_i ( b_clear_i ),
.clear_o ( b_clear_o ),
.clear_ack_i ( b_clear_ack_i ),
.isolate_o ( b_isolate_o ),
.isolate_ack_i ( b_isolate_ack_i ),
(* async *) .async_next_phase_o ( async_b2a_next_phase ),
(* async *) .async_req_o ( async_b2a_req ),
(* async *) .async_ack_i ( async_a2b_ack ),
(* async *) .async_next_phase_i ( async_a2b_next_phase ),
(* async *) .async_req_i ( async_a2b_req ),
(* async *) .async_ack_o ( async_b2a_ack )
);
endmodule
module cdc_reset_ctrlr_half
import cdc_reset_ctrlr_pkg::*;
#(
/// The number of synchronization stages to use for the
/// clear signal request/acknowledge. Must be less than
/// the number of sync stages used in the CDC
parameter int unsigned SYNC_STAGES = 2,
/// Whether an asynchronous reset shall cause a clear
/// request to be sent to the other side.
parameter logic CLEAR_ON_ASYNC_RESET = 1'b1
)(
// Synchronous side
input logic clk_i,
input logic rst_ni,
input logic clear_i,
output logic isolate_o,
input logic isolate_ack_i,
output logic clear_o,
input logic clear_ack_i,
// Asynchronous clear sequence hanshaking
output clear_seq_phase_e async_next_phase_o,
output logic async_req_o,
input logic async_ack_i,
input clear_seq_phase_e async_next_phase_i,
input logic async_req_i,
output logic async_ack_o
);
// How this module works:
// The module is split into two parts. The initiator part consists of an FSM
// that is triggered by the clear_i signal and transitions through reset
// sequence. During those transitions, the `initiator_isolate_out` and
// `initiator_clear_out` signals are asserted appropriately.
// The receiver part receives the state transitions from the other clock
// domain (initiator part of the `cdc_reset_ctrlr_half` instance in the other
// clock domain) and asserts the `receiver_isolate_out` and
// `receiver_clear_out` appropriately (considering the `isolate_ack_i`
// signal).
// In both, the initiator and the receiver part, the respective FSM
// transitions through 4 phases. In the ISOLATE phase, the isolate signal is
// asserted and the connected CDCs are expected to block all further
// interactions with the outside world and acknowledge the isolation with the
// isolate_ack_i signal. In the CLEAR phase, the clear signal is asserted
// which resets the internal state of the CDC while keeping the isolate signal
// asserted. In the POST_CLEAR phase, the clear signal is deasserted. Finally,
// when returning to the IDLE phase, the isolate signal is deasserted to
// continue normal operation. The FSM uses a dedicated 4-phase handshaking CDC
// to transition between the phases in lock-step and transmits the current
// state to the other domain to avoid issues if the other domain is reset
// asynchronously while a clear procedure is pending.
//---------------------- Initiator Side ----------------------
// Sends clear sequence state transitions to the other side.
typedef enum logic[3:0] {
IDLE,
ISOLATE,
WAIT_ISOLATE_PHASE_ACK,
WAIT_ISOLATE_ACK,
CLEAR,
WAIT_CLEAR_PHASE_ACK,
WAIT_CLEAR_ACK,
POST_CLEAR,
FINISHED
} initiator_state_e;
initiator_state_e initiator_state_d, initiator_state_q;
// The current phase of the clear sequence, sent to the other side using a
// 4-phase CDC
clear_seq_phase_e initiator_clear_seq_phase;
logic initiator_phase_transition_req;
logic initiator_phase_transition_ack;
logic initiator_isolate_out;
logic initiator_clear_out;
always_comb begin
initiator_state_d = initiator_state_q;
initiator_phase_transition_req = 1'b0;
initiator_isolate_out = 1'b0;
initiator_clear_out = 1'b0;
initiator_clear_seq_phase = CLEAR_PHASE_IDLE;
case (initiator_state_q)
IDLE: begin
if (clear_i) begin
initiator_state_d = ISOLATE;
end
end
ISOLATE: begin
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_ISOLATE;
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b0;
if (initiator_phase_transition_ack && isolate_ack_i) begin
initiator_state_d = CLEAR;
end else if (initiator_phase_transition_ack) begin
initiator_state_d = WAIT_ISOLATE_ACK;
end else if (isolate_ack_i) begin
initiator_state_d = WAIT_ISOLATE_PHASE_ACK;
end
end
WAIT_ISOLATE_ACK: begin
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b0;
initiator_clear_seq_phase = CLEAR_PHASE_ISOLATE;
if (isolate_ack_i) begin
initiator_state_d = CLEAR;
end
end
WAIT_ISOLATE_PHASE_ACK: begin
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_ISOLATE;
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b0;
if (initiator_phase_transition_ack) begin
initiator_state_d = CLEAR;
end
end
CLEAR: begin
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b1;
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_CLEAR;
if (initiator_phase_transition_ack && clear_ack_i) begin
initiator_state_d = POST_CLEAR;
end else if (initiator_phase_transition_ack) begin
initiator_state_d = WAIT_CLEAR_ACK;
end else if (clear_ack_i) begin
initiator_state_d = WAIT_CLEAR_PHASE_ACK;
end
end
WAIT_CLEAR_ACK: begin
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_CLEAR;
if (clear_ack_i) begin
initiator_state_d = POST_CLEAR;
end
end
WAIT_CLEAR_PHASE_ACK: begin
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_CLEAR;
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b1;
if (initiator_phase_transition_ack) begin
initiator_state_d = POST_CLEAR;
end
end
POST_CLEAR: begin
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b0;
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_POST_CLEAR;
if (initiator_phase_transition_ack) begin
initiator_state_d = FINISHED;
end
end
FINISHED: begin
initiator_isolate_out = 1'b1;
initiator_clear_out = 1'b0;
initiator_phase_transition_req = 1'b1;
initiator_clear_seq_phase = CLEAR_PHASE_IDLE;
if (initiator_phase_transition_ack) begin
initiator_state_d = IDLE;
end
end
default: begin
initiator_state_d = ISOLATE;
end
endcase
end
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
if (CLEAR_ON_ASYNC_RESET) begin
initiator_state_q <= ISOLATE; // Start in the ISOLATE state which is
// the first state of a clear sequence.
end else begin
initiator_state_q <= IDLE;
end
end else begin
initiator_state_q <= initiator_state_d;
end
end
// Initiator CDC SRC
// We use 4 phase handshaking. That way it doesn't matter if one side is
// sudenly reset asynchronously. With a 2phase CDC, one-sided async resets might
// introduce spurios transactions.
cdc_4phase_src #(
.T(clear_seq_phase_e),
.SYNC_STAGES(2),
.DECOUPLED(0), // Important! The CDC must not be in decoupled mode.
// Otherwise we will proceed to the next state without
// waiting for the new state to arrive on the other side.
.SEND_RESET_MSG(CLEAR_ON_ASYNC_RESET), // Send the ISOLATE phase request immediately on async
// reset if async reset synchronization is enabled.
.RESET_MSG(CLEAR_PHASE_ISOLATE)
) i_state_transition_cdc_src(
.clk_i,
.rst_ni,
.data_i(initiator_clear_seq_phase),
.valid_i(initiator_phase_transition_req),
.ready_o(initiator_phase_transition_ack),
.async_req_o,
.async_ack_i,
.async_data_o(async_next_phase_o)
);
//---------------------- Receiver Side ----------------------
// This part of the circuit receives clear sequence state transitions from the
// other side.
clear_seq_phase_e receiver_phase_q;
clear_seq_phase_e receiver_next_phase;
logic receiver_phase_req, receiver_phase_ack;
logic receiver_isolate_out;
logic receiver_clear_out;
cdc_4phase_dst #(
.T(clear_seq_phase_e),
.SYNC_STAGES(2),
.DECOUPLED(0) // Important! The CDC must not be in decoupled mode. Otherwise
// we will proceed to the next state without waiting for the
// new state to arrive on the other side.
) i_state_transition_cdc_dst(
.clk_i,
.rst_ni,
.data_o(receiver_next_phase),
.valid_o(receiver_phase_req),
.ready_i(receiver_phase_ack),
.async_req_i,
.async_ack_o,
.async_data_i(async_next_phase_i)
);
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
receiver_phase_q <= CLEAR_PHASE_IDLE;
end else if (receiver_phase_req && receiver_phase_ack) begin
receiver_phase_q <= receiver_next_phase;
end
end
always_comb begin
receiver_isolate_out = 1'b0;
receiver_clear_out = 1'b0;
receiver_phase_ack = 1'b0;
// If there is a new phase requestd, checkout which one it is and act accordingly
if (receiver_phase_req) begin
case (receiver_next_phase)
CLEAR_PHASE_IDLE: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b0;
receiver_phase_ack = 1'b1;
end
CLEAR_PHASE_ISOLATE: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b1;
// Wait for the isolate to be acknowledged before ack'ing the phase
receiver_phase_ack = isolate_ack_i;
end
CLEAR_PHASE_CLEAR: begin
receiver_clear_out = 1'b1;
receiver_isolate_out = 1'b1;
// Wait for the clear to be acknowledged before ack'ing the phase
receiver_phase_ack = clear_ack_i;
end
CLEAR_PHASE_POST_CLEAR: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b1;
receiver_phase_ack = 1'b1;
end
default: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b0;
receiver_phase_ack = 1'b0;
end
endcase
end else begin
// No phase change is requested for the moment. Act according to the
// current phase signal
case (receiver_phase_q)
CLEAR_PHASE_IDLE: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b0;
end
CLEAR_PHASE_ISOLATE: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b1;
end
CLEAR_PHASE_CLEAR: begin
receiver_clear_out = 1'b1;
receiver_isolate_out = 1'b1;
end
CLEAR_PHASE_POST_CLEAR: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b1;
end
default: begin
receiver_clear_out = 1'b0;
receiver_isolate_out = 1'b0;
receiver_phase_ack = 1'b0;
end
endcase
end
end
// Output Assignment
// The clear and isolate signal are the OR combination of the receiver and
// initiator's clear/isolate signal. This ensures that the correct sequence is
// followed even if both sides are cleared independently at roughly the same
// time.
assign clear_o = initiator_clear_out || receiver_clear_out;
assign isolate_o = initiator_isolate_out || receiver_isolate_out;
endmodule : cdc_reset_ctrlr_half
// Copyright 2018 ETH Zurich and University of Bologna.
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Fabian Schuiki <[email protected]> (original CDC)
// Manuel Eggimann <[email protected]> (clearability feature)
/// A two-phase clock domain crossing.
///
/// CONSTRAINT: Requires max_delay of min_period(src_clk_i, dst_clk_i) through
/// the paths async_req, async_ack, async_data.
///
///
/// Reset Behavior:
///
/// In contrast to the cdc_2phase version without clear signal, this module
/// supports one-sided warm resets (asynchronously and synchronously). The way
/// this is implemented is described in more detail in the cdc_reset_ctrlr
/// module. To summarize a synchronous clear request i.e. src/dst_clear_i will
/// cause the respective other clock domain to reset as well without introducing
/// any spurious transactions. This is acomplished by an internal module
/// (cdc_reset_ctrlr) that starts a reset sequence on both sides of the CDC in
/// lock-step that first isolates the CDC from the outside world and then resets
/// it. The reset sequencer provides the following behavior:
/// 1. There are no spurious invalid or duplicated transactions regardless how
/// the individual sides are reset (can also happen roughly simultaneosly)
/// 2. The CDC becomes unready at the src side in the next cycle after
/// synchronous reset request until the reset sequence is completed. A currently
/// pending transactions might still complete (if the dst accepts at the
/// exact time the reset is request on the src die).
/// 3. During the reset sequence the dst might withdraw the valid signal. This
/// might violate higher level protocols. If you need this feature you would
/// have to path the existing implementation to wait with the isolate_ack
/// assertion until all open handshakes were acknowledged.
/// 4. If the parameter CLEAR_ON_ASYNC_RESET is enabled, the same behavior as
/// above is also valid for asynchronous resets on either side. However, this
/// increases the minimum number of synchronization stages (SYNC_STAGES
/// parameter) from 2 to 3 (read the cdc_reset_ctrlr header to figure out
/// why).
///
///
/* verilator lint_off DECLFILENAME */
// Copyright 2018, 2021 ETH Zurich and University of Bologna.
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// SPDX-License-Identifier: SHL-0.51
//
// Author: Stefan Mach <[email protected]>
// Description: Common register defines for RTL designs
// Abridged Summary of available FF macros:
// `FF: asynchronous active-low reset
// `FFAR: asynchronous active-high reset
// `FFARN: [deprecated] asynchronous active-low reset
// `FFSR: synchronous active-high reset
// `FFSRN: synchronous active-low reset
// `FFNR: without reset
// `FFL: load-enable and asynchronous active-low reset
// `FFLAR: load-enable and asynchronous active-high reset
// `FFLARN: [deprecated] load-enable and asynchronous active-low reset
// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear
// `FFLSR: load-enable and synchronous active-high reset
// `FFLSRN: load-enable and synchronous active-low reset
// `FFLNR: load-enable without reset
// Flip-Flop with asynchronous active-low reset
// __q: Q output of FF
// __d: D input of FF
// __reset_value: value assigned upon reset
// (__clk: clock input)
// (__arst_n: asynchronous reset, active-low)
// Flip-Flop with asynchronous active-high reset
// __q: Q output of FF
// __d: D input of FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __arst: asynchronous reset, active-high
// DEPRECATED - use `FF instead
// Flip-Flop with asynchronous active-low reset
// __q: Q output of FF
// __d: D input of FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __arst_n: asynchronous reset, active-low
// Flip-Flop with synchronous active-high reset
// __q: Q output of FF
// __d: D input of FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __reset_clk: reset input, active-high
// Flip-Flop with synchronous active-low reset
// __q: Q output of FF
// __d: D input of FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __reset_n_clk: reset input, active-low
// Always-enable Flip-Flop without reset
// __q: Q output of FF
// __d: D input of FF
// __clk: clock input
// Flip-Flop with load-enable and asynchronous active-low reset (implicit clock and reset)
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __reset_value: value assigned upon reset
// (__clk: clock input)
// (__arst_n: asynchronous reset, active-low)
// Flip-Flop with load-enable and asynchronous active-high reset
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __arst: asynchronous reset, active-high
// DEPRECATED - use `FFL instead
// Flip-Flop with load-enable and asynchronous active-low reset
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __arst_n: asynchronous reset, active-low
// Flip-Flop with load-enable and synchronous active-high reset
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __reset_clk: reset input, active-high
// Flip-Flop with load-enable and synchronous active-low reset
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __reset_n_clk: reset input, active-low
// Flip-Flop with load-enable and asynchronous active-low reset and synchronous clear
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __clear: assign reset value into FF
// __reset_value: value assigned upon reset
// __clk: clock input
// __arst_n: asynchronous reset, active-low
// Load-enable Flip-Flop without reset
// __q: Q output of FF
// __d: D input of FF
// __load: load d value into FF
// __clk: clock input
module cdc_2phase_clearable #(
parameter type T = logic,
parameter int unsigned SYNC_STAGES = 3,
parameter int CLEAR_ON_ASYNC_RESET = 1
)(
input logic src_rst_ni,
input logic src_clk_i,
input logic src_clear_i,
output logic src_clear_pending_o,
input T src_data_i,
input logic src_valid_i,
output logic src_ready_o,
input logic dst_rst_ni,
input logic dst_clk_i,
input logic dst_clear_i,
output logic dst_clear_pending_o,
output T dst_data_o,
output logic dst_valid_o,
input logic dst_ready_i
);
logic s_src_clear_req;
logic s_src_clear_ack_q;
logic s_src_ready;
logic s_src_isolate_req;
logic s_src_isolate_ack_q;
logic s_dst_clear_req;
logic s_dst_clear_ack_q;
logic s_dst_valid;
logic s_dst_isolate_req;
logic s_dst_isolate_ack_q;
// Asynchronous handshake signals between the CDCs
(* dont_touch = "true" *) logic async_req;
(* dont_touch = "true" *) logic async_ack;
(* dont_touch = "true" *) T async_data;
if (CLEAR_ON_ASYNC_RESET) begin : gen_elaboration_assertion
if (SYNC_STAGES < 3)
$error("The clearable 2-phase CDC with async reset",
"synchronization requires at least 3 synchronizer stages for the FIFO.");
end else begin : gen_elaboration_assertion
if (SYNC_STAGES < 2) begin : gen_elaboration_assertion
$error("A minimum of 2 synchronizer stages is required for proper functionality.");
end
end
// The sender in the source domain.
cdc_2phase_src_clearable #(
.T ( T ),
.SYNC_STAGES ( SYNC_STAGES )
) i_src (
.rst_ni ( src_rst_ni ),
.clk_i ( src_clk_i ),
.clear_i ( s_src_clear_req ),
.data_i ( src_data_i ),
.valid_i ( src_valid_i & !s_src_isolate_req ),
.ready_o ( s_src_ready ),
.async_req_o ( async_req ),
.async_ack_i ( async_ack ),
.async_data_o ( async_data )
);
assign src_ready_o = s_src_ready & !s_src_isolate_req;
// The receiver in the destination domain.
cdc_2phase_dst_clearable #(
.T ( T ),
.SYNC_STAGES ( SYNC_STAGES )
) i_dst (
.rst_ni ( dst_rst_ni ),
.clk_i ( dst_clk_i ),
.clear_i ( s_dst_clear_req ),
.data_o ( dst_data_o ),
.valid_o ( s_dst_valid ),
.ready_i ( dst_ready_i & !s_dst_isolate_req ),
.async_req_i ( async_req ),
.async_ack_o ( async_ack ),
.async_data_i ( async_data )
);
assign dst_valid_o = s_dst_valid & !s_dst_isolate_req;
// Synchronize the clear and reset signaling in both directions (see header of
// the cdc_reset_ctrlr module for more details.)
cdc_reset_ctrlr #(
.SYNC_STAGES(SYNC_STAGES-1)
) i_cdc_reset_ctrlr (
.a_clk_i ( src_clk_i ),
.a_rst_ni ( src_rst_ni ),
.a_clear_i ( src_clear_i ),
.a_clear_o ( s_src_clear_req ),
.a_clear_ack_i ( s_src_clear_ack_q ),
.a_isolate_o ( s_src_isolate_req ),
.a_isolate_ack_i ( s_src_isolate_ack_q ),
.b_clk_i ( dst_clk_i ),
.b_rst_ni ( dst_rst_ni ),
.b_clear_i ( dst_clear_i ),
.b_clear_o ( s_dst_clear_req ),
.b_clear_ack_i ( s_dst_clear_ack_q ),
.b_isolate_o ( s_dst_isolate_req ),
.b_isolate_ack_i ( s_dst_isolate_ack_q )
);
// Just delay the isolate request by one cycle. We can ensure isolation within
// one cycle by just deasserting valid and ready signals on both sides of the CDC.
always_ff @(posedge src_clk_i, negedge src_rst_ni) begin
if (!src_rst_ni) begin
s_src_isolate_ack_q <= 1'b0;
s_src_clear_ack_q <= 1'b0;
end else begin
s_src_isolate_ack_q <= s_src_isolate_req;
s_src_clear_ack_q <= s_src_clear_req;
end
end
always_ff @(posedge dst_clk_i, negedge dst_rst_ni) begin
if (!dst_rst_ni) begin
s_dst_isolate_ack_q <= 1'b0;
s_dst_clear_ack_q <= 1'b0;
end else begin
s_dst_isolate_ack_q <= s_dst_isolate_req;
s_dst_clear_ack_q <= s_dst_clear_req;
end
end
assign src_clear_pending_o = s_src_isolate_req; // The isolate signal stays
// asserted during the whole
// clear sequence.
assign dst_clear_pending_o = s_dst_isolate_req;
endmodule
/// Half of the two-phase clock domain crossing located in the source domain.
module cdc_2phase_src_clearable #(
parameter type T = logic,
parameter int unsigned SYNC_STAGES = 2
) (
input logic rst_ni,
input logic clk_i,
input logic clear_i,
input T data_i,
input logic valid_i,
output logic ready_o,
output logic async_req_o,
input logic async_ack_i,
output T async_data_o
);
(* dont_touch = "true" *)
logic req_src_d, req_src_q, ack_synced;
(* dont_touch = "true" *)
T data_src_d, data_src_q;
// Synchronize the async ACK
sync #(
.STAGES(SYNC_STAGES)
) i_sync(
.clk_i,
.rst_ni,
.serial_i( async_ack_i ),
.serial_o( ack_synced )
);
// If we receive the clear signal clear the content of the request flip-flop
// and the data register
always_comb begin
data_src_d = data_src_q;
req_src_d = req_src_q;
if (clear_i) begin
req_src_d = 1'b0;
// The req_src and data_src registers change when a new data item is accepted.
end else if (valid_i && ready_o) begin
req_src_d = ~req_src_q;
data_src_d = data_i;
end
end
always_ff @(posedge (clk_i)) begin
data_src_q <= (data_src_d);
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
req_src_q <= 0;
end else begin
req_src_q <= req_src_d;
end
end
// Output assignments.
assign ready_o = (req_src_q == ack_synced);
assign async_req_o = req_src_q;
assign async_data_o = data_src_q;
// Assertions
endmodule
/// Half of the two-phase clock domain crossing located in the destination
/// domain.
module cdc_2phase_dst_clearable #(
parameter type T = logic,
parameter int unsigned SYNC_STAGES = 2
)(
input logic rst_ni,
input logic clk_i,
input logic clear_i,
output T data_o,
output logic valid_o,
input logic ready_i,
input logic async_req_i,
output logic async_ack_o,
input T async_data_i
);
(* dont_touch = "true" *)
(* async_reg = "true" *)
logic ack_dst_d, ack_dst_q, req_synced, req_synced_q1;
(* dont_touch = "true" *)
T data_dst_d, data_dst_q;
//Synchronize the request
sync #(
.STAGES(SYNC_STAGES)
) i_sync(
.clk_i,
.rst_ni,
.serial_i( async_req_i ),
.serial_o( req_synced )
);
// The ack_dst register changes when a new data item is accepted.
always_comb begin
ack_dst_d = ack_dst_q;
if (clear_i) begin
ack_dst_d = 1'b0;
end else if (valid_o && ready_i) begin
ack_dst_d = ~ack_dst_q;
end
end
// The data_dst register samples when a new data item is presented. This is
// indicated by a transition in the req_synced line.
always_comb begin
data_dst_d = data_dst_q;
if (req_synced != req_synced_q1 && !valid_o) begin
data_dst_d = async_data_i;
end
end
always_ff @(posedge (clk_i)) begin
data_dst_q <= (data_dst_d);
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
ack_dst_q <= 0;
req_synced_q1 <= 1'b0;
end else begin
ack_dst_q <= ack_dst_d;
// The req_synced_q1 is the delayed version of the synchronized req_synced
// used to detect transitions in the request.
req_synced_q1 <= req_synced;
end
end
// Output assignments.
assign valid_o = (ack_dst_q != req_synced_q1);
assign data_o = data_dst_q;
assign async_ack_o = ack_dst_q;
endmodule
/* verilator lint_on DECLFILENAME */
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Author: Florian Zaruba <[email protected]>
module fifo_v2 #(
parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
parameter int unsigned ALM_EMPTY_TH = 1, // almost empty threshold (when to assert alm_empty_o)
parameter int unsigned ALM_FULL_TH = 1, // almost full threshold (when to assert alm_full_o)
parameter type dtype = logic [DATA_WIDTH-1:0],
// DO NOT OVERWRITE THIS PARAMETER
parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i, // flush the queue
input logic testmode_i, // test_mode to bypass clock gating
// status flags
output logic full_o, // queue is full
output logic empty_o, // queue is empty
output logic alm_full_o, // FIFO fillstate >= the specified threshold
output logic alm_empty_o, // FIFO fillstate <= the specified threshold
// as long as the queue is not full we can push new data
input dtype data_i, // data to push into the queue
input logic push_i, // data is valid and can be pushed to the queue
// as long as the queue is not empty we can pop new elements
output dtype data_o, // output data
input logic pop_i // pop head from queue
);
logic [ADDR_DEPTH-1:0] usage;
// generate threshold parameters
if (DEPTH == 0) begin
assign alm_full_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0
assign alm_empty_o = 1'b0; // that signal does not make any sense in a FIFO of depth 0
end else begin
assign alm_full_o = (usage >= ALM_FULL_TH[ADDR_DEPTH-1:0]);
assign alm_empty_o = (usage <= ALM_EMPTY_TH[ADDR_DEPTH-1:0]);
end
fifo_v3 #(
.FALL_THROUGH ( FALL_THROUGH ),
.DATA_WIDTH ( DATA_WIDTH ),
.DEPTH ( DEPTH ),
.dtype ( dtype )
) i_fifo_v3 (
.clk_i,
.rst_ni,
.flush_i,
.testmode_i,
.full_o,
.empty_o,
.usage_o (usage),
.data_i,
.push_i,
.data_o,
.pop_i
);
// pragma translate_off
// pragma translate_on
endmodule // fifo_v2
// Copyright (c) 2014-2020 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Andreas Kurth <[email protected]>
// - Florian Zaruba <[email protected]>
// - Wolfgang Roenninger <[email protected]>
// - Fabian Schuiki <[email protected]>
// - Matheus Cavalcante <[email protected]>
//! AXI Package
/// Contains all necessary type definitions, constants, and generally useful functions.
package axi_pkg;
/// AXI Transaction Burst Width.
parameter int unsigned BurstWidth = 32'd2;
/// AXI Transaction Response Width.
parameter int unsigned RespWidth = 32'd2;
/// AXI Transaction Cacheability Width.
parameter int unsigned CacheWidth = 32'd4;
/// AXI Transaction Protection Width.
parameter int unsigned ProtWidth = 32'd3;
/// AXI Transaction Quality of Service Width.
parameter int unsigned QosWidth = 32'd4;
/// AXI Transaction Region Width.
parameter int unsigned RegionWidth = 32'd4;
/// AXI Transaction Length Width.
parameter int unsigned LenWidth = 32'd8;
/// AXI Transaction Size Width.
parameter int unsigned SizeWidth = 32'd3;
/// AXI Lock Width.
parameter int unsigned LockWidth = 32'd1;
/// AXI5 Atomic Operation Width.
parameter int unsigned AtopWidth = 32'd6;
/// AXI5 Non-Secure Address Identifier.
parameter int unsigned NsaidWidth = 32'd4;
/// AXI Transaction Burst Width.
typedef logic [BurstWidth-1:0] burst_t;
/// AXI Transaction Response Type.
typedef logic [RespWidth-1:0] resp_t;
/// AXI Transaction Cacheability Type.
typedef logic [CacheWidth-1:0] cache_t;
/// AXI Transaction Protection Type.
typedef logic [ProtWidth-1:0] prot_t;
/// AXI Transaction Quality of Service Type.
typedef logic [QosWidth-1:0] qos_t;
/// AXI Transaction Region Type.
typedef logic [RegionWidth-1:0] region_t;
/// AXI Transaction Length Type.
typedef logic [LenWidth-1:0] len_t;
/// AXI Transaction Size Type.
typedef logic [SizeWidth-1:0] size_t;
/// AXI5 Atomic Operation Type.
typedef logic [AtopWidth-1:0] atop_t; // atomic operations
/// AXI5 Non-Secure Address Identifier.
typedef logic [NsaidWidth-1:0] nsaid_t;
/// In a fixed burst:
/// - The address is the same for every transfer in the burst.
/// - The byte lanes that are valid are constant for all beats in the burst. However, within
/// those byte lanes, the actual bytes that have `wstrb` asserted can differ for each beat in
/// the burst.
/// This burst type is used for repeated accesses to the same location such as when loading or
/// emptying a FIFO.
localparam BURST_FIXED = 2'b00;
/// In an incrementing burst, the address for each transfer in the burst is an increment of the
/// address for the previous transfer. The increment value depends on the size of the transfer.
/// For example, the address for each transfer in a burst with a size of 4 bytes is the previous
/// address plus four.
/// This burst type is used for accesses to normal sequential memory.
localparam BURST_INCR = 2'b01;
/// A wrapping burst is similar to an incrementing burst, except that the address wraps around to
/// a lower address if an upper address limit is reached.
/// The following restrictions apply to wrapping bursts:
/// - The start address must be aligned to the size of each transfer.
/// - The length of the burst must be 2, 4, 8, or 16 transfers.
localparam BURST_WRAP = 2'b10;
/// Normal access success. Indicates that a normal access has been successful. Can also indicate
/// that an exclusive access has failed.
localparam RESP_OKAY = 2'b00;
/// Exclusive access okay. Indicates that either the read or write portion of an exclusive access
/// has been successful.
localparam RESP_EXOKAY = 2'b01;
/// Slave error. Used when the access has reached the slave successfully, but the slave wishes to
/// return an error condition to the originating master.
localparam RESP_SLVERR = 2'b10;
/// Decode error. Generated, typically by an interconnect component, to indicate that there is no
/// slave at the transaction address.
localparam RESP_DECERR = 2'b11;
/// When this bit is asserted, the interconnect, or any component, can delay the transaction
/// reaching its final destination for any number of cycles.
localparam CACHE_BUFFERABLE = 4'b0001;
/// When HIGH, Modifiable indicates that the characteristics of the transaction can be modified.
/// When Modifiable is LOW, the transaction is Non-modifiable.
localparam CACHE_MODIFIABLE = 4'b0010;
/// When this bit is asserted, read allocation of the transaction is recommended but is not
/// mandatory.
localparam CACHE_RD_ALLOC = 4'b0100;
/// When this bit is asserted, write allocation of the transaction is recommended but is not
/// mandatory.
localparam CACHE_WR_ALLOC = 4'b1000;
/// Maximum number of bytes per burst, as specified by `size` (see Table A3-2).
function automatic shortint unsigned num_bytes(size_t size);
return 1 << size;
endfunction
/// An overly long address type.
/// It lets us define functions that work generically for shorter addresses. We rely on the
/// synthesizer to optimize the unused bits away.
typedef logic [127:0] largest_addr_t;
/// Aligned address of burst (see A3-51).
function automatic largest_addr_t aligned_addr(largest_addr_t addr, size_t size);
return (addr >> size) << size;
endfunction
/// Warp boundary of a `BURST_WRAP` transfer (see A3-51).
/// This is the lowest address accessed within a wrapping burst.
/// This address is aligned to the size and length of the burst.
/// The length of a `BURST_WRAP` has to be 2, 4, 8, or 16 transfers.
function automatic largest_addr_t wrap_boundary (largest_addr_t addr, size_t size, len_t len);
largest_addr_t wrap_addr;
// pragma translate_off
// pragma translate_on
// In A3-51 the wrap boundary is defined as:
// `Wrap_Boundary = (INT(Start_Address / (Number_Bytes × Burst_Length))) ×
// (Number_Bytes × Burst_Length)`
// Whereas the aligned address is defined as:
// `Aligned_Address = (INT(Start_Address / Number_Bytes)) × Number_Bytes`
// This leads to the wrap boundary using the same calculation as the aligned address, difference
// being the additional dependency on the burst length. The addition in the case statement
// is equal to the multiplication with `Burst_Length` as a shift (used by `aligned_addr`) is
// equivalent with multiplication and division by a power of two, which conveniently are the
// only allowed values for `len` of a `BURST_WRAP`.
unique case (len)
4'b1 : wrap_addr = (addr >> (unsigned'(size) + 1)) << (unsigned'(size) + 1); // multiply `Number_Bytes` by `2`
4'b11 : wrap_addr = (addr >> (unsigned'(size) + 2)) << (unsigned'(size) + 2); // multiply `Number_Bytes` by `4`
4'b111 : wrap_addr = (addr >> (unsigned'(size) + 3)) << (unsigned'(size) + 3); // multiply `Number_Bytes` by `8`
4'b1111 : wrap_addr = (addr >> (unsigned'(size) + 4)) << (unsigned'(size) + 4); // multiply `Number_Bytes` by `16`
default : wrap_addr = '0;
endcase
return wrap_addr;
endfunction
/// Address of beat (see A3-51).
function automatic largest_addr_t
beat_addr(largest_addr_t addr, size_t size, len_t len, burst_t burst, shortint unsigned i_beat);
largest_addr_t ret_addr = addr;
largest_addr_t wrp_bond = '0;
if (burst == BURST_WRAP) begin
// do not trigger the function if there is no wrapping burst, to prevent assumptions firing
wrp_bond = wrap_boundary(addr, size, len);
end
if (i_beat != 0 && burst != BURST_FIXED) begin
// From A3-51:
// For an INCR burst, and for a WRAP burst for which the address has not wrapped, this
// equation determines the address of any transfer after the first transfer in a burst:
// `Address_N = Aligned_Address + (N – 1) × Number_Bytes` (N counts from 1 to len!)
ret_addr = aligned_addr(addr, size) + i_beat * num_bytes(size);
// From A3-51:
// For a WRAP burst, if Address_N = Wrap_Boundary + (Number_Bytes × Burst_Length), then:
// * Use this equation for the current transfer:
// `Address_N = Wrap_Boundary`
// * Use this equation for any subsequent transfers:
// `Address_N = Start_Address + ((N – 1) × Number_Bytes) – (Number_Bytes × Burst_Length)`
// This means that the address calculation of a `BURST_WRAP` fundamentally works the same
// as for a `BURST_INC`, the difference is when the calculated address increments
// over the wrap threshold, the address wraps around by subtracting the accessed address
// space from the normal `BURST_INCR` address. The lower wrap boundary is equivalent to
// The wrap trigger condition minus the container size (`num_bytes(size) * (len + 1)`).
if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin
ret_addr = ret_addr - (num_bytes(size) * (len + 1));
end
end
return ret_addr;
endfunction
/// Index of lowest byte in beat (see A3-51).
function automatic shortint unsigned
beat_lower_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst,
shortint unsigned strobe_width, shortint unsigned i_beat);
largest_addr_t _addr = beat_addr(addr, size, len, burst, i_beat);
return _addr - (_addr / strobe_width) * strobe_width;
endfunction
/// Index of highest byte in beat (see A3-51).
function automatic shortint unsigned
beat_upper_byte(largest_addr_t addr, size_t size, len_t len, burst_t burst,
shortint unsigned strobe_width, shortint unsigned i_beat);
if (i_beat == 0) begin
return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;
end else begin
return beat_lower_byte(addr, size, len, burst, strobe_width, i_beat) + num_bytes(size) - 1;
end
endfunction
/// Is the bufferable bit set?
function automatic logic bufferable(cache_t cache);
return |(cache & CACHE_BUFFERABLE);
endfunction
/// Is the modifiable bit set?
function automatic logic modifiable(cache_t cache);
return |(cache & CACHE_MODIFIABLE);
endfunction
/// Memory Type.
typedef enum logic [3:0] {
DEVICE_NONBUFFERABLE,
DEVICE_BUFFERABLE,
NORMAL_NONCACHEABLE_NONBUFFERABLE,
NORMAL_NONCACHEABLE_BUFFERABLE,
WTHRU_NOALLOCATE,
WTHRU_RALLOCATE,
WTHRU_WALLOCATE,
WTHRU_RWALLOCATE,
WBACK_NOALLOCATE,
WBACK_RALLOCATE,
WBACK_WALLOCATE,
WBACK_RWALLOCATE
} mem_type_t;
/// Create an `AR_CACHE` field from a `mem_type_t` type.
function automatic logic [3:0] get_arcache(mem_type_t mtype);
unique case (mtype)
DEVICE_NONBUFFERABLE : return 4'b0000;
DEVICE_BUFFERABLE : return 4'b0001;
NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010;
NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011;
WTHRU_NOALLOCATE : return 4'b1010;
WTHRU_RALLOCATE : return 4'b1110;
WTHRU_WALLOCATE : return 4'b1010;
WTHRU_RWALLOCATE : return 4'b1110;
WBACK_NOALLOCATE : return 4'b1011;
WBACK_RALLOCATE : return 4'b1111;
WBACK_WALLOCATE : return 4'b1011;
WBACK_RWALLOCATE : return 4'b1111;
endcase // mtype
endfunction
/// Create an `AW_CACHE` field from a `mem_type_t` type.
function automatic logic [3:0] get_awcache(mem_type_t mtype);
unique case (mtype)
DEVICE_NONBUFFERABLE : return 4'b0000;
DEVICE_BUFFERABLE : return 4'b0001;
NORMAL_NONCACHEABLE_NONBUFFERABLE : return 4'b0010;
NORMAL_NONCACHEABLE_BUFFERABLE : return 4'b0011;
WTHRU_NOALLOCATE : return 4'b0110;
WTHRU_RALLOCATE : return 4'b0110;
WTHRU_WALLOCATE : return 4'b1110;
WTHRU_RWALLOCATE : return 4'b1110;
WBACK_NOALLOCATE : return 4'b0111;
WBACK_RALLOCATE : return 4'b0111;
WBACK_WALLOCATE : return 4'b1111;
WBACK_RWALLOCATE : return 4'b1111;
endcase // mtype
endfunction
/// RESP precedence: DECERR > SLVERR > OKAY > EXOKAY. This is not defined in the AXI standard but
/// depends on the implementation. We consistently use the precedence above. Rationale:
/// - EXOKAY means an exclusive access was successful, whereas OKAY means it was not. Thus, if
/// OKAY and EXOKAY are to be merged, OKAY precedes because the exclusive access was not fully
/// successful.
/// - Both DECERR and SLVERR mean (part of) a transaction were unsuccessful, whereas OKAY means an
/// entire transaction was successful. Thus both DECERR and SLVERR precede OKAY.
/// - DECERR means (part of) a transactions could not be routed to a slave component, whereas
/// SLVERR means the transaction reached a slave component but lead to an error condition there.
/// Thus DECERR precedes SLVERR because DECERR happens earlier in the handling of a transaction.
function automatic resp_t resp_precedence(resp_t resp_a, resp_t resp_b);
unique case (resp_a)
RESP_OKAY: begin
// Any response except EXOKAY precedes OKAY.
if (resp_b == RESP_EXOKAY) begin
return resp_a;
end else begin
return resp_b;
end
end
RESP_EXOKAY: begin
// Any response precedes EXOKAY.
return resp_b;
end
RESP_SLVERR: begin
// Only DECERR precedes SLVERR.
if (resp_b == RESP_DECERR) begin
return resp_b;
end else begin
return resp_a;
end
end
RESP_DECERR: begin
// No response precedes DECERR.
return resp_a;
end
endcase
endfunction
/// AW Width: Returns the width of the AW channel payload
function automatic int unsigned aw_width(int unsigned addr_width, int unsigned id_width,
int unsigned user_width );
// Sum the individual bit widths of the signals
return (id_width + addr_width + LenWidth + SizeWidth + BurstWidth + LockWidth + CacheWidth +
ProtWidth + QosWidth + RegionWidth + AtopWidth + user_width );
endfunction
/// W Width: Returns the width of the W channel payload
function automatic int unsigned w_width(int unsigned data_width, int unsigned user_width );
// Sum the individual bit widths of the signals
return (data_width + data_width / 32'd8 + 32'd1 + user_width);
// ^- StrobeWidth ^- LastWidth
endfunction
/// B Width: Returns the width of the B channel payload
function automatic int unsigned b_width(int unsigned id_width, int unsigned user_width );
// Sum the individual bit widths of the signals
return (id_width + RespWidth + user_width);
endfunction
/// AR Width: Returns the width of the AR channel payload
function automatic int unsigned ar_width(int unsigned addr_width, int unsigned id_width,
int unsigned user_width );
// Sum the individual bit widths of the signals
return (id_width + addr_width + LenWidth + SizeWidth + BurstWidth + LockWidth + CacheWidth +
ProtWidth + QosWidth + RegionWidth + user_width );
endfunction
/// R Width: Returns the width of the R channel payload
function automatic int unsigned r_width(int unsigned data_width, int unsigned id_width,
int unsigned user_width );
// Sum the individual bit widths of the signals
return (id_width + data_width + RespWidth + 32'd1 + user_width);
// ^- LastWidth
endfunction
/// Request Width: Returns the width of the request channel
function automatic int unsigned req_width(int unsigned addr_width, int unsigned data_width,
int unsigned id_width, int unsigned aw_user_width,
int unsigned ar_user_width, int unsigned w_user_width );
// Sum the individual bit widths of the signals and their handshakes
// v- valids
return (aw_width(addr_width, id_width, aw_user_width) + 32'd1 +
w_width(data_width, w_user_width) + 32'd1 +
ar_width(addr_width, id_width, ar_user_width) + 32'd1 + 32'd1 + 32'd1 );
// ^- R, ^- B ready
endfunction
/// Response Width: Returns the width of the response channel
function automatic int unsigned rsp_width(int unsigned data_width, int unsigned id_width,
int unsigned r_user_width, int unsigned b_user_width );
// Sum the individual bit widths of the signals and their handshakes
// v- valids
return (r_width(data_width, id_width, r_user_width) + 32'd1 +
b_width(id_width, b_user_width) + 32'd1 + 32'd1 + 32'd1 + 32'd1);
// ^- AW, ^- AR, ^- W ready
endfunction
// ATOP[5:0]
/// - Sends a single data value with an address.
/// - The target swaps the value at the addressed location with the data value that is supplied in
/// the transaction.
/// - The original data value at the addressed location is returned.
/// - Outbound data size is 1, 2, 4, or 8 bytes.
/// - Inbound data size is the same as the outbound data size.
localparam ATOP_ATOMICSWAP = 6'b110000;
/// - Sends two data values, the compare value and the swap value, to the addressed location.
/// The compare and swap values are of equal size.
/// - The data value at the addressed location is checked against the compare value:
/// - If the values match, the swap value is written to the addressed location.
/// - If the values do not match, the swap value is not written to the addressed location.
/// - The original data value at the addressed location is returned.
/// - Outbound data size is 2, 4, 8, 16, or 32 bytes.
/// - Inbound data size is half of the outbound data size because the outbound data contains both
/// compare and swap values, whereas the inbound data has only the original data value.
localparam ATOP_ATOMICCMP = 6'b110001;
// ATOP[5:4]
/// Perform no atomic operation.
localparam ATOP_NONE = 2'b00;
/// - Sends a single data value with an address and the atomic operation to be performed.
/// - The target performs the operation using the sent data and value at the addressed location as
/// operands.
/// - The result is stored in the address location.
/// - A single response is given without data.
/// - Outbound data size is 1, 2, 4, or 8 bytes.
localparam ATOP_ATOMICSTORE = 2'b01;
/// Sends a single data value with an address and the atomic operation to be performed.
/// - The original data value at the addressed location is returned.
/// - The target performs the operation using the sent data and value at the addressed location as
/// operands.
/// - The result is stored in the address location.
/// - Outbound data size is 1, 2, 4, or 8 bytes.
/// - Inbound data size is the same as the outbound data size.
localparam ATOP_ATOMICLOAD = 2'b10;
// ATOP[3]
/// For AtomicStore and AtomicLoad transactions `AWATOP[3]` indicates the endianness that is
/// required for the atomic operation. The value of `AWATOP[3]` applies to arithmetic operations
/// only and is ignored for bitwise logical operations.
/// When deasserted, this bit indicates that the operation is little-endian.
localparam ATOP_LITTLE_END = 1'b0;
/// When asserted, this bit indicates that the operation is big-endian.
localparam ATOP_BIG_END = 1'b1;
// ATOP[2:0]
/// The value in memory is added to the sent data and the result stored in memory.
localparam ATOP_ADD = 3'b000;
/// Every set bit in the sent data clears the corresponding bit of the data in memory.
localparam ATOP_CLR = 3'b001;
/// Bitwise exclusive OR of the sent data and value in memory.
localparam ATOP_EOR = 3'b010;
/// Every set bit in the sent data sets the corresponding bit of the data in memory.
localparam ATOP_SET = 3'b011;
/// The value stored in memory is the maximum of the existing value and sent data. This operation
/// assumes signed data.
localparam ATOP_SMAX = 3'b100;
/// The value stored in memory is the minimum of the existing value and sent data. This operation
/// assumes signed data.
localparam ATOP_SMIN = 3'b101;
/// The value stored in memory is the maximum of the existing value and sent data. This operation
/// assumes unsigned data.
localparam ATOP_UMAX = 3'b110;
/// The value stored in memory is the minimum of the existing value and sent data. This operation
/// assumes unsigned data.
localparam ATOP_UMIN = 3'b111;
// ATOP[5] == 1'b1 indicated that an atomic transaction has a read response
// Ussage eg: if (req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
localparam ATOP_R_RESP = 32'd5;
// `xbar_latency_e` and `xbar_cfg_t` are documented in `doc/axi_xbar.md`.
/// Slice on Demux AW channel.
localparam logic [9:0] DemuxAw = (1 << 9);
/// Slice on Demux W channel.
localparam logic [9:0] DemuxW = (1 << 8);
/// Slice on Demux B channel.
localparam logic [9:0] DemuxB = (1 << 7);
/// Slice on Demux AR channel.
localparam logic [9:0] DemuxAr = (1 << 6);
/// Slice on Demux R channel.
localparam logic [9:0] DemuxR = (1 << 5);
/// Slice on Mux AW channel.
localparam logic [9:0] MuxAw = (1 << 4);
/// Slice on Mux W channel.
localparam logic [9:0] MuxW = (1 << 3);
/// Slice on Mux B channel.
localparam logic [9:0] MuxB = (1 << 2);
/// Slice on Mux AR channel.
localparam logic [9:0] MuxAr = (1 << 1);
/// Slice on Mux R channel.
localparam logic [9:0] MuxR = (1 << 0);
/// Latency configuration for `axi_xbar`.
typedef enum logic [9:0] {
NO_LATENCY = 10'b000_00_000_00,
CUT_SLV_AX = DemuxAw | DemuxAr,
CUT_MST_AX = MuxAw | MuxAr,
CUT_ALL_AX = DemuxAw | DemuxAr | MuxAw | MuxAr,
CUT_SLV_PORTS = DemuxAw | DemuxW | DemuxB | DemuxAr | DemuxR,
CUT_MST_PORTS = MuxAw | MuxW | MuxB | MuxAr | MuxR,
CUT_ALL_PORTS = 10'b111_11_111_11
} xbar_latency_e;
/// Configuration for `axi_xbar`.
typedef struct packed {
/// Number of slave ports of the crossbar.
/// This many master modules are connected to it.
int unsigned NoSlvPorts;
/// Number of master ports of the crossbar.
/// This many slave modules are connected to it.
int unsigned NoMstPorts;
/// Maximum number of open transactions each master connected to the crossbar can have in
/// flight at the same time.
int unsigned MaxMstTrans;
/// Maximum number of open transactions each slave connected to the crossbar can have in
/// flight at the same time.
int unsigned MaxSlvTrans;
/// Determine if the internal FIFOs of the crossbar are instantiated in fallthrough mode.
/// 0: No fallthrough
/// 1: Fallthrough
bit FallThrough;
/// The Latency mode of the xbar. This determines if the channels on the ports have
/// a spill register instantiated.
/// Example configurations are provided with the enum `xbar_latency_e`.
xbar_latency_e LatencyMode;
/// This is the number of `axi_multicut` stages instantiated in the line cross of the channels.
/// Having multiple stages can potentially add a large number of FFs!
int unsigned PipelineStages;
/// AXI ID width of the salve ports. The ID width of the master ports is determined
/// Automatically. See `axi_mux` for details.
int unsigned AxiIdWidthSlvPorts;
/// The used ID portion to determine if a different salve is used for the same ID.
/// See `axi_demux` for details.
int unsigned AxiIdUsedSlvPorts;
/// Are IDs unique?
bit UniqueIds;
/// AXI4+ATOP address field width.
int unsigned AxiAddrWidth;
/// AXI4+ATOP data field width.
int unsigned AxiDataWidth;
/// The number of address rules defined for routing of the transactions.
/// Each master port can have multiple rules, should have however at least one.
/// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`.
int unsigned NoAddrRules;
} xbar_cfg_t;
/// Commonly used rule types for `axi_xbar` (64-bit addresses).
typedef struct packed {
int unsigned idx;
logic [63:0] start_addr;
logic [63:0] end_addr;
} xbar_rule_64_t;
/// Commonly used rule types for `axi_xbar` (32-bit addresses).
typedef struct packed {
int unsigned idx;
logic [31:0] start_addr;
logic [31:0] end_addr;
} xbar_rule_32_t;
endpackage
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_pkg.sv
* Author: Florian Zaruba <[email protected]>
* Date: 30.6.2018
*
* Description: Debug-module package, contains common system definitions.
*
*/
package dm;
localparam logic [3:0] DbgVersion013 = 4'h2;
// size of program buffer in junks of 32-bit words
localparam logic [4:0] ProgBufSize = 5'h8;
// amount of data count registers implemented
localparam logic [3:0] DataCount = 4'h2;
// address to which a hart should jump when it was requested to halt
localparam logic [63:0] HaltAddress = 64'h800;
localparam logic [63:0] ResumeAddress = HaltAddress + 8;
localparam logic [63:0] ExceptionAddress = HaltAddress + 16;
// address where data0-15 is shadowed or if shadowed in a CSR
// address of the first CSR used for shadowing the data
localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
// debug registers
typedef enum logic [7:0] {
Data0 = 8'h04,
Data1 = 8'h05,
Data2 = 8'h06,
Data3 = 8'h07,
Data4 = 8'h08,
Data5 = 8'h09,
Data6 = 8'h0A,
Data7 = 8'h0B,
Data8 = 8'h0C,
Data9 = 8'h0D,
Data10 = 8'h0E,
Data11 = 8'h0F,
DMControl = 8'h10,
DMStatus = 8'h11, // r/o
Hartinfo = 8'h12,
HaltSum1 = 8'h13,
HAWindowSel = 8'h14,
HAWindow = 8'h15,
AbstractCS = 8'h16,
Command = 8'h17,
AbstractAuto = 8'h18,
DevTreeAddr0 = 8'h19,
DevTreeAddr1 = 8'h1A,
DevTreeAddr2 = 8'h1B,
DevTreeAddr3 = 8'h1C,
NextDM = 8'h1D,
ProgBuf0 = 8'h20,
ProgBuf1 = 8'h21,
ProgBuf2 = 8'h22,
ProgBuf3 = 8'h23,
ProgBuf4 = 8'h24,
ProgBuf5 = 8'h25,
ProgBuf6 = 8'h26,
ProgBuf7 = 8'h27,
ProgBuf8 = 8'h28,
ProgBuf9 = 8'h29,
ProgBuf10 = 8'h2A,
ProgBuf11 = 8'h2B,
ProgBuf12 = 8'h2C,
ProgBuf13 = 8'h2D,
ProgBuf14 = 8'h2E,
ProgBuf15 = 8'h2F,
AuthData = 8'h30,
HaltSum2 = 8'h34,
HaltSum3 = 8'h35,
SBAddress3 = 8'h37,
SBCS = 8'h38,
SBAddress0 = 8'h39,
SBAddress1 = 8'h3A,
SBAddress2 = 8'h3B,
SBData0 = 8'h3C,
SBData1 = 8'h3D,
SBData2 = 8'h3E,
SBData3 = 8'h3F,
HaltSum0 = 8'h40
} dm_csr_e;
// debug causes
localparam logic [2:0] CauseBreakpoint = 3'h1;
localparam logic [2:0] CauseTrigger = 3'h2;
localparam logic [2:0] CauseRequest = 3'h3;
localparam logic [2:0] CauseSingleStep = 3'h4;
typedef struct packed {
logic [31:23] zero1;
logic impebreak;
logic [21:20] zero0;
logic allhavereset;
logic anyhavereset;
logic allresumeack;
logic anyresumeack;
logic allnonexistent;
logic anynonexistent;
logic allunavail;
logic anyunavail;
logic allrunning;
logic anyrunning;
logic allhalted;
logic anyhalted;
logic authenticated;
logic authbusy;
logic hasresethaltreq;
logic devtreevalid;
logic [3:0] version;
} dmstatus_t;
typedef struct packed {
logic haltreq;
logic resumereq;
logic hartreset;
logic ackhavereset;
logic zero1;
logic hasel;
logic [25:16] hartsello;
logic [15:6] hartselhi;
logic [5:4] zero0;
logic setresethaltreq;
logic clrresethaltreq;
logic ndmreset;
logic dmactive;
} dmcontrol_t;
typedef struct packed {
logic [31:24] zero1;
logic [23:20] nscratch;
logic [19:17] zero0;
logic dataaccess;
logic [15:12] datasize;
logic [11:0] dataaddr;
} hartinfo_t;
typedef enum logic [2:0] {
CmdErrNone, CmdErrBusy, CmdErrNotSupported,
CmdErrorException, CmdErrorHaltResume,
CmdErrorBus, CmdErrorOther = 7
} cmderr_e;
typedef struct packed {
logic [31:29] zero3;
logic [28:24] progbufsize;
logic [23:13] zero2;
logic busy;
logic zero1;
cmderr_e cmderr;
logic [7:4] zero0;
logic [3:0] datacount;
} abstractcs_t;
typedef enum logic [7:0] {
AccessRegister = 8'h0,
QuickAccess = 8'h1,
AccessMemory = 8'h2
} cmd_e;
typedef struct packed {
cmd_e cmdtype;
logic [23:0] control;
} command_t;
typedef struct packed {
logic [31:16] autoexecprogbuf;
logic [15:12] zero0;
logic [11:0] autoexecdata;
} abstractauto_t;
typedef struct packed {
logic zero1;
logic [22:20] aarsize;
logic aarpostincrement;
logic postexec;
logic transfer;
logic write;
logic [15:0] regno;
} ac_ar_cmd_t;
// DTM
typedef enum logic [1:0] {
DTM_NOP = 2'h0,
DTM_READ = 2'h1,
DTM_WRITE = 2'h2
} dtm_op_e;
typedef enum logic [1:0] {
DTM_SUCCESS = 2'h0,
DTM_ERR = 2'h2,
DTM_BUSY = 2'h3
} dtm_op_status_e;
typedef struct packed {
logic [31:29] sbversion;
logic [28:23] zero0;
logic sbbusyerror;
logic sbbusy;
logic sbreadonaddr;
logic [19:17] sbaccess;
logic sbautoincrement;
logic sbreadondata;
logic [14:12] sberror;
logic [11:5] sbasize;
logic sbaccess128;
logic sbaccess64;
logic sbaccess32;
logic sbaccess16;
logic sbaccess8;
} sbcs_t;
typedef struct packed {
logic [6:0] addr;
dtm_op_e op;
logic [31:0] data;
} dmi_req_t;
typedef struct packed {
logic [31:0] data;
logic [1:0] resp;
} dmi_resp_t;
typedef struct packed {
logic [31:18] zero1;
logic dmihardreset;
logic dmireset;
logic zero0;
logic [14:12] idle;
logic [11:10] dmistat;
logic [9:4] abits;
logic [3:0] version;
} dtmcs_t;
// privilege levels
typedef enum logic[1:0] {
PRIV_LVL_M = 2'b11,
PRIV_LVL_S = 2'b01,
PRIV_LVL_U = 2'b00
} priv_lvl_t;
// debugregs in core
typedef struct packed {
logic [31:28] xdebugver;
logic [27:16] zero2;
logic ebreakm;
logic zero1;
logic ebreaks;
logic ebreaku;
logic stepie;
logic stopcount;
logic stoptime;
logic [8:6] cause;
logic zero0;
logic mprven;
logic nmip;
logic step;
priv_lvl_t prv;
} dcsr_t;
// CSRs
typedef enum logic [11:0] {
// Floating-Point CSRs
CSR_FFLAGS = 12'h001,
CSR_FRM = 12'h002,
CSR_FCSR = 12'h003,
CSR_FTRAN = 12'h800,
// Supervisor Mode CSRs
CSR_SSTATUS = 12'h100,
CSR_SIE = 12'h104,
CSR_STVEC = 12'h105,
CSR_SCOUNTEREN = 12'h106,
CSR_SSCRATCH = 12'h140,
CSR_SEPC = 12'h141,
CSR_SCAUSE = 12'h142,
CSR_STVAL = 12'h143,
CSR_SIP = 12'h144,
CSR_SATP = 12'h180,
// Machine Mode CSRs
CSR_MSTATUS = 12'h300,
CSR_MISA = 12'h301,
CSR_MEDELEG = 12'h302,
CSR_MIDELEG = 12'h303,
CSR_MIE = 12'h304,
CSR_MTVEC = 12'h305,
CSR_MCOUNTEREN = 12'h306,
CSR_MSCRATCH = 12'h340,
CSR_MEPC = 12'h341,
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_PMPCFG0 = 12'h3A0,
CSR_PMPADDR0 = 12'h3B0,
CSR_MVENDORID = 12'hF11,
CSR_MARCHID = 12'hF12,
CSR_MIMPID = 12'hF13,
CSR_MHARTID = 12'hF14,
CSR_MCYCLE = 12'hB00,
CSR_MINSTRET = 12'hB02,
CSR_DCACHE = 12'h701,
CSR_ICACHE = 12'h700,
CSR_TSELECT = 12'h7A0,
CSR_TDATA1 = 12'h7A1,
CSR_TDATA2 = 12'h7A2,
CSR_TDATA3 = 12'h7A3,
CSR_TINFO = 12'h7A4,
// Debug CSR
CSR_DCSR = 12'h7b0,
CSR_DPC = 12'h7b1,
CSR_DSCRATCH0 = 12'h7b2, // optional
CSR_DSCRATCH1 = 12'h7b3, // optional
// Counters and Timers
CSR_CYCLE = 12'hC00,
CSR_TIME = 12'hC01,
CSR_INSTRET = 12'hC02
} csr_reg_t;
// SBA state
typedef enum logic [2:0] {
Idle,
Read,
Write,
WaitRead,
WaitWrite
} sba_state_e;
// Instruction Generation Helpers
function automatic logic [31:0] jal (logic [4:0] rd,
logic [20:0] imm);
// OpCode Jal
return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f};
endfunction
function automatic logic [31:0] jalr (logic [4:0] rd,
logic [4:0] rs1,
logic [11:0] offset);
// OpCode Jal
return {offset[11:0], rs1, 3'b0, rd, 7'h67};
endfunction
function automatic logic [31:0] andi (logic [4:0] rd,
logic [4:0] rs1,
logic [11:0] imm);
// OpCode andi
return {imm[11:0], rs1, 3'h7, rd, 7'h13};
endfunction
function automatic logic [31:0] slli (logic [4:0] rd,
logic [4:0] rs1,
logic [5:0] shamt);
// OpCode slli
return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13};
endfunction
function automatic logic [31:0] srli (logic [4:0] rd,
logic [4:0] rs1,
logic [5:0] shamt);
// OpCode srli
return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13};
endfunction
function automatic logic [31:0] load (logic [2:0] size,
logic [4:0] dest,
logic [4:0] base,
logic [11:0] offset);
// OpCode Load
return {offset[11:0], base, size, dest, 7'h03};
endfunction
function automatic logic [31:0] auipc (logic [4:0] rd,
logic [20:0] imm);
// OpCode Auipc
return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17};
endfunction
function automatic logic [31:0] store (logic [2:0] size,
logic [4:0] src,
logic [4:0] base,
logic [11:0] offset);
// OpCode Store
return {offset[11:5], src, base, size, offset[4:0], 7'h23};
endfunction
function automatic logic [31:0] float_load (logic [2:0] size,
logic [4:0] dest,
logic [4:0] base,
logic [11:0] offset);
// OpCode Load
return {offset[11:0], base, size, dest, 7'b00_001_11};
endfunction
function automatic logic [31:0] float_store (logic [2:0] size,
logic [4:0] src,
logic [4:0] base,
logic [11:0] offset);
// OpCode Store
return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11};
endfunction
function automatic logic [31:0] csrw (csr_reg_t csr,
logic [4:0] rs1);
// CSRRW, rd, OpCode System
return {csr, rs1, 3'h1, 5'h0, 7'h73};
endfunction
function automatic logic [31:0] csrr (csr_reg_t csr,
logic [4:0] dest);
// rs1, CSRRS, rd, OpCode System
return {csr, 5'h0, 3'h2, dest, 7'h73};
endfunction
function automatic logic [31:0] branch(logic [4:0] src2,
logic [4:0] src1,
logic [2:0] funct3,
logic [11:0] offset);
// OpCode Branch
return {offset[11], offset[9:4], src2, src1, funct3,
offset[3:0], offset[10], 7'b11_000_11};
endfunction
function automatic logic [31:0] ebreak ();
return 32'h00100073;
endfunction
function automatic logic [31:0] wfi ();
return 32'h10500073;
endfunction
function automatic logic [31:0] nop ();
return 32'h00000013;
endfunction
function automatic logic [31:0] illegal ();
return 32'h00000000;
endfunction
endpackage : dm
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: $filename.v
*
* Description: Auto-generated bootrom
*/
// Auto-generated code
module debug_rom (
input logic clk_i,
input logic req_i,
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int unsigned RomSize = 20;
logic [RomSize-1:0][63:0] mem;
assign mem = {
64'h7b200073_7b202473,
64'h7b302573_10852823,
64'hf1402473_a79ff06f,
64'h7b202473_7b302573,
64'h10052423_00100073,
64'h7b202473_7b302573,
64'h10052c23_00c51513,
64'h00c55513_00000517,
64'hfd5ff06f_fa0418e3,
64'h00247413_40044403,
64'h00a40433_f1402473,
64'h02041c63_00147413,
64'h40044403_00a40433,
64'h10852023_f1402473,
64'h00c51513_00c55513,
64'h00000517_7b351073,
64'h7b241073_0ff0000f,
64'h00000013_0500006f,
64'h00000013_0840006f,
64'h00000013_0180006f
};
logic [$clog2(RomSize)-1:0] addr_q;
always_ff @(posedge clk_i) begin
if (req_i) begin
addr_q <= addr_i[$clog2(RomSize)-1+3:3];
end
end
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
always_comb begin : p_outmux
rdata_o = '0;
if (addr_q < $clog2(RomSize)'(RomSize)) begin
rdata_o = mem[addr_q];
end
end
endmodule
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: $filename.v
*
* Description: Auto-generated bootrom
*/
// Auto-generated code
module debug_rom_one_scratch (
input logic clk_i,
input logic req_i,
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int unsigned RomSize = 14;
logic [RomSize-1:0][63:0] mem;
assign mem = {
64'h7b200073_7b202473,
64'h10802823_f1402473,
64'haa5ff06f_7b202473,
64'h10002423_00100073,
64'h7b202473_10002c23,
64'hfddff06f_fc0414e3,
64'h00247413_40044403,
64'hf1402473_02041263,
64'h00147413_40044403,
64'h10802023_f1402473,
64'h7b241073_0ff0000f,
64'h00000013_0380006f,
64'h00000013_0580006f,
64'h00000013_0180006f
};
logic [$clog2(RomSize)-1:0] addr_q;
always_ff @(posedge clk_i) begin
if (req_i) begin
addr_q <= addr_i[$clog2(RomSize)-1+3:3];
end
end
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
always_comb begin : p_outmux
rdata_o = '0;
if (addr_q < $clog2(RomSize)'(RomSize)) begin
rdata_o = mem[addr_q];
end
end
endmodule
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_csrs.sv
* Author: Florian Zaruba <[email protected]>
* Date: 30.6.2018
*
* Description: Debug CSRs. Communication over Debug Transport Module (DTM)
*/
module dm_csrs #(
parameter int unsigned NrHarts = 1,
parameter int unsigned BusWidth = 32,
parameter logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}}
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic testmode_i,
input logic dmi_rst_ni, // sync. DTM reset,
// active-low
input logic dmi_req_valid_i,
output logic dmi_req_ready_o,
input dm::dmi_req_t dmi_req_i,
// every request needs a response one cycle later
output logic dmi_resp_valid_o,
input logic dmi_resp_ready_i,
output dm::dmi_resp_t dmi_resp_o,
// global ctrl
output logic ndmreset_o, // non-debug module reset active-high
output logic dmactive_o, // 1 -> debug-module is active,
// 0 -> synchronous re-set
// hart status
input dm::hartinfo_t [NrHarts-1:0] hartinfo_i, // static hartinfo
input logic [NrHarts-1:0] halted_i, // hart is halted
input logic [NrHarts-1:0] unavailable_i, // e.g.: powered down
input logic [NrHarts-1:0] resumeack_i, // hart acknowledged resume request
// hart control
output logic [19:0] hartsel_o, // hartselect to ctrl module
output logic [NrHarts-1:0] haltreq_o, // request to halt a hart
output logic [NrHarts-1:0] resumereq_o, // request hart to resume
output logic clear_resumeack_o,
output logic cmd_valid_o, // debugger writing to cmd field
output dm::command_t cmd_o, // abstract command
input logic cmderror_valid_i, // an error occurred
input dm::cmderr_e cmderror_i, // this error occurred
input logic cmdbusy_i, // cmd is currently busy executing
output logic [dm::ProgBufSize-1:0][31:0] progbuf_o, // to system bus
output logic [dm::DataCount-1:0][31:0] data_o,
input logic [dm::DataCount-1:0][31:0] data_i,
input logic data_valid_i,
// system bus access module (SBA)
output logic [BusWidth-1:0] sbaddress_o,
input logic [BusWidth-1:0] sbaddress_i,
output logic sbaddress_write_valid_o,
// control signals in
output logic sbreadonaddr_o,
output logic sbautoincrement_o,
output logic [2:0] sbaccess_o,
// data out
output logic sbreadondata_o,
output logic [BusWidth-1:0] sbdata_o,
output logic sbdata_read_valid_o,
output logic sbdata_write_valid_o,
// read data in
input logic [BusWidth-1:0] sbdata_i,
input logic sbdata_valid_i,
// control signals
input logic sbbusy_i,
input logic sberror_valid_i, // bus error occurred
input logic [2:0] sberror_i // bus error occurred
);
// the amount of bits we need to represent all harts
localparam int unsigned HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
localparam int unsigned NrHartsAligned = 2**HartSelLen;
dm::dtm_op_e dtm_op;
assign dtm_op = dm::dtm_op_e'(dmi_req_i.op);
logic resp_queue_full;
logic resp_queue_empty;
logic resp_queue_push;
logic resp_queue_pop;
localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1);
localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1);
logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
logic [((NrHarts-1)/2**5 + 1) * 32 - 1 : 0] halted;
logic [(NrHarts-1)/2**5:0][31:0] halted_reshaped0;
logic [(NrHarts-1)/2**10:0][31:0] halted_reshaped1;
logic [(NrHarts-1)/2**15:0][31:0] halted_reshaped2;
logic [((NrHarts-1)/2**10+1)*32-1:0] halted_flat1;
logic [((NrHarts-1)/2**15+1)*32-1:0] halted_flat2;
logic [31:0] halted_flat3;
// haltsum0
logic [14:0] hartsel_idx0;
always_comb begin : p_haltsum0
halted = '0;
haltsum0 = '0;
hartsel_idx0 = hartsel_o[19:5];
halted[NrHarts-1:0] = halted_i;
halted_reshaped0 = halted;
if (hartsel_idx0 < 15'((NrHarts-1)/2**5+1)) begin
haltsum0 = halted_reshaped0[hartsel_idx0];
end
end
// haltsum1
logic [9:0] hartsel_idx1;
always_comb begin : p_reduction1
halted_flat1 = '0;
haltsum1 = '0;
hartsel_idx1 = hartsel_o[19:10];
for (int unsigned k = 0; k < (NrHarts-1)/2**5+1; k++) begin
halted_flat1[k] = |halted_reshaped0[k];
end
halted_reshaped1 = halted_flat1;
if (hartsel_idx1 < 10'(((NrHarts-1)/2**10+1))) begin
haltsum1 = halted_reshaped1[hartsel_idx1];
end
end
// haltsum2
logic [4:0] hartsel_idx2;
always_comb begin : p_reduction2
halted_flat2 = '0;
haltsum2 = '0;
hartsel_idx2 = hartsel_o[19:15];
for (int unsigned k = 0; k < (NrHarts-1)/2**10+1; k++) begin
halted_flat2[k] = |halted_reshaped1[k];
end
halted_reshaped2 = halted_flat2;
if (hartsel_idx2 < 5'(((NrHarts-1)/2**15+1))) begin
haltsum2 = halted_reshaped2[hartsel_idx2];
end
end
// haltsum3
always_comb begin : p_reduction3
halted_flat3 = '0;
for (int unsigned k = 0; k < NrHarts/2**15+1; k++) begin
halted_flat3[k] = |halted_reshaped2[k];
end
haltsum3 = halted_flat3;
end
dm::dmstatus_t dmstatus;
dm::dmcontrol_t dmcontrol_d, dmcontrol_q;
dm::abstractcs_t abstractcs;
dm::cmderr_e cmderr_d, cmderr_q;
dm::command_t command_d, command_q;
logic cmd_valid_d, cmd_valid_q;
dm::abstractauto_t abstractauto_d, abstractauto_q;
dm::sbcs_t sbcs_d, sbcs_q;
logic [63:0] sbaddr_d, sbaddr_q;
logic [63:0] sbdata_d, sbdata_q;
logic [NrHarts-1:0] havereset_d, havereset_q;
// program buffer
logic [dm::ProgBufSize-1:0][31:0] progbuf_d, progbuf_q;
logic [dm::DataCount-1:0][31:0] data_d, data_q;
logic [HartSelLen-1:0] selected_hart;
dm::dmi_resp_t resp_queue_inp;
assign dmi_resp_valid_o = ~resp_queue_empty;
assign dmi_req_ready_o = ~resp_queue_full;
assign resp_queue_push = dmi_req_valid_i & dmi_req_ready_o;
// SBA
assign sbautoincrement_o = sbcs_q.sbautoincrement;
assign sbreadonaddr_o = sbcs_q.sbreadonaddr;
assign sbreadondata_o = sbcs_q.sbreadondata;
assign sbaccess_o = sbcs_q.sbaccess;
assign sbdata_o = sbdata_q[BusWidth-1:0];
assign sbaddress_o = sbaddr_q[BusWidth-1:0];
assign hartsel_o = {dmcontrol_q.hartselhi, dmcontrol_q.hartsello};
// needed to avoid lint warnings
logic [NrHartsAligned-1:0] havereset_d_aligned, havereset_q_aligned,
resumeack_aligned, unavailable_aligned,
halted_aligned;
assign resumeack_aligned = NrHartsAligned'(resumeack_i);
assign unavailable_aligned = NrHartsAligned'(unavailable_i);
assign halted_aligned = NrHartsAligned'(halted_i);
assign havereset_d = NrHarts'(havereset_d_aligned);
assign havereset_q_aligned = NrHartsAligned'(havereset_q);
dm::hartinfo_t [NrHartsAligned-1:0] hartinfo_aligned;
always_comb begin : p_hartinfo_align
hartinfo_aligned = '0;
hartinfo_aligned[NrHarts-1:0] = hartinfo_i;
end
// helper variables
dm::dm_csr_e dm_csr_addr;
dm::sbcs_t sbcs;
dm::abstractcs_t a_abstractcs;
logic [3:0] autoexecdata_idx; // 0 == Data0 ... 11 == Data11
// Get the data index, i.e. 0 for dm::Data0 up to 11 for dm::Data11
assign dm_csr_addr = dm::dm_csr_e'({1'b0, dmi_req_i.addr});
// Xilinx Vivado 2020.1 does not allow subtraction of two enums; do the subtraction with logic
// types instead.
assign autoexecdata_idx = 4'({dm_csr_addr} - {dm::Data0});
always_comb begin : csr_read_write
// --------------------
// Static Values (R/O)
// --------------------
// dmstatus
dmstatus = '0;
dmstatus.version = dm::DbgVersion013;
// no authentication implemented
dmstatus.authenticated = 1'b1;
// we do not support halt-on-reset sequence
dmstatus.hasresethaltreq = 1'b0;
// TODO(zarubaf) things need to change here if we implement the array mask
dmstatus.allhavereset = havereset_q_aligned[selected_hart];
dmstatus.anyhavereset = havereset_q_aligned[selected_hart];
dmstatus.allresumeack = resumeack_aligned[selected_hart];
dmstatus.anyresumeack = resumeack_aligned[selected_hart];
dmstatus.allunavail = unavailable_aligned[selected_hart];
dmstatus.anyunavail = unavailable_aligned[selected_hart];
// as soon as we are out of the legal Hart region tell the debugger
// that there are only non-existent harts
dmstatus.allnonexistent = logic'(32'(hartsel_o) > (NrHarts - 1));
dmstatus.anynonexistent = logic'(32'(hartsel_o) > (NrHarts - 1));
// We are not allowed to be in multiple states at once. This is a to
// make the running/halted and unavailable states exclusive.
dmstatus.allhalted = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
dmstatus.anyhalted = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
dmstatus.allrunning = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
dmstatus.anyrunning = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
// abstractcs
abstractcs = '0;
abstractcs.datacount = dm::DataCount;
abstractcs.progbufsize = dm::ProgBufSize;
abstractcs.busy = cmdbusy_i;
abstractcs.cmderr = cmderr_q;
// abstractautoexec
abstractauto_d = abstractauto_q;
abstractauto_d.zero0 = '0;
// default assignments
havereset_d_aligned = NrHartsAligned'(havereset_q);
dmcontrol_d = dmcontrol_q;
cmderr_d = cmderr_q;
command_d = command_q;
progbuf_d = progbuf_q;
data_d = data_q;
sbcs_d = sbcs_q;
sbaddr_d = 64'(sbaddress_i);
sbdata_d = sbdata_q;
resp_queue_inp.data = 32'h0;
resp_queue_inp.resp = dm::DTM_SUCCESS;
cmd_valid_d = 1'b0;
sbaddress_write_valid_o = 1'b0;
sbdata_read_valid_o = 1'b0;
sbdata_write_valid_o = 1'b0;
clear_resumeack_o = 1'b0;
// helper variables
sbcs = '0;
a_abstractcs = '0;
// reads
if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) begin
unique case (dm_csr_addr) inside
[(dm::Data0):DataEnd]: begin
resp_queue_inp.data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
// An abstract command was executing while one of the data registers was read
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
dm::DMControl: resp_queue_inp.data = dmcontrol_q;
dm::DMStatus: resp_queue_inp.data = dmstatus;
dm::Hartinfo: resp_queue_inp.data = hartinfo_aligned[selected_hart];
dm::AbstractCS: resp_queue_inp.data = abstractcs;
dm::AbstractAuto: resp_queue_inp.data = abstractauto_q;
// command is read-only
dm::Command: resp_queue_inp.data = '0;
[(dm::ProgBuf0):ProgBufEnd]: begin
resp_queue_inp.data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
// range of autoexecprogbuf is 31:16
cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
// An abstract command was executing while one of the progbuf registers was read
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
dm::HaltSum0: resp_queue_inp.data = haltsum0;
dm::HaltSum1: resp_queue_inp.data = haltsum1;
dm::HaltSum2: resp_queue_inp.data = haltsum2;
dm::HaltSum3: resp_queue_inp.data = haltsum3;
dm::SBCS: begin
resp_queue_inp.data = sbcs_q;
end
dm::SBAddress0: begin
resp_queue_inp.data = sbaddr_q[31:0];
end
dm::SBAddress1: begin
resp_queue_inp.data = sbaddr_q[63:32];
end
dm::SBData0: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbdata_read_valid_o = (sbcs_q.sberror == '0);
resp_queue_inp.data = sbdata_q[31:0];
end
end
dm::SBData1: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
resp_queue_inp.data = sbdata_q[63:32];
end
end
default:;
endcase
end
// write
if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_WRITE) begin
unique case (dm_csr_addr) inside
[(dm::Data0):DataEnd]: begin
if (dm::DataCount > 0) begin
// attempts to write them while busy is set does not change their value
if (!cmdbusy_i) begin
data_d[dmi_req_i.addr[$clog2(dm::DataCount)-1:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
//An abstract command was executing while one of the data registers was written
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
end
dm::DMControl: begin
dmcontrol_d = dmi_req_i.data;
// clear the havreset of the selected hart
if (dmcontrol_d.ackhavereset) begin
havereset_d_aligned[selected_hart] = 1'b0;
end
end
dm::DMStatus:; // write are ignored to R/O register
dm::Hartinfo:; // hartinfo is R/O
// only command error is write-able
dm::AbstractCS: begin // W1C
// Gets set if an abstract command fails. The bits in this
// field remain set until they are cleared by writing 1 to
// them. No abstract command is started until the value is
// reset to 0.
a_abstractcs = dm::abstractcs_t'(dmi_req_i.data);
// reads during abstract command execution are not allowed
if (!cmdbusy_i) begin
cmderr_d = dm::cmderr_e'(~a_abstractcs.cmderr & cmderr_q);
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
dm::Command: begin
// writes are ignored if a command is already busy
if (!cmdbusy_i) begin
cmd_valid_d = 1'b1;
command_d = dm::command_t'(dmi_req_i.data);
// if there was an attempted to write during a busy execution
// and the cmderror field is zero set the busy error
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
dm::AbstractAuto: begin
// this field can only be written legally when there is no command executing
if (!cmdbusy_i) begin
abstractauto_d = 32'h0;
abstractauto_d.autoexecdata = 12'(dmi_req_i.data[dm::DataCount-1:0]);
abstractauto_d.autoexecprogbuf = 16'(dmi_req_i.data[dm::ProgBufSize-1+16:16]);
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
[(dm::ProgBuf0):ProgBufEnd]: begin
// attempts to write them while busy is set does not change their value
if (!cmdbusy_i) begin
progbuf_d[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
// this should probably throw an error if executed during another command
// was busy
// range of autoexecprogbuf is 31:16
cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
//An abstract command was executing while one of the progbuf registers was written
end else begin
resp_queue_inp.resp = dm::DTM_BUSY;
if (cmderr_q == dm::CmdErrNone) begin
cmderr_d = dm::CmdErrBusy;
end
end
end
dm::SBCS: begin
// access while the SBA was busy
if (sbbusy_i) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbcs = dm::sbcs_t'(dmi_req_i.data);
sbcs_d = sbcs;
// R/W1C
sbcs_d.sbbusyerror = sbcs_q.sbbusyerror & (~sbcs.sbbusyerror);
sbcs_d.sberror = sbcs_q.sberror & {3{~(sbcs.sberror == 3'd1)}};
end
end
dm::SBAddress0: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbaddr_d[31:0] = dmi_req_i.data;
sbaddress_write_valid_o = (sbcs_q.sberror == '0);
end
end
dm::SBAddress1: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbaddr_d[63:32] = dmi_req_i.data;
end
end
dm::SBData0: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbdata_d[31:0] = dmi_req_i.data;
sbdata_write_valid_o = (sbcs_q.sberror == '0);
end
end
dm::SBData1: begin
// access while the SBA was busy
if (sbbusy_i || sbcs_q.sbbusyerror) begin
sbcs_d.sbbusyerror = 1'b1;
resp_queue_inp.resp = dm::DTM_BUSY;
end else begin
sbdata_d[63:32] = dmi_req_i.data;
end
end
default:;
endcase
end
// hart threw a command error and has precedence over bus writes
if (cmderror_valid_i) begin
cmderr_d = cmderror_i;
end
// update data registers
if (data_valid_i) begin
data_d = data_i;
end
// set the havereset flag when we did a ndmreset
if (ndmreset_o) begin
havereset_d_aligned[NrHarts-1:0] = '1;
end
// -------------
// System Bus
// -------------
// set bus error
if (sberror_valid_i) begin
sbcs_d.sberror = sberror_i;
end
// update read data
if (sbdata_valid_i) begin
sbdata_d = 64'(sbdata_i);
end
// dmcontrol
// TODO(zarubaf) we currently do not implement the hartarry mask
dmcontrol_d.hasel = 1'b0;
// we do not support resetting an individual hart
dmcontrol_d.hartreset = 1'b0;
dmcontrol_d.setresethaltreq = 1'b0;
dmcontrol_d.clrresethaltreq = 1'b0;
dmcontrol_d.zero1 = '0;
dmcontrol_d.zero0 = '0;
// Non-writeable, clear only
dmcontrol_d.ackhavereset = 1'b0;
if (!dmcontrol_q.resumereq && dmcontrol_d.resumereq) begin
clear_resumeack_o = 1'b1;
end
if (dmcontrol_q.resumereq && resumeack_i) begin
dmcontrol_d.resumereq = 1'b0;
end
// static values for dcsr
sbcs_d.sbversion = 3'd1;
sbcs_d.sbbusy = sbbusy_i;
sbcs_d.sbasize = $bits(sbcs_d.sbasize)'(BusWidth);
sbcs_d.sbaccess128 = logic'(BusWidth >= 32'd128);
sbcs_d.sbaccess64 = logic'(BusWidth >= 32'd64);
sbcs_d.sbaccess32 = logic'(BusWidth >= 32'd32);
sbcs_d.sbaccess16 = logic'(BusWidth >= 32'd16);
sbcs_d.sbaccess8 = logic'(BusWidth >= 32'd8);
end
// output multiplexer
always_comb begin : p_outmux
selected_hart = hartsel_o[HartSelLen-1:0];
// default assignment
haltreq_o = '0;
resumereq_o = '0;
if (selected_hart <= HartSelLen'(NrHarts-1)) begin
haltreq_o[selected_hart] = dmcontrol_q.haltreq;
resumereq_o[selected_hart] = dmcontrol_q.resumereq;
end
end
assign dmactive_o = dmcontrol_q.dmactive;
assign cmd_o = command_q;
assign cmd_valid_o = cmd_valid_q;
assign progbuf_o = progbuf_q;
assign data_o = data_q;
assign resp_queue_pop = dmi_resp_ready_i & ~resp_queue_empty;
assign ndmreset_o = dmcontrol_q.ndmreset;
// response FIFO
fifo_v2 #(
.dtype ( logic [$bits(dmi_resp_o)-1:0] ),
.DEPTH ( 2 )
) i_fifo (
.clk_i,
.rst_ni,
.flush_i ( ~dmi_rst_ni ), // Flush the queue if the DTM is
// reset
.testmode_i ( testmode_i ),
.full_o ( resp_queue_full ),
.empty_o ( resp_queue_empty ),
.alm_full_o ( ),
.alm_empty_o ( ),
.data_i ( resp_queue_inp ),
.push_i ( resp_queue_push ),
.data_o ( dmi_resp_o ),
.pop_i ( resp_queue_pop )
);
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
// PoR
if (!rst_ni) begin
dmcontrol_q <= '0;
// this is the only write-able bit during reset
cmderr_q <= dm::CmdErrNone;
command_q <= '0;
cmd_valid_q <= '0;
abstractauto_q <= '0;
progbuf_q <= '0;
data_q <= '0;
sbcs_q <= '{default: '0, sbaccess: 3'd2};
sbaddr_q <= '0;
sbdata_q <= '0;
havereset_q <= '1;
end else begin
havereset_q <= SelectableHarts & havereset_d;
// synchronous re-set of debug module, active-low, except for dmactive
if (!dmcontrol_q.dmactive) begin
dmcontrol_q.haltreq <= '0;
dmcontrol_q.resumereq <= '0;
dmcontrol_q.hartreset <= '0;
dmcontrol_q.ackhavereset <= '0;
dmcontrol_q.zero1 <= '0;
dmcontrol_q.hasel <= '0;
dmcontrol_q.hartsello <= '0;
dmcontrol_q.hartselhi <= '0;
dmcontrol_q.zero0 <= '0;
dmcontrol_q.setresethaltreq <= '0;
dmcontrol_q.clrresethaltreq <= '0;
dmcontrol_q.ndmreset <= '0;
// this is the only write-able bit during reset
dmcontrol_q.dmactive <= dmcontrol_d.dmactive;
cmderr_q <= dm::CmdErrNone;
command_q <= '0;
cmd_valid_q <= '0;
abstractauto_q <= '0;
progbuf_q <= '0;
data_q <= '0;
sbcs_q <= '{default: '0, sbaccess: 3'd2};
sbaddr_q <= '0;
sbdata_q <= '0;
end else begin
dmcontrol_q <= dmcontrol_d;
cmderr_q <= cmderr_d;
command_q <= command_d;
cmd_valid_q <= cmd_valid_d;
abstractauto_q <= abstractauto_d;
progbuf_q <= progbuf_d;
data_q <= data_d;
sbcs_q <= sbcs_d;
sbaddr_q <= sbaddr_d;
sbdata_q <= sbdata_d;
end
end
end
endmodule : dm_csrs
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_mem.sv
* Author: Florian Zaruba <[email protected]>
* Date: 11.7.2018
*
* Description: Memory module for execution-based debug clients
*
*/
module dm_mem #(
parameter int unsigned NrHarts = 1,
parameter int unsigned BusWidth = 32,
parameter logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}},
parameter int unsigned DmBaseAddress = '0
) (
input logic clk_i, // Clock
input logic rst_ni, // debug module reset
output logic [NrHarts-1:0] debug_req_o,
input logic ndmreset_i,
input logic [19:0] hartsel_i,
// from Ctrl and Status register
input logic [NrHarts-1:0] haltreq_i,
input logic [NrHarts-1:0] resumereq_i,
input logic clear_resumeack_i,
// state bits
output logic [NrHarts-1:0] halted_o, // hart acknowledge halt
output logic [NrHarts-1:0] resuming_o, // hart is resuming
input logic [dm::ProgBufSize-1:0][31:0] progbuf_i, // program buffer to expose
input logic [dm::DataCount-1:0][31:0] data_i, // data in
output logic [dm::DataCount-1:0][31:0] data_o, // data out
output logic data_valid_o, // data out is valid
// abstract command interface
input logic cmd_valid_i,
input dm::command_t cmd_i,
output logic cmderror_valid_o,
output dm::cmderr_e cmderror_o,
output logic cmdbusy_o,
// data interface
// SRAM interface
input logic req_i,
input logic we_i,
input logic [BusWidth-1:0] addr_i,
input logic [BusWidth-1:0] wdata_i,
input logic [BusWidth/8-1:0] be_i,
output logic [BusWidth-1:0] rdata_o
);
localparam int unsigned DbgAddressBits = 12;
localparam int unsigned HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
localparam int unsigned NrHartsAligned = 2**HartSelLen;
localparam int unsigned MaxAar = (BusWidth == 64) ? 4 : 3;
localparam bit HasSndScratch = (DmBaseAddress != 0);
// Depending on whether we are at the zero page or not we either use `x0` or `x10/a0`
localparam logic [4:0] LoadBaseAddr = (DmBaseAddress == 0) ? 5'd0 : 5'd10;
localparam logic [DbgAddressBits-1:0] DataBaseAddr = (dm::DataAddr);
localparam logic [DbgAddressBits-1:0] DataEndAddr = (dm::DataAddr + 4*dm::DataCount - 1);
localparam logic [DbgAddressBits-1:0] ProgBufBaseAddr = (dm::DataAddr - 4*dm::ProgBufSize);
localparam logic [DbgAddressBits-1:0] ProgBufEndAddr = (dm::DataAddr - 1);
localparam logic [DbgAddressBits-1:0] AbstractCmdBaseAddr = (ProgBufBaseAddr - 4*10);
localparam logic [DbgAddressBits-1:0] AbstractCmdEndAddr = (ProgBufBaseAddr - 1);
localparam logic [DbgAddressBits-1:0] WhereToAddr = 'h300;
localparam logic [DbgAddressBits-1:0] FlagsBaseAddr = 'h400;
localparam logic [DbgAddressBits-1:0] FlagsEndAddr = 'h7FF;
localparam logic [DbgAddressBits-1:0] HaltedAddr = 'h100;
localparam logic [DbgAddressBits-1:0] GoingAddr = 'h108;
localparam logic [DbgAddressBits-1:0] ResumingAddr = 'h110;
localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h118;
logic [dm::ProgBufSize/2-1:0][63:0] progbuf;
logic [7:0][63:0] abstract_cmd;
logic [NrHarts-1:0] halted_d, halted_q;
logic [NrHarts-1:0] resuming_d, resuming_q;
logic resume, go, going;
logic exception;
logic unsupported_command;
logic [63:0] rom_rdata;
logic [63:0] rdata_d, rdata_q;
logic word_enable32_q;
// this is needed to avoid lint warnings related to array indexing
// resize hartsel to valid range
logic [HartSelLen-1:0] hartsel, wdata_hartsel;
assign hartsel = hartsel_i[HartSelLen-1:0];
assign wdata_hartsel = wdata_i[HartSelLen-1:0];
logic [NrHartsAligned-1:0] resumereq_aligned, haltreq_aligned,
halted_d_aligned, halted_q_aligned,
halted_aligned, resumereq_wdata_aligned,
resuming_d_aligned, resuming_q_aligned;
assign resumereq_aligned = NrHartsAligned'(resumereq_i);
assign haltreq_aligned = NrHartsAligned'(haltreq_i);
assign resumereq_wdata_aligned = NrHartsAligned'(resumereq_i);
assign halted_q_aligned = NrHartsAligned'(halted_q);
assign halted_d = NrHarts'(halted_d_aligned);
assign resuming_q_aligned = NrHartsAligned'(resuming_q);
assign resuming_d = NrHarts'(resuming_d_aligned);
// distinguish whether we need to forward data from the ROM or the FSM
// latch the address for this
logic fwd_rom_d, fwd_rom_q;
dm::ac_ar_cmd_t ac_ar;
// Abstract Command Access Register
assign ac_ar = dm::ac_ar_cmd_t'(cmd_i.control);
assign debug_req_o = haltreq_i;
assign halted_o = halted_q;
assign resuming_o = resuming_q;
// reshape progbuf
assign progbuf = progbuf_i;
typedef enum logic [1:0] { Idle, Go, Resume, CmdExecuting } state_e;
state_e state_d, state_q;
// hart ctrl queue
always_comb begin : p_hart_ctrl_queue
cmderror_valid_o = 1'b0;
cmderror_o = dm::CmdErrNone;
state_d = state_q;
go = 1'b0;
resume = 1'b0;
cmdbusy_o = 1'b1;
unique case (state_q)
Idle: begin
cmdbusy_o = 1'b0;
if (cmd_valid_i && halted_q_aligned[hartsel] && !unsupported_command) begin
// give the go signal
state_d = Go;
end else if (cmd_valid_i) begin
// hart must be halted for all requests
cmderror_valid_o = 1'b1;
cmderror_o = dm::CmdErrorHaltResume;
end
// CSRs want to resume, the request is ignored when the hart is
// requested to halt or it didn't clear the resuming_q bit before
if (resumereq_aligned[hartsel] && !resuming_q_aligned[hartsel] &&
!haltreq_aligned[hartsel] && halted_q_aligned[hartsel]) begin
state_d = Resume;
end
end
Go: begin
// we are already busy here since we scheduled the execution of a program
cmdbusy_o = 1'b1;
go = 1'b1;
// the thread is now executing the command, track its state
if (going) begin
state_d = CmdExecuting;
end
end
Resume: begin
cmdbusy_o = 1'b1;
resume = 1'b1;
if (resuming_q_aligned[hartsel]) begin
state_d = Idle;
end
end
CmdExecuting: begin
cmdbusy_o = 1'b1;
go = 1'b0;
// wait until the hart has halted again
if (halted_aligned[hartsel]) begin
state_d = Idle;
end
end
default: ;
endcase
// only signal once that cmd is unsupported so that we can clear cmderr
// in subsequent writes to abstractcs
if (unsupported_command && cmd_valid_i) begin
cmderror_valid_o = 1'b1;
cmderror_o = dm::CmdErrNotSupported;
end
if (exception) begin
cmderror_valid_o = 1'b1;
cmderror_o = dm::CmdErrorException;
end
if (ndmreset_i) begin
// Clear state of hart and its control signals when it is being reset.
state_d = Idle;
go = 1'b0;
resume = 1'b0;
end
end
// word mux for 32bit and 64bit buses
logic [63:0] word_mux;
assign word_mux = (fwd_rom_q) ? rom_rdata : rdata_q;
if (BusWidth == 64) begin : gen_word_mux64
assign rdata_o = word_mux;
end else begin : gen_word_mux32
assign rdata_o = (word_enable32_q) ? word_mux[32 +: 32] : word_mux[0 +: 32];
end
// read/write logic
logic [dm::DataCount-1:0][31:0] data_bits;
logic [7:0][7:0] rdata;
always_comb begin : p_rw_logic
halted_d_aligned = NrHartsAligned'(halted_q);
resuming_d_aligned = NrHartsAligned'(resuming_q);
rdata_d = rdata_q;
data_bits = data_i;
rdata = '0;
// write data in csr register
data_valid_o = 1'b0;
exception = 1'b0;
halted_aligned = '0;
going = 1'b0;
// The resume ack signal is lowered when the resume request is deasserted
if (clear_resumeack_i) begin
resuming_d_aligned[hartsel] = 1'b0;
end
// we've got a new request
if (req_i) begin
// this is a write
if (we_i) begin
unique case (addr_i[DbgAddressBits-1:0]) inside
HaltedAddr: begin
halted_aligned[wdata_hartsel] = 1'b1;
halted_d_aligned[wdata_hartsel] = 1'b1;
end
GoingAddr: begin
going = 1'b1;
end
ResumingAddr: begin
// clear the halted flag as the hart resumed execution
halted_d_aligned[wdata_hartsel] = 1'b0;
// set the resuming flag which needs to be cleared by the debugger
resuming_d_aligned[wdata_hartsel] = 1'b1;
end
// an exception occurred during execution
ExceptionAddr: exception = 1'b1;
// core can write data registers
[DataBaseAddr:DataEndAddr]: begin
data_valid_o = 1'b1;
for (int dc = 0; dc < dm::DataCount; dc++) begin
if ((addr_i[DbgAddressBits-1:2] - DataBaseAddr[DbgAddressBits-1:2]) == dc) begin
for (int i = 0; i < $bits(be_i); i++) begin
if (be_i[i]) begin
if (i>3) begin // for upper 32bit data write (only used for BusWidth == 64)
if ((dc+1) < dm::DataCount) begin // ensure we write to an implemented data register
data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
end
end else begin // for lower 32bit data write
data_bits[dc][i*8+:8] = wdata_i[i*8+:8];
end
end
end
end
end
end
default ;
endcase
// this is a read
end else begin
unique case (addr_i[DbgAddressBits-1:0]) inside
// variable ROM content
WhereToAddr: begin
// variable jump to abstract cmd, program_buffer or resume
if (resumereq_wdata_aligned[wdata_hartsel]) begin
rdata_d = {32'b0, dm::jal('0, 21'(dm::ResumeAddress[11:0])-21'(WhereToAddr))};
end
// there is a command active so jump there
if (cmdbusy_o) begin
// transfer not set is shortcut to the program buffer if postexec is set
// keep this statement narrow to not catch invalid commands
if (cmd_i.cmdtype == dm::AccessRegister &&
!ac_ar.transfer && ac_ar.postexec) begin
rdata_d = {32'b0, dm::jal('0, 21'(ProgBufBaseAddr)-21'(WhereToAddr))};
// this is a legit abstract cmd -> execute it
end else begin
rdata_d = {32'b0, dm::jal('0, 21'(AbstractCmdBaseAddr)-21'(WhereToAddr))};
end
end
end
[DataBaseAddr:DataEndAddr]: begin
rdata_d = {
data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1) + 1'b1)],
data_i[$clog2(dm::DataCount)'(((addr_i[DbgAddressBits-1:3] - DataBaseAddr[DbgAddressBits-1:3]) << 1))]
};
end
[ProgBufBaseAddr:ProgBufEndAddr]: begin
rdata_d = progbuf[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
ProgBufBaseAddr[DbgAddressBits-1:3])];
end
// two slots for abstract command
[AbstractCmdBaseAddr:AbstractCmdEndAddr]: begin
// return the correct address index
rdata_d = abstract_cmd[3'(addr_i[DbgAddressBits-1:3] -
AbstractCmdBaseAddr[DbgAddressBits-1:3])];
end
// harts are polling for flags here
[FlagsBaseAddr:FlagsEndAddr]: begin
// release the corresponding hart
if (({addr_i[DbgAddressBits-1:3], 3'b0} - FlagsBaseAddr[DbgAddressBits-1:0]) ==
(DbgAddressBits'(hartsel) & {{(DbgAddressBits-3){1'b1}}, 3'b0})) begin
rdata[DbgAddressBits'(hartsel) & DbgAddressBits'(3'b111)] = {6'b0, resume, go};
end
rdata_d = rdata;
end
default: ;
endcase
end
end
if (ndmreset_i) begin
// When harts are reset, they are neither halted nor resuming.
halted_d_aligned = '0;
resuming_d_aligned = '0;
end
data_o = data_bits;
end
always_comb begin : p_abstract_cmd_rom
// this abstract command is currently unsupported
unsupported_command = 1'b0;
// default memory
// if ac_ar.transfer is not set then we can take a shortcut to the program buffer
abstract_cmd[0][31:0] = dm::illegal();
// load debug module base address into a0, this is shared among all commands
abstract_cmd[0][63:32] = HasSndScratch ? dm::auipc(5'd10, '0) : dm::nop();
// clr lowest 12b -> DM base offset
abstract_cmd[1][31:0] = HasSndScratch ? dm::srli(5'd10, 5'd10, 6'd12) : dm::nop();
abstract_cmd[1][63:32] = HasSndScratch ? dm::slli(5'd10, 5'd10, 6'd12) : dm::nop();
abstract_cmd[2][31:0] = dm::nop();
abstract_cmd[2][63:32] = dm::nop();
abstract_cmd[3][31:0] = dm::nop();
abstract_cmd[3][63:32] = dm::nop();
abstract_cmd[4][31:0] = HasSndScratch ? dm::csrr(dm::CSR_DSCRATCH1, 5'd10) : dm::nop();
abstract_cmd[4][63:32] = dm::ebreak();
abstract_cmd[7:5] = '0;
// this depends on the command being executed
unique case (cmd_i.cmdtype)
// --------------------
// Access Register
// --------------------
dm::AccessRegister: begin
if (32'(ac_ar.aarsize) < MaxAar && ac_ar.transfer && ac_ar.write) begin
// store a0 in dscratch1
abstract_cmd[0][31:0] = HasSndScratch ? dm::csrw(dm::CSR_DSCRATCH1, 5'd10) : dm::nop();
// this range is reserved
if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
unsupported_command = 1'b1;
// A0 access needs to be handled separately, as we use A0 to load
// the DM address offset need to access DSCRATCH1 in this case
end else if (HasSndScratch && ac_ar.regno[12] && (!ac_ar.regno[5]) &&
(ac_ar.regno[4:0] == 5'd10)) begin
// store s0 in dscratch
abstract_cmd[2][31:0] = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
// load from data register
abstract_cmd[2][63:32] = dm::load(ac_ar.aarsize, 5'd8, LoadBaseAddr, dm::DataAddr);
// and store it in the corresponding CSR
abstract_cmd[3][31:0] = dm::csrw(dm::CSR_DSCRATCH1, 5'd8);
// restore s0 again from dscratch
abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
// GPR/FPR access
end else if (ac_ar.regno[12]) begin
// determine whether we want to access the floating point register or not
if (ac_ar.regno[5]) begin
abstract_cmd[2][31:0] =
dm::float_load(ac_ar.aarsize, ac_ar.regno[4:0], LoadBaseAddr, dm::DataAddr);
end else begin
abstract_cmd[2][31:0] =
dm::load(ac_ar.aarsize, ac_ar.regno[4:0], LoadBaseAddr, dm::DataAddr);
end
// CSR access
end else begin
// data register to CSR
// store s0 in dscratch
abstract_cmd[2][31:0] = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
// load from data register
abstract_cmd[2][63:32] = dm::load(ac_ar.aarsize, 5'd8, LoadBaseAddr, dm::DataAddr);
// and store it in the corresponding CSR
abstract_cmd[3][31:0] = dm::csrw(dm::csr_reg_t'(ac_ar.regno[11:0]), 5'd8);
// restore s0 again from dscratch
abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
end
end else if (32'(ac_ar.aarsize) < MaxAar && ac_ar.transfer && !ac_ar.write) begin
// store a0 in dscratch1
abstract_cmd[0][31:0] = HasSndScratch ?
dm::csrw(dm::CSR_DSCRATCH1, LoadBaseAddr) :
dm::nop();
// this range is reserved
if (ac_ar.regno[15:14] != '0) begin
abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
unsupported_command = 1'b1;
// A0 access needs to be handled separately, as we use A0 to load
// the DM address offset need to access DSCRATCH1 in this case
end else if (HasSndScratch && ac_ar.regno[12] && (!ac_ar.regno[5]) &&
(ac_ar.regno[4:0] == 5'd10)) begin
// store s0 in dscratch
abstract_cmd[2][31:0] = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
// read value from CSR into s0
abstract_cmd[2][63:32] = dm::csrr(dm::CSR_DSCRATCH1, 5'd8);
// and store s0 into data section
abstract_cmd[3][31:0] = dm::store(ac_ar.aarsize, 5'd8, LoadBaseAddr, dm::DataAddr);
// restore s0 again from dscratch
abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
// GPR/FPR access
end else if (ac_ar.regno[12]) begin
// determine whether we want to access the floating point register or not
if (ac_ar.regno[5]) begin
abstract_cmd[2][31:0] =
dm::float_store(ac_ar.aarsize, ac_ar.regno[4:0], LoadBaseAddr, dm::DataAddr);
end else begin
abstract_cmd[2][31:0] =
dm::store(ac_ar.aarsize, ac_ar.regno[4:0], LoadBaseAddr, dm::DataAddr);
end
// CSR access
end else begin
// CSR register to data
// store s0 in dscratch
abstract_cmd[2][31:0] = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
// read value from CSR into s0
abstract_cmd[2][63:32] = dm::csrr(dm::csr_reg_t'(ac_ar.regno[11:0]), 5'd8);
// and store s0 into data section
abstract_cmd[3][31:0] = dm::store(ac_ar.aarsize, 5'd8, LoadBaseAddr, dm::DataAddr);
// restore s0 again from dscratch
abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
end
end else if (32'(ac_ar.aarsize) >= MaxAar || ac_ar.aarpostincrement == 1'b1) begin
// this should happend when e.g. ac_ar.aarsize >= MaxAar
// Openocd will try to do an access with aarsize=64 bits
// first before falling back to 32 bits.
abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
unsupported_command = 1'b1;
end
// Check whether we need to execute the program buffer. When we
// get an unsupported command we really should abort instead of
// still trying to execute the program buffer, makes it easier
// for the debugger to recover
if (ac_ar.postexec && !unsupported_command) begin
// issue a nop, we will automatically run into the program buffer
abstract_cmd[4][63:32] = dm::nop();
end
end
// not supported at the moment
// dm::QuickAccess:;
// dm::AccessMemory:;
default: begin
abstract_cmd[0][31:0] = dm::ebreak();
unsupported_command = 1'b1;
end
endcase
end
logic [63:0] rom_addr;
assign rom_addr = 64'(addr_i);
// Depending on whether the debug module is located
// at the zero page we can instantiate a simplified version
// which only requires one scratch register per hart.
// For all other cases we need to set aside
// two registers per hart, hence we also need
// two scratch registers.
if (HasSndScratch) begin : gen_rom_snd_scratch
debug_rom i_debug_rom (
.clk_i,
.req_i,
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
end else begin : gen_rom_one_scratch
// It uses the zero register (`x0`) as the base
// for its loads. The zero register does not need to
// be saved.
debug_rom_one_scratch i_debug_rom (
.clk_i,
.req_i,
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
end
// ROM starts at the HaltAddress of the core e.g.: it immediately jumps to
// the ROM base address
assign fwd_rom_d = logic'(addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]);
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
fwd_rom_q <= 1'b0;
rdata_q <= '0;
state_q <= Idle;
word_enable32_q <= 1'b0;
end else begin
fwd_rom_q <= fwd_rom_d;
rdata_q <= rdata_d;
state_q <= state_d;
word_enable32_q <= addr_i[2];
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
halted_q <= 1'b0;
resuming_q <= 1'b0;
end else begin
halted_q <= SelectableHarts & halted_d;
resuming_q <= SelectableHarts & resuming_d;
end
end
endmodule : dm_mem
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: axi_riscv_debug_module.sv
* Author: Andreas Traber <[email protected]>
* Author: Florian Zaruba <[email protected]>
*
* Description: Clock domain crossings for JTAG to DMI very heavily based
* on previous work by Andreas Traber for the PULP project.
* This is mainly a wrapper around the existing CDCs.
*/
module dmi_cdc (
// JTAG side (master side)
input logic tck_i,
input logic trst_ni,
input dm::dmi_req_t jtag_dmi_req_i,
output logic jtag_dmi_ready_o,
input logic jtag_dmi_valid_i,
input logic jtag_dmi_cdc_clear_i, // Synchronous clear signal.
// Triggers reset sequencing
// accross CDC
output dm::dmi_resp_t jtag_dmi_resp_o,
output logic jtag_dmi_valid_o,
input logic jtag_dmi_ready_i,
// core side (slave side)
input logic clk_i,
input logic rst_ni,
output logic core_dmi_rst_no,
output dm::dmi_req_t core_dmi_req_o,
output logic core_dmi_valid_o,
input logic core_dmi_ready_i,
input dm::dmi_resp_t core_dmi_resp_i,
output logic core_dmi_ready_o,
input logic core_dmi_valid_i
);
logic core_clear_pending;
cdc_2phase_clearable #(.T(dm::dmi_req_t)) i_cdc_req (
.src_rst_ni ( trst_ni ),
.src_clear_i ( jtag_dmi_cdc_clear_i ),
.src_clk_i ( tck_i ),
.src_clear_pending_o(), // Not used
.src_data_i ( jtag_dmi_req_i ),
.src_valid_i ( jtag_dmi_valid_i ),
.src_ready_o ( jtag_dmi_ready_o ),
.dst_rst_ni ( rst_ni ),
.dst_clear_i ( 1'b0 ), // No functional reset from core side
// used (only async).
.dst_clear_pending_o( core_clear_pending ), // use the clear pending signal
// to synchronously clear the
// response FIFO in the dm_top
// csrs
.dst_clk_i ( clk_i ),
.dst_data_o ( core_dmi_req_o ),
.dst_valid_o ( core_dmi_valid_o ),
.dst_ready_i ( core_dmi_ready_i )
);
cdc_2phase_clearable #(.T(dm::dmi_resp_t)) i_cdc_resp (
.src_rst_ni ( rst_ni ),
.src_clear_i ( 1'b0 ), // No functional reset from core side
// used (only async ).
.src_clear_pending_o(), // Not used
.src_clk_i ( clk_i ),
.src_data_i ( core_dmi_resp_i ),
.src_valid_i ( core_dmi_valid_i ),
.src_ready_o ( core_dmi_ready_o ),
.dst_rst_ni ( trst_ni ),
.dst_clear_i ( jtag_dmi_cdc_clear_i ),
.dst_clear_pending_o(), //Not used
.dst_clk_i ( tck_i ),
.dst_data_o ( jtag_dmi_resp_o ),
.dst_valid_o ( jtag_dmi_valid_o ),
.dst_ready_i ( jtag_dmi_ready_i )
);
// We need to flush the DMI response FIFO in DM top using the core clock
// synchronous clear signal core_dmi_rst_no. We repurpose the clear
// pending signal in the core clock domain by generating a 1 cycle pulse from
// it.
logic core_clear_pending_q;
logic core_dmi_rst_nq;
logic clear_pending_rise_edge_detect;
assign clear_pending_rise_edge_detect = !core_clear_pending_q && core_clear_pending;
always_ff @(posedge clk_i, negedge rst_ni) begin
if (!rst_ni) begin
core_dmi_rst_nq <= 1'b1;
core_clear_pending_q <= 1'b0;
end else begin
core_dmi_rst_nq <= ~clear_pending_rise_edge_detect; // active-low!
core_clear_pending_q <= core_clear_pending;
end
end
assign core_dmi_rst_no = core_dmi_rst_nq;
endmodule : dmi_cdc
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dmi_jtag_tap.sv
* Author: Florian Zaruba <[email protected]>
* Date: 19.7.2018
*
* Description: JTAG TAP for DMI (according to debug spec 0.13)
*
*/
module dmi_jtag_tap #(
parameter int unsigned IrLength = 5,
// JTAG IDCODE Value
parameter logic [31:0] IdcodeValue = 32'h00000001
// xxxx version
// xxxxxxxxxxxxxxxx part number
// xxxxxxxxxxx manufacturer id
// 1 required by standard
) (
input logic tck_i, // JTAG test clock pad
input logic tms_i, // JTAG test mode select pad
input logic trst_ni, // JTAG test reset pad
input logic td_i, // JTAG test data input pad
output logic td_o, // JTAG test data output pad
output logic tdo_oe_o, // Data out output enable
input logic testmode_i,
// JTAG is interested in writing the DTM CSR register
output logic tck_o,
// Synchronous reset of the dmi module triggered by JTAG TAP
output logic dmi_clear_o,
output logic update_o,
output logic capture_o,
output logic shift_o,
output logic tdi_o,
output logic dtmcs_select_o,
input logic dtmcs_tdo_i,
// we want to access DMI register
output logic dmi_select_o,
input logic dmi_tdo_i
);
typedef enum logic [3:0] {
TestLogicReset, RunTestIdle, SelectDrScan,
CaptureDr, ShiftDr, Exit1Dr, PauseDr, Exit2Dr,
UpdateDr, SelectIrScan, CaptureIr, ShiftIr,
Exit1Ir, PauseIr, Exit2Ir, UpdateIr
} tap_state_e;
tap_state_e tap_state_q, tap_state_d;
logic update_dr, shift_dr, capture_dr;
typedef enum logic [IrLength-1:0] {
BYPASS0 = 'h0,
IDCODE = 'h1,
DTMCSR = 'h10,
DMIACCESS = 'h11,
BYPASS1 = 'h1f
} ir_reg_e;
// ----------------
// IR logic
// ----------------
// shift register
logic [IrLength-1:0] jtag_ir_shift_d, jtag_ir_shift_q;
// IR register -> this gets captured from shift register upon update_ir
ir_reg_e jtag_ir_d, jtag_ir_q;
logic capture_ir, shift_ir, update_ir, test_logic_reset; // pause_ir
always_comb begin : p_jtag
jtag_ir_shift_d = jtag_ir_shift_q;
jtag_ir_d = jtag_ir_q;
// IR shift register
if (shift_ir) begin
jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
end
// capture IR register
if (capture_ir) begin
jtag_ir_shift_d = IrLength'(4'b0101);
end
// update IR register
if (update_ir) begin
jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
end
if (test_logic_reset) begin
// Bring all TAP state to the initial value.
jtag_ir_shift_d = '0;
jtag_ir_d = IDCODE;
end
end
always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
if (!trst_ni) begin
jtag_ir_shift_q <= '0;
jtag_ir_q <= IDCODE;
end else begin
jtag_ir_shift_q <= jtag_ir_shift_d;
jtag_ir_q <= jtag_ir_d;
end
end
// ----------------
// TAP DR Regs
// ----------------
// - Bypass
// - IDCODE
// - DTM CS
logic [31:0] idcode_d, idcode_q;
logic idcode_select;
logic bypass_select;
logic bypass_d, bypass_q; // this is a 1-bit register
always_comb begin
idcode_d = idcode_q;
bypass_d = bypass_q;
if (capture_dr) begin
if (idcode_select) idcode_d = IdcodeValue;
if (bypass_select) bypass_d = 1'b0;
end
if (shift_dr) begin
if (idcode_select) idcode_d = {td_i, 31'(idcode_q >> 1)};
if (bypass_select) bypass_d = td_i;
end
if (test_logic_reset) begin
// Bring all TAP state to the initial value.
idcode_d = IdcodeValue;
bypass_d = 1'b0;
end
end
// ----------------
// Data reg select
// ----------------
always_comb begin : p_data_reg_sel
dmi_select_o = 1'b0;
dtmcs_select_o = 1'b0;
idcode_select = 1'b0;
bypass_select = 1'b0;
unique case (jtag_ir_q)
BYPASS0: bypass_select = 1'b1;
IDCODE: idcode_select = 1'b1;
DTMCSR: dtmcs_select_o = 1'b1;
DMIACCESS: dmi_select_o = 1'b1;
BYPASS1: bypass_select = 1'b1;
default: bypass_select = 1'b1;
endcase
end
// ----------------
// Output select
// ----------------
logic tdo_mux;
always_comb begin : p_out_sel
// we are shifting out the IR register
if (shift_ir) begin
tdo_mux = jtag_ir_shift_q[0];
// here we are shifting the DR register
end else begin
unique case (jtag_ir_q)
IDCODE: tdo_mux = idcode_q[0]; // Reading ID code
DTMCSR: tdo_mux = dtmcs_tdo_i; // Read from DTMCS TDO
DMIACCESS: tdo_mux = dmi_tdo_i; // Read from DMI TDO
default: tdo_mux = bypass_q; // BYPASS instruction
endcase
end
end
// ----------------
// DFT
// ----------------
logic tck_n, tck_ni;
tc_clk_inverter i_tck_inv (
.clk_i ( tck_i ),
.clk_o ( tck_ni )
);
tc_clk_mux2 i_dft_tck_mux (
.clk0_i ( tck_ni ),
.clk1_i ( tck_i ), // bypass the inverted clock for testing
.clk_sel_i ( testmode_i ),
.clk_o ( tck_n )
);
// TDO changes state at negative edge of TCK
always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
if (!trst_ni) begin
td_o <= 1'b0;
tdo_oe_o <= 1'b0;
end else begin
td_o <= tdo_mux;
tdo_oe_o <= (shift_ir | shift_dr);
end
end
// ----------------
// TAP FSM
// ----------------
// Determination of next state; purely combinatorial
always_comb begin : p_tap_fsm
test_logic_reset = 1'b0;
capture_dr = 1'b0;
shift_dr = 1'b0;
update_dr = 1'b0;
capture_ir = 1'b0;
shift_ir = 1'b0;
// pause_ir = 1'b0; unused
update_ir = 1'b0;
unique case (tap_state_q)
TestLogicReset: begin
tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
test_logic_reset = 1'b1;
end
RunTestIdle: begin
tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
end
// DR Path
SelectDrScan: begin
tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
end
CaptureDr: begin
capture_dr = 1'b1;
tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
end
ShiftDr: begin
shift_dr = 1'b1;
tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
end
Exit1Dr: begin
tap_state_d = (tms_i) ? UpdateDr : PauseDr;
end
PauseDr: begin
tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
end
Exit2Dr: begin
tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
end
UpdateDr: begin
update_dr = 1'b1;
tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
end
// IR Path
SelectIrScan: begin
tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
end
// In this controller state, the shift register bank in the
// Instruction Register parallel loads a pattern of fixed values on
// the rising edge of TCK. The last two significant bits must always
// be "01".
CaptureIr: begin
capture_ir = 1'b1;
tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
end
// In this controller state, the instruction register gets connected
// between TDI and TDO, and the captured pattern gets shifted on
// each rising edge of TCK. The instruction available on the TDI
// pin is also shifted in to the instruction register.
ShiftIr: begin
shift_ir = 1'b1;
tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
end
Exit1Ir: begin
tap_state_d = (tms_i) ? UpdateIr : PauseIr;
end
PauseIr: begin
// pause_ir = 1'b1; // unused
tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
end
Exit2Ir: begin
tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
end
// In this controller state, the instruction in the instruction
// shift register is latched to the latch bank of the Instruction
// Register on every falling edge of TCK. This instruction becomes
// the current instruction once it is latched.
UpdateIr: begin
update_ir = 1'b1;
tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
end
default: ; // can't actually happen since case is full
endcase
end
always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
if (!trst_ni) begin
tap_state_q <= RunTestIdle;
idcode_q <= IdcodeValue;
bypass_q <= 1'b0;
end else begin
tap_state_q <= tap_state_d;
idcode_q <= idcode_d;
bypass_q <= bypass_d;
end
end
// Pass through JTAG signals to debug custom DR logic.
// In case of a single TAP those are just feed-through.
assign tck_o = tck_i;
assign tdi_o = td_i;
assign update_o = update_dr;
assign shift_o = shift_dr;
assign capture_o = capture_dr;
assign dmi_clear_o = test_logic_reset;
endmodule : dmi_jtag_tap
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_sba.sv
* Author: Florian Zaruba <[email protected]>
* Date: 1.8.2018
*
* Description: System Bus Access Module
*
*/
module dm_sba #(
parameter int unsigned BusWidth = 32,
parameter bit ReadByteEnable = 1
) (
input logic clk_i, // Clock
input logic rst_ni,
input logic dmactive_i, // synchronous reset active low
output logic master_req_o,
output logic [BusWidth-1:0] master_add_o,
output logic master_we_o,
output logic [BusWidth-1:0] master_wdata_o,
output logic [BusWidth/8-1:0] master_be_o,
input logic master_gnt_i,
input logic master_r_valid_i,
input logic master_r_err_i,
input logic master_r_other_err_i, // *other_err_i has priority over *err_i
input logic [BusWidth-1:0] master_r_rdata_i,
input logic [BusWidth-1:0] sbaddress_i,
input logic sbaddress_write_valid_i,
// control signals in
input logic sbreadonaddr_i,
output logic [BusWidth-1:0] sbaddress_o,
input logic sbautoincrement_i,
input logic [2:0] sbaccess_i,
// data in
input logic sbreadondata_i,
input logic [BusWidth-1:0] sbdata_i,
input logic sbdata_read_valid_i,
input logic sbdata_write_valid_i,
// read data out
output logic [BusWidth-1:0] sbdata_o,
output logic sbdata_valid_o,
// control signals
output logic sbbusy_o,
output logic sberror_valid_o, // bus error occurred
output logic [2:0] sberror_o // bus error occurred
);
localparam int BeIdxWidth = $clog2(BusWidth/8);
dm::sba_state_e state_d, state_q;
logic [BusWidth-1:0] address;
logic req;
logic gnt;
logic we;
logic [BusWidth/8-1:0] be;
logic [BusWidth/8-1:0] be_mask;
logic [BeIdxWidth-1:0] be_idx;
assign sbbusy_o = logic'(state_q != dm::Idle);
always_comb begin : p_be_mask
be_mask = '0;
// generate byte enable mask
unique case (sbaccess_i)
3'b000: begin
be_mask[be_idx] = '1;
end
3'b001: begin
be_mask[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1;
end
3'b010: begin
if (BusWidth == 32'd64) be_mask[int'({be_idx[$high(be_idx)], 2'h0}) +: 4] = '1;
else be_mask = '1;
end
3'b011: be_mask = '1;
default: ;
endcase
end
logic [BusWidth-1:0] sbaccess_mask;
assign sbaccess_mask = {BusWidth{1'b1}} << sbaccess_i;
logic addr_incr_en;
logic [BusWidth-1:0] addr_incr;
assign addr_incr = (addr_incr_en) ? (BusWidth'(1'b1) << sbaccess_i) : '0;
assign sbaddress_o = sbaddress_i + addr_incr;
always_comb begin : p_fsm
req = 1'b0;
address = sbaddress_i;
we = 1'b0;
be = '0;
be_idx = sbaddress_i[BeIdxWidth-1:0];
sberror_o = '0;
sberror_valid_o = 1'b0;
addr_incr_en = 1'b0;
state_d = state_q;
unique case (state_q)
dm::Idle: begin
// debugger requested a read
if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = dm::Read;
// debugger requested a write
if (sbdata_write_valid_i) state_d = dm::Write;
// perform another read
if (sbdata_read_valid_i && sbreadondata_i) state_d = dm::Read;
end
dm::Read: begin
req = 1'b1;
if (ReadByteEnable) be = be_mask;
if (gnt) state_d = dm::WaitRead;
end
dm::Write: begin
req = 1'b1;
we = 1'b1;
be = be_mask;
if (gnt) state_d = dm::WaitWrite;
end
dm::WaitRead: begin
if (sbdata_valid_o) begin
state_d = dm::Idle;
// auto-increment address
addr_incr_en = sbautoincrement_i;
// check whether an "other" error has been encountered.
if (master_r_other_err_i) begin
sberror_valid_o = 1'b1;
sberror_o = 3'd7;
// check whether there was a bus error (== bad address).
end else if (master_r_err_i) begin
sberror_valid_o = 1'b1;
sberror_o = 3'd2;
end
end
end
dm::WaitWrite: begin
if (sbdata_valid_o) begin
state_d = dm::Idle;
// auto-increment address
addr_incr_en = sbautoincrement_i;
// check whether an "other" error has been encountered.
if (master_r_other_err_i) begin
sberror_valid_o = 1'b1;
sberror_o = 3'd7;
// check whether there was a bus error (== bad address).
end else if (master_r_err_i) begin
sberror_valid_o = 1'b1;
sberror_o = 3'd2;
end
end
end
default: state_d = dm::Idle; // catch parasitic state
endcase
// handle error case
if (32'(sbaccess_i) > BeIdxWidth && state_q != dm::Idle) begin
req = 1'b0;
state_d = dm::Idle;
sberror_valid_o = 1'b1;
sberror_o = 3'd4; // unsupported size was requested
end
//if sbaccess_i lsbs of address are not 0 - report misalignment error
if (|(sbaddress_i & ~sbaccess_mask) && state_q != dm::Idle) begin
req = 1'b0;
state_d = dm::Idle;
sberror_valid_o = 1'b1;
sberror_o = 3'd3; // alignment error
end
// further error handling should go here ...
end
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
state_q <= dm::Idle;
end else begin
state_q <= state_d;
end
end
logic [BeIdxWidth-1:0] be_idx_masked;
assign be_idx_masked = be_idx & BeIdxWidth'(sbaccess_mask);
assign master_req_o = req;
assign master_add_o = address[BusWidth-1:0];
assign master_we_o = we;
assign master_wdata_o = sbdata_i[BusWidth-1:0] << (8 * be_idx_masked);
assign master_be_o = be[BusWidth/8-1:0];
assign gnt = master_gnt_i;
assign sbdata_valid_o = master_r_valid_i;
assign sbdata_o = master_r_rdata_i[BusWidth-1:0] >> (8 * be_idx_masked);
endmodule : dm_sba
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dm_top.sv
* Author: Florian Zaruba <[email protected]>
* Date: 30.6.2018
*
* Description: Top-level of debug module (DM). This is an AXI-Slave.
* DTM protocol is equal to SiFives debug protocol to leverage
* SW infrastructure re-use. As of version 0.13
*/
module dm_top #(
parameter int unsigned NrHarts = 1,
parameter int unsigned BusWidth = 32,
parameter int unsigned DmBaseAddress = 'h1000, // default to non-zero page
// Bitmask to select physically available harts for systems
// that don't use hart numbers in a contiguous fashion.
parameter logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}},
// toggle new behavior to drive master_be_o during a read
parameter bit ReadByteEnable = 1
) (
input logic clk_i, // clock
// asynchronous reset active low, connect PoR here, not the system reset
input logic rst_ni,
input logic testmode_i,
output logic ndmreset_o, // non-debug module reset
output logic dmactive_o, // debug module is active
output logic [NrHarts-1:0] debug_req_o, // async debug request
// communicate whether the hart is unavailable (e.g.: power down)
input logic [NrHarts-1:0] unavailable_i,
input dm::hartinfo_t [NrHarts-1:0] hartinfo_i,
input logic slave_req_i,
input logic slave_we_i,
input logic [BusWidth-1:0] slave_addr_i,
input logic [BusWidth/8-1:0] slave_be_i,
input logic [BusWidth-1:0] slave_wdata_i,
output logic [BusWidth-1:0] slave_rdata_o,
output logic master_req_o,
output logic [BusWidth-1:0] master_add_o,
output logic master_we_o,
output logic [BusWidth-1:0] master_wdata_o,
output logic [BusWidth/8-1:0] master_be_o,
input logic master_gnt_i,
input logic master_r_valid_i,
input logic master_r_err_i,
input logic master_r_other_err_i, // *other_err_i has priority over *err_i
input logic [BusWidth-1:0] master_r_rdata_i,
// Connection to DTM - compatible to RocketChip Debug Module
input logic dmi_rst_ni, // Synchronous clear request from
// the DTM to clear the DMI response
// FIFO.
input logic dmi_req_valid_i,
output logic dmi_req_ready_o,
input dm::dmi_req_t dmi_req_i,
output logic dmi_resp_valid_o,
input logic dmi_resp_ready_i,
output dm::dmi_resp_t dmi_resp_o
);
// Debug CSRs
logic [NrHarts-1:0] halted;
// logic [NrHarts-1:0] running;
logic [NrHarts-1:0] resumeack;
logic [NrHarts-1:0] haltreq;
logic [NrHarts-1:0] resumereq;
logic clear_resumeack;
logic cmd_valid;
dm::command_t cmd;
logic cmderror_valid;
dm::cmderr_e cmderror;
logic cmdbusy;
logic [dm::ProgBufSize-1:0][31:0] progbuf;
logic [dm::DataCount-1:0][31:0] data_csrs_mem;
logic [dm::DataCount-1:0][31:0] data_mem_csrs;
logic data_valid;
logic ndmreset;
logic [19:0] hartsel;
// System Bus Access Module
logic [BusWidth-1:0] sbaddress_csrs_sba;
logic [BusWidth-1:0] sbaddress_sba_csrs;
logic sbaddress_write_valid;
logic sbreadonaddr;
logic sbautoincrement;
logic [2:0] sbaccess;
logic sbreadondata;
logic [BusWidth-1:0] sbdata_write;
logic sbdata_read_valid;
logic sbdata_write_valid;
logic [BusWidth-1:0] sbdata_read;
logic sbdata_valid;
logic sbbusy;
logic sberror_valid;
logic [2:0] sberror;
assign ndmreset_o = ndmreset;
dm_csrs #(
.NrHarts(NrHarts),
.BusWidth(BusWidth),
.SelectableHarts(SelectableHarts)
) i_dm_csrs (
.clk_i,
.rst_ni,
.testmode_i,
.dmi_rst_ni,
.dmi_req_valid_i,
.dmi_req_ready_o,
.dmi_req_i,
.dmi_resp_valid_o,
.dmi_resp_ready_i,
.dmi_resp_o,
.ndmreset_o ( ndmreset ),
.dmactive_o,
.hartsel_o ( hartsel ),
.hartinfo_i,
.halted_i ( halted ),
.unavailable_i,
.resumeack_i ( resumeack ),
.haltreq_o ( haltreq ),
.resumereq_o ( resumereq ),
.clear_resumeack_o ( clear_resumeack ),
.cmd_valid_o ( cmd_valid ),
.cmd_o ( cmd ),
.cmderror_valid_i ( cmderror_valid ),
.cmderror_i ( cmderror ),
.cmdbusy_i ( cmdbusy ),
.progbuf_o ( progbuf ),
.data_i ( data_mem_csrs ),
.data_valid_i ( data_valid ),
.data_o ( data_csrs_mem ),
.sbaddress_o ( sbaddress_csrs_sba ),
.sbaddress_i ( sbaddress_sba_csrs ),
.sbaddress_write_valid_o ( sbaddress_write_valid ),
.sbreadonaddr_o ( sbreadonaddr ),
.sbautoincrement_o ( sbautoincrement ),
.sbaccess_o ( sbaccess ),
.sbreadondata_o ( sbreadondata ),
.sbdata_o ( sbdata_write ),
.sbdata_read_valid_o ( sbdata_read_valid ),
.sbdata_write_valid_o ( sbdata_write_valid ),
.sbdata_i ( sbdata_read ),
.sbdata_valid_i ( sbdata_valid ),
.sbbusy_i ( sbbusy ),
.sberror_valid_i ( sberror_valid ),
.sberror_i ( sberror )
);
dm_sba #(
.BusWidth(BusWidth),
.ReadByteEnable(ReadByteEnable)
) i_dm_sba (
.clk_i,
.rst_ni,
.dmactive_i ( dmactive_o ),
.master_req_o,
.master_add_o,
.master_we_o,
.master_wdata_o,
.master_be_o,
.master_gnt_i,
.master_r_valid_i,
.master_r_err_i,
.master_r_other_err_i,
.master_r_rdata_i,
.sbaddress_i ( sbaddress_csrs_sba ),
.sbaddress_o ( sbaddress_sba_csrs ),
.sbaddress_write_valid_i ( sbaddress_write_valid ),
.sbreadonaddr_i ( sbreadonaddr ),
.sbautoincrement_i ( sbautoincrement ),
.sbaccess_i ( sbaccess ),
.sbreadondata_i ( sbreadondata ),
.sbdata_i ( sbdata_write ),
.sbdata_read_valid_i ( sbdata_read_valid ),
.sbdata_write_valid_i ( sbdata_write_valid ),
.sbdata_o ( sbdata_read ),
.sbdata_valid_o ( sbdata_valid ),
.sbbusy_o ( sbbusy ),
.sberror_valid_o ( sberror_valid ),
.sberror_o ( sberror )
);
dm_mem #(
.NrHarts(NrHarts),
.BusWidth(BusWidth),
.SelectableHarts(SelectableHarts),
.DmBaseAddress(DmBaseAddress)
) i_dm_mem (
.clk_i,
.rst_ni,
.debug_req_o,
.ndmreset_i ( ndmreset ),
.hartsel_i ( hartsel ),
.haltreq_i ( haltreq ),
.resumereq_i ( resumereq ),
.clear_resumeack_i ( clear_resumeack ),
.halted_o ( halted ),
.resuming_o ( resumeack ),
.cmd_valid_i ( cmd_valid ),
.cmd_i ( cmd ),
.cmderror_valid_o ( cmderror_valid ),
.cmderror_o ( cmderror ),
.cmdbusy_o ( cmdbusy ),
.progbuf_i ( progbuf ),
.data_i ( data_csrs_mem ),
.data_o ( data_mem_csrs ),
.data_valid_o ( data_valid ),
.req_i ( slave_req_i ),
.we_i ( slave_we_i ),
.addr_i ( slave_addr_i ),
.wdata_i ( slave_wdata_i ),
.be_i ( slave_be_i ),
.rdata_o ( slave_rdata_o )
);
endmodule : dm_top
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: axi_riscv_debug_module.sv
* Author: Florian Zaruba <[email protected]>
* Date: 19.7.2018
*
* Description: JTAG DMI (debug module interface)
*
*/
module dmi_jtag #(
parameter logic [31:0] IdcodeValue = 32'h00000001
) (
input logic clk_i, // DMI Clock
input logic rst_ni, // Asynchronous reset active low
input logic testmode_i,
// active-low glitch free reset signal. Is asserted for one dmi clock cycle
// (clk_i) whenever the dmi_jtag is reset (POR or functional reset).
output logic dmi_rst_no,
output dm::dmi_req_t dmi_req_o,
output logic dmi_req_valid_o,
input logic dmi_req_ready_i,
input dm::dmi_resp_t dmi_resp_i,
output logic dmi_resp_ready_o,
input logic dmi_resp_valid_i,
input logic tck_i, // JTAG test clock pad
input logic tms_i, // JTAG test mode select pad
input logic trst_ni, // JTAG test reset pad
input logic td_i, // JTAG test data input pad
output logic td_o, // JTAG test data output pad
output logic tdo_oe_o // Data out output enable
);
typedef enum logic [1:0] {
DMINoError = 2'h0, DMIReservedError = 2'h1,
DMIOPFailed = 2'h2, DMIBusy = 2'h3
} dmi_error_e;
dmi_error_e error_d, error_q;
logic tck;
logic jtag_dmi_clear; // Synchronous reset of DMI triggered by TestLogicReset in
// jtag TAP
logic dmi_clear; // Functional (warm) reset of the entire DMI
logic update;
logic capture;
logic shift;
logic tdi;
logic dtmcs_select;
assign dmi_clear = jtag_dmi_clear || (dtmcs_select && update && dtmcs_q.dmihardreset);
// -------------------------------
// Debug Module Control and Status
// -------------------------------
dm::dtmcs_t dtmcs_d, dtmcs_q;
always_comb begin
dtmcs_d = dtmcs_q;
if (capture) begin
if (dtmcs_select) begin
dtmcs_d = '{
zero1 : '0,
dmihardreset : 1'b0,
dmireset : 1'b0,
zero0 : '0,
idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast
abits : 6'd7, // The size of address in dmi
version : 4'd1 // Version described in spec version 0.13 (and later?)
};
end
end
if (shift) begin
if (dtmcs_select) dtmcs_d = {tdi, 31'(dtmcs_q >> 1)};
end
end
always_ff @(posedge tck or negedge trst_ni) begin
if (!trst_ni) begin
dtmcs_q <= '0;
end else begin
dtmcs_q <= dtmcs_d;
end
end
// ----------------------------
// DMI (Debug Module Interface)
// ----------------------------
logic dmi_select;
logic dmi_tdo;
dm::dmi_req_t dmi_req;
logic dmi_req_ready;
logic dmi_req_valid;
dm::dmi_resp_t dmi_resp;
logic dmi_resp_valid;
logic dmi_resp_ready;
typedef struct packed {
logic [6:0] address;
logic [31:0] data;
logic [1:0] op;
} dmi_t;
typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e;
state_e state_d, state_q;
logic [$bits(dmi_t)-1:0] dr_d, dr_q;
logic [6:0] address_d, address_q;
logic [31:0] data_d, data_q;
dmi_t dmi;
assign dmi = dmi_t'(dr_q);
assign dmi_req.addr = address_q;
assign dmi_req.data = data_q;
assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
// We will always be ready to accept the data we requested.
assign dmi_resp_ready = 1'b1;
logic error_dmi_busy;
logic error_dmi_op_failed;
always_comb begin : p_fsm
error_dmi_busy = 1'b0;
error_dmi_op_failed = 1'b0;
// default assignments
state_d = state_q;
address_d = address_q;
data_d = data_q;
error_d = error_q;
dmi_req_valid = 1'b0;
if (dmi_clear) begin
state_d = Idle;
data_d = '0;
error_d = DMINoError;
address_d = '0;
end else begin
unique case (state_q)
Idle: begin
// make sure that no error is sticky
if (dmi_select && update && (error_q == DMINoError)) begin
// save address and value
address_d = dmi.address;
data_d = dmi.data;
if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
state_d = Read;
end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
state_d = Write;
end
// else this is a nop and we can stay here
end
end
Read: begin
dmi_req_valid = 1'b1;
if (dmi_req_ready) begin
state_d = WaitReadValid;
end
end
WaitReadValid: begin
// load data into register and shift out
if (dmi_resp_valid) begin
unique case (dmi_resp.resp)
dm::DTM_SUCCESS: begin
data_d = dmi_resp.data;
end
dm::DTM_ERR: begin
data_d = 32'hDEAD_BEEF;
error_dmi_op_failed = 1'b1;
end
dm::DTM_BUSY: begin
data_d = 32'hB051_B051;
error_dmi_busy = 1'b1;
end
default: begin
data_d = 32'hBAAD_C0DE;
end
endcase
state_d = Idle;
end
end
Write: begin
dmi_req_valid = 1'b1;
// request sent, wait for response before going back to idle
if (dmi_req_ready) begin
state_d = WaitWriteValid;
end
end
WaitWriteValid: begin
// got a valid answer go back to idle
if (dmi_resp_valid) begin
unique case (dmi_resp.resp)
dm::DTM_ERR: error_dmi_op_failed = 1'b1;
dm::DTM_BUSY: error_dmi_busy = 1'b1;
default: ;
endcase
state_d = Idle;
end
end
default: begin
// just wait for idle here
if (dmi_resp_valid) begin
state_d = Idle;
end
end
endcase
// update means we got another request but we didn't finish
// the one in progress, this state is sticky
if (update && state_q != Idle) begin
error_dmi_busy = 1'b1;
end
// if capture goes high while we are in the read state
// or in the corresponding wait state we are not giving back a valid word
// -> throw an error
if (capture && state_q inside {Read, WaitReadValid}) begin
error_dmi_busy = 1'b1;
end
if (error_dmi_busy && error_q == DMINoError) begin
error_d = DMIBusy;
end
if (error_dmi_op_failed && error_q == DMINoError) begin
error_d = DMIOPFailed;
end
// clear sticky error flag
if (update && dtmcs_q.dmireset && dtmcs_select) begin
error_d = DMINoError;
end
end
end
// shift register
assign dmi_tdo = dr_q[0];
always_comb begin : p_shift
dr_d = dr_q;
if (dmi_clear) begin
dr_d = '0;
end else begin
if (capture) begin
if (dmi_select) begin
if (error_q == DMINoError && !error_dmi_busy) begin
dr_d = {address_q, data_q, DMINoError};
// DMI was busy, report an error
end else if (error_q == DMIBusy || error_dmi_busy) begin
dr_d = {address_q, data_q, DMIBusy};
end
end
end
if (shift) begin
if (dmi_select) begin
dr_d = {tdi, dr_q[$bits(dr_q)-1:1]};
end
end
end
end
always_ff @(posedge tck or negedge trst_ni) begin
if (!trst_ni) begin
dr_q <= '0;
state_q <= Idle;
address_q <= '0;
data_q <= '0;
error_q <= DMINoError;
end else begin
dr_q <= dr_d;
state_q <= state_d;
address_q <= address_d;
data_q <= data_d;
error_q <= error_d;
end
end
// ---------
// TAP
// ---------
dmi_jtag_tap #(
.IrLength (5),
.IdcodeValue(IdcodeValue)
) i_dmi_jtag_tap (
.tck_i,
.tms_i,
.trst_ni,
.td_i,
.td_o,
.tdo_oe_o,
.testmode_i,
.tck_o ( tck ),
.dmi_clear_o ( jtag_dmi_clear ),
.update_o ( update ),
.capture_o ( capture ),
.shift_o ( shift ),
.tdi_o ( tdi ),
.dtmcs_select_o ( dtmcs_select ),
.dtmcs_tdo_i ( dtmcs_q[0] ),
.dmi_select_o ( dmi_select ),
.dmi_tdo_i ( dmi_tdo )
);
// ---------
// CDC
// ---------
dmi_cdc i_dmi_cdc (
// JTAG side (master side)
.tck_i ( tck ),
.trst_ni ( trst_ni ),
.jtag_dmi_cdc_clear_i ( dmi_clear ),
.jtag_dmi_req_i ( dmi_req ),
.jtag_dmi_ready_o ( dmi_req_ready ),
.jtag_dmi_valid_i ( dmi_req_valid ),
.jtag_dmi_resp_o ( dmi_resp ),
.jtag_dmi_valid_o ( dmi_resp_valid ),
.jtag_dmi_ready_i ( dmi_resp_ready ),
// core side
.clk_i,
.rst_ni,
.core_dmi_rst_no ( dmi_rst_no ),
.core_dmi_req_o ( dmi_req_o ),
.core_dmi_valid_o ( dmi_req_valid_o ),
.core_dmi_ready_i ( dmi_req_ready_i ),
.core_dmi_resp_i ( dmi_resp_i ),
.core_dmi_ready_o ( dmi_resp_ready_o ),
.core_dmi_valid_i ( dmi_resp_valid_i )
);
endmodule : dmi_jtag
// Copyright 2021 Thales DIS design services SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Jean-Roch COULON ([email protected])
package cva6_config_pkg;
localparam CVA6ConfigXlen = 64;
localparam CVA6ConfigFpuEn = 1;
localparam CVA6ConfigF16En = 0;
localparam CVA6ConfigF16AltEn = 0;
localparam CVA6ConfigF8En = 0;
localparam CVA6ConfigFVecEn = 0;
localparam CVA6ConfigCvxifEn = 1;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigFetchUserEn = 0;
localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen;
localparam CVA6ConfigDataUserEn = 0;
localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen;
localparam CVA6ConfigRenameEn = 0;
endpackage
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: riscv_pkg.sv
* Author: Florian Zaruba <[email protected]>
* Date: 30.6.2017
*
* Description: Common RISC-V definitions.
*/
package riscv;
// ----------------------
// Import cva6 config from cva6_config_pkg
// ----------------------
localparam XLEN = cva6_config_pkg::CVA6ConfigXlen;
localparam FPU_EN = cva6_config_pkg::CVA6ConfigFpuEn;
// ----------------------
// Data and Address length
// ----------------------
typedef enum logic [3:0] {
ModeOff = 0,
ModeSv32 = 1,
ModeSv39 = 8,
ModeSv48 = 9,
ModeSv57 = 10,
ModeSv64 = 11
} vm_mode_t;
// Warning: When using STD_CACHE, configuration must be PLEN=56 and VLEN=64
// Warning: VLEN must be superior or equal to PLEN
localparam VLEN = (XLEN == 32) ? 32 : 64; // virtual address length
localparam PLEN = (XLEN == 32) ? 34 : 56; // physical address length
localparam IS_XLEN32 = (XLEN == 32) ? 1'b1 : 1'b0;
localparam IS_XLEN64 = (XLEN == 32) ? 1'b0 : 1'b1;
localparam ModeW = (XLEN == 32) ? 1 : 4;
localparam ASIDW = (XLEN == 32) ? 9 : 16;
localparam PPNW = (XLEN == 32) ? 22 : 44;
localparam vm_mode_t MODE_SV = (XLEN == 32) ? ModeSv32 : ModeSv39;
localparam SV = (MODE_SV == ModeSv32) ? 32 : 39;
localparam VPN2 = (VLEN-31 < 8) ? VLEN-31 : 8;
localparam XLEN_ALIGN_BYTES = $clog2(XLEN/8);
typedef logic [XLEN-1:0] xlen_t;
// --------------------
// Privilege Spec
// --------------------
typedef enum logic[1:0] {
PRIV_LVL_M = 2'b11,
PRIV_LVL_S = 2'b01,
PRIV_LVL_U = 2'b00
} priv_lvl_t;
// type which holds xlen
typedef enum logic [1:0] {
XLEN_32 = 2'b01,
XLEN_64 = 2'b10,
XLEN_128 = 2'b11
} xlen_e;
typedef enum logic [1:0] {
Off = 2'b00,
Initial = 2'b01,
Clean = 2'b10,
Dirty = 2'b11
} xs_t;
typedef struct packed {
logic sd; // signal dirty state - read-only
logic [62:36] wpri4; // writes preserved reads ignored
xlen_e sxl; // variable supervisor mode xlen - hardwired to zero
xlen_e uxl; // variable user mode xlen - hardwired to zero
logic [8:0] wpri3; // writes preserved reads ignored
logic tsr; // trap sret
logic tw; // time wait
logic tvm; // trap virtual memory
logic mxr; // make executable readable
logic sum; // permit supervisor user memory access
logic mprv; // modify privilege - privilege level for ld/st
xs_t xs; // extension register - hardwired to zero
xs_t fs; // floating point extension register
priv_lvl_t mpp; // holds the previous privilege mode up to machine
logic [1:0] wpri2; // writes preserved reads ignored
logic spp; // holds the previous privilege mode up to supervisor
logic mpie; // machine interrupts enable bit active prior to trap
logic wpri1; // writes preserved reads ignored
logic spie; // supervisor interrupts enable bit active prior to trap
logic upie; // user interrupts enable bit active prior to trap - hardwired to zero
logic mie; // machine interrupts enable
logic wpri0; // writes preserved reads ignored
logic sie; // supervisor interrupts enable
logic uie; // user interrupts enable - hardwired to zero
} status_rv_t;
typedef struct packed {
logic [ModeW-1:0] mode;
logic [ASIDW-1:0] asid;
logic [PPNW-1:0] ppn;
} satp_t;
// --------------------
// Instruction Types
// --------------------
typedef struct packed {
logic [31:25] funct7;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:12] funct3;
logic [11:7] rd;
logic [6:0] opcode;
} rtype_t;
typedef struct packed {
logic [31:27] rs3;
logic [26:25] funct2;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:12] funct3;
logic [11:7] rd;
logic [6:0] opcode;
} r4type_t;
typedef struct packed {
logic [31:27] funct5;
logic [26:25] fmt;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:12] rm;
logic [11:7] rd;
logic [6:0] opcode;
} rftype_t; // floating-point
typedef struct packed {
logic [31:30] funct2;
logic [29:25] vecfltop;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:14] repl;
logic [13:12] vfmt;
logic [11:7] rd;
logic [6:0] opcode;
} rvftype_t; // vectorial floating-point
typedef struct packed {
logic [31:20] imm;
logic [19:15] rs1;
logic [14:12] funct3;
logic [11:7] rd;
logic [6:0] opcode;
} itype_t;
typedef struct packed {
logic [31:25] imm;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:12] funct3;
logic [11:7] imm0;
logic [6:0] opcode;
} stype_t;
typedef struct packed {
logic [31:12] imm;
logic [11:7] rd;
logic [6:0] opcode;
} utype_t;
// atomic instructions
typedef struct packed {
logic [31:27] funct5;
logic aq;
logic rl;
logic [24:20] rs2;
logic [19:15] rs1;
logic [14:12] funct3;
logic [11:7] rd;
logic [6:0] opcode;
} atype_t;
typedef union packed {
logic [31:0] instr;
rtype_t rtype;
r4type_t r4type;
rftype_t rftype;
rvftype_t rvftype;
itype_t itype;
stype_t stype;
utype_t utype;
atype_t atype;
} instruction_t;
// --------------------
// Opcodes
// --------------------
// RV32/64G listings:
// Quadrant 0
localparam OpcodeLoad = 7'b00_000_11;
localparam OpcodeLoadFp = 7'b00_001_11;
localparam OpcodeCustom0 = 7'b00_010_11;
localparam OpcodeMiscMem = 7'b00_011_11;
localparam OpcodeOpImm = 7'b00_100_11;
localparam OpcodeAuipc = 7'b00_101_11;
localparam OpcodeOpImm32 = 7'b00_110_11;
// Quadrant 1
localparam OpcodeStore = 7'b01_000_11;
localparam OpcodeStoreFp = 7'b01_001_11;
localparam OpcodeCustom1 = 7'b01_010_11;
localparam OpcodeAmo = 7'b01_011_11;
localparam OpcodeOp = 7'b01_100_11;
localparam OpcodeLui = 7'b01_101_11;
localparam OpcodeOp32 = 7'b01_110_11;
// Quadrant 2
localparam OpcodeMadd = 7'b10_000_11;
localparam OpcodeMsub = 7'b10_001_11;
localparam OpcodeNmsub = 7'b10_010_11;
localparam OpcodeNmadd = 7'b10_011_11;
localparam OpcodeOpFp = 7'b10_100_11;
localparam OpcodeRsrvd1 = 7'b10_101_11;
localparam OpcodeCustom2 = 7'b10_110_11;
// Quadrant 3
localparam OpcodeBranch = 7'b11_000_11;
localparam OpcodeJalr = 7'b11_001_11;
localparam OpcodeRsrvd2 = 7'b11_010_11;
localparam OpcodeJal = 7'b11_011_11;
localparam OpcodeSystem = 7'b11_100_11;
localparam OpcodeRsrvd3 = 7'b11_101_11;
localparam OpcodeCustom3 = 7'b11_110_11;
// RV64C/RV32C listings:
// Quadrant 0
localparam OpcodeC0 = 2'b00;
localparam OpcodeC0Addi4spn = 3'b000;
localparam OpcodeC0Fld = 3'b001;
localparam OpcodeC0Lw = 3'b010;
localparam OpcodeC0Ld = 3'b011;
localparam OpcodeC0Rsrvd = 3'b100;
localparam OpcodeC0Fsd = 3'b101;
localparam OpcodeC0Sw = 3'b110;
localparam OpcodeC0Sd = 3'b111;
// Quadrant 1
localparam OpcodeC1 = 2'b01;
localparam OpcodeC1Addi = 3'b000;
localparam OpcodeC1Addiw = 3'b001; //for RV64I only
localparam OpcodeC1Jal = 3'b001; //for RV32I only
localparam OpcodeC1Li = 3'b010;
localparam OpcodeC1LuiAddi16sp = 3'b011;
localparam OpcodeC1MiscAlu = 3'b100;
localparam OpcodeC1J = 3'b101;
localparam OpcodeC1Beqz = 3'b110;
localparam OpcodeC1Bnez = 3'b111;
// Quadrant 2
localparam OpcodeC2 = 2'b10;
localparam OpcodeC2Slli = 3'b000;
localparam OpcodeC2Fldsp = 3'b001;
localparam OpcodeC2Lwsp = 3'b010;
localparam OpcodeC2Ldsp = 3'b011;
localparam OpcodeC2JalrMvAdd = 3'b100;
localparam OpcodeC2Fsdsp = 3'b101;
localparam OpcodeC2Swsp = 3'b110;
localparam OpcodeC2Sdsp = 3'b111;
// ----------------------
// Virtual Memory
// ----------------------
// memory management, pte for sv39
typedef struct packed {
logic [9:0] reserved;
logic [44-1:0] ppn; // PPN length for
logic [1:0] rsw;
logic d;
logic a;
logic g;
logic u;
logic x;
logic w;
logic r;
logic v;
} pte_t;
// memory management, pte for sv32
typedef struct packed {
logic [22-1:0] ppn; // PPN length for
logic [1:0] rsw;
logic d;
logic a;
logic g;
logic u;
logic x;
logic w;
logic r;
logic v;
} pte_sv32_t;
// ----------------------
// Exception Cause Codes
// ----------------------
localparam logic [XLEN-1:0] INSTR_ADDR_MISALIGNED = 0;
localparam logic [XLEN-1:0] INSTR_ACCESS_FAULT = 1; // Illegal access as governed by PMPs and PMAs
localparam logic [XLEN-1:0] ILLEGAL_INSTR = 2;
localparam logic [XLEN-1:0] BREAKPOINT = 3;
localparam logic [XLEN-1:0] LD_ADDR_MISALIGNED = 4;
localparam logic [XLEN-1:0] LD_ACCESS_FAULT = 5; // Illegal access as governed by PMPs and PMAs
localparam logic [XLEN-1:0] ST_ADDR_MISALIGNED = 6;
localparam logic [XLEN-1:0] ST_ACCESS_FAULT = 7; // Illegal access as governed by PMPs and PMAs
localparam logic [XLEN-1:0] ENV_CALL_UMODE = 8; // environment call from user mode
localparam logic [XLEN-1:0] ENV_CALL_SMODE = 9; // environment call from supervisor mode
localparam logic [XLEN-1:0] ENV_CALL_MMODE = 11; // environment call from machine mode
localparam logic [XLEN-1:0] INSTR_PAGE_FAULT = 12; // Instruction page fault
localparam logic [XLEN-1:0] LOAD_PAGE_FAULT = 13; // Load page fault
localparam logic [XLEN-1:0] STORE_PAGE_FAULT = 15; // Store page fault
localparam logic [XLEN-1:0] DEBUG_REQUEST = 24; // Debug request
localparam int unsigned IRQ_S_SOFT = 1;
localparam int unsigned IRQ_M_SOFT = 3;
localparam int unsigned IRQ_S_TIMER = 5;
localparam int unsigned IRQ_M_TIMER = 7;
localparam int unsigned IRQ_S_EXT = 9;
localparam int unsigned IRQ_M_EXT = 11;
localparam logic [XLEN-1:0] MIP_SSIP = 1 << IRQ_S_SOFT;
localparam logic [XLEN-1:0] MIP_MSIP = 1 << IRQ_M_SOFT;
localparam logic [XLEN-1:0] MIP_STIP = 1 << IRQ_S_TIMER;
localparam logic [XLEN-1:0] MIP_MTIP = 1 << IRQ_M_TIMER;
localparam logic [XLEN-1:0] MIP_SEIP = 1 << IRQ_S_EXT;
localparam logic [XLEN-1:0] MIP_MEIP = 1 << IRQ_M_EXT;
localparam logic [XLEN-1:0] S_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_SOFT;
localparam logic [XLEN-1:0] M_SW_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_SOFT;
localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_TIMER;
localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_TIMER;
localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_EXT;
localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_EXT;
// -----
// CSRs
// -----
typedef enum logic [11:0] {
// Floating-Point CSRs
CSR_FFLAGS = 12'h001,
CSR_FRM = 12'h002,
CSR_FCSR = 12'h003,
CSR_FTRAN = 12'h800,
// Supervisor Mode CSRs
CSR_SSTATUS = 12'h100,
CSR_SIE = 12'h104,
CSR_STVEC = 12'h105,
CSR_SCOUNTEREN = 12'h106,
CSR_SSCRATCH = 12'h140,
CSR_SEPC = 12'h141,
CSR_SCAUSE = 12'h142,
CSR_STVAL = 12'h143,
CSR_SIP = 12'h144,
CSR_SATP = 12'h180,
// Machine Mode CSRs
CSR_MSTATUS = 12'h300,
CSR_MISA = 12'h301,
CSR_MEDELEG = 12'h302,
CSR_MIDELEG = 12'h303,
CSR_MIE = 12'h304,
CSR_MTVEC = 12'h305,
CSR_MCOUNTEREN = 12'h306,
CSR_MSCRATCH = 12'h340,
CSR_MEPC = 12'h341,
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_PMPCFG0 = 12'h3A0,
CSR_PMPCFG1 = 12'h3A1,
CSR_PMPCFG2 = 12'h3A2,
CSR_PMPCFG3 = 12'h3A3,
CSR_PMPADDR0 = 12'h3B0,
CSR_PMPADDR1 = 12'h3B1,
CSR_PMPADDR2 = 12'h3B2,
CSR_PMPADDR3 = 12'h3B3,
CSR_PMPADDR4 = 12'h3B4,
CSR_PMPADDR5 = 12'h3B5,
CSR_PMPADDR6 = 12'h3B6,
CSR_PMPADDR7 = 12'h3B7,
CSR_PMPADDR8 = 12'h3B8,
CSR_PMPADDR9 = 12'h3B9,
CSR_PMPADDR10 = 12'h3BA,
CSR_PMPADDR11 = 12'h3BB,
CSR_PMPADDR12 = 12'h3BC,
CSR_PMPADDR13 = 12'h3BD,
CSR_PMPADDR14 = 12'h3BE,
CSR_PMPADDR15 = 12'h3BF,
CSR_MVENDORID = 12'hF11,
CSR_MARCHID = 12'hF12,
CSR_MIMPID = 12'hF13,
CSR_MHARTID = 12'hF14,
CSR_MCYCLE = 12'hB00,
CSR_MCYCLEH = 12'hB80,
CSR_MINSTRET = 12'hB02,
CSR_MINSTRETH = 12'hB82,
// Performance counters (Machine Mode)
CSR_ML1_ICACHE_MISS = 12'hB03, // L1 Instr Cache Miss
CSR_ML1_DCACHE_MISS = 12'hB04, // L1 Data Cache Miss
CSR_MITLB_MISS = 12'hB05, // ITLB Miss
CSR_MDTLB_MISS = 12'hB06, // DTLB Miss
CSR_MLOAD = 12'hB07, // Loads
CSR_MSTORE = 12'hB08, // Stores
CSR_MEXCEPTION = 12'hB09, // Taken exceptions
CSR_MEXCEPTION_RET = 12'hB0A, // Exception return
CSR_MBRANCH_JUMP = 12'hB0B, // Software change of PC
CSR_MCALL = 12'hB0C, // Procedure call
CSR_MRET = 12'hB0D, // Procedure Return
CSR_MMIS_PREDICT = 12'hB0E, // Branch mis-predicted
CSR_MSB_FULL = 12'hB0F, // Scoreboard full
CSR_MIF_EMPTY = 12'hB10, // instruction fetch queue empty
CSR_MHPM_COUNTER_17 = 12'hB11, // reserved
CSR_MHPM_COUNTER_18 = 12'hB12, // reserved
CSR_MHPM_COUNTER_19 = 12'hB13, // reserved
CSR_MHPM_COUNTER_20 = 12'hB14, // reserved
CSR_MHPM_COUNTER_21 = 12'hB15, // reserved
CSR_MHPM_COUNTER_22 = 12'hB16, // reserved
CSR_MHPM_COUNTER_23 = 12'hB17, // reserved
CSR_MHPM_COUNTER_24 = 12'hB18, // reserved
CSR_MHPM_COUNTER_25 = 12'hB19, // reserved
CSR_MHPM_COUNTER_26 = 12'hB1A, // reserved
CSR_MHPM_COUNTER_27 = 12'hB1B, // reserved
CSR_MHPM_COUNTER_28 = 12'hB1C, // reserved
CSR_MHPM_COUNTER_29 = 12'hB1D, // reserved
CSR_MHPM_COUNTER_30 = 12'hB1E, // reserved
CSR_MHPM_COUNTER_31 = 12'hB1F, // reserved
// Cache Control (platform specifc)
CSR_DCACHE = 12'h701,
CSR_ICACHE = 12'h700,
// Triggers
CSR_TSELECT = 12'h7A0,
CSR_TDATA1 = 12'h7A1,
CSR_TDATA2 = 12'h7A2,
CSR_TDATA3 = 12'h7A3,
CSR_TINFO = 12'h7A4,
// Debug CSR
CSR_DCSR = 12'h7b0,
CSR_DPC = 12'h7b1,
CSR_DSCRATCH0 = 12'h7b2, // optional
CSR_DSCRATCH1 = 12'h7b3, // optional
// Counters and Timers (User Mode - R/O Shadows)
CSR_CYCLE = 12'hC00,
CSR_CYCLEH = 12'hC80,
CSR_TIME = 12'hC01,
CSR_TIMEH = 12'hC81,
CSR_INSTRET = 12'hC02,
CSR_INSTRETH = 12'hC82,
// Performance counters (User Mode - R/O Shadows)
CSR_L1_ICACHE_MISS = 12'hC03, // L1 Instr Cache Miss
CSR_L1_DCACHE_MISS = 12'hC04, // L1 Data Cache Miss
CSR_ITLB_MISS = 12'hC05, // ITLB Miss
CSR_DTLB_MISS = 12'hC06, // DTLB Miss
CSR_LOAD = 12'hC07, // Loads
CSR_STORE = 12'hC08, // Stores
CSR_EXCEPTION = 12'hC09, // Taken exceptions
CSR_EXCEPTION_RET = 12'hC0A, // Exception return
CSR_BRANCH_JUMP = 12'hC0B, // Software change of PC
CSR_CALL = 12'hC0C, // Procedure call
CSR_RET = 12'hC0D, // Procedure Return
CSR_MIS_PREDICT = 12'hC0E, // Branch mis-predicted
CSR_SB_FULL = 12'hC0F, // Scoreboard full
CSR_IF_EMPTY = 12'hC10, // instruction fetch queue empty
CSR_HPM_COUNTER_17 = 12'hC11, // reserved
CSR_HPM_COUNTER_18 = 12'hC12, // reserved
CSR_HPM_COUNTER_19 = 12'hC13, // reserved
CSR_HPM_COUNTER_20 = 12'hC14, // reserved
CSR_HPM_COUNTER_21 = 12'hC15, // reserved
CSR_HPM_COUNTER_22 = 12'hC16, // reserved
CSR_HPM_COUNTER_23 = 12'hC17, // reserved
CSR_HPM_COUNTER_24 = 12'hC18, // reserved
CSR_HPM_COUNTER_25 = 12'hC19, // reserved
CSR_HPM_COUNTER_26 = 12'hC1A, // reserved
CSR_HPM_COUNTER_27 = 12'hC1B, // reserved
CSR_HPM_COUNTER_28 = 12'hC1C, // reserved
CSR_HPM_COUNTER_29 = 12'hC1D, // reserved
CSR_HPM_COUNTER_30 = 12'hC1E, // reserved
CSR_HPM_COUNTER_31 = 12'hC1F // reserved
} csr_reg_t;
localparam logic [63:0] SSTATUS_UIE = 'h00000001;
localparam logic [63:0] SSTATUS_SIE = 'h00000002;
localparam logic [63:0] SSTATUS_SPIE = 'h00000020;
localparam logic [63:0] SSTATUS_SPP = 'h00000100;
localparam logic [63:0] SSTATUS_FS = 'h00006000;
localparam logic [63:0] SSTATUS_XS = 'h00018000;
localparam logic [63:0] SSTATUS_SUM = 'h00040000;
localparam logic [63:0] SSTATUS_MXR = 'h00080000;
localparam logic [63:0] SSTATUS_UPIE = 'h00000010;
localparam logic [63:0] SSTATUS_UXL = 64'h0000000300000000;
localparam logic [63:0] SSTATUS_SD = {IS_XLEN64, 31'h00000000, ~IS_XLEN64, 31'h00000000};
localparam logic [63:0] MSTATUS_UIE = 'h00000001;
localparam logic [63:0] MSTATUS_SIE = 'h00000002;
localparam logic [63:0] MSTATUS_HIE = 'h00000004;
localparam logic [63:0] MSTATUS_MIE = 'h00000008;
localparam logic [63:0] MSTATUS_UPIE = 'h00000010;
localparam logic [63:0] MSTATUS_SPIE = 'h00000020;
localparam logic [63:0] MSTATUS_HPIE = 'h00000040;
localparam logic [63:0] MSTATUS_MPIE = 'h00000080;
localparam logic [63:0] MSTATUS_SPP = 'h00000100;
localparam logic [63:0] MSTATUS_HPP = 'h00000600;
localparam logic [63:0] MSTATUS_MPP = 'h00001800;
localparam logic [63:0] MSTATUS_FS = 'h00006000;
localparam logic [63:0] MSTATUS_XS = 'h00018000;
localparam logic [63:0] MSTATUS_MPRV = 'h00020000;
localparam logic [63:0] MSTATUS_SUM = 'h00040000;
localparam logic [63:0] MSTATUS_MXR = 'h00080000;
localparam logic [63:0] MSTATUS_TVM = 'h00100000;
localparam logic [63:0] MSTATUS_TW = 'h00200000;
localparam logic [63:0] MSTATUS_TSR = 'h00400000;
localparam logic [63:0] MSTATUS_UXL = {30'h0000000, IS_XLEN64, IS_XLEN64, 32'h00000000};
localparam logic [63:0] MSTATUS_SXL = {28'h0000000, IS_XLEN64, IS_XLEN64, 34'h00000000};
localparam logic [63:0] MSTATUS_SD = {IS_XLEN64, 31'h00000000, ~IS_XLEN64, 31'h00000000};
typedef enum logic [2:0] {
CSRRW = 3'h1,
CSRRS = 3'h2,
CSRRC = 3'h3,
CSRRWI = 3'h5,
CSRRSI = 3'h6,
CSRRCI = 3'h7
} csr_op_t;
// decoded CSR address
typedef struct packed {
logic [1:0] rw;
priv_lvl_t priv_lvl;
logic [7:0] address;
} csr_addr_t;
typedef union packed {
csr_reg_t address;
csr_addr_t csr_decode;
} csr_t;
// Floating-Point control and status register (32-bit!)
typedef struct packed {
logic [31:15] reserved; // reserved for L extension, return 0 otherwise
logic [6:0] fprec; // div/sqrt precision control
logic [2:0] frm; // float rounding mode
logic [4:0] fflags; // float exception flags
} fcsr_t;
// PMP
typedef enum logic [1:0] {
OFF = 2'b00,
TOR = 2'b01,
NA4 = 2'b10,
NAPOT = 2'b11
} pmp_addr_mode_t;
// PMP Access Type
typedef enum logic [2:0] {
ACCESS_NONE = 3'b000,
ACCESS_READ = 3'b001,
ACCESS_WRITE = 3'b010,
ACCESS_EXEC = 3'b100
} pmp_access_t;
typedef struct packed {
logic x;
logic w;
logic r;
} pmpcfg_access_t;
// packed struct of a PMP configuration register (8bit)
typedef struct packed {
logic locked; // lock this configuration
logic [1:0] reserved;
pmp_addr_mode_t addr_mode; // Off, TOR, NA4, NAPOT
pmpcfg_access_t access_type;
} pmpcfg_t;
// -----
// Debug
// -----
typedef struct packed {
logic [31:28] xdebugver;
logic [27:16] zero2;
logic ebreakm;
logic zero1;
logic ebreaks;
logic ebreaku;
logic stepie;
logic stopcount;
logic stoptime;
logic [8:6] cause;
logic zero0;
logic mprven;
logic nmip;
logic step;
priv_lvl_t prv;
} dcsr_t;
// Instruction Generation *incomplete*
function automatic logic [31:0] jal (logic[4:0] rd, logic [20:0] imm);
// OpCode Jal
return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f};
endfunction
function automatic logic [31:0] jalr (logic[4:0] rd, logic[4:0] rs1, logic [11:0] offset);
// OpCode Jal
return {offset[11:0], rs1, 3'b0, rd, 7'h67};
endfunction
function automatic logic [31:0] andi (logic[4:0] rd, logic[4:0] rs1, logic [11:0] imm);
// OpCode andi
return {imm[11:0], rs1, 3'h7, rd, 7'h13};
endfunction
function automatic logic [31:0] slli (logic[4:0] rd, logic[4:0] rs1, logic [5:0] shamt);
// OpCode slli
return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13};
endfunction
function automatic logic [31:0] srli (logic[4:0] rd, logic[4:0] rs1, logic [5:0] shamt);
// OpCode srli
return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13};
endfunction
function automatic logic [31:0] load (logic [2:0] size, logic[4:0] dest, logic[4:0] base, logic [11:0] offset);
// OpCode Load
return {offset[11:0], base, size, dest, 7'h03};
endfunction
function automatic logic [31:0] auipc (logic[4:0] rd, logic [20:0] imm);
// OpCode Auipc
return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17};
endfunction
function automatic logic [31:0] store (logic [2:0] size, logic[4:0] src, logic[4:0] base, logic [11:0] offset);
// OpCode Store
return {offset[11:5], src, base, size, offset[4:0], 7'h23};
endfunction
function automatic logic [31:0] float_load (logic [2:0] size, logic[4:0] dest, logic[4:0] base, logic [11:0] offset);
// OpCode Load
return {offset[11:0], base, size, dest, 7'b00_001_11};
endfunction
function automatic logic [31:0] float_store (logic [2:0] size, logic[4:0] src, logic[4:0] base, logic [11:0] offset);
// OpCode Store
return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11};
endfunction
function automatic logic [31:0] csrw (csr_reg_t csr, logic[4:0] rs1);
// CSRRW, rd, OpCode System
return {csr, rs1, 3'h1, 5'h0, 7'h73};
endfunction
function automatic logic [31:0] csrr (csr_reg_t csr, logic [4:0] dest);
// rs1, CSRRS, rd, OpCode System
return {csr, 5'h0, 3'h2, dest, 7'h73};
endfunction
function automatic logic [31:0] branch(logic [4:0] src2, logic [4:0] src1, logic [2:0] funct3, logic [11:0] offset);
// OpCode Branch
return {offset[11], offset[9:4], src2, src1, funct3, offset[3:0], offset[10], 7'b11_000_11};
endfunction
function automatic logic [31:0] ebreak ();
return 32'h00100073;
endfunction
function automatic logic [31:0] wfi ();
return 32'h10500073;
endfunction
function automatic logic [31:0] nop ();
return 32'h00000013;
endfunction
function automatic logic [31:0] illegal ();
return 32'h00000000;
endfunction
// trace log compatible to spikes commit log feature
// pragma translate_off
function string spikeCommitLog(logic [63:0] pc, priv_lvl_t priv_lvl, logic [31:0] instr, logic [4:0] rd, logic [63:0] result, logic rd_fpr);
string rd_s;
string instr_word;
automatic string rf_s = rd_fpr ? "f" : "x";
if (instr[1:0] != 2'b11) begin
instr_word = $sformatf("(0x%h)", instr[15:0]);
end else begin
instr_word = $sformatf("(0x%h)", instr);
end
if (rd < 10) rd_s = $sformatf("%s %0d", rf_s, rd);
else rd_s = $sformatf("%s%0d", rf_s, rd);
if (rd_fpr || rd != 0) begin
// 0 0x0000000080000118 (0xeecf8f93) x31 0x0000000080004000
return $sformatf("%d 0x%h %s %s 0x%h\n", priv_lvl, pc, instr_word, rd_s, result);
end else begin
// 0 0x000000008000019c (0x0040006f)
return $sformatf("%d 0x%h %s\n", priv_lvl, pc, instr_word);
end
endfunction
typedef struct {
byte priv;
longint unsigned pc;
byte is_fp;
byte rd;
longint unsigned data;
int unsigned instr;
byte was_exception;
} commit_log_t;
// pragma translate_on
endpackage
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: ariane_pkg.sv
* Author: Florian Zaruba <[email protected]>
* Date: 8.4.2017
*
* Description: Contains all the necessary defines for Ariane
* in one package.
*/
// this is needed to propagate the
// configuration in case Ariane is
// instantiated in OpenPiton
package ariane_pkg;
// ---------------
// Global Config
// ---------------
// This is the new user config interface system. If you need to parameterize something
// within Ariane add a field here and assign a default value to the config. Please make
// sure to add a propper parameter check to the `check_cfg` function.
localparam NrMaxRules = 16;
typedef struct packed {
int RASDepth;
int BTBEntries;
int BHTEntries;
// PMAs
int unsigned NrNonIdempotentRules; // Number of non idempotent rules
logic [NrMaxRules-1:0][63:0] NonIdempotentAddrBase; // base which needs to match
logic [NrMaxRules-1:0][63:0] NonIdempotentLength; // bit mask which bits to consider when matching the rule
int unsigned NrExecuteRegionRules; // Number of regions which have execute property
logic [NrMaxRules-1:0][63:0] ExecuteRegionAddrBase; // base which needs to match
logic [NrMaxRules-1:0][63:0] ExecuteRegionLength; // bit mask which bits to consider when matching the rule
int unsigned NrCachedRegionRules; // Number of regions which have cached property
logic [NrMaxRules-1:0][63:0] CachedRegionAddrBase; // base which needs to match
logic [NrMaxRules-1:0][63:0] CachedRegionLength; // bit mask which bits to consider when matching the rule
// cache config
bit Axi64BitCompliant; // set to 1 when using in conjunction with 64bit AXI bus adapter
bit SwapEndianess; // set to 1 to swap endianess inside L1.5 openpiton adapter
//
logic [63:0] DmBaseAddress; // offset of the debug module
int unsigned NrPMPEntries; // Number of PMP entries
} ariane_cfg_t;
localparam ariane_cfg_t ArianeDefaultConfig = '{
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
// idempotent region
NrNonIdempotentRules: 2,
NonIdempotentAddrBase: {64'b0, 64'b0},
NonIdempotentLength: {64'b0, 64'b0},
NrExecuteRegionRules: 3,
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: {64'h8000_0000, 64'h1_0000, 64'h0},
ExecuteRegionLength: {64'h40000000, 64'h10000, 64'h1000},
// cached region
NrCachedRegionRules: 1,
CachedRegionAddrBase: {64'h8000_0000},
CachedRegionLength: {64'h40000000},
// cache config
Axi64BitCompliant: 1'b1,
SwapEndianess: 1'b0,
// debug
DmBaseAddress: 64'h0,
NrPMPEntries: 8
};
// Function being called to check parameters
function automatic void check_cfg (ariane_cfg_t Cfg);
// pragma translate_off
// pragma translate_on
endfunction
function automatic logic range_check(logic[63:0] base, logic[63:0] len, logic[63:0] address);
// if len is a power of two, and base is properly aligned, this check could be simplified
return (address >= base) && (address < (65'(base)+len));
endfunction : range_check
function automatic logic is_inside_nonidempotent_regions (ariane_cfg_t Cfg, logic[63:0] address);
logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k = 0; k < Cfg.NrNonIdempotentRules; k++) begin
pass[k] = range_check(Cfg.NonIdempotentAddrBase[k], Cfg.NonIdempotentLength[k], address);
end
return |pass;
endfunction : is_inside_nonidempotent_regions
function automatic logic is_inside_execute_regions (ariane_cfg_t Cfg, logic[63:0] address);
// if we don't specify any region we assume everything is accessible
logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k = 0; k < Cfg.NrExecuteRegionRules; k++) begin
pass[k] = range_check(Cfg.ExecuteRegionAddrBase[k], Cfg.ExecuteRegionLength[k], address);
end
return |pass;
endfunction : is_inside_execute_regions
function automatic logic is_inside_cacheable_regions (ariane_cfg_t Cfg, logic[63:0] address);
automatic logic[NrMaxRules-1:0] pass;
pass = '0;
for (int unsigned k = 0; k < Cfg.NrCachedRegionRules; k++) begin
pass[k] = range_check(Cfg.CachedRegionAddrBase[k], Cfg.CachedRegionLength[k], address);
end
return |pass;
endfunction : is_inside_cacheable_regions
// TODO: Slowly move those parameters to the new system.
localparam NR_SB_ENTRIES = 8; // number of scoreboard entries
localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits
// to uniquely identify the entry in the scoreboard
localparam ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1;
localparam BITS_SATURATION_COUNTER = 2;
localparam NR_COMMIT_PORTS = 2;
localparam ENABLE_RENAME = cva6_config_pkg::CVA6ConfigRenameEn;
localparam ISSUE_WIDTH = 1;
// amount of pipeline registers inserted for load/store return path
// this can be tuned to trade-off IPC vs. cycle time
localparam int unsigned NR_LOAD_PIPE_REGS = 1;
localparam int unsigned NR_STORE_PIPE_REGS = 0;
// depth of store-buffers, this needs to be a power of two
localparam int unsigned DEPTH_SPEC = 4;
// in this case we can use a small commit queue since we have a write buffer in the dcache
// we could in principle do without the commit queue in this case, but the timing degrades if we do that due
// to longer paths into the commit stage
localparam int unsigned DEPTH_COMMIT = 4;
localparam bit RVC = cva6_config_pkg::CVA6ConfigCExtEn; // Is C extension configuration
// Floating-point extensions configuration
localparam bit RVF = (riscv::IS_XLEN64 | riscv::IS_XLEN32) & riscv::FPU_EN; // Is F extension enabled for both 32 Bit and 64 bit CPU
localparam bit RVD = (riscv::IS_XLEN64 ? 1:0) & riscv::FPU_EN; // Is D extension enabled for only 64 bit CPU
localparam bit RVA = cva6_config_pkg::CVA6ConfigAExtEn; // Is A extension enabled
// Transprecision floating-point extensions configuration
localparam bit XF16 = cva6_config_pkg::CVA6ConfigF16En; // Is half-precision float extension (Xf16) enabled
localparam bit XF16ALT = cva6_config_pkg::CVA6ConfigF16AltEn; // Is alternative half-precision float extension (Xf16alt) enabled
localparam bit XF8 = cva6_config_pkg::CVA6ConfigF8En; // Is quarter-precision float extension (Xf8) enabled
localparam bit XFVEC = cva6_config_pkg::CVA6ConfigFVecEn; // Is vectorial float extension (Xfvec) enabled
// Transprecision float unit
localparam int unsigned LAT_COMP_FP32 = 'd2;
localparam int unsigned LAT_COMP_FP64 = 'd3;
localparam int unsigned LAT_COMP_FP16 = 'd1;
localparam int unsigned LAT_COMP_FP16ALT = 'd1;
localparam int unsigned LAT_COMP_FP8 = 'd1;
localparam int unsigned LAT_DIVSQRT = 'd2;
localparam int unsigned LAT_NONCOMP = 'd1;
localparam int unsigned LAT_CONV = 'd2;
// --------------------------------------
// vvvv Don't change these by hand! vvvv
localparam bit FP_PRESENT = RVF | RVD | XF16 | XF16ALT | XF8;
// Length of widest floating-point format
localparam FLEN = RVD ? 64 : // D ext.
RVF ? 32 : // F ext.
XF16 ? 16 : // Xf16 ext.
XF16ALT ? 16 : // Xf16alt ext.
XF8 ? 8 : // Xf8 ext.
1; // Unused in case of no FP
localparam bit NSX = XF16 | XF16ALT | XF8 | XFVEC; // Are non-standard extensions present?
localparam bit RVFVEC = RVF & XFVEC & FLEN>32; // FP32 vectors available if vectors and larger fmt enabled
localparam bit XF16VEC = XF16 & XFVEC & FLEN>16; // FP16 vectors available if vectors and larger fmt enabled
localparam bit XF16ALTVEC = XF16ALT & XFVEC & FLEN>16; // FP16ALT vectors available if vectors and larger fmt enabled
localparam bit XF8VEC = XF8 & XFVEC & FLEN>8; // FP8 vectors available if vectors and larger fmt enabled
// ^^^^ until here ^^^^
// ---------------------
localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN-32{1'b0}}, 32'd3};
localparam riscv::xlen_t ISA_CODE = (RVA << 0) // A - Atomic Instructions extension
| (RVC << 2) // C - Compressed extension
| (RVD << 3) // D - Double precsision floating-point extension
| (RVF << 5) // F - Single precsision floating-point extension
| (1 << 8) // I - RV32I/64I/128I base ISA
| (1 << 12) // M - Integer Multiply/Divide extension
| (0 << 13) // N - User level interrupts supported
| (1 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (NSX << 23) // X - Non-standard extensions present
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL
// 32 registers + 1 bit for re-naming = 6
localparam REG_ADDR_SIZE = 6;
localparam bit CVXIF_PRESENT = cva6_config_pkg::CVA6ConfigCvxifEn;
// when cvx interface is present, use an additional writeback port
localparam NR_WB_PORTS = CVXIF_PRESENT ? 5 : 4;
// Read ports for general purpose register files
localparam NR_RGPR_PORTS = 2;
typedef logic [(NR_RGPR_PORTS == 3 ? riscv::XLEN : FLEN)-1:0] rs3_len_t;
// static debug hartinfo
localparam dm::hartinfo_t DebugHartInfo = '{
zero1: '0,
nscratch: 2, // Debug module needs at least two scratch regs
zero0: '0,
dataaccess: 1'b1, // data registers are memory mapped in the debugger
datasize: dm::DataCount,
dataaddr: dm::DataAddr
};
// enables a commit log which matches spikes commit log format for easier trace comparison
localparam bit ENABLE_SPIKE_COMMIT_LOG = 1'b1;
// ------------- Dangerouse -------------
// if set to zero a flush will not invalidate the cache-lines, in a single core environment
// where coherence is not necessary this can improve performance. This needs to be switched on
// when more than one core is in a system
localparam logic INVALIDATE_ON_FLUSH = 1'b1;
localparam bit ENABLE_CYCLE_COUNT = 1'b1;
localparam bit ENABLE_WFI = 1'b1;
localparam bit ZERO_TVAL = 1'b0;
// read mask for SSTATUS over MMSTATUS
localparam logic [63:0] SMODE_STATUS_WRITE_MASK = riscv::SSTATUS_SIE
| riscv::SSTATUS_SPIE
| riscv::SSTATUS_SPP
| riscv::SSTATUS_FS
| riscv::SSTATUS_SUM
| riscv::SSTATUS_MXR;
// ---------------
// User bits
// ---------------
localparam FETCH_USER_WIDTH = (cva6_config_pkg::CVA6ConfigFetchUserEn == 0) ? 1: cva6_config_pkg::CVA6ConfigFetchUserWidth; // Possible cases: between 1 and 64
localparam DATA_USER_WIDTH = (cva6_config_pkg::CVA6ConfigDataUserEn == 0) ? 1: cva6_config_pkg::CVA6ConfigDataUserWidth; // Possible cases: between 1 and 64
//localparam AXI_USER_WIDTH = DATA_USER_WIDTH > FETCH_USER_WIDTH*2 ? DATA_USER_WIDTH : FETCH_USER_WIDTH*2;
localparam AXI_USER_WIDTH = 1;
localparam DATA_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn;
localparam FETCH_USER_EN = cva6_config_pkg::CVA6ConfigFetchUserEn;
//localparam AXI_USER_EN = cva6_config_pkg::CVA6ConfigDataUserEn | cva6_config_pkg::CVA6ConfigFetchUserEn;
localparam AXI_USER_EN = 1;
// ---------------
// Fetch Stage
// ---------------
// leave as is (fails with >8 entries and wider fetch width)
localparam int unsigned FETCH_FIFO_DEPTH = 4;
localparam int unsigned FETCH_WIDTH = 32;
// maximum instructions we can fetch on one request (we support compressed instructions)
localparam int unsigned INSTR_PER_FETCH = RVC == 1'b1 ? (FETCH_WIDTH / 16) : 1;
localparam int unsigned LOG2_INSTR_PER_FETCH = RVC == 1'b1 ? $clog2(ariane_pkg::INSTR_PER_FETCH) : 1;
// ---------------
// Enable BITMANIP
// ---------------
localparam bit BITMANIP = 1'b0;
// Only use struct when signals have same direction
// exception
typedef struct packed {
riscv::xlen_t cause; // cause of exception
riscv::xlen_t tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic valid;
} exception_t;
typedef enum logic [2:0] {
NoCF, // No control flow prediction
Branch, // Branch
Jump, // Jump to address from immediate
JumpR, // Jump to address from registers
Return // Return Address Prediction
} cf_t;
// branch-predict
// this is the struct we get back from ex stage and we will use it to update
// all the necessary data structures
// bp_resolve_t
typedef struct packed {
logic valid; // prediction with all its values is valid
logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict
logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not
logic is_mispredict; // set if this was a mis-predict
logic is_taken; // branch is taken
cf_t cf_type; // Type of control flow change
} bp_resolve_t;
// branchpredict scoreboard entry
// this is the struct which we will inject into the pipeline to guide the various
// units towards the correct branch decision and resolve
typedef struct packed {
cf_t cf; // type of control flow prediction
logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not
} branchpredict_sbe_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic [riscv::VLEN-1:0] target_address;
} btb_update_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] target_address;
} btb_prediction_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] ra;
} ras_t;
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] pc; // update at PC
logic taken;
} bht_update_t;
typedef struct packed {
logic valid;
logic taken;
} bht_prediction_t;
typedef enum logic[3:0] {
NONE, // 0
LOAD, // 1
STORE, // 2
ALU, // 3
CTRL_FLOW, // 4
MULT, // 5
CSR, // 6
FPU, // 7
FPU_VEC, // 8
CVXIF // 9
} fu_t;
localparam EXC_OFF_RST = 8'h80;
localparam SupervisorIrq = 1;
localparam MachineIrq = 0;
// All information needed to determine whether we need to associate an interrupt
// with the corresponding instruction or not.
typedef struct packed {
riscv::xlen_t mie;
riscv::xlen_t mip;
riscv::xlen_t mideleg;
logic sie;
logic global_enable;
} irq_ctrl_t;
// ---------------
// Cache config
// ---------------
// for usage in OpenPiton we have to propagate the openpiton L15 configuration from l15.h
// I$
localparam int unsigned CONFIG_L1I_SIZE = 16*1024;
localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width
localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit
localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned ICACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit
// D$
localparam int unsigned CONFIG_L1D_SIZE = 32*1024;
localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64
localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC); // in bit, contains also offset width
localparam int unsigned DCACHE_TAG_WIDTH = riscv::PLEN-DCACHE_INDEX_WIDTH; // in bit
localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned DCACHE_USER_LINE_WIDTH = (AXI_USER_WIDTH == 1) ? 4 : 128; // in bit
localparam int unsigned DCACHE_USER_WIDTH = DATA_USER_WIDTH;
// ---------------
// EX Stage
// ---------------
typedef enum logic [7:0] { // basic ALU op
ADD, SUB, ADDW, SUBW,
// logic operations
XORL, ORL, ANDL,
// shifts
SRA, SRL, SLL, SRLW, SLLW, SRAW,
// comparisons
LTS, LTU, GES, GEU, EQ, NE,
// jumps
JALR, BRANCH,
// set lower than operations
SLTS, SLTU,
// CSR functions
MRET, SRET, DRET, ECALL, WFI, FENCE, FENCE_I, SFENCE_VMA, CSR_WRITE, CSR_READ, CSR_SET, CSR_CLEAR,
// LSU functions
LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU,
// Atomic Memory Operations
AMO_LRW, AMO_LRD, AMO_SCW, AMO_SCD,
AMO_SWAPW, AMO_ADDW, AMO_ANDW, AMO_ORW, AMO_XORW, AMO_MAXW, AMO_MAXWU, AMO_MINW, AMO_MINWU,
AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD, AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND, AMO_MINDU,
// Multiplications
MUL, MULH, MULHU, MULHSU, MULW,
// Divisions
DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW,
// Floating-Point Load and Store Instructions
FLD, FLW, FLH, FLB, FSD, FSW, FSH, FSB,
// Floating-Point Computational Instructions
FADD, FSUB, FMUL, FDIV, FMIN_MAX, FSQRT, FMADD, FMSUB, FNMSUB, FNMADD,
// Floating-Point Conversion and Move Instructions
FCVT_F2I, FCVT_I2F, FCVT_F2F, FSGNJ, FMV_F2X, FMV_X2F,
// Floating-Point Compare Instructions
FCMP,
// Floating-Point Classify Instruction
FCLASS,
// Vectorial Floating-Point Instructions that don't directly map onto the scalar ones
VFMIN, VFMAX, VFSGNJ, VFSGNJN, VFSGNJX, VFEQ, VFNE, VFLT, VFGE, VFLE, VFGT, VFCPKAB_S, VFCPKCD_S, VFCPKAB_D, VFCPKCD_D,
// Offload Instructions to be directed into cv_x_if
OFFLOAD,
// Or-Combine and REV8
ORCB, REV8,
// Bitwise Rotation
ROL, ROLW, ROR, RORI, RORIW, RORW,
// Sign and Zero Extend
SEXTB, SEXTH, ZEXTH,
// Count population
CPOP, CPOPW,
// Count Leading/Training Zeros
CLZ, CLZW, CTZ, CTZW,
// Carry less multiplication Op's
CLMUL, CLMULH, CLMULR,
// Single bit instructions Op's
BCLR, BCLRI, BEXT, BEXTI, BINV, BINVI, BSET, BSETI,
// Integer minimum/maximum
MAX, MAXU, MIN, MINU,
// Shift with Add Unsigned Word and Unsigned Word Op's (Bitmanip)
SH1ADDUW, SH2ADDUW, SH3ADDUW, ADDUW, SLLIUW,
// Shift with Add (Bitmanip)
SH1ADD, SH2ADD, SH3ADD,
// Bitmanip Logical with negate op (Bitmanip)
ANDN, ORN, XNOR
} fu_op;
typedef struct packed {
fu_t fu;
fu_op operator;
riscv::xlen_t operand_a;
riscv::xlen_t operand_b;
riscv::xlen_t imm;
logic [TRANS_ID_BITS-1:0] trans_id;
} fu_data_t;
function automatic logic op_is_branch (input fu_op op);
unique case (op) inside
EQ, NE, LTS, GES, LTU, GEU: return 1'b1;
default : return 1'b0; // all other ops
endcase
endfunction
// -------------------------------
// Extract Src/Dst FP Reg from Op
// -------------------------------
function automatic logic is_rs1_fpr (input fu_op op);
if (FP_PRESENT) begin // makes function static for non-fp case
unique case (op) inside
[FMUL:FNMADD], // Computational Operations (except ADD/SUB)
FCVT_F2I, // Float-Int Casts
FCVT_F2F, // Float-Float Casts
FSGNJ, // Sign Injections
FMV_F2X, // FPR-GPR Moves
FCMP, // Comparisons
FCLASS, // Classifications
[VFMIN:VFCPKCD_D] : return 1'b1; // Additional Vectorial FP ops
default : return 1'b0; // all other ops
endcase
end else
return 1'b0;
endfunction
function automatic logic is_rs2_fpr (input fu_op op);
if (FP_PRESENT) begin // makes function static for non-fp case
unique case (op) inside
[FSD:FSB], // FP Stores
[FADD:FMIN_MAX], // Computational Operations (no sqrt)
[FMADD:FNMADD], // Fused Computational Operations
FCVT_F2F, // Vectorial F2F Conversions requrie target
[FSGNJ:FMV_F2X], // Sign Injections and moves mapped to SGNJ
FCMP, // Comparisons
[VFMIN:VFCPKCD_D] : return 1'b1; // Additional Vectorial FP ops
default : return 1'b0; // all other ops
endcase
end else
return 1'b0;
endfunction
// ternary operations encode the rs3 address in the imm field, also add/sub
function automatic logic is_imm_fpr (input fu_op op);
if (FP_PRESENT) begin // makes function static for non-fp case
unique case (op) inside
[FADD:FSUB], // ADD/SUB need inputs as Operand B/C
[FMADD:FNMADD], // Fused Computational Operations
[VFCPKAB_S:VFCPKCD_D] : return 1'b1; // Vectorial FP cast and pack ops
default : return 1'b0; // all other ops
endcase
end else
return 1'b0;
endfunction
function automatic logic is_rd_fpr (input fu_op op);
if (FP_PRESENT) begin // makes function static for non-fp case
unique case (op) inside
[FLD:FLB], // FP Loads
[FADD:FNMADD], // Computational Operations
FCVT_I2F, // Int-Float Casts
FCVT_F2F, // Float-Float Casts
FSGNJ, // Sign Injections
FMV_X2F, // GPR-FPR Moves
[VFMIN:VFSGNJX], // Vectorial MIN/MAX and SGNJ
[VFCPKAB_S:VFCPKCD_D] : return 1'b1; // Vectorial FP cast and pack ops
default : return 1'b0; // all other ops
endcase
end else
return 1'b0;
endfunction
function automatic logic is_amo (fu_op op);
case (op) inside
[AMO_LRW:AMO_MINDU]: begin
return 1'b1;
end
default: return 1'b0;
endcase
endfunction
typedef struct packed {
logic valid;
logic [riscv::VLEN-1:0] vaddr;
logic overflow;
riscv::xlen_t data;
logic [(riscv::XLEN/8)-1:0] be;
fu_t fu;
fu_op operator;
logic [TRANS_ID_BITS-1:0] trans_id;
} lsu_ctrl_t;
// ---------------
// IF/ID Stage
// ---------------
// store the decompressed instruction
typedef struct packed {
logic [riscv::VLEN-1:0] address; // the address of the instructions from below
logic [31:0] instruction; // instruction word
branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path
exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions
} fetch_entry_t;
// ---------------
// ID/EX/WB Stage
// ---------------
typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction
logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
// with the transaction id in any case make the width more generic
fu_t fu; // functional unit to use
fu_op op; // operation to perform in each functional unit
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
riscv::xlen_t result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
logic valid; // is the result valid
logic use_imm; // should we use the immediate as operand b?
logic use_zimm; // use zimm as operand a
logic use_pc; // set if we need to use the PC as operand a, PC from exception
exception_t ex; // exception has occurred
branchpredict_sbe_t bp; // branch predict scoreboard data structure
logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if
// we want jump accordingly e.g.: +4, +2
} scoreboard_entry_t;
// ---------------
// MMU instanciation
// ---------------
localparam bit MMU_PRESENT = 1'b1; // MMU is present
// --------------------
// Atomics
// --------------------
typedef enum logic [3:0] {
AMO_NONE =4'b0000,
AMO_LR =4'b0001,
AMO_SC =4'b0010,
AMO_SWAP =4'b0011,
AMO_ADD =4'b0100,
AMO_AND =4'b0101,
AMO_OR =4'b0110,
AMO_XOR =4'b0111,
AMO_MAX =4'b1000,
AMO_MAXU =4'b1001,
AMO_MIN =4'b1010,
AMO_MINU =4'b1011,
AMO_CAS1 =4'b1100, // unused, not part of riscv spec, but provided in OpenPiton
AMO_CAS2 =4'b1101 // unused, not part of riscv spec, but provided in OpenPiton
} amo_t;
typedef struct packed {
logic valid; // valid flag
logic is_2M; //
logic is_1G; //
logic [27-1:0] vpn; // VPN (39bits) = 27bits + 12bits offset
logic [ASID_WIDTH-1:0] asid;
riscv::pte_t content;
} tlb_update_t;
// Bits required for representation of physical address space as 4K pages
// (e.g. 27*4K == 39bit address space).
localparam PPN4K_WIDTH = 38;
typedef struct packed {
logic valid; // valid flag
logic is_4M; //
logic [20-1:0] vpn; //VPN (32bits) = 20bits + 12bits offset
logic [9-1:0] asid; //ASID length = 9 for Sv32 mmu
riscv::pte_sv32_t content;
} tlb_update_sv32_t;
typedef enum logic [1:0] {
FE_NONE,
FE_INSTR_ACCESS_FAULT,
FE_INSTR_PAGE_FAULT
} frontend_exception_t;
// ----------------------
// cache request ports
// ----------------------
// I$ address translation requests
typedef struct packed {
logic fetch_valid; // address translation valid
logic [riscv::PLEN-1:0] fetch_paddr; // physical address in
exception_t fetch_exception; // exception occurred during fetch
} icache_areq_i_t;
typedef struct packed {
logic fetch_req; // address translation request
logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out
} icache_areq_o_t;
// I$ data requests
typedef struct packed {
logic req; // we request a new word
logic kill_s1; // kill the current request
logic kill_s2; // kill the last request
logic spec; // request is speculative
logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup
} icache_dreq_i_t;
typedef struct packed {
logic ready; // icache is ready
logic valid; // signals a valid read
logic [FETCH_WIDTH-1:0] data; // 2+ cycle out: tag
logic [FETCH_USER_WIDTH-1:0] user; // User bits
logic [riscv::VLEN-1:0] vaddr; // virtual address out
exception_t ex; // we've encountered an exception
} icache_dreq_o_t;
// AMO request going to cache. this request is unconditionally valid as soon
// as request goes high.
// Furthermore, those signals are kept stable until the response indicates
// completion by asserting ack.
typedef struct packed {
logic req; // this request is valid
amo_t amo_op; // atomic memory operation to perform
logic [1:0] size; // 2'b10 --> word operation, 2'b11 --> double word operation
logic [63:0] operand_a; // address
logic [63:0] operand_b; // data as layouted in the register
} amo_req_t;
// AMO response coming from cache.
typedef struct packed {
logic ack; // response is valid
logic [63:0] result; // sign-extended, result
} amo_resp_t;
// D$ data requests
typedef struct packed {
logic [DCACHE_INDEX_WIDTH-1:0] address_index;
logic [DCACHE_TAG_WIDTH-1:0] address_tag;
riscv::xlen_t data_wdata;
logic [DCACHE_USER_WIDTH-1:0] data_wuser;
logic data_req;
logic data_we;
logic [(riscv::XLEN/8)-1:0] data_be;
logic [1:0] data_size;
logic kill_req;
logic tag_valid;
} dcache_req_i_t;
typedef struct packed {
logic data_gnt;
logic data_rvalid;
riscv::xlen_t data_rdata;
logic [DCACHE_USER_WIDTH-1:0] data_ruser;
} dcache_req_o_t;
// ----------------------
// Arithmetic Functions
// ----------------------
function automatic riscv::xlen_t sext32 (logic [31:0] operand);
return {{riscv::XLEN-32{operand[31]}}, operand[31:0]};
endfunction
// ----------------------
// Immediate functions
// ----------------------
function automatic logic [riscv::VLEN-1:0] uj_imm (logic [31:0] instruction_i);
return { {44+riscv::VLEN-64 {instruction_i[31]}}, instruction_i[19:12], instruction_i[20], instruction_i[30:21], 1'b0 };
endfunction
function automatic logic [riscv::VLEN-1:0] i_imm (logic [31:0] instruction_i);
return { {52+riscv::VLEN-64 {instruction_i[31]}}, instruction_i[31:20] };
endfunction
function automatic logic [riscv::VLEN-1:0] sb_imm (logic [31:0] instruction_i);
return { {51+riscv::VLEN-64 {instruction_i[31]}}, instruction_i[31], instruction_i[7], instruction_i[30:25], instruction_i[11:8], 1'b0 };
endfunction
// ----------------------
// LSU Functions
// ----------------------
// align data to address e.g.: shift data to be naturally 64
function automatic riscv::xlen_t data_align (logic [2:0] addr, logic [63:0] data);
// Set addr[2] to 1'b0 when 32bits
logic [2:0] addr_tmp = {(addr[2] && riscv::IS_XLEN64), addr[1:0]};
logic [63:0] data_tmp = {64{1'b0}};
case (addr_tmp)
3'b000: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-1:0]};
3'b001: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-9:0], data[riscv::XLEN-1:riscv::XLEN-8]};
3'b010: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-17:0], data[riscv::XLEN-1:riscv::XLEN-16]};
3'b011: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-25:0], data[riscv::XLEN-1:riscv::XLEN-24]};
3'b100: data_tmp = {data[31:0], data[63:32]};
3'b101: data_tmp = {data[23:0], data[63:24]};
3'b110: data_tmp = {data[15:0], data[63:16]};
3'b111: data_tmp = {data[7:0], data[63:8]};
endcase
return data_tmp[riscv::XLEN-1:0];
endfunction
// generate byte enable mask
function automatic logic [7:0] be_gen(logic [2:0] addr, logic [1:0] size);
case (size)
2'b11: begin
return 8'b1111_1111;
end
2'b10: begin
case (addr[2:0])
3'b000: return 8'b0000_1111;
3'b001: return 8'b0001_1110;
3'b010: return 8'b0011_1100;
3'b011: return 8'b0111_1000;
3'b100: return 8'b1111_0000;
endcase
end
2'b01: begin
case (addr[2:0])
3'b000: return 8'b0000_0011;
3'b001: return 8'b0000_0110;
3'b010: return 8'b0000_1100;
3'b011: return 8'b0001_1000;
3'b100: return 8'b0011_0000;
3'b101: return 8'b0110_0000;
3'b110: return 8'b1100_0000;
endcase
end
2'b00: begin
case (addr[2:0])
3'b000: return 8'b0000_0001;
3'b001: return 8'b0000_0010;
3'b010: return 8'b0000_0100;
3'b011: return 8'b0000_1000;
3'b100: return 8'b0001_0000;
3'b101: return 8'b0010_0000;
3'b110: return 8'b0100_0000;
3'b111: return 8'b1000_0000;
endcase
end
endcase
return 8'b0;
endfunction
function automatic logic [3:0] be_gen_32(logic [1:0] addr, logic [1:0] size);
case (size)
2'b10: begin
return 4'b1111;
end
2'b01: begin
case (addr[1:0])
2'b00: return 4'b0011;
2'b01: return 4'b0110;
2'b10: return 4'b1100;
endcase
end
2'b00: begin
case (addr[1:0])
2'b00: return 4'b0001;
2'b01: return 4'b0010;
2'b10: return 4'b0100;
2'b11: return 4'b1000;
endcase
end
default: return 4'b0;
endcase
return 4'b0;
endfunction
// ----------------------
// Extract Bytes from Op
// ----------------------
function automatic logic [1:0] extract_transfer_size(fu_op op);
case (op)
LD, SD, FLD, FSD,
AMO_LRD, AMO_SCD,
AMO_SWAPD, AMO_ADDD,
AMO_ANDD, AMO_ORD,
AMO_XORD, AMO_MAXD,
AMO_MAXDU, AMO_MIND,
AMO_MINDU: begin
return 2'b11;
end
LW, LWU, SW, FLW, FSW,
AMO_LRW, AMO_SCW,
AMO_SWAPW, AMO_ADDW,
AMO_ANDW, AMO_ORW,
AMO_XORW, AMO_MAXW,
AMO_MAXWU, AMO_MINW,
AMO_MINWU: begin
return 2'b10;
end
LH, LHU, SH, FLH, FSH: return 2'b01;
LB, LBU, SB, FLB, FSB: return 2'b00;
default: return 2'b11;
endcase
endfunction
endpackage
// Copyright 2022 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Fabian Schuiki <[email protected]>
// Florian Zaruba <[email protected]>
// Stefan Mach <[email protected]>
// Thomas Benz <[email protected]>
// Paul Scheffler <[email protected]>
// Wolfgang Roenninger <[email protected]>
//
// AUTOMATICALLY GENERATED by gen_bootrom.py; edit the script instead.
module cheshire_bootrom #(
parameter int unsigned AddrWidth = 32,
parameter int unsigned DataWidth = 32
)(
input logic clk_i,
input logic rst_ni,
input logic req_i,
input logic [AddrWidth-1:0] addr_i,
output logic [DataWidth-1:0] data_o
);
localparam unsigned NumWords = 4096;
logic [$clog2(NumWords)-1:0] word;
assign word = addr_i / (DataWidth / 8);
always_comb begin
data_o = '0;
unique case (word)
000: data_o = 32'h6f020117 /* 0x0000 */;
001: data_o = 32'hff810113 /* 0x0004 */;
002: data_o = 32'h00002197 /* 0x0008 */;
003: data_o = 32'h53018193 /* 0x000c */;
004: data_o = 32'h42014081 /* 0x0010 */;
005: data_o = 32'h43014281 /* 0x0014 */;
006: data_o = 32'h44014381 /* 0x0018 */;
007: data_o = 32'h45014481 /* 0x001c */;
008: data_o = 32'h46014581 /* 0x0020 */;
009: data_o = 32'h47014681 /* 0x0024 */;
010: data_o = 32'h48014781 /* 0x0028 */;
011: data_o = 32'h49014881 /* 0x002c */;
012: data_o = 32'h4a014981 /* 0x0030 */;
013: data_o = 32'h4b014a81 /* 0x0034 */;
014: data_o = 32'h4c014b81 /* 0x0038 */;
015: data_o = 32'h4d014c81 /* 0x003c */;
016: data_o = 32'h4e014d81 /* 0x0040 */;
017: data_o = 32'h4f014e81 /* 0x0044 */;
018: data_o = 32'h01001297 /* 0x0048 */;
019: data_o = 32'hfb828293 /* 0x004c */;
020: data_o = 32'ha023537d /* 0x0050 */;
021: data_o = 32'ha2230062 /* 0x0054 */;
022: data_o = 32'h43050062 /* 0x0058 */;
023: data_o = 32'h0062a823 /* 0x005c */;
024: data_o = 32'h43014281 /* 0x0060 */;
025: data_o = 32'h0000100f /* 0x0064 */;
026: data_o = 32'h13e000ef /* 0x0068 */;
027: data_o = 32'h0506a009 /* 0x006c */;
028: data_o = 32'h00156513 /* 0x0070 */;
029: data_o = 32'h01000297 /* 0x0074 */;
030: data_o = 32'hf8c28293 /* 0x0078 */;
031: data_o = 32'h00a2a223 /* 0x007c */;
032: data_o = 32'h10500073 /* 0x0080 */;
033: data_o = 32'h1141bff5 /* 0x0084 */;
034: data_o = 32'he022e406 /* 0x0088 */;
035: data_o = 32'h00ef842a /* 0x008c */;
036: data_o = 32'h85aa1cc0 /* 0x0090 */;
037: data_o = 32'hbc018513 /* 0x0094 */;
038: data_o = 32'h218010ef /* 0x0098 */;
039: data_o = 32'h00ef8522 /* 0x009c */;
040: data_o = 32'h85aa1920 /* 0x00a0 */;
041: data_o = 32'hbf018513 /* 0x00a4 */;
042: data_o = 32'h208010ef /* 0x00a8 */;
043: data_o = 32'h00ef8522 /* 0x00ac */;
044: data_o = 32'h85aa19e0 /* 0x00b0 */;
045: data_o = 32'hc2018513 /* 0x00b4 */;
046: data_o = 32'h1f8010ef /* 0x00b8 */;
047: data_o = 32'h00ef8522 /* 0x00bc */;
048: data_o = 32'h85aa1800 /* 0x00c0 */;
049: data_o = 32'hc5018513 /* 0x00c4 */;
050: data_o = 32'h1e8010ef /* 0x00c8 */;
051: data_o = 32'h00ef8522 /* 0x00cc */;
052: data_o = 32'h64021540 /* 0x00d0 */;
053: data_o = 32'h85aa60a2 /* 0x00d4 */;
054: data_o = 32'hc8018513 /* 0x00d8 */;
055: data_o = 32'h106f0141 /* 0x00dc */;
056: data_o = 32'h71391d20 /* 0x00e0 */;
057: data_o = 32'h561b85aa /* 0x00e4 */;
058: data_o = 32'h55370015 /* 0x00e8 */;
059: data_o = 32'h00340200 /* 0x00ec */;
060: data_o = 32'h00050513 /* 0x00f0 */;
061: data_o = 32'hf822fc06 /* 0x00f4 */;
062: data_o = 32'hc002f426 /* 0x00f8 */;
063: data_o = 32'h10efc202 /* 0x00fc */;
064: data_o = 32'h00286f20 /* 0x0100 */;
065: data_o = 32'h718010ef /* 0x0104 */;
066: data_o = 32'h000625b7 /* 0x0108 */;
067: data_o = 32'ha8058593 /* 0x010c */;
068: data_o = 32'h10ef0028 /* 0x0110 */;
069: data_o = 32'h45810330 /* 0x0114 */;
070: data_o = 32'h10ef0028 /* 0x0118 */;
071: data_o = 32'h00280710 /* 0x011c */;
072: data_o = 32'h3ff010ef /* 0x0120 */;
073: data_o = 32'hc5b7fd6d /* 0x0124 */;
074: data_o = 32'h859300be /* 0x0128 */;
075: data_o = 32'h0028c205 /* 0x012c */;
076: data_o = 32'h015010ef /* 0x0130 */;
077: data_o = 32'h10ef0028 /* 0x0134 */;
078: data_o = 32'h860a0730 /* 0x0138 */;
079: data_o = 32'h00284581 /* 0x013c */;
080: data_o = 32'h1e3010ef /* 0x0140 */;
081: data_o = 32'h45850050 /* 0x0144 */;
082: data_o = 32'h10ef0028 /* 0x0148 */;
083: data_o = 32'h45821d90 /* 0x014c */;
084: data_o = 32'h700004b7 /* 0x0150 */;
085: data_o = 32'h00048613 /* 0x0154 */;
086: data_o = 32'h002846a1 /* 0x0158 */;
087: data_o = 32'h571010ef /* 0x015c */;
088: data_o = 32'h00048593 /* 0x0160 */;
089: data_o = 32'hcb018513 /* 0x0164 */;
090: data_o = 32'h148010ef /* 0x0168 */;
091: data_o = 32'h44054592 /* 0x016c */;
092: data_o = 32'h86936689 /* 0x0170 */;
093: data_o = 32'h16138006 /* 0x0174 */;
094: data_o = 32'h002801f4 /* 0x0178 */;
095: data_o = 32'h551010ef /* 0x017c */;
096: data_o = 32'h01f41593 /* 0x0180 */;
097: data_o = 32'hcd018513 /* 0x0184 */;
098: data_o = 32'h128010ef /* 0x0188 */;
099: data_o = 32'h0000100f /* 0x018c */;
100: data_o = 32'h047e4601 /* 0x0190 */;
101: data_o = 32'h00048593 /* 0x0194 */;
102: data_o = 32'h94024501 /* 0x0198 */;
103: data_o = 32'h744270e2 /* 0x019c */;
104: data_o = 32'h612174a2 /* 0x01a0 */;
105: data_o = 32'h11418082 /* 0x01a4 */;
106: data_o = 32'h0437e022 /* 0x01a8 */;
107: data_o = 32'h04130200 /* 0x01ac */;
108: data_o = 32'h54080004 /* 0x01b0 */;
109: data_o = 32'h859365f1 /* 0x01b4 */;
110: data_o = 32'he4062005 /* 0x01b8 */;
111: data_o = 32'h146010ef /* 0x01bc */;
112: data_o = 32'h02001537 /* 0x01c0 */;
113: data_o = 32'h00050513 /* 0x01c4 */;
114: data_o = 32'hebfff0ef /* 0x01c8 */;
115: data_o = 32'h47094854 /* 0x01cc */;
116: data_o = 32'h02e68663 /* 0x01d0 */;
117: data_o = 32'h0006879b /* 0x01d4 */;
118: data_o = 32'h00f76a63 /* 0x01d8 */;
119: data_o = 32'h8513cb9d /* 0x01dc */;
120: data_o = 32'h10efd181 /* 0x01e0 */;
121: data_o = 32'h00730ce0 /* 0x01e4 */;
122: data_o = 32'hbff51050 /* 0x01e8 */;
123: data_o = 32'h9c63470d /* 0x01ec */;
124: data_o = 32'h851300e7 /* 0x01f0 */;
125: data_o = 32'h10efd581 /* 0x01f4 */;
126: data_o = 32'hb7f50ba0 /* 0x01f8 */;
127: data_o = 32'hd3818513 /* 0x01fc */;
128: data_o = 32'h0b0010ef /* 0x0200 */;
129: data_o = 32'h484cb7cd /* 0x0204 */;
130: data_o = 32'hd7818513 /* 0x0208 */;
131: data_o = 32'h0a4010ef /* 0x020c */;
132: data_o = 32'h8513bfd9 /* 0x0210 */;
133: data_o = 32'h10efcf01 /* 0x0214 */;
134: data_o = 32'h540809a0 /* 0x0218 */;
135: data_o = 32'hec7ff0ef /* 0x021c */;
136: data_o = 32'h515cb7d9 /* 0x0220 */;
137: data_o = 32'h17825108 /* 0x0224 */;
138: data_o = 32'h91011502 /* 0x0228 */;
139: data_o = 32'h80828d5d /* 0x022c */;
140: data_o = 32'h5508555c /* 0x0230 */;
141: data_o = 32'h15021782 /* 0x0234 */;
142: data_o = 32'h8d5d9101 /* 0x0238 */;
143: data_o = 32'h595c8082 /* 0x023c */;
144: data_o = 32'h17825908 /* 0x0240 */;
145: data_o = 32'h91011502 /* 0x0244 */;
146: data_o = 32'h80828d5d /* 0x0248 */;
147: data_o = 32'h5d085d5c /* 0x024c */;
148: data_o = 32'h15021782 /* 0x0250 */;
149: data_o = 32'h8d5d9101 /* 0x0254 */;
150: data_o = 32'h417c8082 /* 0x0258 */;
151: data_o = 32'h17824128 /* 0x025c */;
152: data_o = 32'h91011502 /* 0x0260 */;
153: data_o = 32'h80828d5d /* 0x0264 */;
154: data_o = 32'h711d8082 /* 0x0268 */;
155: data_o = 32'he0cae4a6 /* 0x026c */;
156: data_o = 32'hf852fc4e /* 0x0270 */;
157: data_o = 32'hf05af456 /* 0x0274 */;
158: data_o = 32'he8628ab2 /* 0x0278 */;
159: data_o = 32'he06ae466 /* 0x027c */;
160: data_o = 32'he8a2ec86 /* 0x0280 */;
161: data_o = 32'hf613ec5e /* 0x0284 */;
162: data_o = 32'h8cc60038 /* 0x0288 */;
163: data_o = 32'h89ae892a /* 0x028c */;
164: data_o = 32'h8b3a8a36 /* 0x0290 */;
165: data_o = 32'h8c428d3e /* 0x0294 */;
166: data_o = 32'he21d84d6 /* 0x0298 */;
167: data_o = 32'h02081793 /* 0x029c */;
168: data_o = 32'h84b39381 /* 0x02a0 */;
169: data_o = 32'h94d641a7 /* 0x02a4 */;
170: data_o = 32'h70638456 /* 0x02a8 */;
171: data_o = 32'h862208fd /* 0x02ac */;
172: data_o = 32'h040586d2 /* 0x02b0 */;
173: data_o = 32'h051385ce /* 0x02b4 */;
174: data_o = 32'h99020200 /* 0x02b8 */;
175: data_o = 32'hfe9419e3 /* 0x02bc */;
176: data_o = 32'h01ab0433 /* 0x02c0 */;
177: data_o = 32'h00848bb3 /* 0x02c4 */;
178: data_o = 32'h000d0d63 /* 0x02c8 */;
179: data_o = 32'hfff44503 /* 0x02cc */;
180: data_o = 32'h408b8633 /* 0x02d0 */;
181: data_o = 32'h147d86d2 /* 0x02d4 */;
182: data_o = 32'h990285ce /* 0x02d8 */;
183: data_o = 32'hfe8b18e3 /* 0x02dc */;
184: data_o = 32'hfc9394ea /* 0x02e0 */;
185: data_o = 32'h8363002c /* 0x02e4 */;
186: data_o = 32'h1c02020c /* 0x02e8 */;
187: data_o = 32'h41548ab3 /* 0x02ec */;
188: data_o = 32'h020c5c13 /* 0x02f0 */;
189: data_o = 32'h018afc63 /* 0x02f4 */;
190: data_o = 32'h0a858626 /* 0x02f8 */;
191: data_o = 32'h85ce86d2 /* 0x02fc */;
192: data_o = 32'h02000513 /* 0x0300 */;
193: data_o = 32'h99020485 /* 0x0304 */;
194: data_o = 32'hff8ae8e3 /* 0x0308 */;
195: data_o = 32'h644660e6 /* 0x030c */;
196: data_o = 32'h79e26906 /* 0x0310 */;
197: data_o = 32'h7aa27a42 /* 0x0314 */;
198: data_o = 32'h6be27b02 /* 0x0318 */;
199: data_o = 32'h6ca26c42 /* 0x031c */;
200: data_o = 32'h85266d02 /* 0x0320 */;
201: data_o = 32'h612564a6 /* 0x0324 */;
202: data_o = 32'h84d68082 /* 0x0328 */;
203: data_o = 32'h715dbf51 /* 0x032c */;
204: data_o = 32'h40e6e486 /* 0x0330 */;
205: data_o = 32'hf44efc26 /* 0x0334 */;
206: data_o = 32'hf84ae0a2 /* 0x0338 */;
207: data_o = 32'h8e3a8ec2 /* 0x033c */;
208: data_o = 32'h84be4846 /* 0x0340 */;
209: data_o = 32'h4000f993 /* 0x0344 */;
210: data_o = 32'h8906e755 /* 0x0348 */;
211: data_o = 32'hfef0f093 /* 0x034c */;
212: data_o = 32'h0a099c63 /* 0x0350 */;
213: data_o = 32'h0200f793 /* 0x0354 */;
214: data_o = 32'h02934901 /* 0x0358 */;
215: data_o = 32'he3d50610 /* 0x035c */;
216: data_o = 32'h870a4781 /* 0x0360 */;
217: data_o = 32'h32d943a5 /* 0x0364 */;
218: data_o = 32'h02000413 /* 0x0368 */;
219: data_o = 32'h8a63a021 /* 0x036c */;
220: data_o = 32'h8e1a0287 /* 0x0370 */;
221: data_o = 32'h03de7f33 /* 0x0374 */;
222: data_o = 32'h0fff7313 /* 0x0378 */;
223: data_o = 32'h03030f9b /* 0x037c */;
224: data_o = 32'h0062833b /* 0x0380 */;
225: data_o = 32'h0ff37313 /* 0x0384 */;
226: data_o = 32'h01e3e463 /* 0x0388 */;
227: data_o = 32'h0ffff313 /* 0x038c */;
228: data_o = 32'h0f330785 /* 0x0390 */;
229: data_o = 32'h0fa300f7 /* 0x0394 */;
230: data_o = 32'h5333fe6f /* 0x0398 */;
231: data_o = 32'h78e303de /* 0x039c */;
232: data_o = 32'hf313fdde /* 0x03a0 */;
233: data_o = 32'h07630020 /* 0x03a4 */;
234: data_o = 32'h0e630603 /* 0x03a8 */;
235: data_o = 32'h97631009 /* 0x03ac */;
236: data_o = 32'hebe90e09 /* 0x03b0 */;
237: data_o = 32'h846347c1 /* 0x03b4 */;
238: data_o = 32'h478920fe /* 0x03b8 */;
239: data_o = 32'h22fe8063 /* 0x03bc */;
240: data_o = 32'h03000793 /* 0x03c0 */;
241: data_o = 32'h00f10023 /* 0x03c4 */;
242: data_o = 32'h8b634785 /* 0x03c8 */;
243: data_o = 32'h84131204 /* 0x03cc */;
244: data_o = 32'h08b30207 /* 0x03d0 */;
245: data_o = 32'h03130024 /* 0x03d4 */;
246: data_o = 32'h802302d0 /* 0x03d8 */;
247: data_o = 32'h0785fe68 /* 0x03dc */;
248: data_o = 32'hf0ef8886 /* 0x03e0 */;
249: data_o = 32'h60a6e89f /* 0x03e4 */;
250: data_o = 32'h74e26406 /* 0x03e8 */;
251: data_o = 32'h79a27942 /* 0x03ec */;
252: data_o = 32'h80826161 /* 0x03f0 */;
253: data_o = 32'h0200f793 /* 0x03f4 */;
254: data_o = 32'h0100f913 /* 0x03f8 */;
255: data_o = 32'h06100293 /* 0x03fc */;
256: data_o = 32'h0293d3a5 /* 0x0400 */;
257: data_o = 32'hbfa90410 /* 0x0404 */;
258: data_o = 32'h00297913 /* 0x0408 */;
259: data_o = 32'h870a4781 /* 0x040c */;
260: data_o = 32'hfa091de3 /* 0x0410 */;
261: data_o = 32'h02089e13 /* 0x0414 */;
262: data_o = 32'h020e5e13 /* 0x0418 */;
263: data_o = 32'hf2938306 /* 0x041c */;
264: data_o = 32'h19630010 /* 0x0420 */;
265: data_o = 32'hf4630a08 /* 0x0424 */;
266: data_o = 32'h031303c7 /* 0x0428 */;
267: data_o = 32'h80630200 /* 0x042c */;
268: data_o = 32'h0f130267 /* 0x0430 */;
269: data_o = 32'h0f930300 /* 0x0434 */;
270: data_o = 32'ha0190200 /* 0x0438 */;
271: data_o = 32'h01f78963 /* 0x043c */;
272: data_o = 32'h03330785 /* 0x0440 */;
273: data_o = 32'h0fa300f7 /* 0x0444 */;
274: data_o = 32'he9e3ffe3 /* 0x0448 */;
275: data_o = 32'h8ee3ffc7 /* 0x044c */;
276: data_o = 32'h1f13f402 /* 0x0450 */;
277: data_o = 32'h5f130208 /* 0x0454 */;
278: data_o = 32'hf8e3020f /* 0x0458 */;
279: data_o = 32'h0313f5e7 /* 0x045c */;
280: data_o = 32'h0f930200 /* 0x0460 */;
281: data_o = 32'h02930300 /* 0x0464 */;
282: data_o = 32'h95630200 /* 0x0468 */;
283: data_o = 32'ha0510067 /* 0x046c */;
284: data_o = 32'h08578163 /* 0x0470 */;
285: data_o = 32'h03330785 /* 0x0474 */;
286: data_o = 32'h0fa300f7 /* 0x0478 */;
287: data_o = 32'h99e3fff3 /* 0x047c */;
288: data_o = 32'hb725ffe7 /* 0x0480 */;
289: data_o = 32'h02089e13 /* 0x0484 */;
290: data_o = 32'h020e5e13 /* 0x0488 */;
291: data_o = 32'h0cfe0b63 /* 0x048c */;
292: data_o = 32'h02081893 /* 0x0490 */;
293: data_o = 32'h0208d893 /* 0x0494 */;
294: data_o = 32'h0cf88563 /* 0x0498 */;
295: data_o = 32'h826348c1 /* 0x049c */;
296: data_o = 32'h48890f1e /* 0x04a0 */;
297: data_o = 32'h0b1e8563 /* 0x04a4 */;
298: data_o = 32'h02000893 /* 0x04a8 */;
299: data_o = 32'hf3178ae3 /* 0x04ac */;
300: data_o = 32'h879388be /* 0x04b0 */;
301: data_o = 32'h83330208 /* 0x04b4 */;
302: data_o = 32'h87930027 /* 0x04b8 */;
303: data_o = 32'h08930018 /* 0x04bc */;
304: data_o = 32'h00230300 /* 0x04c0 */;
305: data_o = 32'h0893ff13 /* 0x04c4 */;
306: data_o = 32'h90e30200 /* 0x04c8 */;
307: data_o = 32'h0793f117 /* 0x04cc */;
308: data_o = 32'hb7390200 /* 0x04d0 */;
309: data_o = 32'h04028863 /* 0x04d4 */;
310: data_o = 32'h7313e0d9 /* 0x04d8 */;
311: data_o = 32'h106300c3 /* 0x04dc */;
312: data_o = 32'hf8e30803 /* 0x04e0 */;
313: data_o = 32'h0313f7c7 /* 0x04e4 */;
314: data_o = 32'h94e30200 /* 0x04e8 */;
315: data_o = 32'hfee3f467 /* 0x04ec */;
316: data_o = 32'h0ee3eb07 /* 0x04f0 */;
317: data_o = 32'h0793fc09 /* 0x04f4 */;
318: data_o = 32'h89e30200 /* 0x04f8 */;
319: data_o = 32'hbf79f809 /* 0x04fc */;
320: data_o = 32'h0040f893 /* 0x0500 */;
321: data_o = 32'h02089b63 /* 0x0504 */;
322: data_o = 32'h0080f893 /* 0x0508 */;
323: data_o = 32'hec088ae3 /* 0x050c */;
324: data_o = 32'h02078413 /* 0x0510 */;
325: data_o = 32'h002408b3 /* 0x0514 */;
326: data_o = 32'h02000313 /* 0x0518 */;
327: data_o = 32'hfe688023 /* 0x051c */;
328: data_o = 32'hbd7d0785 /* 0x0520 */;
329: data_o = 32'he9c7f3e3 /* 0x0524 */;
330: data_o = 32'h02000313 /* 0x0528 */;
331: data_o = 32'hf06793e3 /* 0x052c */;
332: data_o = 32'he6091fe3 /* 0x0530 */;
333: data_o = 32'h02000793 /* 0x0534 */;
334: data_o = 32'h8413b565 /* 0x0538 */;
335: data_o = 32'h08b30207 /* 0x053c */;
336: data_o = 32'h03130024 /* 0x0540 */;
337: data_o = 32'h802302b0 /* 0x0544 */;
338: data_o = 32'h0785fe68 /* 0x0548 */;
339: data_o = 32'h0893bd51 /* 0x054c */;
340: data_o = 32'h87e30200 /* 0x0550 */;
341: data_o = 32'h08b3e917 /* 0x0554 */;
342: data_o = 32'h078500f7 /* 0x0558 */;
343: data_o = 32'h387da831 /* 0x055c */;
344: data_o = 32'h8893b749 /* 0x0560 */;
345: data_o = 32'h87e3fff7 /* 0x0564 */;
346: data_o = 32'h4341e408 /* 0x0568 */;
347: data_o = 32'h066e8e63 /* 0x056c */;
348: data_o = 32'h90e34309 /* 0x0570 */;
349: data_o = 32'h98baf46e /* 0x0574 */;
350: data_o = 32'h06200313 /* 0x0578 */;
351: data_o = 32'h00688023 /* 0x057c */;
352: data_o = 32'hf893b725 /* 0x0580 */;
353: data_o = 32'h9e630200 /* 0x0584 */;
354: data_o = 32'h08930008 /* 0x0588 */;
355: data_o = 32'h89e30200 /* 0x058c */;
356: data_o = 32'h0333e517 /* 0x0590 */;
357: data_o = 32'h078500f7 /* 0x0594 */;
358: data_o = 32'h07800893 /* 0x0598 */;
359: data_o = 32'h01130023 /* 0x059c */;
360: data_o = 32'h0893b721 /* 0x05a0 */;
361: data_o = 32'h8de30200 /* 0x05a4 */;
362: data_o = 32'h8413e317 /* 0x05a8 */;
363: data_o = 32'h08b30207 /* 0x05ac */;
364: data_o = 32'h03130024 /* 0x05b0 */;
365: data_o = 32'h80230580 /* 0x05b4 */;
366: data_o = 32'h0785fe68 /* 0x05b8 */;
367: data_o = 32'hf793b5f5 /* 0x05bc */;
368: data_o = 32'he7990200 /* 0x05c0 */;
369: data_o = 32'h07800793 /* 0x05c4 */;
370: data_o = 32'h00f10023 /* 0x05c8 */;
371: data_o = 32'hb5d54885 /* 0x05cc */;
372: data_o = 32'h05800793 /* 0x05d0 */;
373: data_o = 32'h00f10023 /* 0x05d4 */;
374: data_o = 32'hbde14885 /* 0x05d8 */;
375: data_o = 32'h06200793 /* 0x05dc */;
376: data_o = 32'h00f10023 /* 0x05e0 */;
377: data_o = 32'hb5f14885 /* 0x05e4 */;
378: data_o = 32'h0200f313 /* 0x05e8 */;
379: data_o = 32'h1ee317f9 /* 0x05ec */;
380: data_o = 32'h0333fa03 /* 0x05f0 */;
381: data_o = 32'h87c600f7 /* 0x05f4 */;
382: data_o = 32'h28d3b745 /* 0x05f8 */;
383: data_o = 32'h7159a2a5 /* 0x05fc */;
384: data_o = 32'heca6f0a2 /* 0x0600 */;
385: data_o = 32'he4cee8ca /* 0x0604 */;
386: data_o = 32'hfc56e0d2 /* 0x0608 */;
387: data_o = 32'hf85af486 /* 0x060c */;
388: data_o = 32'hf062f45e /* 0x0610 */;
389: data_o = 32'h89aaec66 /* 0x0614 */;
390: data_o = 32'h84328a2e /* 0x0618 */;
391: data_o = 32'h893e8ab6 /* 0x061c */;
392: data_o = 32'h8d6384c2 /* 0x0620 */;
393: data_o = 32'h27972608 /* 0x0624 */;
394: data_o = 32'hb7870000 /* 0x0628 */;
395: data_o = 32'h97d32a27 /* 0x062c */;
396: data_o = 32'h9563a2a7 /* 0x0630 */;
397: data_o = 32'h27972607 /* 0x0634 */;
398: data_o = 32'hb7870000 /* 0x0638 */;
399: data_o = 32'h17d329a7 /* 0x063c */;
400: data_o = 32'h9d63a2f5 /* 0x0640 */;
401: data_o = 32'h07d32407 /* 0x0644 */;
402: data_o = 32'h06d3f200 /* 0x0648 */;
403: data_o = 32'h17d3e205 /* 0x064c */;
404: data_o = 32'hc789a2f5 /* 0x0650 */;
405: data_o = 32'h22a517d3 /* 0x0654 */;
406: data_o = 32'he20786d3 /* 0x0658 */;
407: data_o = 32'h4004f613 /* 0x065c */;
408: data_o = 32'h4719e211 /* 0x0660 */;
409: data_o = 32'h0346d793 /* 0x0664 */;
410: data_o = 32'h7ff7f793 /* 0x0668 */;
411: data_o = 32'hc017879b /* 0x066c */;
412: data_o = 32'hd2078753 /* 0x0670 */;
413: data_o = 32'h3ff00593 /* 0x0674 */;
414: data_o = 32'h00c69793 /* 0x0678 */;
415: data_o = 32'h83b115d2 /* 0x067c */;
416: data_o = 32'h25978fcd /* 0x0680 */;
417: data_o = 32'hb6870000 /* 0x0684 */;
418: data_o = 32'h25972565 /* 0x0688 */;
419: data_o = 32'hb7870000 /* 0x068c */;
420: data_o = 32'h25972565 /* 0x0690 */;
421: data_o = 32'h25170000 /* 0x0694 */;
422: data_o = 32'h77430000 /* 0x0698 */;
423: data_o = 32'h86d37ad7 /* 0x069c */;
424: data_o = 32'hb787f207 /* 0x06a0 */;
425: data_o = 32'h27972565 /* 0x06a4 */;
426: data_o = 32'hf7d30000 /* 0x06a8 */;
427: data_o = 32'hb6870af6 /* 0x06ac */;
428: data_o = 32'h279724a7 /* 0x06b0 */;
429: data_o = 32'hb5870000 /* 0x06b4 */;
430: data_o = 32'h279726e7 /* 0x06b8 */;
431: data_o = 32'hf7c30000 /* 0x06bc */;
432: data_o = 32'hb70772d7 /* 0x06c0 */;
433: data_o = 32'h279723e7 /* 0x06c4 */;
434: data_o = 32'hb6870000 /* 0x06c8 */;
435: data_o = 32'h95d323a7 /* 0x06cc */;
436: data_o = 32'h87d3c207 /* 0x06d0 */;
437: data_o = 32'h8c1bd205 /* 0x06d4 */;
438: data_o = 32'hf7430005 /* 0x06d8 */;
439: data_o = 32'h36876ae7 /* 0x06dc */;
440: data_o = 32'h25172725 /* 0x06e0 */;
441: data_o = 32'h17d30000 /* 0x06e4 */;
442: data_o = 32'h8753c207 /* 0x06e8 */;
443: data_o = 32'h879bd207 /* 0x06ec */;
444: data_o = 32'h17d23ff7 /* 0x06f0 */;
445: data_o = 32'h12d77753 /* 0x06f4 */;
446: data_o = 32'h22e53687 /* 0x06f8 */;
447: data_o = 32'h00002517 /* 0x06fc */;
448: data_o = 32'h23453607 /* 0x0700 */;
449: data_o = 32'h00002517 /* 0x0704 */;
450: data_o = 32'h72d7f7c7 /* 0x0708 */;
451: data_o = 32'h21453707 /* 0x070c */;
452: data_o = 32'h00002517 /* 0x0710 */;
453: data_o = 32'h21853007 /* 0x0714 */;
454: data_o = 32'h00002517 /* 0x0718 */;
455: data_o = 32'h12f7f6d3 /* 0x071c */;
456: data_o = 32'h0af67653 /* 0x0720 */;
457: data_o = 32'h02f7f7d3 /* 0x0724 */;
458: data_o = 32'h1ae6f753 /* 0x0728 */;
459: data_o = 32'h02b77753 /* 0x072c */;
460: data_o = 32'h1ae6f753 /* 0x0730 */;
461: data_o = 32'h02077753 /* 0x0734 */;
462: data_o = 32'h1ae6f6d3 /* 0x0738 */;
463: data_o = 32'h22053707 /* 0x073c */;
464: data_o = 32'h02c6f6d3 /* 0x0740 */;
465: data_o = 32'h1ad7f7d3 /* 0x0744 */;
466: data_o = 32'h02e7f7d3 /* 0x0748 */;
467: data_o = 32'hf2078753 /* 0x074c */;
468: data_o = 32'h12e7f7d3 /* 0x0750 */;
469: data_o = 32'hf2068753 /* 0x0754 */;
470: data_o = 32'ha2f717d3 /* 0x0758 */;
471: data_o = 32'he20788d3 /* 0x075c */;
472: data_o = 32'hf7d3c799 /* 0x0760 */;
473: data_o = 32'h8c1b1ab7 /* 0x0764 */;
474: data_o = 32'h88d3fff5 /* 0x0768 */;
475: data_o = 32'h0c9be207 /* 0x076c */;
476: data_o = 32'hd793063c /* 0x0770 */;
477: data_o = 32'h059300b4 /* 0x0774 */;
478: data_o = 32'hbcb30c60 /* 0x0778 */;
479: data_o = 32'h8b850195 /* 0x077c */;
480: data_o = 32'hc3a10c91 /* 0x0780 */;
481: data_o = 32'h00002797 /* 0x0784 */;
482: data_o = 32'h1bc7b787 /* 0x0788 */;
483: data_o = 32'hf2068753 /* 0x078c */;
484: data_o = 32'ha2e787d3 /* 0x0790 */;
485: data_o = 32'h14078063 /* 0x0794 */;
486: data_o = 32'h00002797 /* 0x0798 */;
487: data_o = 32'h1b07b787 /* 0x079c */;
488: data_o = 32'ha2f717d3 /* 0x07a0 */;
489: data_o = 32'h12078863 /* 0x07a4 */;
490: data_o = 32'h0007079b /* 0x07a8 */;
491: data_o = 32'h56634701 /* 0x07ac */;
492: data_o = 32'h87bb00fc /* 0x07b0 */;
493: data_o = 32'h871b4187 /* 0x07b4 */;
494: data_o = 32'he493fff7 /* 0x07b8 */;
495: data_o = 32'h4c814004 /* 0x07bc */;
496: data_o = 32'h47814c01 /* 0x07c0 */;
497: data_o = 32'h012cf463 /* 0x07c4 */;
498: data_o = 32'h419907bb /* 0x07c8 */;
499: data_o = 32'h0024fb93 /* 0x07cc */;
500: data_o = 32'h000b8763 /* 0x07d0 */;
501: data_o = 32'h001cb613 /* 0x07d4 */;
502: data_o = 32'h40c00633 /* 0x07d8 */;
503: data_o = 32'h12638ff1 /* 0x07dc */;
504: data_o = 32'h07d30e0c /* 0x07e0 */;
505: data_o = 32'h1653f200 /* 0x07e4 */;
506: data_o = 32'hc619a2f5 /* 0x07e8 */;
507: data_o = 32'hf20687d3 /* 0x07ec */;
508: data_o = 32'h22f797d3 /* 0x07f0 */;
509: data_o = 32'he20786d3 /* 0x07f4 */;
510: data_o = 32'hf2068553 /* 0x07f8 */;
511: data_o = 32'h0813787d /* 0x07fc */;
512: data_o = 32'hf8337ff8 /* 0x0800 */;
513: data_o = 32'h86d60104 /* 0x0804 */;
514: data_o = 32'h85d28622 /* 0x0808 */;
515: data_o = 32'h00ef854e /* 0x080c */;
516: data_o = 32'h8b2a0d20 /* 0x0810 */;
517: data_o = 32'h060c8663 /* 0x0814 */;
518: data_o = 32'h0204f493 /* 0x0818 */;
519: data_o = 32'h04500513 /* 0x081c */;
520: data_o = 32'h0513e099 /* 0x0820 */;
521: data_o = 32'h865a0650 /* 0x0824 */;
522: data_o = 32'h85d286d6 /* 0x0828 */;
523: data_o = 32'h571b9982 /* 0x082c */;
524: data_o = 32'h46b341fc /* 0x0830 */;
525: data_o = 32'h479500ec /* 0x0834 */;
526: data_o = 32'h06133cfd /* 0x0838 */;
527: data_o = 32'he43e001b /* 0x083c */;
528: data_o = 32'h40e6873b /* 0x0840 */;
529: data_o = 32'h4881e066 /* 0x0844 */;
530: data_o = 32'h579b4829 /* 0x0848 */;
531: data_o = 32'h86d601fc /* 0x084c */;
532: data_o = 32'h854e85d2 /* 0x0850 */;
533: data_o = 32'hadbff0ef /* 0x0854 */;
534: data_o = 32'h83638b2a /* 0x0858 */;
535: data_o = 32'h1902020b /* 0x085c */;
536: data_o = 32'h40850433 /* 0x0860 */;
537: data_o = 32'h02095913 /* 0x0864 */;
538: data_o = 32'h01247c63 /* 0x0868 */;
539: data_o = 32'h0405865a /* 0x086c */;
540: data_o = 32'h85d286d6 /* 0x0870 */;
541: data_o = 32'h02000513 /* 0x0874 */;
542: data_o = 32'h99820b05 /* 0x0878 */;
543: data_o = 32'hff2468e3 /* 0x087c */;
544: data_o = 32'h740670a6 /* 0x0880 */;
545: data_o = 32'h694664e6 /* 0x0884 */;
546: data_o = 32'h6a0669a6 /* 0x0888 */;
547: data_o = 32'h7ba27ae2 /* 0x088c */;
548: data_o = 32'h6ce27c02 /* 0x0890 */;
549: data_o = 32'h7b42855a /* 0x0894 */;
550: data_o = 32'h80826165 /* 0x0898 */;
551: data_o = 32'h74068622 /* 0x089c */;
552: data_o = 32'h7b4270a6 /* 0x08a0 */;
553: data_o = 32'h7c027ba2 /* 0x08a4 */;
554: data_o = 32'h88266ce2 /* 0x08a8 */;
555: data_o = 32'h64e687ca /* 0x08ac */;
556: data_o = 32'h86d66946 /* 0x08b0 */;
557: data_o = 32'h7ae285d2 /* 0x08b4 */;
558: data_o = 32'h854e6a06 /* 0x08b8 */;
559: data_o = 32'h616569a6 /* 0x08bc */;
560: data_o = 32'h87d3a005 /* 0x08c0 */;
561: data_o = 32'h8753f206 /* 0x08c4 */;
562: data_o = 32'hf7d3f208 /* 0x08c8 */;
563: data_o = 32'h86d31ae7 /* 0x08cc */;
564: data_o = 32'hbf01e207 /* 0x08d0 */;
565: data_o = 32'hee0707e3 /* 0x08d4 */;
566: data_o = 32'hee0605e3 /* 0x08d8 */;
567: data_o = 32'hb5d5377d /* 0x08dc */;
568: data_o = 32'ha2a52353 /* 0x08e0 */;
569: data_o = 32'h88c28fbe /* 0x08e4 */;
570: data_o = 32'h18030763 /* 0x08e8 */;
571: data_o = 32'h00002797 /* 0x08ec */;
572: data_o = 32'hfe47b787 /* 0x08f0 */;
573: data_o = 32'ha2f517d3 /* 0x08f4 */;
574: data_o = 32'h24079663 /* 0x08f8 */;
575: data_o = 32'h00002797 /* 0x08fc */;
576: data_o = 32'hfcc7b787 /* 0x0900 */;
577: data_o = 32'hf8227139 /* 0x0904 */;
578: data_o = 32'ha2a797d3 /* 0x0908 */;
579: data_o = 32'hfc06f426 /* 0x090c */;
580: data_o = 32'h83ae82aa /* 0x0910 */;
581: data_o = 32'h84b68432 /* 0x0914 */;
582: data_o = 32'h12079c63 /* 0x0918 */;
583: data_o = 32'h00002797 /* 0x091c */;
584: data_o = 32'h0347b787 /* 0x0920 */;
585: data_o = 32'ha2a797d3 /* 0x0924 */;
586: data_o = 32'h20079363 /* 0x0928 */;
587: data_o = 32'h00002797 /* 0x092c */;
588: data_o = 32'h02c7b787 /* 0x0930 */;
589: data_o = 32'ha2f517d3 /* 0x0934 */;
590: data_o = 32'h1e079b63 /* 0x0938 */;
591: data_o = 32'hf20007d3 /* 0x093c */;
592: data_o = 32'h17d34581 /* 0x0940 */;
593: data_o = 32'h9063a2f5 /* 0x0944 */;
594: data_o = 32'hf7931e07 /* 0x0948 */;
595: data_o = 32'he3914008 /* 0x094c */;
596: data_o = 32'h43014719 /* 0x0950 */;
597: data_o = 32'h061347a5 /* 0x0954 */;
598: data_o = 32'h06930300 /* 0x0958 */;
599: data_o = 32'hfa630200 /* 0x095c */;
600: data_o = 32'h030500e7 /* 0x0960 */;
601: data_o = 32'h00610e33 /* 0x0964 */;
602: data_o = 32'hfece0fa3 /* 0x0968 */;
603: data_o = 32'h18e3377d /* 0x096c */;
604: data_o = 32'h16d3fed3 /* 0x0970 */;
605: data_o = 32'h1513c205 /* 0x0974 */;
606: data_o = 32'h87d30207 /* 0x0978 */;
607: data_o = 32'h8793d206 /* 0x097c */;
608: data_o = 32'h5613f581 /* 0x0980 */;
609: data_o = 32'h77d301d5 /* 0x0984 */;
610: data_o = 32'h97b20af5 /* 0x0988 */;
611: data_o = 32'h27972394 /* 0x098c */;
612: data_o = 32'hb7070000 /* 0x0990 */;
613: data_o = 32'h8e1bf727 /* 0x0994 */;
614: data_o = 32'hf7d30006 /* 0x0998 */;
615: data_o = 32'h9f5312d7 /* 0x099c */;
616: data_o = 32'h7653c237 /* 0x09a0 */;
617: data_o = 32'hf7d3d23f /* 0x09a4 */;
618: data_o = 32'h17d30ac7 /* 0x09a8 */;
619: data_o = 32'hcfe1a2f7 /* 0x09ac */;
620: data_o = 32'h77d30f05 /* 0x09b0 */;
621: data_o = 32'h87d3d23f /* 0x09b4 */;
622: data_o = 32'hc781a2f6 /* 0x09b8 */;
623: data_o = 32'h00168e1b /* 0x09bc */;
624: data_o = 32'heb694f01 /* 0x09c0 */;
625: data_o = 32'hd20e07d3 /* 0x09c4 */;
626: data_o = 32'h00002797 /* 0x09c8 */;
627: data_o = 32'hf387b707 /* 0x09cc */;
628: data_o = 32'h0af57553 /* 0x09d0 */;
629: data_o = 32'ha2e517d3 /* 0x09d4 */;
630: data_o = 32'h17d3c781 /* 0x09d8 */;
631: data_o = 32'hc789a2a7 /* 0x09dc */;
632: data_o = 32'h001e7793 /* 0x09e0 */;
633: data_o = 32'h2e05c391 /* 0x09e4 */;
634: data_o = 32'h02000613 /* 0x09e8 */;
635: data_o = 32'h0f6347a9 /* 0x09ec */;
636: data_o = 32'h673b0cc3 /* 0x09f0 */;
637: data_o = 32'h030502fe /* 0x09f4 */;
638: data_o = 32'h006106b3 /* 0x09f8 */;
639: data_o = 32'h02fe4e3b /* 0x09fc */;
640: data_o = 32'h0307071b /* 0x0a00 */;
641: data_o = 32'hfee68fa3 /* 0x0a04 */;
642: data_o = 32'hfe0e13e3 /* 0x0a08 */;
643: data_o = 32'h0038f793 /* 0x0a0c */;
644: data_o = 32'h89634705 /* 0x0a10 */;
645: data_o = 32'h07131ce7 /* 0x0a14 */;
646: data_o = 32'h0e630200 /* 0x0a18 */;
647: data_o = 32'h8b631ae3 /* 0x0a1c */;
648: data_o = 32'h07931205 /* 0x0a20 */;
649: data_o = 32'h87330203 /* 0x0a24 */;
650: data_o = 32'h06930027 /* 0x0a28 */;
651: data_o = 32'h079302d0 /* 0x0a2c */;
652: data_o = 32'h00230013 /* 0x0a30 */;
653: data_o = 32'h870afed7 /* 0x0a34 */;
654: data_o = 32'h862286a6 /* 0x0a38 */;
655: data_o = 32'h859e887e /* 0x0a3c */;
656: data_o = 32'hf0ef8516 /* 0x0a40 */;
657: data_o = 32'h70e2829f /* 0x0a44 */;
658: data_o = 32'h74a27442 /* 0x0a48 */;
659: data_o = 32'h80826121 /* 0x0a4c */;
660: data_o = 32'h00487793 /* 0x0a50 */;
661: data_o = 32'h2717e3f9 /* 0x0a54 */;
662: data_o = 32'h07130000 /* 0x0a58 */;
663: data_o = 32'h478d8827 /* 0x0a5c */;
664: data_o = 32'h74428622 /* 0x0a60 */;
665: data_o = 32'h86a670e2 /* 0x0a64 */;
666: data_o = 32'h887e74a2 /* 0x0a68 */;
667: data_o = 32'h8516859e /* 0x0a6c */;
668: data_o = 32'hf06f6121 /* 0x0a70 */;
669: data_o = 32'h2717ff8f /* 0x0a74 */;
670: data_o = 32'h883e0000 /* 0x0a78 */;
671: data_o = 32'h86a70713 /* 0x0a7c */;
672: data_o = 32'hf06f478d /* 0x0a80 */;
673: data_o = 32'h97d3fe8f /* 0x0a84 */;
674: data_o = 32'hff85a2e7 /* 0x0a88 */;
675: data_o = 32'h120f1f63 /* 0x0a8c */;
676: data_o = 32'hdb0d0f05 /* 0x0a90 */;
677: data_o = 32'hfe07081b /* 0x0a94 */;
678: data_o = 32'h0068083b /* 0x0a98 */;
679: data_o = 32'h40a546a9 /* 0x0a9c */;
680: data_o = 32'h77b3a005 /* 0x0aa0 */;
681: data_o = 32'h051b02df /* 0x0aa4 */;
682: data_o = 32'h879bfff7 /* 0x0aa8 */;
683: data_o = 32'h0fa30307 /* 0x0aac */;
684: data_o = 32'h57b3fef6 /* 0x0ab0 */;
685: data_o = 32'hff6302df /* 0x0ab4 */;
686: data_o = 32'h872a0be0 /* 0x0ab8 */;
687: data_o = 32'h8f3e8376 /* 0x0abc */;
688: data_o = 32'h00130e93 /* 0x0ac0 */;
689: data_o = 32'h01d10633 /* 0x0ac4 */;
690: data_o = 32'hfd071de3 /* 0x0ac8 */;
691: data_o = 32'h0038f793 /* 0x0acc */;
692: data_o = 32'h92634705 /* 0x0ad0 */;
693: data_o = 32'h079310e7 /* 0x0ad4 */;
694: data_o = 32'h8ee30200 /* 0x0ad8 */;
695: data_o = 32'h9f63f40f /* 0x0adc */;
696: data_o = 32'hf7130e05 /* 0x0ae0 */;
697: data_o = 32'hdb2100c8 /* 0x0ae4 */;
698: data_o = 32'h93133ffd /* 0x0ae8 */;
699: data_o = 32'h5313020f /* 0x0aec */;
700: data_o = 32'hf2630203 /* 0x0af0 */;
701: data_o = 32'h07131067 /* 0x0af4 */;
702: data_o = 32'h06130200 /* 0x0af8 */;
703: data_o = 32'h06930300 /* 0x0afc */;
704: data_o = 32'h8ae30200 /* 0x0b00 */;
705: data_o = 32'h0785f2e7 /* 0x0b04 */;
706: data_o = 32'h00f10733 /* 0x0b08 */;
707: data_o = 32'hfec70fa3 /* 0x0b0c */;
708: data_o = 32'hf06783e3 /* 0x0b10 */;
709: data_o = 32'hfed799e3 /* 0x0b14 */;
710: data_o = 32'h1717bf39 /* 0x0b18 */;
711: data_o = 32'h07130000 /* 0x0b1c */;
712: data_o = 32'h47917b67 /* 0x0b20 */;
713: data_o = 32'hf553bf35 /* 0x0b24 */;
714: data_o = 32'h45850aa7 /* 0x0b28 */;
715: data_o = 32'h8622bd39 /* 0x0b2c */;
716: data_o = 32'h70e27442 /* 0x0b30 */;
717: data_o = 32'h74a286a6 /* 0x0b34 */;
718: data_o = 32'h87fe8846 /* 0x0b38 */;
719: data_o = 32'h8516859e /* 0x0b3c */;
720: data_o = 32'hbc656121 /* 0x0b40 */;
721: data_o = 32'h00001717 /* 0x0b44 */;
722: data_o = 32'h4791887e /* 0x0b48 */;
723: data_o = 32'h7a470713 /* 0x0b4c */;
724: data_o = 32'hf1aff06f /* 0x0b50 */;
725: data_o = 32'h0048f793 /* 0x0b54 */;
726: data_o = 32'hf693efb1 /* 0x0b58 */;
727: data_o = 32'h879a0088 /* 0x0b5c */;
728: data_o = 32'hec068be3 /* 0x0b60 */;
729: data_o = 32'h02030693 /* 0x0b64 */;
730: data_o = 32'h00268333 /* 0x0b68 */;
731: data_o = 32'h00230785 /* 0x0b6c */;
732: data_o = 32'hb5d1fee3 /* 0x0b70 */;
733: data_o = 32'h02000793 /* 0x0b74 */;
734: data_o = 32'hf4fe8ae3 /* 0x0b78 */;
735: data_o = 32'hc12d3779 /* 0x0b7c */;
736: data_o = 32'h93011702 /* 0x0b80 */;
737: data_o = 32'h933a0309 /* 0x0b84 */;
738: data_o = 32'h03000693 /* 0x0b88 */;
739: data_o = 32'h02000713 /* 0x0b8c */;
740: data_o = 32'h07b30e85 /* 0x0b90 */;
741: data_o = 32'h8fa301d1 /* 0x0b94 */;
742: data_o = 32'h89e3fed7 /* 0x0b98 */;
743: data_o = 32'h99e3f2ee /* 0x0b9c */;
744: data_o = 32'h0793fe6e /* 0x0ba0 */;
745: data_o = 32'h978a0203 /* 0x0ba4 */;
746: data_o = 32'h02e00713 /* 0x0ba8 */;
747: data_o = 32'h80230305 /* 0x0bac */;
748: data_o = 32'hbd1dfee7 /* 0x0bb0 */;
749: data_o = 32'h02030793 /* 0x0bb4 */;
750: data_o = 32'h00278733 /* 0x0bb8 */;
751: data_o = 32'h02b00693 /* 0x0bbc */;
752: data_o = 32'h00130793 /* 0x0bc0 */;
753: data_o = 32'hfed70023 /* 0x0bc4 */;
754: data_o = 32'h7793b5bd /* 0x0bc8 */;
755: data_o = 32'h8ae3001f /* 0x0bcc */;
756: data_o = 32'h0f05de07 /* 0x0bd0 */;
757: data_o = 32'h0793bd7d /* 0x0bd4 */;
758: data_o = 32'hbdb10200 /* 0x0bd8 */;
759: data_o = 32'hbda13ffd /* 0x0bdc */;
760: data_o = 32'hb7c18376 /* 0x0be0 */;
761: data_o = 32'he20f89e3 /* 0x0be4 */;
762: data_o = 32'hf713e989 /* 0x0be8 */;
763: data_o = 32'h879a00c8 /* 0x0bec */;
764: data_o = 32'hee070de3 /* 0x0bf0 */;
765: data_o = 32'h833ebdd5 /* 0x0bf4 */;
766: data_o = 32'h879abd39 /* 0x0bf8 */;
767: data_o = 32'he111b5f5 /* 0x0bfc */;
768: data_o = 32'ha5cd8082 /* 0x0c00 */;
769: data_o = 32'hed267171 /* 0x0c04 */;
770: data_o = 32'he54ee94a /* 0x0c08 */;
771: data_o = 32'hf0e2f8da /* 0x0c0c */;
772: data_o = 32'hfffff997 /* 0x0c10 */;
773: data_o = 32'hf122f506 /* 0x0c14 */;
774: data_o = 32'hfcd6e152 /* 0x0c18 */;
775: data_o = 32'hece6f4de /* 0x0c1c */;
776: data_o = 32'he4eee8ea /* 0x0c20 */;
777: data_o = 32'h84b2892e /* 0x0c24 */;
778: data_o = 32'h8c3a8b36 /* 0x0c28 */;
779: data_o = 32'h65898993 /* 0x0c2c */;
780: data_o = 32'h89aac191 /* 0x0c30 */;
781: data_o = 32'h000b4503 /* 0x0c34 */;
782: data_o = 32'h01634b81 /* 0x0c38 */;
783: data_o = 32'h67c15205 /* 0x0c3c */;
784: data_o = 32'h6aa517fd /* 0x0c40 */;
785: data_o = 32'h8793f83e /* 0x0c44 */;
786: data_o = 32'hec3e041a /* 0x0c48 */;
787: data_o = 32'h87936785 /* 0x0c4c */;
788: data_o = 32'h0a138007 /* 0x0c50 */;
789: data_o = 32'hf43e0250 /* 0x0c54 */;
790: data_o = 32'h865ea811 /* 0x0c58 */;
791: data_o = 32'h85ca86a6 /* 0x0c5c */;
792: data_o = 32'h99820b85 /* 0x0c60 */;
793: data_o = 32'h000b4503 /* 0x0c64 */;
794: data_o = 32'h12050263 /* 0x0c68 */;
795: data_o = 32'h16e30b05 /* 0x0c6c */;
796: data_o = 32'h4801ff45 /* 0x0c70 */;
797: data_o = 32'h45034641 /* 0x0c74 */;
798: data_o = 32'h0693000b /* 0x0c78 */;
799: data_o = 32'h079b001b /* 0x0c7c */;
800: data_o = 32'hf793fe05 /* 0x0c80 */;
801: data_o = 32'h69630ff7 /* 0x0c84 */;
802: data_o = 32'h871300f6 /* 0x0c88 */;
803: data_o = 32'h078adb81 /* 0x0c8c */;
804: data_o = 32'h439c97ba /* 0x0c90 */;
805: data_o = 32'h878297ba /* 0x0c94 */;
806: data_o = 32'hfd05079b /* 0x0c98 */;
807: data_o = 32'h0ff7f793 /* 0x0c9c */;
808: data_o = 32'h73634725 /* 0x0ca0 */;
809: data_o = 32'h071314f7 /* 0x0ca4 */;
810: data_o = 32'h4a8102a0 /* 0x0ca8 */;
811: data_o = 32'h16e50463 /* 0x0cac */;
812: data_o = 32'h02e00713 /* 0x0cb0 */;
813: data_o = 32'h06634401 /* 0x0cb4 */;
814: data_o = 32'h071b10e5 /* 0x0cb8 */;
815: data_o = 32'h7713f985 /* 0x0cbc */;
816: data_o = 32'h46490ff7 /* 0x0cc0 */;
817: data_o = 32'h00e66e63 /* 0x0cc4 */;
818: data_o = 32'hdfc18613 /* 0x0cc8 */;
819: data_o = 32'h9732070a /* 0x0ccc */;
820: data_o = 32'h97324318 /* 0x0cd0 */;
821: data_o = 32'h45038702 /* 0x0cd4 */;
822: data_o = 32'h6813001b /* 0x0cd8 */;
823: data_o = 32'h06851008 /* 0x0cdc */;
824: data_o = 32'h06700713 /* 0x0ce0 */;
825: data_o = 32'h69638b36 /* 0x0ce4 */;
826: data_o = 32'h071304a7 /* 0x0ce8 */;
827: data_o = 32'h76e30240 /* 0x0cec */;
828: data_o = 32'h071bf6a7 /* 0x0cf0 */;
829: data_o = 32'h7713fdb5 /* 0x0cf4 */;
830: data_o = 32'h06930ff7 /* 0x0cf8 */;
831: data_o = 32'heee30420 /* 0x0cfc */;
832: data_o = 32'h8693f4e6 /* 0x0d00 */;
833: data_o = 32'h070ae481 /* 0x0d04 */;
834: data_o = 32'h43189736 /* 0x0d08 */;
835: data_o = 32'h87029736 /* 0x0d0c */;
836: data_o = 32'h00186813 /* 0x0d10 */;
837: data_o = 32'hb7858b36 /* 0x0d14 */;
838: data_o = 32'h00286813 /* 0x0d18 */;
839: data_o = 32'hbfa18b36 /* 0x0d1c */;
840: data_o = 32'h00486813 /* 0x0d20 */;
841: data_o = 32'hbf818b36 /* 0x0d24 */;
842: data_o = 32'h01086813 /* 0x0d28 */;
843: data_o = 32'hb7a18b36 /* 0x0d2c */;
844: data_o = 32'h00886813 /* 0x0d30 */;
845: data_o = 32'hb7818b36 /* 0x0d34 */;
846: data_o = 32'hf975071b /* 0x0d38 */;
847: data_o = 32'h0ff77713 /* 0x0d3c */;
848: data_o = 32'hece346bd /* 0x0d40 */;
849: data_o = 32'h67e2f0e6 /* 0x0d44 */;
850: data_o = 32'h96b34685 /* 0x0d48 */;
851: data_o = 32'h8efd00e6 /* 0x0d4c */;
852: data_o = 32'h32069963 /* 0x0d50 */;
853: data_o = 32'h086346a9 /* 0x0d54 */;
854: data_o = 32'h479d18d7 /* 0x0d58 */;
855: data_o = 32'heef71fe3 /* 0x0d5c */;
856: data_o = 32'h000c3703 /* 0x0d60 */;
857: data_o = 32'h02186793 /* 0x0d64 */;
858: data_o = 32'h47c1e43e /* 0x0d68 */;
859: data_o = 32'he03e865e /* 0x0d6c */;
860: data_o = 32'h484188a2 /* 0x0d70 */;
861: data_o = 32'h86a64781 /* 0x0d74 */;
862: data_o = 32'h854e85ca /* 0x0d78 */;
863: data_o = 32'hdb2ff0ef /* 0x0d7c */;
864: data_o = 32'h45038baa /* 0x0d80 */;
865: data_o = 32'h0c21000b /* 0x0d84 */;
866: data_o = 32'hee0512e3 /* 0x0d88 */;
867: data_o = 32'h000b841b /* 0x0d8c */;
868: data_o = 32'h009be463 /* 0x0d90 */;
869: data_o = 32'hfff48b93 /* 0x0d94 */;
870: data_o = 32'h865e86a6 /* 0x0d98 */;
871: data_o = 32'h450185ca /* 0x0d9c */;
872: data_o = 32'h70aa9982 /* 0x0da0 */;
873: data_o = 32'h740a8522 /* 0x0da4 */;
874: data_o = 32'h694a64ea /* 0x0da8 */;
875: data_o = 32'h6a0a69aa /* 0x0dac */;
876: data_o = 32'h7b467ae6 /* 0x0db0 */;
877: data_o = 32'h7c067ba6 /* 0x0db4 */;
878: data_o = 32'h6d466ce6 /* 0x0db8 */;
879: data_o = 32'h614d6da6 /* 0x0dbc */;
880: data_o = 32'h45038082 /* 0x0dc0 */;
881: data_o = 32'h45a5001b /* 0x0dc4 */;
882: data_o = 32'h071b8636 /* 0x0dc8 */;
883: data_o = 32'h7713fd05 /* 0x0dcc */;
884: data_o = 32'h68130ff7 /* 0x0dd0 */;
885: data_o = 32'hf9634008 /* 0x0dd4 */;
886: data_o = 32'h071318e5 /* 0x0dd8 */;
887: data_o = 32'h0b6302a0 /* 0x0ddc */;
888: data_o = 32'h8b361ae5 /* 0x0de0 */;
889: data_o = 32'hbdd10685 /* 0x0de4 */;
890: data_o = 32'h46254a81 /* 0x0de8 */;
891: data_o = 32'h002a971b /* 0x0dec */;
892: data_o = 32'h0157073b /* 0x0df0 */;
893: data_o = 32'h0017171b /* 0x0df4 */;
894: data_o = 32'hc5039f29 /* 0x0df8 */;
895: data_o = 32'h0a9b0006 /* 0x0dfc */;
896: data_o = 32'h8b36fd07 /* 0x0e00 */;
897: data_o = 32'hfd05071b /* 0x0e04 */;
898: data_o = 32'h0ff77713 /* 0x0e08 */;
899: data_o = 32'h7fe30685 /* 0x0e0c */;
900: data_o = 32'hbd79fce6 /* 0x0e10 */;
901: data_o = 32'h000c2703 /* 0x0e14 */;
902: data_o = 32'h0a9b0c21 /* 0x0e18 */;
903: data_o = 32'h47630007 /* 0x0e1c */;
904: data_o = 32'h45030007 /* 0x0e20 */;
905: data_o = 32'h8b36001b /* 0x0e24 */;
906: data_o = 32'hb5590685 /* 0x0e28 */;
907: data_o = 32'h001b4503 /* 0x0e2c */;
908: data_o = 32'h00286813 /* 0x0e30 */;
909: data_o = 32'h0abb8b36 /* 0x0e34 */;
910: data_o = 32'h068540e0 /* 0x0e38 */;
911: data_o = 32'h4503bd95 /* 0x0e3c */;
912: data_o = 32'h0713001b /* 0x0e40 */;
913: data_o = 32'h1ae306c0 /* 0x0e44 */;
914: data_o = 32'h4503e8e5 /* 0x0e48 */;
915: data_o = 32'h6813002b /* 0x0e4c */;
916: data_o = 32'h06933008 /* 0x0e50 */;
917: data_o = 32'hb569003b /* 0x0e54 */;
918: data_o = 32'h001b4503 /* 0x0e58 */;
919: data_o = 32'h06800713 /* 0x0e5c */;
920: data_o = 32'h2ee50363 /* 0x0e60 */;
921: data_o = 32'h08086813 /* 0x0e64 */;
922: data_o = 32'hbd9d0685 /* 0x0e68 */;
923: data_o = 32'h04600713 /* 0x0e6c */;
924: data_o = 32'h20e50663 /* 0x0e70 */;
925: data_o = 32'h000c3507 /* 0x0e74 */;
926: data_o = 32'h87d6865e /* 0x0e78 */;
927: data_o = 32'h86a68722 /* 0x0e7c */;
928: data_o = 32'h854e85ca /* 0x0e80 */;
929: data_o = 32'ha5dff0ef /* 0x0e84 */;
930: data_o = 32'h8baa0c21 /* 0x0e88 */;
931: data_o = 32'h7413bbe1 /* 0x0e8c */;
932: data_o = 32'h0c930028 /* 0x0e90 */;
933: data_o = 32'h0363008c /* 0x0e94 */;
934: data_o = 32'h45033204 /* 0x0e98 */;
935: data_o = 32'h86a6000c /* 0x0e9c */;
936: data_o = 32'h85ca865e /* 0x0ea0 */;
937: data_o = 32'h47059982 /* 0x0ea4 */;
938: data_o = 32'h001b8413 /* 0x0ea8 */;
939: data_o = 32'h3b577263 /* 0x0eac */;
940: data_o = 32'hffea879b /* 0x0eb0 */;
941: data_o = 32'h8e131782 /* 0x0eb4 */;
942: data_o = 32'h9381002b /* 0x0eb8 */;
943: data_o = 32'h00fe0bb3 /* 0x0ebc */;
944: data_o = 32'h86a68622 /* 0x0ec0 */;
945: data_o = 32'h85ca0405 /* 0x0ec4 */;
946: data_o = 32'h02000513 /* 0x0ec8 */;
947: data_o = 32'h99e39982 /* 0x0ecc */;
948: data_o = 32'h8c66fe8b /* 0x0ed0 */;
949: data_o = 32'h865ebb41 /* 0x0ed4 */;
950: data_o = 32'h85ca86a6 /* 0x0ed8 */;
951: data_o = 32'h02500513 /* 0x0edc */;
952: data_o = 32'h99820b85 /* 0x0ee0 */;
953: data_o = 32'h3d03b341 /* 0x0ee4 */;
954: data_o = 32'h0793000c /* 0x0ee8 */;
955: data_o = 32'hfc3e008c /* 0x0eec */;
956: data_o = 32'h000d4603 /* 0x0ef0 */;
957: data_o = 32'hec558532 /* 0x0ef4 */;
958: data_o = 32'h05635cf9 /* 0x0ef8 */;
959: data_o = 32'h0c853a06 /* 0x0efc */;
960: data_o = 32'h876a9cea /* 0x0f00 */;
961: data_o = 32'h8763a019 /* 0x0f04 */;
962: data_o = 32'h468324ec /* 0x0f08 */;
963: data_o = 32'h07050017 /* 0x0f0c */;
964: data_o = 32'h07bbfafd /* 0x0f10 */;
965: data_o = 32'hf03e41a7 /* 0x0f14 */;
966: data_o = 32'h40087d93 /* 0x0f18 */;
967: data_o = 32'h000d8a63 /* 0x0f1c */;
968: data_o = 32'h87227782 /* 0x0f20 */;
969: data_o = 32'h0087f363 /* 0x0f24 */;
970: data_o = 32'h079b873e /* 0x0f28 */;
971: data_o = 32'hf03e0007 /* 0x0f2c */;
972: data_o = 32'h00287c13 /* 0x0f30 */;
973: data_o = 32'h220c0e63 /* 0x0f34 */;
974: data_o = 32'h1a060d63 /* 0x0f38 */;
975: data_o = 32'h8763865e /* 0x0f3c */;
976: data_o = 32'h071b000d /* 0x0f40 */;
977: data_o = 32'h0263fff4 /* 0x0f44 */;
978: data_o = 32'h843a1a04 /* 0x0f48 */;
979: data_o = 32'h85ca86a6 /* 0x0f4c */;
980: data_o = 32'h00160c93 /* 0x0f50 */;
981: data_o = 32'h87339982 /* 0x0f54 */;
982: data_o = 32'h976a417c /* 0x0f58 */;
983: data_o = 32'h00074503 /* 0x0f5c */;
984: data_o = 32'h18050663 /* 0x0f60 */;
985: data_o = 32'hbfe18666 /* 0x0f64 */;
986: data_o = 32'h171b46a5 /* 0x0f68 */;
987: data_o = 32'h9f210024 /* 0x0f6c */;
988: data_o = 32'h171b0605 /* 0x0f70 */;
989: data_o = 32'h9f290017 /* 0x0f74 */;
990: data_o = 32'h00064503 /* 0x0f78 */;
991: data_o = 32'hfd07041b /* 0x0f7c */;
992: data_o = 32'hfd05071b /* 0x0f80 */;
993: data_o = 32'h0ff77713 /* 0x0f84 */;
994: data_o = 32'hfee6f1e3 /* 0x0f88 */;
995: data_o = 32'h06938b32 /* 0x0f8c */;
996: data_o = 32'hb3250016 /* 0x0f90 */;
997: data_o = 32'h000c2703 /* 0x0f94 */;
998: data_o = 32'h002b4503 /* 0x0f98 */;
999: data_o = 32'h48930b09 /* 0x0f9c */;
1000: data_o = 32'hd893fff7 /* 0x0fa0 */;
1001: data_o = 32'hf43343f8 /* 0x0fa4 */;
1002: data_o = 32'h0c2100e8 /* 0x0fa8 */;
1003: data_o = 32'h001b0693 /* 0x0fac */;
1004: data_o = 32'h1c93b329 /* 0x0fb0 */;
1005: data_o = 32'hdc930204 /* 0x0fb4 */;
1006: data_o = 32'h0563020c /* 0x0fb8 */;
1007: data_o = 32'h1cfd2e06 /* 0x0fbc */;
1008: data_o = 32'h7713bf3d /* 0x0fc0 */;
1009: data_o = 32'h06930df5 /* 0x0fc4 */;
1010: data_o = 32'h02630470 /* 0x0fc8 */;
1011: data_o = 32'h071316d7 /* 0x0fcc */;
1012: data_o = 32'h07630450 /* 0x0fd0 */;
1013: data_o = 32'h350716e5 /* 0x0fd4 */;
1014: data_o = 32'h865e000c /* 0x0fd8 */;
1015: data_o = 32'h872287d6 /* 0x0fdc */;
1016: data_o = 32'h85ca86a6 /* 0x0fe0 */;
1017: data_o = 32'hf0ef854e /* 0x0fe4 */;
1018: data_o = 32'h0c21e14f /* 0x0fe8 */;
1019: data_o = 32'hb99d8baa /* 0x0fec */;
1020: data_o = 32'h06200713 /* 0x0ff0 */;
1021: data_o = 32'h20e50563 /* 0x0ff4 */;
1022: data_o = 32'h06f00713 /* 0x0ff8 */;
1023: data_o = 32'h20e50b63 /* 0x0ffc */;
1024: data_o = 32'h05800713 /* 0x1000 */;
1025: data_o = 32'h16e50063 /* 0x1004 */;
1026: data_o = 32'hfef87813 /* 0x1008 */;
1027: data_o = 32'h771346a9 /* 0x100c */;
1028: data_o = 32'h06134008 /* 0x1010 */;
1029: data_o = 32'h85ba0690 /* 0x1014 */;
1030: data_o = 32'h1ec51663 /* 0x1018 */;
1031: data_o = 32'h0c93edad /* 0x101c */;
1032: data_o = 32'h7713008c /* 0x1020 */;
1033: data_o = 32'h86422008 /* 0x1024 */;
1034: data_o = 32'h1e071763 /* 0x1028 */;
1035: data_o = 32'h10087713 /* 0x102c */;
1036: data_o = 32'h22071c63 /* 0x1030 */;
1037: data_o = 32'h04067713 /* 0x1034 */;
1038: data_o = 32'h000c2583 /* 0x1038 */;
1039: data_o = 32'h20071363 /* 0x103c */;
1040: data_o = 32'h08067613 /* 0x1040 */;
1041: data_o = 32'h24060a63 /* 0x1044 */;
1042: data_o = 32'h0105959b /* 0x1048 */;
1043: data_o = 32'h4105d59b /* 0x104c */;
1044: data_o = 32'h40f5d61b /* 0x1050 */;
1045: data_o = 32'h00c5c733 /* 0x1054 */;
1046: data_o = 32'h17429f11 /* 0x1058 */;
1047: data_o = 32'he4429341 /* 0x105c */;
1048: data_o = 32'he056865e /* 0x1060 */;
1049: data_o = 32'h883688a2 /* 0x1064 */;
1050: data_o = 32'h01f5d79b /* 0x1068 */;
1051: data_o = 32'h85ca86a6 /* 0x106c */;
1052: data_o = 32'hf0ef854e /* 0x1070 */;
1053: data_o = 32'h8baaabcf /* 0x1074 */;
1054: data_o = 32'hb6ed8c66 /* 0x1078 */;
1055: data_o = 32'h02086813 /* 0x107c */;
1056: data_o = 32'h0713bbd5 /* 0x1080 */;
1057: data_o = 32'h15e30780 /* 0x1084 */;
1058: data_o = 32'h46c1f6e5 /* 0x1088 */;
1059: data_o = 32'h40087713 /* 0x108c */;
1060: data_o = 32'hff387813 /* 0x1090 */;
1061: data_o = 32'h7813c701 /* 0x1094 */;
1062: data_o = 32'h2801ffe8 /* 0x1098 */;
1063: data_o = 32'h06900713 /* 0x109c */;
1064: data_o = 32'h008c0c93 /* 0x10a0 */;
1065: data_o = 32'hf6e50fe3 /* 0x10a4 */;
1066: data_o = 32'h06400713 /* 0x10a8 */;
1067: data_o = 32'hf6e50be3 /* 0x10ac */;
1068: data_o = 32'h20087713 /* 0x10b0 */;
1069: data_o = 32'h10638642 /* 0x10b4 */;
1070: data_o = 32'h77131a07 /* 0x10b8 */;
1071: data_o = 32'h14631008 /* 0x10bc */;
1072: data_o = 32'h77131c07 /* 0x10c0 */;
1073: data_o = 32'h12630406 /* 0x10c4 */;
1074: data_o = 32'h76131807 /* 0x10c8 */;
1075: data_o = 32'h27030806 /* 0x10cc */;
1076: data_o = 32'hc219000c /* 0x10d0 */;
1077: data_o = 32'h8f7d77c2 /* 0x10d4 */;
1078: data_o = 32'he4421702 /* 0x10d8 */;
1079: data_o = 32'he056865e /* 0x10dc */;
1080: data_o = 32'h883688a2 /* 0x10e0 */;
1081: data_o = 32'h93014781 /* 0x10e4 */;
1082: data_o = 32'h8cb2b751 /* 0x10e8 */;
1083: data_o = 32'h020c0e63 /* 0x10ec */;
1084: data_o = 32'h77828be6 /* 0x10f0 */;
1085: data_o = 32'h0d57f263 /* 0x10f4 */;
1086: data_o = 32'hfffa881b /* 0x10f8 */;
1087: data_o = 32'h40f8083b /* 0x10fc */;
1088: data_o = 32'h58131802 /* 0x1100 */;
1089: data_o = 32'h87130208 /* 0x1104 */;
1090: data_o = 32'h0cb3001b /* 0x1108 */;
1091: data_o = 32'ha01100e8 /* 0x110c */;
1092: data_o = 32'h865e0705 /* 0x1110 */;
1093: data_o = 32'h86a6f03a /* 0x1114 */;
1094: data_o = 32'h051385ca /* 0x1118 */;
1095: data_o = 32'h8bba0200 /* 0x111c */;
1096: data_o = 32'h77029982 /* 0x1120 */;
1097: data_o = 32'hfeec96e3 /* 0x1124 */;
1098: data_o = 32'h8be67c62 /* 0x1128 */;
1099: data_o = 32'h77a2be25 /* 0x112c */;
1100: data_o = 32'h0fd57513 /* 0x1130 */;
1101: data_o = 32'h04500713 /* 0x1134 */;
1102: data_o = 32'h00f86833 /* 0x1138 */;
1103: data_o = 32'he8e51de3 /* 0x113c */;
1104: data_o = 32'h02086813 /* 0x1140 */;
1105: data_o = 32'h4503bd49 /* 0x1144 */;
1106: data_o = 32'h6813002b /* 0x1148 */;
1107: data_o = 32'h06930c08 /* 0x114c */;
1108: data_o = 32'hb679003b /* 0x1150 */;
1109: data_o = 32'h41ac87bb /* 0x1154 */;
1110: data_o = 32'hbb7df03e /* 0x1158 */;
1111: data_o = 32'hede34401 /* 0x115c */;
1112: data_o = 32'hb90dc29b /* 0x1160 */;
1113: data_o = 32'h02086813 /* 0x1164 */;
1114: data_o = 32'h771346c1 /* 0x1168 */;
1115: data_o = 32'hb70d4008 /* 0x116c */;
1116: data_o = 32'h871b7782 /* 0x1170 */;
1117: data_o = 32'hfb630017 /* 0x1174 */;
1118: data_o = 32'h871b1357 /* 0x1178 */;
1119: data_o = 32'h0cbbfffa /* 0x117c */;
1120: data_o = 32'h1c8240f7 /* 0x1180 */;
1121: data_o = 32'h020cdc93 /* 0x1184 */;
1122: data_o = 32'h001b8713 /* 0x1188 */;
1123: data_o = 32'ha0199cba /* 0x118c */;
1124: data_o = 32'h07057702 /* 0x1190 */;
1125: data_o = 32'h86a6865e /* 0x1194 */;
1126: data_o = 32'hf03a8bba /* 0x1198 */;
1127: data_o = 32'h051385ca /* 0x119c */;
1128: data_o = 32'h99820200 /* 0x11a0 */;
1129: data_o = 32'hff7c96e3 /* 0x11a4 */;
1130: data_o = 32'h000d4603 /* 0x11a8 */;
1131: data_o = 32'h001a879b /* 0x11ac */;
1132: data_o = 32'h8532f03e /* 0x11b0 */;
1133: data_o = 32'hd80614e3 /* 0x11b4 */;
1134: data_o = 32'hb7bd8cde /* 0x11b8 */;
1135: data_o = 32'h75634705 /* 0x11bc */;
1136: data_o = 32'h841b0f57 /* 0x11c0 */;
1137: data_o = 32'h1402ffea /* 0x11c4 */;
1138: data_o = 32'h001b8713 /* 0x11c8 */;
1139: data_o = 32'h943a9001 /* 0x11cc */;
1140: data_o = 32'h0705a011 /* 0x11d0 */;
1141: data_o = 32'hf03a865e /* 0x11d4 */;
1142: data_o = 32'h85ca86a6 /* 0x11d8 */;
1143: data_o = 32'h02000513 /* 0x11dc */;
1144: data_o = 32'h99828bba /* 0x11e0 */;
1145: data_o = 32'h16e37702 /* 0x11e4 */;
1146: data_o = 32'h4503fe87 /* 0x11e8 */;
1147: data_o = 32'h86a6000c /* 0x11ec */;
1148: data_o = 32'h85ca8622 /* 0x11f0 */;
1149: data_o = 32'h00140b93 /* 0x11f4 */;
1150: data_o = 32'h8c669982 /* 0x11f8 */;
1151: data_o = 32'h4689b4a5 /* 0x11fc */;
1152: data_o = 32'h40087713 /* 0x1200 */;
1153: data_o = 32'h06400613 /* 0x1204 */;
1154: data_o = 32'he8c514e3 /* 0x1208 */;
1155: data_o = 32'he00709e3 /* 0x120c */;
1156: data_o = 32'h46a1b559 /* 0x1210 */;
1157: data_o = 32'h3783bbed /* 0x1214 */;
1158: data_o = 32'h865e000c /* 0x1218 */;
1159: data_o = 32'hd713e442 /* 0x121c */;
1160: data_o = 32'h453343f7 /* 0x1220 */;
1161: data_o = 32'he05600f7 /* 0x1224 */;
1162: data_o = 32'h883688a2 /* 0x1228 */;
1163: data_o = 32'h073393fd /* 0x122c */;
1164: data_o = 32'h86a640e5 /* 0x1230 */;
1165: data_o = 32'h854e85ca /* 0x1234 */;
1166: data_o = 32'h8f6ff0ef /* 0x1238 */;
1167: data_o = 32'h8c668baa /* 0x123c */;
1168: data_o = 32'hf593b415 /* 0x1240 */;
1169: data_o = 32'h872e0ff5 /* 0x1244 */;
1170: data_o = 32'h4703bd19 /* 0x1248 */;
1171: data_o = 32'hb569000c /* 0x124c */;
1172: data_o = 32'h8c668ba2 /* 0x1250 */;
1173: data_o = 32'h3703bc01 /* 0x1254 */;
1174: data_o = 32'h865e000c /* 0x1258 */;
1175: data_o = 32'he056e442 /* 0x125c */;
1176: data_o = 32'h883688a2 /* 0x1260 */;
1177: data_o = 32'hb7f14781 /* 0x1264 */;
1178: data_o = 32'h000c3783 /* 0x1268 */;
1179: data_o = 32'he442865e /* 0x126c */;
1180: data_o = 32'h43f7d713 /* 0x1270 */;
1181: data_o = 32'h00f74533 /* 0x1274 */;
1182: data_o = 32'h88a2e056 /* 0x1278 */;
1183: data_o = 32'h93fd8836 /* 0x127c */;
1184: data_o = 32'h40e50733 /* 0x1280 */;
1185: data_o = 32'h3703b3e5 /* 0x1284 */;
1186: data_o = 32'h865e000c /* 0x1288 */;
1187: data_o = 32'he056e442 /* 0x128c */;
1188: data_o = 32'h883688a2 /* 0x1290 */;
1189: data_o = 32'hbbd94781 /* 0x1294 */;
1190: data_o = 32'h41f5d61b /* 0x1298 */;
1191: data_o = 32'h00c5c733 /* 0x129c */;
1192: data_o = 32'hbb759f11 /* 0x12a0 */;
1193: data_o = 32'hb98df002 /* 0x12a4 */;
1194: data_o = 32'hb781845e /* 0x12a8 */;
1195: data_o = 32'hb711f03a /* 0x12ac */;
1196: data_o = 32'h0313711d /* 0x12b0 */;
1197: data_o = 32'h8e2a0281 /* 0x12b4 */;
1198: data_o = 32'h00000517 /* 0x12b8 */;
1199: data_o = 32'hf832f42e /* 0x12bc */;
1200: data_o = 32'he0bafc36 /* 0x12c0 */;
1201: data_o = 32'h86f2858a /* 0x12c4 */;
1202: data_o = 32'h567d871a /* 0x12c8 */;
1203: data_o = 32'h94650513 /* 0x12cc */;
1204: data_o = 32'he4beec06 /* 0x12d0 */;
1205: data_o = 32'hecc6e8c2 /* 0x12d4 */;
1206: data_o = 32'hf0efe41a /* 0x12d8 */;
1207: data_o = 32'h60e292bf /* 0x12dc */;
1208: data_o = 32'h80826125 /* 0x12e0 */;
1209: data_o = 32'h01002717 /* 0x12e4 */;
1210: data_o = 32'hd1c70713 /* 0x12e8 */;
1211: data_o = 32'h47830751 /* 0x12ec */;
1212: data_o = 32'hf7930007 /* 0x12f0 */;
1213: data_o = 32'hdfe50207 /* 0x12f4 */;
1214: data_o = 32'h01002797 /* 0x12f8 */;
1215: data_o = 32'hd0a78423 /* 0x12fc */;
1216: data_o = 32'h959b8082 /* 0x1300 */;
1217: data_o = 32'h553b0045 /* 0x1304 */;
1218: data_o = 32'h279702b5 /* 0x1308 */;
1219: data_o = 32'h87930100 /* 0x130c */;
1220: data_o = 32'h8223cf67 /* 0x1310 */;
1221: data_o = 32'h07130007 /* 0x1314 */;
1222: data_o = 32'h8623f800 /* 0x1318 */;
1223: data_o = 32'h271700e7 /* 0x131c */;
1224: data_o = 32'h76930100 /* 0x1320 */;
1225: data_o = 32'h551b0ff5 /* 0x1324 */;
1226: data_o = 32'h01230085 /* 0x1328 */;
1227: data_o = 32'h7513ced7 /* 0x132c */;
1228: data_o = 32'h82230ff5 /* 0x1330 */;
1229: data_o = 32'h470d00a7 /* 0x1334 */;
1230: data_o = 32'h00e78623 /* 0x1338 */;
1231: data_o = 32'hfc700713 /* 0x133c */;
1232: data_o = 32'h00e78423 /* 0x1340 */;
1233: data_o = 32'h02000713 /* 0x1344 */;
1234: data_o = 32'h00e78823 /* 0x1348 */;
1235: data_o = 32'h78938082 /* 0x134c */;
1236: data_o = 32'h48010026 /* 0x1350 */;
1237: data_o = 32'h95638a05 /* 0x1354 */;
1238: data_o = 32'h491c0008 /* 0x1358 */;
1239: data_o = 32'hcba94805 /* 0x135c */;
1240: data_o = 32'h611cc611 /* 0x1360 */;
1241: data_o = 32'hc9184705 /* 0x1364 */;
1242: data_o = 32'h0207a023 /* 0x1368 */;
1243: data_o = 32'h6789c5a9 /* 0x136c */;
1244: data_o = 32'h87936114 /* 0x1370 */;
1245: data_o = 32'ha0117107 /* 0x1374 */;
1246: data_o = 32'h4ad8c3a5 /* 0x1378 */;
1247: data_o = 32'h5de337fd /* 0x137c */;
1248: data_o = 32'hf793fe07 /* 0x1380 */;
1249: data_o = 32'h37fd1ff5 /* 0x1384 */;
1250: data_o = 32'h0098181b /* 0x1388 */;
1251: data_o = 32'h0107e7b3 /* 0x138c */;
1252: data_o = 32'hd2dc2781 /* 0x1390 */;
1253: data_o = 32'h40000737 /* 0x1394 */;
1254: data_o = 32'h8ff94adc /* 0x1398 */;
1255: data_o = 32'hffed2781 /* 0x139c */;
1256: data_o = 32'h00088663 /* 0x13a0 */;
1257: data_o = 32'h00052823 /* 0x13a4 */;
1258: data_o = 32'hd29c4785 /* 0x13a8 */;
1259: data_o = 32'h80824501 /* 0x13ac */;
1260: data_o = 32'h0006081b /* 0x13b0 */;
1261: data_o = 32'h8be3b775 /* 0x13b4 */;
1262: data_o = 32'h1141fe08 /* 0x13b8 */;
1263: data_o = 32'he406611c /* 0x13bc */;
1264: data_o = 32'h00052823 /* 0x13c0 */;
1265: data_o = 32'hd3984705 /* 0x13c4 */;
1266: data_o = 32'h45a14601 /* 0x13c8 */;
1267: data_o = 32'hf83ff0ef /* 0x13cc */;
1268: data_o = 32'h450160a2 /* 0x13d0 */;
1269: data_o = 32'h80820141 /* 0x13d4 */;
1270: data_o = 32'h8082557d /* 0x13d8 */;
1271: data_o = 32'h87ae88aa /* 0x13dc */;
1272: data_o = 32'h1a060c63 /* 0x13e0 */;
1273: data_o = 32'h0077f513 /* 0x13e4 */;
1274: data_o = 32'h40051263 /* 0x13e8 */;
1275: data_o = 32'h73137139 /* 0x13ec */;
1276: data_o = 32'hfc060027 /* 0x13f0 */;
1277: data_o = 32'hf426f822 /* 0x13f4 */;
1278: data_o = 32'hec4ef04a /* 0x13f8 */;
1279: data_o = 32'h42818b05 /* 0x13fc */;
1280: data_o = 32'h00031863 /* 0x1400 */;
1281: data_o = 32'h0108a583 /* 0x1404 */;
1282: data_o = 32'he1994285 /* 0x1408 */;
1283: data_o = 32'h0007029b /* 0x140c */;
1284: data_o = 32'h10071163 /* 0x1410 */;
1285: data_o = 32'h10078863 /* 0x1414 */;
1286: data_o = 32'h00c03733 /* 0x1418 */;
1287: data_o = 32'h00d035b3 /* 0x141c */;
1288: data_o = 32'h0017171b /* 0x1420 */;
1289: data_o = 32'h559b8f4d /* 0x1424 */;
1290: data_o = 32'h1f1b0017 /* 0x1428 */;
1291: data_o = 32'hf5930187 /* 0x142c */;
1292: data_o = 32'hb8030ff5 /* 0x1430 */;
1293: data_o = 32'hde9b0008 /* 0x1434 */;
1294: data_o = 32'hde1b0037 /* 0x1438 */;
1295: data_o = 32'h5f1b0037 /* 0x143c */;
1296: data_o = 32'hc5b5418f /* 0x1440 */;
1297: data_o = 32'h0057d71b /* 0x1444 */;
1298: data_o = 32'h0057d59b /* 0x1448 */;
1299: data_o = 32'h9f93cf39 /* 0x144c */;
1300: data_o = 32'hdf930205 /* 0x1450 */;
1301: data_o = 32'h87b201ef /* 0x1454 */;
1302: data_o = 32'h79139fb2 /* 0x1458 */;
1303: data_o = 32'h79930036 /* 0x145c */;
1304: data_o = 32'ha03d0016 /* 0x1460 */;
1305: data_o = 32'h0037c703 /* 0x1464 */;
1306: data_o = 32'h0007c483 /* 0x1468 */;
1307: data_o = 32'h0017c403 /* 0x146c */;
1308: data_o = 32'h0027c383 /* 0x1470 */;
1309: data_o = 32'h009105a3 /* 0x1474 */;
1310: data_o = 32'h00810523 /* 0x1478 */;
1311: data_o = 32'h007104a3 /* 0x147c */;
1312: data_o = 32'h00e10423 /* 0x1480 */;
1313: data_o = 32'h07914722 /* 0x1484 */;
1314: data_o = 32'h02e82423 /* 0x1488 */;
1315: data_o = 32'h01f78d63 /* 0x148c */;
1316: data_o = 32'h0148c703 /* 0x1490 */;
1317: data_o = 32'h1363db61 /* 0x1494 */;
1318: data_o = 32'h43980c09 /* 0x1498 */;
1319: data_o = 32'h24230791 /* 0x149c */;
1320: data_o = 32'h97e302e8 /* 0x14a0 */;
1321: data_o = 32'h971bfff7 /* 0x14a4 */;
1322: data_o = 32'h6b630025 /* 0x14a8 */;
1323: data_o = 32'hf6130fc7 /* 0x14ac */;
1324: data_o = 32'h179b1ffe /* 0x14b0 */;
1325: data_o = 32'h367d00cf /* 0x14b4 */;
1326: data_o = 32'h929b8e5d /* 0x14b8 */;
1327: data_o = 32'h66330092 /* 0x14bc */;
1328: data_o = 32'h67890056 /* 0x14c0 */;
1329: data_o = 32'h87932601 /* 0x14c4 */;
1330: data_o = 32'ha0197107 /* 0x14c8 */;
1331: data_o = 32'h10078963 /* 0x14cc */;
1332: data_o = 32'h01482703 /* 0x14d0 */;
1333: data_o = 32'h5be337fd /* 0x14d4 */;
1334: data_o = 32'h2223fe07 /* 0x14d8 */;
1335: data_o = 32'ha78302c8 /* 0x14dc */;
1336: data_o = 32'hcf910108 /* 0x14e0 */;
1337: data_o = 32'h000f0d63 /* 0x14e4 */;
1338: data_o = 32'h001f7713 /* 0x14e8 */;
1339: data_o = 32'h12071b63 /* 0x14ec */;
1340: data_o = 32'h40000737 /* 0x14f0 */;
1341: data_o = 32'h01482783 /* 0x14f4 */;
1342: data_o = 32'h27818ff9 /* 0x14f8 */;
1343: data_o = 32'h1163ffe5 /* 0x14fc */;
1344: data_o = 32'h70e20403 /* 0x1500 */;
1345: data_o = 32'h74a27442 /* 0x1504 */;
1346: data_o = 32'h69e27902 /* 0x1508 */;
1347: data_o = 32'h61214501 /* 0x150c */;
1348: data_o = 32'hb7038082 /* 0x1510 */;
1349: data_o = 32'h45850008 /* 0x1514 */;
1350: data_o = 32'h00b8a823 /* 0x1518 */;
1351: data_o = 32'h02072023 /* 0x151c */;
1352: data_o = 32'hee079ce3 /* 0x1520 */;
1353: data_o = 32'hfc030fe3 /* 0x1524 */;
1354: data_o = 32'h0008b783 /* 0x1528 */;
1355: data_o = 32'h0008a823 /* 0x152c */;
1356: data_o = 32'hd3984705 /* 0x1530 */;
1357: data_o = 32'h45a14601 /* 0x1534 */;
1358: data_o = 32'hf0ef8546 /* 0x1538 */;
1359: data_o = 32'hb7d1e15f /* 0x153c */;
1360: data_o = 32'h0008b783 /* 0x1540 */;
1361: data_o = 32'h744270e2 /* 0x1544 */;
1362: data_o = 32'h0008a823 /* 0x1548 */;
1363: data_o = 32'hd3984705 /* 0x154c */;
1364: data_o = 32'h790274a2 /* 0x1550 */;
1365: data_o = 32'h450169e2 /* 0x1554 */;
1366: data_o = 32'h80826121 /* 0x1558 */;
1367: data_o = 32'h00099c63 /* 0x155c */;
1368: data_o = 32'h0027d703 /* 0x1560 */;
1369: data_o = 32'h0007d383 /* 0x1564 */;
1370: data_o = 32'h00e11523 /* 0x1568 */;
1371: data_o = 32'h00711423 /* 0x156c */;
1372: data_o = 32'hbf114722 /* 0x1570 */;
1373: data_o = 32'h0037c703 /* 0x1574 */;
1374: data_o = 32'h0007c483 /* 0x1578 */;
1375: data_o = 32'h0017c403 /* 0x157c */;
1376: data_o = 32'h0027c383 /* 0x1580 */;
1377: data_o = 32'h00910423 /* 0x1584 */;
1378: data_o = 32'h008104a3 /* 0x1588 */;
1379: data_o = 32'h00710523 /* 0x158c */;
1380: data_o = 32'h00e105a3 /* 0x1590 */;
1381: data_o = 32'hbdc54722 /* 0x1594 */;
1382: data_o = 32'he40696e3 /* 0x1598 */;
1383: data_o = 32'hbb45863a /* 0x159c */;
1384: data_o = 32'h0148c783 /* 0x15a0 */;
1385: data_o = 32'h00e605b3 /* 0x15a4 */;
1386: data_o = 32'h0005cf83 /* 0x15a8 */;
1387: data_o = 32'h40ee85bb /* 0x15ac */;
1388: data_o = 32'h05a3ef9d /* 0x15b0 */;
1389: data_o = 32'h4f8501f1 /* 0x15b4 */;
1390: data_o = 32'h1cbffc63 /* 0x15b8 */;
1391: data_o = 32'h00e60fb3 /* 0x15bc */;
1392: data_o = 32'h001fc383 /* 0x15c0 */;
1393: data_o = 32'h05234f8d /* 0x15c4 */;
1394: data_o = 32'h95630071 /* 0x15c8 */;
1395: data_o = 32'h973201f5 /* 0x15cc */;
1396: data_o = 32'h00274783 /* 0x15d0 */;
1397: data_o = 32'h00f104a3 /* 0x15d4 */;
1398: data_o = 32'h00010423 /* 0x15d8 */;
1399: data_o = 32'h70e2a83d /* 0x15dc */;
1400: data_o = 32'h74a27442 /* 0x15e0 */;
1401: data_o = 32'h69e27902 /* 0x15e4 */;
1402: data_o = 32'h6121557d /* 0x15e8 */;
1403: data_o = 32'h04238082 /* 0x15ec */;
1404: data_o = 32'h478501f1 /* 0x15f0 */;
1405: data_o = 32'h18b7fa63 /* 0x15f4 */;
1406: data_o = 32'h00e607b3 /* 0x15f8 */;
1407: data_o = 32'h0017c383 /* 0x15fc */;
1408: data_o = 32'h47814f8d /* 0x1600 */;
1409: data_o = 32'h007104a3 /* 0x1604 */;
1410: data_o = 32'h01f59563 /* 0x1608 */;
1411: data_o = 32'h4783963a /* 0x160c */;
1412: data_o = 32'h05230026 /* 0x1610 */;
1413: data_o = 32'h05a300f1 /* 0x1614 */;
1414: data_o = 32'h47a20001 /* 0x1618 */;
1415: data_o = 32'h02f82423 /* 0x161c */;
1416: data_o = 32'h0637b579 /* 0x1620 */;
1417: data_o = 32'h4f0d4000 /* 0x1624 */;
1418: data_o = 32'h27834f85 /* 0x1628 */;
1419: data_o = 32'hd71b0148 /* 0x162c */;
1420: data_o = 32'h77130087 /* 0x1630 */;
1421: data_o = 32'h27810ff7 /* 0x1634 */;
1422: data_o = 32'h2783cb21 /* 0x1638 */;
1423: data_o = 32'h76e30288 /* 0x163c */;
1424: data_o = 32'h073bffc5 /* 0x1640 */;
1425: data_o = 32'hc58340ae /* 0x1644 */;
1426: data_o = 32'h27810148 /* 0x1648 */;
1427: data_o = 32'h0aef7663 /* 0x164c */;
1428: data_o = 32'h10059163 /* 0x1650 */;
1429: data_o = 32'h0087d81b /* 0x1654 */;
1430: data_o = 32'h0107d59b /* 0x1658 */;
1431: data_o = 32'h0187d71b /* 0x165c */;
1432: data_o = 32'h00f681a3 /* 0x1660 */;
1433: data_o = 32'h01068123 /* 0x1664 */;
1434: data_o = 32'h00b680a3 /* 0x1668 */;
1435: data_o = 32'h00e68023 /* 0x166c */;
1436: data_o = 32'h0008b803 /* 0x1670 */;
1437: data_o = 32'h01482783 /* 0x1674 */;
1438: data_o = 32'h25110691 /* 0x1678 */;
1439: data_o = 32'h0087d71b /* 0x167c */;
1440: data_o = 32'h0ff77713 /* 0x1680 */;
1441: data_o = 32'hfb552781 /* 0x1684 */;
1442: data_o = 32'h27818ff1 /* 0x1688 */;
1443: data_o = 32'h78e3ffd9 /* 0x168c */;
1444: data_o = 32'h6709e7c5 /* 0x1690 */;
1445: data_o = 32'h71070713 /* 0x1694 */;
1446: data_o = 32'hd331a011 /* 0x1698 */;
1447: data_o = 32'h01482783 /* 0x169c */;
1448: data_o = 32'hd79b377d /* 0x16a0 */;
1449: data_o = 32'hf7930087 /* 0x16a4 */;
1450: data_o = 32'hdbe50ff7 /* 0x16a8 */;
1451: data_o = 32'h02882783 /* 0x16ac */;
1452: data_o = 32'h0148c603 /* 0x16b0 */;
1453: data_o = 32'h0015071b /* 0x16b4 */;
1454: data_o = 32'hee6d2781 /* 0x16b8 */;
1455: data_o = 32'h0187d61b /* 0x16bc */;
1456: data_o = 32'h00c68023 /* 0x16c0 */;
1457: data_o = 32'he2ee0de3 /* 0x16c4 */;
1458: data_o = 32'h0107d71b /* 0x16c8 */;
1459: data_o = 32'h00e680a3 /* 0x16cc */;
1460: data_o = 32'h0025071b /* 0x16d0 */;
1461: data_o = 32'h00ee0863 /* 0x16d4 */;
1462: data_o = 32'h0087d71b /* 0x16d8 */;
1463: data_o = 32'h00e68123 /* 0x16dc */;
1464: data_o = 32'h0035071b /* 0x16e0 */;
1465: data_o = 32'h40ee873b /* 0x16e4 */;
1466: data_o = 32'h1ae34605 /* 0x16e8 */;
1467: data_o = 32'h81a3e0c7 /* 0x16ec */;
1468: data_o = 32'h08e300f6 /* 0x16f0 */;
1469: data_o = 32'hb5a9e003 /* 0x16f4 */;
1470: data_o = 32'h0015071b /* 0x16f8 */;
1471: data_o = 32'hd59be98d /* 0x16fc */;
1472: data_o = 32'h80230187 /* 0x1700 */;
1473: data_o = 32'h0b6300b6 /* 0x1704 */;
1474: data_o = 32'hd59b04ee /* 0x1708 */;
1475: data_o = 32'h071b0107 /* 0x170c */;
1476: data_o = 32'h80a30025 /* 0x1710 */;
1477: data_o = 32'h05bb00b6 /* 0x1714 */;
1478: data_o = 32'h986340ee /* 0x1718 */;
1479: data_o = 32'hd79b03f5 /* 0x171c */;
1480: data_o = 32'h81230087 /* 0x1720 */;
1481: data_o = 32'hb80300f6 /* 0x1724 */;
1482: data_o = 32'h250d0008 /* 0x1728 */;
1483: data_o = 32'h8023bdfd /* 0x172c */;
1484: data_o = 32'h056300f6 /* 0x1730 */;
1485: data_o = 32'hd59b02ee /* 0x1734 */;
1486: data_o = 32'h071b0087 /* 0x1738 */;
1487: data_o = 32'h80a30025 /* 0x173c */;
1488: data_o = 32'h05bb00b6 /* 0x1740 */;
1489: data_o = 32'h896340ee /* 0x1744 */;
1490: data_o = 32'hb80303f5 /* 0x1748 */;
1491: data_o = 32'h853a0008 /* 0x174c */;
1492: data_o = 32'hf713bde9 /* 0x1750 */;
1493: data_o = 32'he7190036 /* 0x1754 */;
1494: data_o = 32'hbf29c29c /* 0x1758 */;
1495: data_o = 32'h0008b803 /* 0x175c */;
1496: data_o = 32'hb5e18572 /* 0x1760 */;
1497: data_o = 32'h0016f713 /* 0x1764 */;
1498: data_o = 32'h0107d59b /* 0x1768 */;
1499: data_o = 32'h9023e70d /* 0x176c */;
1500: data_o = 32'h912300f6 /* 0x1770 */;
1501: data_o = 32'hbdfd00b6 /* 0x1774 */;
1502: data_o = 32'h0107d79b /* 0x1778 */;
1503: data_o = 32'h00f68123 /* 0x177c */;
1504: data_o = 32'h0008b803 /* 0x1780 */;
1505: data_o = 32'hb555250d /* 0x1784 */;
1506: data_o = 32'h000104a3 /* 0x1788 */;
1507: data_o = 32'hb5514781 /* 0x178c */;
1508: data_o = 32'h00010523 /* 0x1790 */;
1509: data_o = 32'hd81bb581 /* 0x1794 */;
1510: data_o = 32'hd71b0087 /* 0x1798 */;
1511: data_o = 32'h80230187 /* 0x179c */;
1512: data_o = 32'h80a300f6 /* 0x17a0 */;
1513: data_o = 32'h81230106 /* 0x17a4 */;
1514: data_o = 32'h81a300b6 /* 0x17a8 */;
1515: data_o = 32'hb80300e6 /* 0x17ac */;
1516: data_o = 32'hb5c90008 /* 0x17b0 */;
1517: data_o = 32'h00f68023 /* 0x17b4 */;
1518: data_o = 32'hd4ee03e3 /* 0x17b8 */;
1519: data_o = 32'h0087d71b /* 0x17bc */;
1520: data_o = 32'h00e680a3 /* 0x17c0 */;
1521: data_o = 32'h0025071b /* 0x17c4 */;
1522: data_o = 32'h00ee0863 /* 0x17c8 */;
1523: data_o = 32'h0107d71b /* 0x17cc */;
1524: data_o = 32'h00e68123 /* 0x17d0 */;
1525: data_o = 32'h0035071b /* 0x17d4 */;
1526: data_o = 32'h40ee873b /* 0x17d8 */;
1527: data_o = 32'h10e34605 /* 0x17dc */;
1528: data_o = 32'hd79bd2c7 /* 0x17e0 */;
1529: data_o = 32'h81a30187 /* 0x17e4 */;
1530: data_o = 32'hb72100f6 /* 0x17e8 */;
1531: data_o = 32'h8082557d /* 0x17ec */;
1532: data_o = 32'he288c685 /* 0x17f0 */;
1533: data_o = 32'hc68cc115 /* 0x17f4 */;
1534: data_o = 32'hca01c185 /* 0x17f8 */;
1535: data_o = 32'h0015d59b /* 0x17fc */;
1536: data_o = 32'h00c5e563 /* 0x1800 */;
1537: data_o = 32'h4501c6d0 /* 0x1804 */;
1538: data_o = 32'ha7b78082 /* 0x1808 */;
1539: data_o = 32'h87930007 /* 0x180c */;
1540: data_o = 32'hc6dc1207 /* 0x1810 */;
1541: data_o = 32'h80824501 /* 0x1814 */;
1542: data_o = 32'h8082557d /* 0x1818 */;
1543: data_o = 32'h07b76110 /* 0x181c */;
1544: data_o = 32'h46b74000 /* 0x1820 */;
1545: data_o = 32'h2223000f /* 0x1824 */;
1546: data_o = 32'h2a230006 /* 0x1828 */;
1547: data_o = 32'hca1c0206 /* 0x182c */;
1548: data_o = 32'h882a4a5c /* 0x1830 */;
1549: data_o = 32'h23f68693 /* 0x1834 */;
1550: data_o = 32'h400005b7 /* 0x1838 */;
1551: data_o = 32'ha0212781 /* 0x183c */;
1552: data_o = 32'h27814a5c /* 0x1840 */;
1553: data_o = 32'hf733c695 /* 0x1844 */;
1554: data_o = 32'h979b00b7 /* 0x1848 */;
1555: data_o = 32'h8fd90107 /* 0x184c */;
1556: data_o = 32'h36fd2781 /* 0x1850 */;
1557: data_o = 32'h07b7f7f5 /* 0x1854 */;
1558: data_o = 32'hca1c8000 /* 0x1858 */;
1559: data_o = 32'hd21c4785 /* 0x185c */;
1560: data_o = 32'h45014a5c /* 0x1860 */;
1561: data_o = 32'h0167d79b /* 0x1864 */;
1562: data_o = 32'h0a238b85 /* 0x1868 */;
1563: data_o = 32'h808200f8 /* 0x186c */;
1564: data_o = 32'h00062823 /* 0x1870 */;
1565: data_o = 32'h8082557d /* 0x1874 */;
1566: data_o = 32'hf456711d /* 0x1878 */;
1567: data_o = 32'hec866a85 /* 0x187c */;
1568: data_o = 32'he4a6e8a2 /* 0x1880 */;
1569: data_o = 32'hfc4ee0ca /* 0x1884 */;
1570: data_o = 32'hf05af852 /* 0x1888 */;
1571: data_o = 32'he862ec5e /* 0x188c */;
1572: data_o = 32'h8a93e466 /* 0x1890 */;
1573: data_o = 32'hfa63800a /* 0x1894 */;
1574: data_o = 32'h8a1b08ba /* 0x1898 */;
1575: data_o = 32'h8b3a7ff5 /* 0x189c */;
1576: data_o = 32'h00ba579b /* 0x18a0 */;
1577: data_o = 32'h8b0584ae /* 0x18a4 */;
1578: data_o = 32'h002b7b13 /* 0x18a8 */;
1579: data_o = 32'h00ba5a1b /* 0x18ac */;
1580: data_o = 32'h3a7dcbbd /* 0x18b0 */;
1581: data_o = 32'h000a0c1b /* 0x18b4 */;
1582: data_o = 32'h8baa1a02 /* 0x18b8 */;
1583: data_o = 32'h89b68932 /* 0x18bc */;
1584: data_o = 32'h020a5a13 /* 0x18c0 */;
1585: data_o = 32'h8cd64401 /* 0x18c4 */;
1586: data_o = 32'h0e63a821 /* 0x18c8 */;
1587: data_o = 32'h079b0544 /* 0x18cc */;
1588: data_o = 32'h875a0014 /* 0x18d0 */;
1589: data_o = 32'h01878363 /* 0x18d4 */;
1590: data_o = 32'h04054701 /* 0x18d8 */;
1591: data_o = 32'h8004849b /* 0x18dc */;
1592: data_o = 32'h0004859b /* 0x18e0 */;
1593: data_o = 32'h009af463 /* 0x18e4 */;
1594: data_o = 32'h000c859b /* 0x18e8 */;
1595: data_o = 32'h05634601 /* 0x18ec */;
1596: data_o = 32'h16130009 /* 0x18f0 */;
1597: data_o = 32'h964a0084 /* 0x18f4 */;
1598: data_o = 32'h85634681 /* 0x18f8 */;
1599: data_o = 32'h16930009 /* 0x18fc */;
1600: data_o = 32'h96ce0084 /* 0x1900 */;
1601: data_o = 32'hf0ef855e /* 0x1904 */;
1602: data_o = 32'hd161ad7f /* 0x1908 */;
1603: data_o = 32'h644660e6 /* 0x190c */;
1604: data_o = 32'h690664a6 /* 0x1910 */;
1605: data_o = 32'h7a4279e2 /* 0x1914 */;
1606: data_o = 32'h7b027aa2 /* 0x1918 */;
1607: data_o = 32'h6c426be2 /* 0x191c */;
1608: data_o = 32'h61256ca2 /* 0x1920 */;
1609: data_o = 32'h45018082 /* 0x1924 */;
1610: data_o = 32'h6446b7d5 /* 0x1928 */;
1611: data_o = 32'h64a660e6 /* 0x192c */;
1612: data_o = 32'h79e26906 /* 0x1930 */;
1613: data_o = 32'h7aa27a42 /* 0x1934 */;
1614: data_o = 32'h6be27b02 /* 0x1938 */;
1615: data_o = 32'h6ca26c42 /* 0x193c */;
1616: data_o = 32'hbc696125 /* 0x1940 */;
1617: data_o = 32'h873e455c /* 0x1944 */;
1618: data_o = 32'h00f5f363 /* 0x1948 */;
1619: data_o = 32'h451c872e /* 0x194c */;
1620: data_o = 32'h0017171b /* 0x1950 */;
1621: data_o = 32'h02071693 /* 0x1954 */;
1622: data_o = 32'h17829fb9 /* 0x1958 */;
1623: data_o = 32'h92819381 /* 0x195c */;
1624: data_o = 32'hd7b317fd /* 0x1960 */;
1625: data_o = 32'h674102d7 /* 0x1964 */;
1626: data_o = 32'h17fd177d /* 0x1968 */;
1627: data_o = 32'h00e7f6b3 /* 0x196c */;
1628: data_o = 32'h00f68363 /* 0x1970 */;
1629: data_o = 32'h611487ba /* 0x1974 */;
1630: data_o = 32'h45017641 /* 0x1978 */;
1631: data_o = 32'h8f714e98 /* 0x197c */;
1632: data_o = 32'h27818fd9 /* 0x1980 */;
1633: data_o = 32'hcedcce9c /* 0x1984 */;
1634: data_o = 32'h61188082 /* 0x1988 */;
1635: data_o = 32'h01e5959b /* 0x198c */;
1636: data_o = 32'h0fff06b7 /* 0x1990 */;
1637: data_o = 32'h45014f1c /* 0x1994 */;
1638: data_o = 32'h93c117c2 /* 0x1998 */;
1639: data_o = 32'h8fd58fcd /* 0x199c */;
1640: data_o = 32'hcf1c2781 /* 0x19a0 */;
1641: data_o = 32'h8082cf5c /* 0x19a4 */;
1642: data_o = 32'hf8227139 /* 0x19a8 */;
1643: data_o = 32'hf04af426 /* 0x19ac */;
1644: data_o = 32'hec4efc06 /* 0x19b0 */;
1645: data_o = 32'he456e852 /* 0x19b4 */;
1646: data_o = 32'h71010080 /* 0x19b8 */;
1647: data_o = 32'h4685848a /* 0x19bc */;
1648: data_o = 32'h86267101 /* 0x19c0 */;
1649: data_o = 32'h892a4585 /* 0x19c4 */;
1650: data_o = 32'h504000ef /* 0x19c8 */;
1651: data_o = 32'h12051c63 /* 0x19cc */;
1652: data_o = 32'h00001517 /* 0x19d0 */;
1653: data_o = 32'hb3850513 /* 0x19d4 */;
1654: data_o = 32'h8d9ff0ef /* 0x19d8 */;
1655: data_o = 32'h1517608c /* 0x19dc */;
1656: data_o = 32'h05130000 /* 0x19e0 */;
1657: data_o = 32'hf0efb4a5 /* 0x19e4 */;
1658: data_o = 32'h448c8cbf /* 0x19e8 */;
1659: data_o = 32'h00001517 /* 0x19ec */;
1660: data_o = 32'hb5450513 /* 0x19f0 */;
1661: data_o = 32'h8bdff0ef /* 0x19f4 */;
1662: data_o = 32'h151744cc /* 0x19f8 */;
1663: data_o = 32'h05130000 /* 0x19fc */;
1664: data_o = 32'hf0efb5e5 /* 0x1a00 */;
1665: data_o = 32'h48cc8aff /* 0x1a04 */;
1666: data_o = 32'h00001517 /* 0x1a08 */;
1667: data_o = 32'hb6850513 /* 0x1a0c */;
1668: data_o = 32'h8a1ff0ef /* 0x1a10 */;
1669: data_o = 32'h15176c8c /* 0x1a14 */;
1670: data_o = 32'h05130000 /* 0x1a18 */;
1671: data_o = 32'hf0efb725 /* 0x1a1c */;
1672: data_o = 32'h708c893f /* 0x1a20 */;
1673: data_o = 32'h00001517 /* 0x1a24 */;
1674: data_o = 32'hb7c50513 /* 0x1a28 */;
1675: data_o = 32'h885ff0ef /* 0x1a2c */;
1676: data_o = 32'h151764ac /* 0x1a30 */;
1677: data_o = 32'h05130000 /* 0x1a34 */;
1678: data_o = 32'hf0efb8e5 /* 0x1a38 */;
1679: data_o = 32'h48ac877f /* 0x1a3c */;
1680: data_o = 32'h00001517 /* 0x1a40 */;
1681: data_o = 32'hba050513 /* 0x1a44 */;
1682: data_o = 32'h869ff0ef /* 0x1a48 */;
1683: data_o = 32'h151748ec /* 0x1a4c */;
1684: data_o = 32'h05130000 /* 0x1a50 */;
1685: data_o = 32'hf0efbba5 /* 0x1a54 */;
1686: data_o = 32'h44ac85bf /* 0x1a58 */;
1687: data_o = 32'h4685854a /* 0x1a5c */;
1688: data_o = 32'h00ef860a /* 0x1a60 */;
1689: data_o = 32'h8a2a46a0 /* 0x1a64 */;
1690: data_o = 32'h08010913 /* 0x1a68 */;
1691: data_o = 32'h4a914981 /* 0x1a6c */;
1692: data_o = 32'h1517e155 /* 0x1a70 */;
1693: data_o = 32'h85ce0000 /* 0x1a74 */;
1694: data_o = 32'hbee50513 /* 0x1a78 */;
1695: data_o = 32'h835ff0ef /* 0x1a7c */;
1696: data_o = 32'hfa093583 /* 0x1a80 */;
1697: data_o = 32'h00001517 /* 0x1a84 */;
1698: data_o = 32'hbfc50513 /* 0x1a88 */;
1699: data_o = 32'h825ff0ef /* 0x1a8c */;
1700: data_o = 32'hfa893583 /* 0x1a90 */;
1701: data_o = 32'h00001517 /* 0x1a94 */;
1702: data_o = 32'hc0450513 /* 0x1a98 */;
1703: data_o = 32'h815ff0ef /* 0x1a9c */;
1704: data_o = 32'hfb093583 /* 0x1aa0 */;
1705: data_o = 32'h00001517 /* 0x1aa4 */;
1706: data_o = 32'hc0c50513 /* 0x1aa8 */;
1707: data_o = 32'h805ff0ef /* 0x1aac */;
1708: data_o = 32'h00001517 /* 0x1ab0 */;
1709: data_o = 32'hc1850513 /* 0x1ab4 */;
1710: data_o = 32'hff8ff0ef /* 0x1ab8 */;
1711: data_o = 32'hfb890493 /* 0x1abc */;
1712: data_o = 32'h0004c583 /* 0x1ac0 */;
1713: data_o = 32'h00001517 /* 0x1ac4 */;
1714: data_o = 32'h05130485 /* 0x1ac8 */;
1715: data_o = 32'hf0efc0c5 /* 0x1acc */;
1716: data_o = 32'h97e3fe2f /* 0x1ad0 */;
1717: data_o = 32'h0517ff24 /* 0x1ad4 */;
1718: data_o = 32'h05130000 /* 0x1ad8 */;
1719: data_o = 32'h29857725 /* 0x1adc */;
1720: data_o = 32'hfd0ff0ef /* 0x1ae0 */;
1721: data_o = 32'h08090913 /* 0x1ae4 */;
1722: data_o = 32'hf95995e3 /* 0x1ae8 */;
1723: data_o = 32'hfc040113 /* 0x1aec */;
1724: data_o = 32'h855270e2 /* 0x1af0 */;
1725: data_o = 32'h74a27442 /* 0x1af4 */;
1726: data_o = 32'h69e27902 /* 0x1af8 */;
1727: data_o = 32'h6aa26a42 /* 0x1afc */;
1728: data_o = 32'h80826121 /* 0x1b00 */;
1729: data_o = 32'h15178a2a /* 0x1b04 */;
1730: data_o = 32'h05130000 /* 0x1b08 */;
1731: data_o = 32'hf0ef9da5 /* 0x1b0c */;
1732: data_o = 32'hbfe9fa2f /* 0x1b10 */;
1733: data_o = 32'h00001517 /* 0x1b14 */;
1734: data_o = 32'hb1c50513 /* 0x1b18 */;
1735: data_o = 32'hf94ff0ef /* 0x1b1c */;
1736: data_o = 32'h7139b7f1 /* 0x1b20 */;
1737: data_o = 32'hf04af822 /* 0x1b24 */;
1738: data_o = 32'he852ec4e /* 0x1b28 */;
1739: data_o = 32'hfc06e456 /* 0x1b2c */;
1740: data_o = 32'h0080f426 /* 0x1b30 */;
1741: data_o = 32'h8a8a7101 /* 0x1b34 */;
1742: data_o = 32'h8a32892e /* 0x1b38 */;
1743: data_o = 32'h46857101 /* 0x1b3c */;
1744: data_o = 32'h45858656 /* 0x1b40 */;
1745: data_o = 32'h00ef89aa /* 0x1b44 */;
1746: data_o = 32'hed153860 /* 0x1b48 */;
1747: data_o = 32'h048aa583 /* 0x1b4c */;
1748: data_o = 32'h860a4685 /* 0x1b50 */;
1749: data_o = 32'h00ef854e /* 0x1b54 */;
1750: data_o = 32'h84aa3760 /* 0x1b58 */;
1751: data_o = 32'h179bed0d /* 0x1b5c */;
1752: data_o = 32'h17820079 /* 0x1b60 */;
1753: data_o = 32'h978a9381 /* 0x1b64 */;
1754: data_o = 32'h2023739c /* 0x1b68 */;
1755: data_o = 32'h011300fa /* 0x1b6c */;
1756: data_o = 32'h70e2fc04 /* 0x1b70 */;
1757: data_o = 32'h74428526 /* 0x1b74 */;
1758: data_o = 32'h790274a2 /* 0x1b78 */;
1759: data_o = 32'h6a4269e2 /* 0x1b7c */;
1760: data_o = 32'h61216aa2 /* 0x1b80 */;
1761: data_o = 32'h84aa8082 /* 0x1b84 */;
1762: data_o = 32'h00001517 /* 0x1b88 */;
1763: data_o = 32'h95850513 /* 0x1b8c */;
1764: data_o = 32'hf20ff0ef /* 0x1b90 */;
1765: data_o = 32'h1517bfe9 /* 0x1b94 */;
1766: data_o = 32'h05130000 /* 0x1b98 */;
1767: data_o = 32'hf0efa9a5 /* 0x1b9c */;
1768: data_o = 32'hb7f1f12f /* 0x1ba0 */;
1769: data_o = 32'h02069713 /* 0x1ba4 */;
1770: data_o = 32'h43818793 /* 0x1ba8 */;
1771: data_o = 32'h71599301 /* 0x1bac */;
1772: data_o = 32'hf0a297ba /* 0x1bb0 */;
1773: data_o = 32'h0007c403 /* 0x1bb4 */;
1774: data_o = 32'hf486e8ca /* 0x1bb8 */;
1775: data_o = 32'h0034091b /* 0x1bbc */;
1776: data_o = 32'he4ceeca6 /* 0x1bc0 */;
1777: data_o = 32'hfc56e0d2 /* 0x1bc4 */;
1778: data_o = 32'hf45ef85a /* 0x1bc8 */;
1779: data_o = 32'hec66f062 /* 0x1bcc */;
1780: data_o = 32'h7913e86a /* 0x1bd0 */;
1781: data_o = 32'h47a11fc9 /* 0x1bd4 */;
1782: data_o = 32'h1327ea63 /* 0x1bd8 */;
1783: data_o = 32'h0105971b /* 0x1bdc */;
1784: data_o = 32'h0107571b /* 0x1be0 */;
1785: data_o = 32'h0085981b /* 0x1be4 */;
1786: data_o = 32'h0087571b /* 0x1be8 */;
1787: data_o = 32'h0285d313 /* 0x1bec */;
1788: data_o = 32'h0205d893 /* 0x1bf0 */;
1789: data_o = 32'h0105d793 /* 0x1bf4 */;
1790: data_o = 32'h00e86833 /* 0x1bf8 */;
1791: data_o = 32'h8d328a36 /* 0x1bfc */;
1792: data_o = 32'h46814705 /* 0x1c00 */;
1793: data_o = 32'h0593860a /* 0x1c04 */;
1794: data_o = 32'h8b2a0300 /* 0x1c08 */;
1795: data_o = 32'h00610023 /* 0x1c0c */;
1796: data_o = 32'h011100a3 /* 0x1c10 */;
1797: data_o = 32'h00010123 /* 0x1c14 */;
1798: data_o = 32'h00f101a3 /* 0x1c18 */;
1799: data_o = 32'h01011223 /* 0x1c1c */;
1800: data_o = 32'hc59ff0ef /* 0x1c20 */;
1801: data_o = 32'hcc79ed2d /* 0x1c24 */;
1802: data_o = 32'h00391c13 /* 0x1c28 */;
1803: data_o = 32'h4b854981 /* 0x1c2c */;
1804: data_o = 32'h4a854481 /* 0x1c30 */;
1805: data_o = 32'h04c00c93 /* 0x1c34 */;
1806: data_o = 32'h00344701 /* 0x1c38 */;
1807: data_o = 32'h85e24601 /* 0x1c3c */;
1808: data_o = 32'hf0ef855a /* 0x1c40 */;
1809: data_o = 32'hed21c37f /* 0x1c44 */;
1810: data_o = 32'hfe0908e3 /* 0x1c48 */;
1811: data_o = 32'h00014583 /* 0x1c4c */;
1812: data_o = 32'h47850038 /* 0x1c50 */;
1813: data_o = 32'h00099463 /* 0x1c54 */;
1814: data_o = 32'h03958563 /* 0x1c58 */;
1815: data_o = 32'h0803e489 /* 0x1c5c */;
1816: data_o = 32'h4b630007 /* 0x1c60 */;
1817: data_o = 32'hc8310008 /* 0x1c64 */;
1818: data_o = 32'h00074683 /* 0x1c68 */;
1819: data_o = 32'h008d0833 /* 0x1c6c */;
1820: data_o = 32'h0fa34485 /* 0x1c70 */;
1821: data_o = 32'h347dfed8 /* 0x1c74 */;
1822: data_o = 32'h0127f863 /* 0x1c78 */;
1823: data_o = 32'h07052785 /* 0x1c7c */;
1824: data_o = 32'h4985bfd1 /* 0x1c80 */;
1825: data_o = 32'hff27ece3 /* 0x1c84 */;
1826: data_o = 32'h4785f845 /* 0x1c88 */;
1827: data_o = 32'h04fa0463 /* 0x1c8c */;
1828: data_o = 32'h46814709 /* 0x1c90 */;
1829: data_o = 32'h45814601 /* 0x1c94 */;
1830: data_o = 32'hf0ef855a /* 0x1c98 */;
1831: data_o = 32'h70a6bdff /* 0x1c9c */;
1832: data_o = 32'h64e67406 /* 0x1ca0 */;
1833: data_o = 32'h69a66946 /* 0x1ca4 */;
1834: data_o = 32'h7ae26a06 /* 0x1ca8 */;
1835: data_o = 32'h7ba27b42 /* 0x1cac */;
1836: data_o = 32'h6ce27c02 /* 0x1cb0 */;
1837: data_o = 32'h61656d42 /* 0x1cb4 */;
1838: data_o = 32'h06638082 /* 0x1cb8 */;
1839: data_o = 32'hf6e3015a /* 0x1cbc */;
1840: data_o = 32'h4485fd27 /* 0x1cc0 */;
1841: data_o = 32'h8ce3bf65 /* 0x1cc4 */;
1842: data_o = 32'h4b83fe0b /* 0x1cc8 */;
1843: data_o = 32'hbb930007 /* 0x1ccc */;
1844: data_o = 32'hb7f5001b /* 0x1cd0 */;
1845: data_o = 32'hfa0b8ee3 /* 0x1cd4 */;
1846: data_o = 32'h84936489 /* 0x1cd8 */;
1847: data_o = 32'h00607104 /* 0x1cdc */;
1848: data_o = 32'h00344701 /* 0x1ce0 */;
1849: data_o = 32'h05934601 /* 0x1ce4 */;
1850: data_o = 32'h855a0200 /* 0x1ce8 */;
1851: data_o = 32'hb8dff0ef /* 0x1cec */;
1852: data_o = 32'hc703003c /* 0x1cf0 */;
1853: data_o = 32'h07850007 /* 0x1cf4 */;
1854: data_o = 32'h1ce3ff41 /* 0x1cf8 */;
1855: data_o = 32'h34fdfef4 /* 0x1cfc */;
1856: data_o = 32'hb779f0e5 /* 0x1d00 */;
1857: data_o = 32'h15e34785 /* 0x1d04 */;
1858: data_o = 32'hb7f9f8fa /* 0x1d08 */;
1859: data_o = 32'h00001517 /* 0x1d0c */;
1860: data_o = 32'h051385a2 /* 0x1d10 */;
1861: data_o = 32'hf0ef9cc5 /* 0x1d14 */;
1862: data_o = 32'h557dd9af /* 0x1d18 */;
1863: data_o = 32'h7139b749 /* 0x1d1c */;
1864: data_o = 32'h46814701 /* 0x1d20 */;
1865: data_o = 32'h05934601 /* 0x1d24 */;
1866: data_o = 32'hf8220500 /* 0x1d28 */;
1867: data_o = 32'hfc06f426 /* 0x1d2c */;
1868: data_o = 32'hec4ef04a /* 0x1d30 */;
1869: data_o = 32'he40284aa /* 0x1d34 */;
1870: data_o = 32'hb41ff0ef /* 0x1d38 */;
1871: data_o = 32'hc909842a /* 0x1d3c */;
1872: data_o = 32'h852270e2 /* 0x1d40 */;
1873: data_o = 32'h74a27442 /* 0x1d44 */;
1874: data_o = 32'h69e27902 /* 0x1d48 */;
1875: data_o = 32'h80826121 /* 0x1d4c */;
1876: data_o = 32'h15934905 /* 0x1d50 */;
1877: data_o = 32'h468102e9 /* 0x1d54 */;
1878: data_o = 32'h85930030 /* 0x1d58 */;
1879: data_o = 32'h85260955 /* 0x1d5c */;
1880: data_o = 32'he45ff0ef /* 0x1d60 */;
1881: data_o = 32'hfd69842a /* 0x1d64 */;
1882: data_o = 32'h151765a2 /* 0x1d68 */;
1883: data_o = 32'h05130000 /* 0x1d6c */;
1884: data_o = 32'hf9939a65 /* 0x1d70 */;
1885: data_o = 32'h841b0ff5 /* 0x1d74 */;
1886: data_o = 32'hf0ef0009 /* 0x1d78 */;
1887: data_o = 32'h91e3d36f /* 0x1d7c */;
1888: data_o = 32'h1797fd29 /* 0x1d80 */;
1889: data_o = 32'hb5830000 /* 0x1d84 */;
1890: data_o = 32'h469dbde7 /* 0x1d88 */;
1891: data_o = 32'h85260030 /* 0x1d8c */;
1892: data_o = 32'hf0efe402 /* 0x1d90 */;
1893: data_o = 32'h842ae13f /* 0x1d94 */;
1894: data_o = 32'h6422f545 /* 0x1d98 */;
1895: data_o = 32'h00001517 /* 0x1d9c */;
1896: data_o = 32'h99450513 /* 0x1da0 */;
1897: data_o = 32'hf0ef85a2 /* 0x1da4 */;
1898: data_o = 32'h1793d0af /* 0x1da8 */;
1899: data_o = 32'h19820184 /* 0x1dac */;
1900: data_o = 32'h899383e1 /* 0x1db0 */;
1901: data_o = 32'h74131aa9 /* 0x1db4 */;
1902: data_o = 32'h93e30ff4 /* 0x1db8 */;
1903: data_o = 32'h0913f937 /* 0x1dbc */;
1904: data_o = 32'h19220770 /* 0x1dc0 */;
1905: data_o = 32'h00304681 /* 0x1dc4 */;
1906: data_o = 32'h06590593 /* 0x1dc8 */;
1907: data_o = 32'he4028526 /* 0x1dcc */;
1908: data_o = 32'hdd5ff0ef /* 0x1dd0 */;
1909: data_o = 32'hf52d842a /* 0x1dd4 */;
1910: data_o = 32'h151765a2 /* 0x1dd8 */;
1911: data_o = 32'h05130000 /* 0x1ddc */;
1912: data_o = 32'h09939765 /* 0x1de0 */;
1913: data_o = 32'hf0ef1a50 /* 0x1de4 */;
1914: data_o = 32'h199accaf /* 0x1de8 */;
1915: data_o = 32'h00304681 /* 0x1dec */;
1916: data_o = 32'h07798593 /* 0x1df0 */;
1917: data_o = 32'he4028526 /* 0x1df4 */;
1918: data_o = 32'hdadff0ef /* 0x1df8 */;
1919: data_o = 32'hf129842a /* 0x1dfc */;
1920: data_o = 32'h15176422 /* 0x1e00 */;
1921: data_o = 32'h05130000 /* 0x1e04 */;
1922: data_o = 32'h85a296e5 /* 0x1e08 */;
1923: data_o = 32'h0ff47413 /* 0x1e0c */;
1924: data_o = 32'hca0ff0ef /* 0x1e10 */;
1925: data_o = 32'h0913c839 /* 0x1e14 */;
1926: data_o = 32'h89930659 /* 0x1e18 */;
1927: data_o = 32'h46810779 /* 0x1e1c */;
1928: data_o = 32'h85ca0030 /* 0x1e20 */;
1929: data_o = 32'he4028526 /* 0x1e24 */;
1930: data_o = 32'hd7dff0ef /* 0x1e28 */;
1931: data_o = 32'h1517842a /* 0x1e2c */;
1932: data_o = 32'h05130000 /* 0x1e30 */;
1933: data_o = 32'h15e39225 /* 0x1e34 */;
1934: data_o = 32'h65a2f004 /* 0x1e38 */;
1935: data_o = 32'hc74ff0ef /* 0x1e3c */;
1936: data_o = 32'h00304681 /* 0x1e40 */;
1937: data_o = 32'h852685ce /* 0x1e44 */;
1938: data_o = 32'hf0efe402 /* 0x1e48 */;
1939: data_o = 32'h842ad5bf /* 0x1e4c */;
1940: data_o = 32'h00001517 /* 0x1e50 */;
1941: data_o = 32'h92050513 /* 0x1e54 */;
1942: data_o = 32'hee0414e3 /* 0x1e58 */;
1943: data_o = 32'h85a26422 /* 0x1e5c */;
1944: data_o = 32'h0ff47413 /* 0x1e60 */;
1945: data_o = 32'hc4cff0ef /* 0x1e64 */;
1946: data_o = 32'h0593f85d /* 0x1e68 */;
1947: data_o = 32'h15a603d0 /* 0x1e6c */;
1948: data_o = 32'h0030468d /* 0x1e70 */;
1949: data_o = 32'h0ff58593 /* 0x1e74 */;
1950: data_o = 32'he4028526 /* 0x1e78 */;
1951: data_o = 32'hd29ff0ef /* 0x1e7c */;
1952: data_o = 32'h1fe3842a /* 0x1e80 */;
1953: data_o = 32'h65a2ea05 /* 0x1e84 */;
1954: data_o = 32'h00001517 /* 0x1e88 */;
1955: data_o = 32'h90850513 /* 0x1e8c */;
1956: data_o = 32'hc20ff0ef /* 0x1e90 */;
1957: data_o = 32'h00001797 /* 0x1e94 */;
1958: data_o = 32'had47b583 /* 0x1e98 */;
1959: data_o = 32'h00304681 /* 0x1e9c */;
1960: data_o = 32'he4028526 /* 0x1ea0 */;
1961: data_o = 32'hd01ff0ef /* 0x1ea4 */;
1962: data_o = 32'h1be3842a /* 0x1ea8 */;
1963: data_o = 32'h64a2e805 /* 0x1eac */;
1964: data_o = 32'h00001517 /* 0x1eb0 */;
1965: data_o = 32'h90050513 /* 0x1eb4 */;
1966: data_o = 32'hf49385a6 /* 0x1eb8 */;
1967: data_o = 32'hf0ef0ff4 /* 0x1ebc */;
1968: data_o = 32'h8fe3bf2f /* 0x1ec0 */;
1969: data_o = 32'h841be604 /* 0x1ec4 */;
1970: data_o = 32'hbd9d0004 /* 0x1ec8 */;
1971: data_o = 32'hf8a27119 /* 0x1ecc */;
1972: data_o = 32'hf4a6fc86 /* 0x1ed0 */;
1973: data_o = 32'heccef0ca /* 0x1ed4 */;
1974: data_o = 32'he4d6e8d2 /* 0x1ed8 */;
1975: data_o = 32'hfc5ee0da /* 0x1edc */;
1976: data_o = 32'hf466f862 /* 0x1ee0 */;
1977: data_o = 32'hec6ef06a /* 0x1ee4 */;
1978: data_o = 32'h80634401 /* 0x1ee8 */;
1979: data_o = 32'h941b1206 /* 0x1eec */;
1980: data_o = 32'h14020085 /* 0x1ef0 */;
1981: data_o = 32'h8b364705 /* 0x1ef4 */;
1982: data_o = 32'h84b2892a /* 0x1ef8 */;
1983: data_o = 32'h86639001 /* 0x1efc */;
1984: data_o = 32'h071312e6 /* 0x1f00 */;
1985: data_o = 32'h15170290 /* 0x1f04 */;
1986: data_o = 32'h17930000 /* 0x1f08 */;
1987: data_o = 32'h86b20297 /* 0x1f0c */;
1988: data_o = 32'h862e0785 /* 0x1f10 */;
1989: data_o = 32'h90250513 /* 0x1f14 */;
1990: data_o = 32'h8c5d85da /* 0x1f18 */;
1991: data_o = 32'hb94ff0ef /* 0x1f1c */;
1992: data_o = 32'h01045793 /* 0x1f20 */;
1993: data_o = 32'h02845893 /* 0x1f24 */;
1994: data_o = 32'h01845813 /* 0x1f28 */;
1995: data_o = 32'h00f101a3 /* 0x1f2c */;
1996: data_o = 32'h47858021 /* 0x1f30 */;
1997: data_o = 32'h46814705 /* 0x1f34 */;
1998: data_o = 32'h0593860a /* 0x1f38 */;
1999: data_o = 32'h854a0300 /* 0x1f3c */;
2000: data_o = 32'h00810223 /* 0x1f40 */;
2001: data_o = 32'h01110023 /* 0x1f44 */;
2002: data_o = 32'h000100a3 /* 0x1f48 */;
2003: data_o = 32'h01010123 /* 0x1f4c */;
2004: data_o = 32'h00f102a3 /* 0x1f50 */;
2005: data_o = 32'h925ff0ef /* 0x1f54 */;
2006: data_o = 32'he945842a /* 0x1f58 */;
2007: data_o = 32'h0c134d01 /* 0x1f5c */;
2008: data_o = 32'h4b812000 /* 0x1f60 */;
2009: data_o = 32'h49914a01 /* 0x1f64 */;
2010: data_o = 32'h0a934d85 /* 0x1f68 */;
2011: data_o = 32'h4c8d0fe0 /* 0x1f6c */;
2012: data_o = 32'h00344701 /* 0x1f70 */;
2013: data_o = 32'h05934601 /* 0x1f74 */;
2014: data_o = 32'h854a0200 /* 0x1f78 */;
2015: data_o = 32'h8fdff0ef /* 0x1f7c */;
2016: data_o = 32'he541842a /* 0x1f80 */;
2017: data_o = 32'h1063003c /* 0x1f84 */;
2018: data_o = 32'hc583040a /* 0x1f88 */;
2019: data_o = 32'h24050007 /* 0x1f8c */;
2020: data_o = 32'h971b0785 /* 0x1f90 */;
2021: data_o = 32'h571b0185 /* 0x1f94 */;
2022: data_o = 32'h5e634187 /* 0x1f98 */;
2023: data_o = 32'h09e30007 /* 0x1f9c */;
2024: data_o = 32'hc583fd34 /* 0x1fa0 */;
2025: data_o = 32'h24050007 /* 0x1fa4 */;
2026: data_o = 32'h971b0785 /* 0x1fa8 */;
2027: data_o = 32'h571b0185 /* 0x1fac */;
2028: data_o = 32'h46e34187 /* 0x1fb0 */;
2029: data_o = 32'h1517fe07 /* 0x1fb4 */;
2030: data_o = 32'h05130000 /* 0x1fb8 */;
2031: data_o = 32'hf0ef89a5 /* 0x1fbc */;
2032: data_o = 32'h0f63af2f /* 0x1fc0 */;
2033: data_o = 32'h003c0134 /* 0x1fc4 */;
2034: data_o = 32'hc58397a2 /* 0x1fc8 */;
2035: data_o = 32'h07850007 /* 0x1fcc */;
2036: data_o = 32'h0f05f713 /* 0x1fd0 */;
2037: data_o = 32'h07558763 /* 0x1fd4 */;
2038: data_o = 32'h2405c711 /* 0x1fd8 */;
2039: data_o = 32'hff3417e3 /* 0x1fdc */;
2040: data_o = 32'hb7794a05 /* 0x1fe0 */;
2041: data_o = 32'h00001517 /* 0x1fe4 */;
2042: data_o = 32'h89c50513 /* 0x1fe8 */;
2043: data_o = 32'hac4ff0ef /* 0x1fec */;
2044: data_o = 32'h46814709 /* 0x1ff0 */;
2045: data_o = 32'h45814601 /* 0x1ff4 */;
2046: data_o = 32'hf0ef854a /* 0x1ff8 */;
2047: data_o = 32'h079387ff /* 0x1ffc */;
2048: data_o = 32'h84330104 /* 0x2000 */;
2049: data_o = 32'h44030027 /* 0x2004 */;
2050: data_o = 32'h70e6ff84 /* 0x2008 */;
2051: data_o = 32'h74468522 /* 0x200c */;
2052: data_o = 32'h790674a6 /* 0x2010 */;
2053: data_o = 32'h6a4669e6 /* 0x2014 */;
2054: data_o = 32'h6b066aa6 /* 0x2018 */;
2055: data_o = 32'h7c427be2 /* 0x201c */;
2056: data_o = 32'h7d027ca2 /* 0x2020 */;
2057: data_o = 32'h61096de2 /* 0x2024 */;
2058: data_o = 32'h07938082 /* 0x2028 */;
2059: data_o = 32'h05170510 /* 0x202c */;
2060: data_o = 32'h17a20000 /* 0x2030 */;
2061: data_o = 32'h05130785 /* 0x2034 */;
2062: data_o = 32'h8c5d7a25 /* 0x2038 */;
2063: data_o = 32'ha74ff0ef /* 0x203c */;
2064: data_o = 32'h2b85b5c5 /* 0x2040 */;
2065: data_o = 32'h20000793 /* 0x2044 */;
2066: data_o = 32'h0d636585 /* 0x2048 */;
2067: data_o = 32'h003c0394 /* 0x204c */;
2068: data_o = 32'he03c051b /* 0x2050 */;
2069: data_o = 32'h008786b3 /* 0x2054 */;
2070: data_o = 32'h0004059b /* 0x2058 */;
2071: data_o = 32'h87ea9d01 /* 0x205c */;
2072: data_o = 32'h0016c603 /* 0x2060 */;
2073: data_o = 32'h02079713 /* 0x2064 */;
2074: data_o = 32'h97269301 /* 0x2068 */;
2075: data_o = 32'h00c70023 /* 0x206c */;
2076: data_o = 32'h06852785 /* 0x2070 */;
2077: data_o = 32'hfef516e3 /* 0x2074 */;
2078: data_o = 32'h1fd5879b /* 0x2078 */;
2079: data_o = 32'h0037959b /* 0x207c */;
2080: data_o = 32'h93811782 /* 0x2080 */;
2081: data_o = 32'h020c1693 /* 0x2084 */;
2082: data_o = 32'h8e9d9281 /* 0x2088 */;
2083: data_o = 32'h96a64701 /* 0x208c */;
2084: data_o = 32'h854a4601 /* 0x2090 */;
2085: data_o = 32'hfe4ff0ef /* 0x2094 */;
2086: data_o = 32'hf925842a /* 0x2098 */;
2087: data_o = 32'h00344701 /* 0x209c */;
2088: data_o = 32'h45c14601 /* 0x20a0 */;
2089: data_o = 32'hf0ef854a /* 0x20a4 */;
2090: data_o = 32'h842afd2f /* 0x20a8 */;
2091: data_o = 32'h0c1bfd39 /* 0x20ac */;
2092: data_o = 32'h0d1b200c /* 0x20b0 */;
2093: data_o = 32'h4a05200d /* 0x20b4 */;
2094: data_o = 32'heb7b1ce3 /* 0x20b8 */;
2095: data_o = 32'h03bb0463 /* 0x20bc */;
2096: data_o = 32'h15aa45cd /* 0x20c0 */;
2097: data_o = 32'h46850585 /* 0x20c4 */;
2098: data_o = 32'h854a0030 /* 0x20c8 */;
2099: data_o = 32'hf0efe402 /* 0x20cc */;
2100: data_o = 32'h65a2ad7f /* 0x20d0 */;
2101: data_o = 32'h0517842a /* 0x20d4 */;
2102: data_o = 32'h05130000 /* 0x20d8 */;
2103: data_o = 32'hf0ef7d25 /* 0x20dc */;
2104: data_o = 32'hb7259d2f /* 0x20e0 */;
2105: data_o = 32'h46814709 /* 0x20e4 */;
2106: data_o = 32'h45814601 /* 0x20e8 */;
2107: data_o = 32'hf0ef854a /* 0x20ec */;
2108: data_o = 32'hbf21f8af /* 0x20f0 */;
2109: data_o = 32'h00000000 /* 0x20f4 */;
2110: data_o = 32'h6978615b /* 0x20f8 */;
2111: data_o = 32'h636c6c5f /* 0x20fc */;
2112: data_o = 32'h5841205d /* 0x2100 */;
2113: data_o = 32'h4c4c2049 /* 0x2104 */;
2114: data_o = 32'h65562043 /* 0x2108 */;
2115: data_o = 32'h6f697372 /* 0x210c */;
2116: data_o = 32'h2020206e /* 0x2110 */;
2117: data_o = 32'h2020203a /* 0x2114 */;
2118: data_o = 32'h20202020 /* 0x2118 */;
2119: data_o = 32'h6c257830 /* 0x211c */;
2120: data_o = 32'h000a0d78 /* 0x2120 */;
2121: data_o = 32'h00000000 /* 0x2124 */;
2122: data_o = 32'h6978615b /* 0x2128 */;
2123: data_o = 32'h636c6c5f /* 0x212c */;
2124: data_o = 32'h6553205d /* 0x2130 */;
2125: data_o = 32'h73412074 /* 0x2134 */;
2126: data_o = 32'h69636f73 /* 0x2138 */;
2127: data_o = 32'h76697461 /* 0x213c */;
2128: data_o = 32'h20797469 /* 0x2140 */;
2129: data_o = 32'h2020203a /* 0x2144 */;
2130: data_o = 32'h20202020 /* 0x2148 */;
2131: data_o = 32'h0a0d6425 /* 0x214c */;
2132: data_o = 32'h00000000 /* 0x2150 */;
2133: data_o = 32'h00000000 /* 0x2154 */;
2134: data_o = 32'h6978615b /* 0x2158 */;
2135: data_o = 32'h636c6c5f /* 0x215c */;
2136: data_o = 32'h754e205d /* 0x2160 */;
2137: data_o = 32'h6c42206d /* 0x2164 */;
2138: data_o = 32'h736b636f /* 0x2168 */;
2139: data_o = 32'h20202020 /* 0x216c */;
2140: data_o = 32'h20202020 /* 0x2170 */;
2141: data_o = 32'h2020203a /* 0x2174 */;
2142: data_o = 32'h20202020 /* 0x2178 */;
2143: data_o = 32'h0a0d6425 /* 0x217c */;
2144: data_o = 32'h00000000 /* 0x2180 */;
2145: data_o = 32'h00000000 /* 0x2184 */;
2146: data_o = 32'h6978615b /* 0x2188 */;
2147: data_o = 32'h636c6c5f /* 0x218c */;
2148: data_o = 32'h754e205d /* 0x2190 */;
2149: data_o = 32'h694c206d /* 0x2194 */;
2150: data_o = 32'h2073656e /* 0x2198 */;
2151: data_o = 32'h20202020 /* 0x219c */;
2152: data_o = 32'h20202020 /* 0x21a0 */;
2153: data_o = 32'h2020203a /* 0x21a4 */;
2154: data_o = 32'h20202020 /* 0x21a8 */;
2155: data_o = 32'h0a0d6425 /* 0x21ac */;
2156: data_o = 32'h00000000 /* 0x21b0 */;
2157: data_o = 32'h00000000 /* 0x21b4 */;
2158: data_o = 32'h6978615b /* 0x21b8 */;
2159: data_o = 32'h636c6c5f /* 0x21bc */;
2160: data_o = 32'h4942205d /* 0x21c0 */;
2161: data_o = 32'h4f205453 /* 0x21c4 */;
2162: data_o = 32'h6f637475 /* 0x21c8 */;
2163: data_o = 32'h2020656d /* 0x21cc */;
2164: data_o = 32'h20202020 /* 0x21d0 */;
2165: data_o = 32'h2020203a /* 0x21d4 */;
2166: data_o = 32'h20202020 /* 0x21d8 */;
2167: data_o = 32'h0a0d6425 /* 0x21dc */;
2168: data_o = 32'h00000000 /* 0x21e0 */;
2169: data_o = 32'h00000000 /* 0x21e4 */;
2170: data_o = 32'h69706f43 /* 0x21e8 */;
2171: data_o = 32'h64206465 /* 0x21ec */;
2172: data_o = 32'h63697665 /* 0x21f0 */;
2173: data_o = 32'h72742065 /* 0x21f4 */;
2174: data_o = 32'h74206565 /* 0x21f8 */;
2175: data_o = 32'h7830206f /* 0x21fc */;
2176: data_o = 32'h0d786c25 /* 0x2200 */;
2177: data_o = 32'h0000000a /* 0x2204 */;
2178: data_o = 32'h69706f43 /* 0x2208 */;
2179: data_o = 32'h66206465 /* 0x220c */;
2180: data_o = 32'h776d7269 /* 0x2210 */;
2181: data_o = 32'h20657261 /* 0x2214 */;
2182: data_o = 32'h30206f74 /* 0x2218 */;
2183: data_o = 32'h786c2578 /* 0x221c */;
2184: data_o = 32'h00000a0d /* 0x2220 */;
2185: data_o = 32'h00000000 /* 0x2224 */;
2186: data_o = 32'h746f6f42 /* 0x2228 */;
2187: data_o = 32'h65646f6d /* 0x222c */;
2188: data_o = 32'h203a3020 /* 0x2230 */;
2189: data_o = 32'h746f6f42 /* 0x2234 */;
2190: data_o = 32'h20676e69 /* 0x2238 */;
2191: data_o = 32'h6d6f7266 /* 0x223c */;
2192: data_o = 32'h20445320 /* 0x2240 */;
2193: data_o = 32'h64726143 /* 0x2244 */;
2194: data_o = 32'h00000a0d /* 0x2248 */;
2195: data_o = 32'h00000000 /* 0x224c */;
2196: data_o = 32'h746f6f42 /* 0x2250 */;
2197: data_o = 32'h65646f6d /* 0x2254 */;
2198: data_o = 32'h203a3120 /* 0x2258 */;
2199: data_o = 32'h6e696f44 /* 0x225c */;
2200: data_o = 32'h6f6e2067 /* 0x2260 */;
2201: data_o = 32'h6e696874 /* 0x2264 */;
2202: data_o = 32'h293a2067 /* 0x2268 */;
2203: data_o = 32'h00000a0d /* 0x226c */;
2204: data_o = 32'h746f6f42 /* 0x2270 */;
2205: data_o = 32'h65646f6d /* 0x2274 */;
2206: data_o = 32'h203a3220 /* 0x2278 */;
2207: data_o = 32'h6e696f44 /* 0x227c */;
2208: data_o = 32'h6f6e2067 /* 0x2280 */;
2209: data_o = 32'h6e696874 /* 0x2284 */;
2210: data_o = 32'h293a2067 /* 0x2288 */;
2211: data_o = 32'h00000a0d /* 0x228c */;
2212: data_o = 32'h746f6f42 /* 0x2290 */;
2213: data_o = 32'h65646f6d /* 0x2294 */;
2214: data_o = 32'h203a3320 /* 0x2298 */;
2215: data_o = 32'h6e696f44 /* 0x229c */;
2216: data_o = 32'h6f6e2067 /* 0x22a0 */;
2217: data_o = 32'h6e696874 /* 0x22a4 */;
2218: data_o = 32'h293a2067 /* 0x22a8 */;
2219: data_o = 32'h00000a0d /* 0x22ac */;
2220: data_o = 32'h746f6f42 /* 0x22b0 */;
2221: data_o = 32'h65646f6d /* 0x22b4 */;
2222: data_o = 32'h3a642520 /* 0x22b8 */;
2223: data_o = 32'h696f4420 /* 0x22bc */;
2224: data_o = 32'h6e20676e /* 0x22c0 */;
2225: data_o = 32'h6968746f /* 0x22c4 */;
2226: data_o = 32'h3a20676e /* 0x22c8 */;
2227: data_o = 32'h000a0d29 /* 0x22cc */;
2228: data_o = 32'h2b696e66 /* 0x22d0 */;
2229: data_o = 32'h00000000 /* 0x22d4 */;
2230: data_o = 32'h00696e66 /* 0x22d8 */;
2231: data_o = 32'h00000000 /* 0x22dc */;
2232: data_o = 32'h006e616e /* 0x22e0 */;
2233: data_o = 32'h00000000 /* 0x22e4 */;
2234: data_o = 32'h2d696e66 /* 0x22e8 */;
2235: data_o = 32'h00000000 /* 0x22ec */;
2236: data_o = 32'hffffea40 /* 0x22f0 */;
2237: data_o = 32'hffffe9a8 /* 0x22f4 */;
2238: data_o = 32'hffffe9a8 /* 0x22f8 */;
2239: data_o = 32'hffffea38 /* 0x22fc */;
2240: data_o = 32'hffffe9a8 /* 0x2300 */;
2241: data_o = 32'hffffe9a8 /* 0x2304 */;
2242: data_o = 32'hffffe9a8 /* 0x2308 */;
2243: data_o = 32'hffffe9a8 /* 0x230c */;
2244: data_o = 32'hffffe9a8 /* 0x2310 */;
2245: data_o = 32'hffffe9a8 /* 0x2314 */;
2246: data_o = 32'hffffe9a8 /* 0x2318 */;
2247: data_o = 32'hffffea30 /* 0x231c */;
2248: data_o = 32'hffffe9a8 /* 0x2320 */;
2249: data_o = 32'hffffea28 /* 0x2324 */;
2250: data_o = 32'hffffe9a8 /* 0x2328 */;
2251: data_o = 32'hffffe9a8 /* 0x232c */;
2252: data_o = 32'hffffea20 /* 0x2330 */;
2253: data_o = 32'hffffeb24 /* 0x2334 */;
2254: data_o = 32'hffffe9ac /* 0x2338 */;
2255: data_o = 32'hffffe9a2 /* 0x233c */;
2256: data_o = 32'hffffe9ac /* 0x2340 */;
2257: data_o = 32'hffffeb0a /* 0x2344 */;
2258: data_o = 32'hffffe9ac /* 0x2348 */;
2259: data_o = 32'hffffe9ac /* 0x234c */;
2260: data_o = 32'hffffe9ac /* 0x2350 */;
2261: data_o = 32'hffffe9ac /* 0x2354 */;
2262: data_o = 32'hffffe9ac /* 0x2358 */;
2263: data_o = 32'hffffe9ac /* 0x235c */;
2264: data_o = 32'hffffe9ac /* 0x2360 */;
2265: data_o = 32'hffffe9a2 /* 0x2364 */;
2266: data_o = 32'hffffe9ac /* 0x2368 */;
2267: data_o = 32'hffffe9ac /* 0x236c */;
2268: data_o = 32'hffffe9ac /* 0x2370 */;
2269: data_o = 32'hffffe9ac /* 0x2374 */;
2270: data_o = 32'hffffe9ac /* 0x2378 */;
2271: data_o = 32'hffffe9a2 /* 0x237c */;
2272: data_o = 32'hffffeb56 /* 0x2380 */;
2273: data_o = 32'hffffe8da /* 0x2384 */;
2274: data_o = 32'hffffe8da /* 0x2388 */;
2275: data_o = 32'hffffe8da /* 0x238c */;
2276: data_o = 32'hffffe8da /* 0x2390 */;
2277: data_o = 32'hffffe8da /* 0x2394 */;
2278: data_o = 32'hffffe8da /* 0x2398 */;
2279: data_o = 32'hffffe8da /* 0x239c */;
2280: data_o = 32'hffffe8da /* 0x23a0 */;
2281: data_o = 32'hffffe8da /* 0x23a4 */;
2282: data_o = 32'hffffe8da /* 0x23a8 */;
2283: data_o = 32'hffffe8da /* 0x23ac */;
2284: data_o = 32'hffffe8da /* 0x23b0 */;
2285: data_o = 32'hffffe8da /* 0x23b4 */;
2286: data_o = 32'hffffe8da /* 0x23b8 */;
2287: data_o = 32'hffffe8da /* 0x23bc */;
2288: data_o = 32'hffffe8da /* 0x23c0 */;
2289: data_o = 32'hffffe8da /* 0x23c4 */;
2290: data_o = 32'hffffe8da /* 0x23c8 */;
2291: data_o = 32'hffffe8da /* 0x23cc */;
2292: data_o = 32'hffffe8da /* 0x23d0 */;
2293: data_o = 32'hffffe8da /* 0x23d4 */;
2294: data_o = 32'hffffe8da /* 0x23d8 */;
2295: data_o = 32'hffffe8da /* 0x23dc */;
2296: data_o = 32'hffffe8da /* 0x23e0 */;
2297: data_o = 32'hffffe8da /* 0x23e4 */;
2298: data_o = 32'hffffe8da /* 0x23e8 */;
2299: data_o = 32'hffffe8da /* 0x23ec */;
2300: data_o = 32'hffffe8da /* 0x23f0 */;
2301: data_o = 32'hffffe8da /* 0x23f4 */;
2302: data_o = 32'hffffe8da /* 0x23f8 */;
2303: data_o = 32'hffffe8da /* 0x23fc */;
2304: data_o = 32'hffffec42 /* 0x2400 */;
2305: data_o = 32'hffffeaec /* 0x2404 */;
2306: data_o = 32'hffffec42 /* 0x2408 */;
2307: data_o = 32'hffffe8da /* 0x240c */;
2308: data_o = 32'hffffe8da /* 0x2410 */;
2309: data_o = 32'hffffe8da /* 0x2414 */;
2310: data_o = 32'hffffe8da /* 0x2418 */;
2311: data_o = 32'hffffe8da /* 0x241c */;
2312: data_o = 32'hffffe8da /* 0x2420 */;
2313: data_o = 32'hffffe8da /* 0x2424 */;
2314: data_o = 32'hffffe8da /* 0x2428 */;
2315: data_o = 32'hffffe8da /* 0x242c */;
2316: data_o = 32'hffffe8da /* 0x2430 */;
2317: data_o = 32'hffffe8da /* 0x2434 */;
2318: data_o = 32'hffffe8da /* 0x2438 */;
2319: data_o = 32'hffffe8da /* 0x243c */;
2320: data_o = 32'hffffe8da /* 0x2440 */;
2321: data_o = 32'hffffe8da /* 0x2444 */;
2322: data_o = 32'hffffe8da /* 0x2448 */;
2323: data_o = 32'hffffec70 /* 0x244c */;
2324: data_o = 32'hffffe8da /* 0x2450 */;
2325: data_o = 32'hffffe8da /* 0x2454 */;
2326: data_o = 32'hffffe8da /* 0x2458 */;
2327: data_o = 32'hffffe8da /* 0x245c */;
2328: data_o = 32'hffffe8da /* 0x2460 */;
2329: data_o = 32'hffffe8da /* 0x2464 */;
2330: data_o = 32'hffffe8da /* 0x2468 */;
2331: data_o = 32'hffffe8da /* 0x246c */;
2332: data_o = 32'hffffe8da /* 0x2470 */;
2333: data_o = 32'hffffec70 /* 0x2474 */;
2334: data_o = 32'hffffeb0e /* 0x2478 */;
2335: data_o = 32'hffffec70 /* 0x247c */;
2336: data_o = 32'hffffec42 /* 0x2480 */;
2337: data_o = 32'hffffeaec /* 0x2484 */;
2338: data_o = 32'hffffec42 /* 0x2488 */;
2339: data_o = 32'h00000000 /* 0x248c */;
2340: data_o = 32'h00000000 /* 0x2490 */;
2341: data_o = 32'h3ff00000 /* 0x2494 */;
2342: data_o = 32'h00000000 /* 0x2498 */;
2343: data_o = 32'h40240000 /* 0x249c */;
2344: data_o = 32'h00000000 /* 0x24a0 */;
2345: data_o = 32'h40590000 /* 0x24a4 */;
2346: data_o = 32'h00000000 /* 0x24a8 */;
2347: data_o = 32'h408f4000 /* 0x24ac */;
2348: data_o = 32'h00000000 /* 0x24b0 */;
2349: data_o = 32'h40c38800 /* 0x24b4 */;
2350: data_o = 32'h00000000 /* 0x24b8 */;
2351: data_o = 32'h40f86a00 /* 0x24bc */;
2352: data_o = 32'h00000000 /* 0x24c0 */;
2353: data_o = 32'h412e8480 /* 0x24c4 */;
2354: data_o = 32'h00000000 /* 0x24c8 */;
2355: data_o = 32'h416312d0 /* 0x24cc */;
2356: data_o = 32'h00000000 /* 0x24d0 */;
2357: data_o = 32'h4197d784 /* 0x24d4 */;
2358: data_o = 32'h00000000 /* 0x24d8 */;
2359: data_o = 32'h41cdcd65 /* 0x24dc */;
2360: data_o = 32'h63204453 /* 0x24e0 */;
2361: data_o = 32'h20647261 /* 0x24e4 */;
2362: data_o = 32'h79706f63 /* 0x24e8 */;
2363: data_o = 32'h20666f20 /* 0x24ec */;
2364: data_o = 32'h64616568 /* 0x24f0 */;
2365: data_o = 32'h66207265 /* 0x24f4 */;
2366: data_o = 32'h656c6961 /* 0x24f8 */;
2367: data_o = 32'h0a0d2164 /* 0x24fc */;
2368: data_o = 32'h00000000 /* 0x2500 */;
2369: data_o = 32'h00000000 /* 0x2504 */;
2370: data_o = 32'h20545047 /* 0x2508 */;
2371: data_o = 32'h74726170 /* 0x250c */;
2372: data_o = 32'h6f697469 /* 0x2510 */;
2373: data_o = 32'h6174206e /* 0x2514 */;
2374: data_o = 32'h20656c62 /* 0x2518 */;
2375: data_o = 32'h64616568 /* 0x251c */;
2376: data_o = 32'h0d3a7265 /* 0x2520 */;
2377: data_o = 32'h0000000a /* 0x2524 */;
2378: data_o = 32'h67697309 /* 0x2528 */;
2379: data_o = 32'h7574616e /* 0x252c */;
2380: data_o = 32'h093a6572 /* 0x2530 */;
2381: data_o = 32'h25783020 /* 0x2534 */;
2382: data_o = 32'h0a0d786c /* 0x2538 */;
2383: data_o = 32'h00000000 /* 0x253c */;
2384: data_o = 32'h76657209 /* 0x2540 */;
2385: data_o = 32'h6f697369 /* 0x2544 */;
2386: data_o = 32'h20093a6e /* 0x2548 */;
2387: data_o = 32'h78257830 /* 0x254c */;
2388: data_o = 32'h00000a0d /* 0x2550 */;
2389: data_o = 32'h00000000 /* 0x2554 */;
2390: data_o = 32'h61656809 /* 0x2558 */;
2391: data_o = 32'h20726564 /* 0x255c */;
2392: data_o = 32'h657a6973 /* 0x2560 */;
2393: data_o = 32'h2009093a /* 0x2564 */;
2394: data_o = 32'h78257830 /* 0x2568 */;
2395: data_o = 32'h00000a0d /* 0x256c */;
2396: data_o = 32'h73657209 /* 0x2570 */;
2397: data_o = 32'h65767265 /* 0x2574 */;
2398: data_o = 32'h20093a64 /* 0x2578 */;
2399: data_o = 32'h78257830 /* 0x257c */;
2400: data_o = 32'h00000a0d /* 0x2580 */;
2401: data_o = 32'h00000000 /* 0x2584 */;
2402: data_o = 32'h20796d09 /* 0x2588 */;
2403: data_o = 32'h3a61626c /* 0x258c */;
2404: data_o = 32'h78302009 /* 0x2590 */;
2405: data_o = 32'h0d786c25 /* 0x2594 */;
2406: data_o = 32'h0000000a /* 0x2598 */;
2407: data_o = 32'h00000000 /* 0x259c */;
2408: data_o = 32'h746c6109 /* 0x25a0 */;
2409: data_o = 32'h616e7265 /* 0x25a4 */;
2410: data_o = 32'h6c206574 /* 0x25a8 */;
2411: data_o = 32'h093a6162 /* 0x25ac */;
2412: data_o = 32'h25783020 /* 0x25b0 */;
2413: data_o = 32'h0a0d786c /* 0x25b4 */;
2414: data_o = 32'h00000000 /* 0x25b8 */;
2415: data_o = 32'h00000000 /* 0x25bc */;
2416: data_o = 32'h72617009 /* 0x25c0 */;
2417: data_o = 32'h69746974 /* 0x25c4 */;
2418: data_o = 32'h65206e6f /* 0x25c8 */;
2419: data_o = 32'h7972746e /* 0x25cc */;
2420: data_o = 32'h61626c20 /* 0x25d0 */;
2421: data_o = 32'h3020093a /* 0x25d4 */;
2422: data_o = 32'h786c2578 /* 0x25d8 */;
2423: data_o = 32'h00000a0d /* 0x25dc */;
2424: data_o = 32'h6d756e09 /* 0x25e0 */;
2425: data_o = 32'h20726562 /* 0x25e4 */;
2426: data_o = 32'h74726170 /* 0x25e8 */;
2427: data_o = 32'h6f697469 /* 0x25ec */;
2428: data_o = 32'h6e65206e /* 0x25f0 */;
2429: data_o = 32'h65697274 /* 0x25f4 */;
2430: data_o = 32'h20093a73 /* 0x25f8 */;
2431: data_o = 32'h0a0d6425 /* 0x25fc */;
2432: data_o = 32'h00000000 /* 0x2600 */;
2433: data_o = 32'h00000000 /* 0x2604 */;
2434: data_o = 32'h7a697309 /* 0x2608 */;
2435: data_o = 32'h61702065 /* 0x260c */;
2436: data_o = 32'h74697472 /* 0x2610 */;
2437: data_o = 32'h206e6f69 /* 0x2614 */;
2438: data_o = 32'h72746e65 /* 0x2618 */;
2439: data_o = 32'h3a736569 /* 0x261c */;
2440: data_o = 32'h20092020 /* 0x2620 */;
2441: data_o = 32'h0a0d6425 /* 0x2624 */;
2442: data_o = 32'h00000000 /* 0x2628 */;
2443: data_o = 32'h00000000 /* 0x262c */;
2444: data_o = 32'h63204453 /* 0x2630 */;
2445: data_o = 32'h20647261 /* 0x2634 */;
2446: data_o = 32'h79706f63 /* 0x2638 */;
2447: data_o = 32'h20666f20 /* 0x263c */;
2448: data_o = 32'h74726170 /* 0x2640 */;
2449: data_o = 32'h6f697469 /* 0x2644 */;
2450: data_o = 32'h6e65206e /* 0x2648 */;
2451: data_o = 32'h65697274 /* 0x264c */;
2452: data_o = 32'h61662073 /* 0x2650 */;
2453: data_o = 32'h64656c69 /* 0x2654 */;
2454: data_o = 32'h000a0d21 /* 0x2658 */;
2455: data_o = 32'h00000000 /* 0x265c */;
2456: data_o = 32'h20545047 /* 0x2660 */;
2457: data_o = 32'h74726170 /* 0x2664 */;
2458: data_o = 32'h6f697469 /* 0x2668 */;
2459: data_o = 32'h6e65206e /* 0x266c */;
2460: data_o = 32'h20797274 /* 0x2670 */;
2461: data_o = 32'h0a0d6425 /* 0x2674 */;
2462: data_o = 32'h00000000 /* 0x2678 */;
2463: data_o = 32'h00000000 /* 0x267c */;
2464: data_o = 32'h72696609 /* 0x2680 */;
2465: data_o = 32'h6c207473 /* 0x2684 */;
2466: data_o = 32'h093a6162 /* 0x2688 */;
2467: data_o = 32'h25783020 /* 0x268c */;
2468: data_o = 32'h0a0d786c /* 0x2690 */;
2469: data_o = 32'h00000000 /* 0x2694 */;
2470: data_o = 32'h73616c09 /* 0x2698 */;
2471: data_o = 32'h626c2074 /* 0x269c */;
2472: data_o = 32'h20093a61 /* 0x26a0 */;
2473: data_o = 32'h6c257830 /* 0x26a4 */;
2474: data_o = 32'h000a0d78 /* 0x26a8 */;
2475: data_o = 32'h00000000 /* 0x26ac */;
2476: data_o = 32'h74746109 /* 0x26b0 */;
2477: data_o = 32'h75626972 /* 0x26b4 */;
2478: data_o = 32'h3a736574 /* 0x26b8 */;
2479: data_o = 32'h78302009 /* 0x26bc */;
2480: data_o = 32'h0d786c25 /* 0x26c0 */;
2481: data_o = 32'h0000000a /* 0x26c4 */;
2482: data_o = 32'h6d616e09 /* 0x26c8 */;
2483: data_o = 32'h00093a65 /* 0x26cc */;
2484: data_o = 32'h00006325 /* 0x26d0 */;
2485: data_o = 32'h00000000 /* 0x26d4 */;
2486: data_o = 32'h5d64735b /* 0x26d8 */;
2487: data_o = 32'h73657220 /* 0x26dc */;
2488: data_o = 32'h656c5f70 /* 0x26e0 */;
2489: data_o = 32'h7830206e /* 0x26e4 */;
2490: data_o = 32'h74207825 /* 0x26e8 */;
2491: data_o = 32'h6c206f6f /* 0x26ec */;
2492: data_o = 32'h65677261 /* 0x26f0 */;
2493: data_o = 32'h726f6620 /* 0x26f4 */;
2494: data_o = 32'h5f647320 /* 0x26f8 */;
2495: data_o = 32'h20646d63 /* 0x26fc */;
2496: data_o = 32'h78616d28 /* 0x2700 */;
2497: data_o = 32'h20736920 /* 0x2704 */;
2498: data_o = 32'h0a0d2938 /* 0x2708 */;
2499: data_o = 32'h00000000 /* 0x270c */;
2500: data_o = 32'h5d64735b /* 0x2710 */;
2501: data_o = 32'h444d4320 /* 0x2714 */;
2502: data_o = 32'h65722030 /* 0x2718 */;
2503: data_o = 32'h6e6f7073 /* 0x271c */;
2504: data_o = 32'h203a6573 /* 0x2720 */;
2505: data_o = 32'h78257830 /* 0x2724 */;
2506: data_o = 32'h00000a0d /* 0x2728 */;
2507: data_o = 32'h00000000 /* 0x272c */;
2508: data_o = 32'h5d64735b /* 0x2730 */;
2509: data_o = 32'h444d4320 /* 0x2734 */;
2510: data_o = 32'h65722038 /* 0x2738 */;
2511: data_o = 32'h6e6f7073 /* 0x273c */;
2512: data_o = 32'h203a6573 /* 0x2740 */;
2513: data_o = 32'h6c257830 /* 0x2744 */;
2514: data_o = 32'h000a0d78 /* 0x2748 */;
2515: data_o = 32'h00000000 /* 0x274c */;
2516: data_o = 32'h5d64735b /* 0x2750 */;
2517: data_o = 32'h444d4320 /* 0x2754 */;
2518: data_o = 32'h72203535 /* 0x2758 */;
2519: data_o = 32'h6f707365 /* 0x275c */;
2520: data_o = 32'h3a65736e /* 0x2760 */;
2521: data_o = 32'h25783020 /* 0x2764 */;
2522: data_o = 32'h0a0d786c /* 0x2768 */;
2523: data_o = 32'h00000000 /* 0x276c */;
2524: data_o = 32'h5d64735b /* 0x2770 */;
2525: data_o = 32'h4d434120 /* 0x2774 */;
2526: data_o = 32'h20313444 /* 0x2778 */;
2527: data_o = 32'h70736572 /* 0x277c */;
2528: data_o = 32'h65736e6f /* 0x2780 */;
2529: data_o = 32'h7830203a /* 0x2784 */;
2530: data_o = 32'h0d786c25 /* 0x2788 */;
2531: data_o = 32'h0000000a /* 0x278c */;
2532: data_o = 32'h5d64735b /* 0x2790 */;
2533: data_o = 32'h444d4320 /* 0x2794 */;
2534: data_o = 32'h72203835 /* 0x2798 */;
2535: data_o = 32'h6f707365 /* 0x279c */;
2536: data_o = 32'h3a65736e /* 0x27a0 */;
2537: data_o = 32'h25783020 /* 0x27a4 */;
2538: data_o = 32'h000a0d78 /* 0x27a8 */;
2539: data_o = 32'h00000000 /* 0x27ac */;
2540: data_o = 32'h5d64735b /* 0x27b0 */;
2541: data_o = 32'h444d4320 /* 0x27b4 */;
2542: data_o = 32'h72203631 /* 0x27b8 */;
2543: data_o = 32'h6f707365 /* 0x27bc */;
2544: data_o = 32'h3a65736e /* 0x27c0 */;
2545: data_o = 32'h25783020 /* 0x27c4 */;
2546: data_o = 32'h000a0d78 /* 0x27c8 */;
2547: data_o = 32'h00000000 /* 0x27cc */;
2548: data_o = 32'h5d64735b /* 0x27d0 */;
2549: data_o = 32'h6e695320 /* 0x27d4 */;
2550: data_o = 32'h20656c67 /* 0x27d8 */;
2551: data_o = 32'h636f6c62 /* 0x27dc */;
2552: data_o = 32'h7274206b /* 0x27e0 */;
2553: data_o = 32'h66736e61 /* 0x27e4 */;
2554: data_o = 32'h66207265 /* 0x27e8 */;
2555: data_o = 32'h206d6f72 /* 0x27ec */;
2556: data_o = 32'h2041424c /* 0x27f0 */;
2557: data_o = 32'h6c257830 /* 0x27f4 */;
2558: data_o = 32'h6f742078 /* 0x27f8 */;
2559: data_o = 32'h25783020 /* 0x27fc */;
2560: data_o = 32'h0a0d786c /* 0x2800 */;
2561: data_o = 32'h00000000 /* 0x2804 */;
2562: data_o = 32'h5d64735b /* 0x2808 */;
2563: data_o = 32'h6c754d20 /* 0x280c */;
2564: data_o = 32'h62206974 /* 0x2810 */;
2565: data_o = 32'h6b636f6c /* 0x2814 */;
2566: data_o = 32'h61727420 /* 0x2818 */;
2567: data_o = 32'h6566736e /* 0x281c */;
2568: data_o = 32'h666f2072 /* 0x2820 */;
2569: data_o = 32'h20642520 /* 0x2824 */;
2570: data_o = 32'h636f6c62 /* 0x2828 */;
2571: data_o = 32'h6620736b /* 0x282c */;
2572: data_o = 32'h206d6f72 /* 0x2830 */;
2573: data_o = 32'h2041424c /* 0x2834 */;
2574: data_o = 32'h6c257830 /* 0x2838 */;
2575: data_o = 32'h6f742078 /* 0x283c */;
2576: data_o = 32'h25783020 /* 0x2840 */;
2577: data_o = 32'h0a0d786c /* 0x2844 */;
2578: data_o = 32'h00000000 /* 0x2848 */;
2579: data_o = 32'h00000000 /* 0x284c */;
2580: data_o = 32'h5d64735b /* 0x2850 */;
2581: data_o = 32'h746f4720 /* 0x2854 */;
2582: data_o = 32'h6f6c6220 /* 0x2858 */;
2583: data_o = 32'h72206b63 /* 0x285c */;
2584: data_o = 32'h20646165 /* 0x2860 */;
2585: data_o = 32'h6d6d6f63 /* 0x2864 */;
2586: data_o = 32'h20646e61 /* 0x2868 */;
2587: data_o = 32'h70736572 /* 0x286c */;
2588: data_o = 32'h65736e6f /* 0x2870 */;
2589: data_o = 32'h7830203a /* 0x2874 */;
2590: data_o = 32'h0a0d7825 /* 0x2878 */;
2591: data_o = 32'h00000000 /* 0x287c */;
2592: data_o = 32'h5d64735b /* 0x2880 */;
2593: data_o = 32'h72724520 /* 0x2884 */;
2594: data_o = 32'h7420726f /* 0x2888 */;
2595: data_o = 32'h6e656b6f /* 0x288c */;
2596: data_o = 32'h63657220 /* 0x2890 */;
2597: data_o = 32'h65766965 /* 0x2894 */;
2598: data_o = 32'h30203a64 /* 0x2898 */;
2599: data_o = 32'h0d782578 /* 0x289c */;
2600: data_o = 32'h0000000a /* 0x28a0 */;
2601: data_o = 32'h00000000 /* 0x28a4 */;
2602: data_o = 32'h5d64735b /* 0x28a8 */;
2603: data_o = 32'h444d4320 /* 0x28ac */;
2604: data_o = 32'h72203231 /* 0x28b0 */;
2605: data_o = 32'h6f707365 /* 0x28b4 */;
2606: data_o = 32'h3a65736e /* 0x28b8 */;
2607: data_o = 32'h25783020 /* 0x28bc */;
2608: data_o = 32'h000a0d78 /* 0x28c0 */;
2609: data_o = 32'h00000000 /* 0x28c4 */;
2610: data_o = 32'hffffffff /* 0x28c8 */;
2611: data_o = 32'h7fefffff /* 0x28cc */;
2612: data_o = 32'hffffffff /* 0x28d0 */;
2613: data_o = 32'hffefffff /* 0x28d4 */;
2614: data_o = 32'h509f79fb /* 0x28d8 */;
2615: data_o = 32'h3fd34413 /* 0x28dc */;
2616: data_o = 32'h8b60c8b3 /* 0x28e0 */;
2617: data_o = 32'h3fc68a28 /* 0x28e4 */;
2618: data_o = 32'h00000000 /* 0x28e8 */;
2619: data_o = 32'h3ff80000 /* 0x28ec */;
2620: data_o = 32'h636f4361 /* 0x28f0 */;
2621: data_o = 32'h3fd287a7 /* 0x28f4 */;
2622: data_o = 32'h0979a371 /* 0x28f8 */;
2623: data_o = 32'h400a934f /* 0x28fc */;
2624: data_o = 32'h00000000 /* 0x2900 */;
2625: data_o = 32'h3fe00000 /* 0x2904 */;
2626: data_o = 32'hfefa39ef /* 0x2908 */;
2627: data_o = 32'h3fe62e42 /* 0x290c */;
2628: data_o = 32'hbbb55516 /* 0x2910 */;
2629: data_o = 32'h40026bb1 /* 0x2914 */;
2630: data_o = 32'h00000000 /* 0x2918 */;
2631: data_o = 32'h402c0000 /* 0x291c */;
2632: data_o = 32'h00000000 /* 0x2920 */;
2633: data_o = 32'h40240000 /* 0x2924 */;
2634: data_o = 32'h00000000 /* 0x2928 */;
2635: data_o = 32'h40180000 /* 0x292c */;
2636: data_o = 32'h00000000 /* 0x2930 */;
2637: data_o = 32'h40000000 /* 0x2934 */;
2638: data_o = 32'h00000000 /* 0x2938 */;
2639: data_o = 32'h3ff00000 /* 0x293c */;
2640: data_o = 32'heb1c432d /* 0x2940 */;
2641: data_o = 32'h3f1a36e2 /* 0x2944 */;
2642: data_o = 32'h00000000 /* 0x2948 */;
2643: data_o = 32'h412e8480 /* 0x294c */;
2644: data_o = 32'h00000000 /* 0x2950 */;
2645: data_o = 32'h41cdcd65 /* 0x2954 */;
2646: data_o = 32'h00000000 /* 0x2958 */;
2647: data_o = 32'hc1cdcd65 /* 0x295c */;
2648: data_o = 32'h0001aa87 /* 0x2960 */;
2649: data_o = 32'h00004800 /* 0x2964 */;
2650: data_o = 32'h000200ff /* 0x2968 */;
2651: data_o = 32'h00005000 /* 0x296c */;
2652: data_o = 32'h05020101 /* 0x2970 */;
2653: data_o = 32'h05000000 /* 0x2974 */;
2654: data_o = 32'h00000000 /* 0x2978 */;
2655: data_o = 32'h00000000 /* 0x297c */;
2656: data_o = 32'h00000000 /* 0x2980 */;
2657: data_o = 32'h00000000 /* 0x2984 */;
2658: data_o = 32'h00000000 /* 0x2988 */;
2659: data_o = 32'h00000000 /* 0x298c */;
2660: data_o = 32'h00000000 /* 0x2990 */;
2661: data_o = 32'h00000000 /* 0x2994 */;
2662: data_o = 32'h00000000 /* 0x2998 */;
2663: data_o = 32'h00000000 /* 0x299c */;
2664: data_o = 32'h00000000 /* 0x29a0 */;
2665: data_o = 32'h00000000 /* 0x29a4 */;
2666: data_o = 32'h00000000 /* 0x29a8 */;
2667: data_o = 32'h00000000 /* 0x29ac */;
2668: data_o = 32'h00000000 /* 0x29b0 */;
2669: data_o = 32'h00000000 /* 0x29b4 */;
2670: data_o = 32'h00000000 /* 0x29b8 */;
2671: data_o = 32'h00000000 /* 0x29bc */;
2672: data_o = 32'h00000000 /* 0x29c0 */;
2673: data_o = 32'h00000000 /* 0x29c4 */;
2674: data_o = 32'h00000000 /* 0x29c8 */;
2675: data_o = 32'h00000000 /* 0x29cc */;
2676: data_o = 32'h00000000 /* 0x29d0 */;
2677: data_o = 32'h00000000 /* 0x29d4 */;
2678: data_o = 32'h00000000 /* 0x29d8 */;
2679: data_o = 32'h00000000 /* 0x29dc */;
2680: data_o = 32'h00000000 /* 0x29e0 */;
2681: data_o = 32'h00000000 /* 0x29e4 */;
2682: data_o = 32'h00000000 /* 0x29e8 */;
2683: data_o = 32'h00000000 /* 0x29ec */;
2684: data_o = 32'h00000000 /* 0x29f0 */;
2685: data_o = 32'h00000000 /* 0x29f4 */;
2686: data_o = 32'h00000000 /* 0x29f8 */;
2687: data_o = 32'h00000000 /* 0x29fc */;
2688: data_o = 32'h00000000 /* 0x2a00 */;
2689: data_o = 32'h00000000 /* 0x2a04 */;
2690: data_o = 32'h00000000 /* 0x2a08 */;
2691: data_o = 32'h00000000 /* 0x2a0c */;
2692: data_o = 32'h00000000 /* 0x2a10 */;
2693: data_o = 32'h00000000 /* 0x2a14 */;
2694: data_o = 32'h00000000 /* 0x2a18 */;
2695: data_o = 32'h00000000 /* 0x2a1c */;
2696: data_o = 32'h00000000 /* 0x2a20 */;
2697: data_o = 32'h00000000 /* 0x2a24 */;
2698: data_o = 32'h00000000 /* 0x2a28 */;
2699: data_o = 32'h00000000 /* 0x2a2c */;
2700: data_o = 32'h00000000 /* 0x2a30 */;
2701: data_o = 32'h00000000 /* 0x2a34 */;
2702: data_o = 32'h00000000 /* 0x2a38 */;
2703: data_o = 32'h00000000 /* 0x2a3c */;
2704: data_o = 32'h00000000 /* 0x2a40 */;
2705: data_o = 32'h00000000 /* 0x2a44 */;
2706: data_o = 32'h00000000 /* 0x2a48 */;
2707: data_o = 32'h00000000 /* 0x2a4c */;
2708: data_o = 32'h00000000 /* 0x2a50 */;
2709: data_o = 32'h00000000 /* 0x2a54 */;
2710: data_o = 32'h00000000 /* 0x2a58 */;
2711: data_o = 32'h00000000 /* 0x2a5c */;
2712: data_o = 32'h00000000 /* 0x2a60 */;
2713: data_o = 32'h00000000 /* 0x2a64 */;
2714: data_o = 32'h00000000 /* 0x2a68 */;
2715: data_o = 32'h00000000 /* 0x2a6c */;
2716: data_o = 32'h00000000 /* 0x2a70 */;
2717: data_o = 32'h00000000 /* 0x2a74 */;
2718: data_o = 32'h00000000 /* 0x2a78 */;
2719: data_o = 32'h00000000 /* 0x2a7c */;
2720: data_o = 32'h00000000 /* 0x2a80 */;
2721: data_o = 32'h00000000 /* 0x2a84 */;
2722: data_o = 32'h00000000 /* 0x2a88 */;
2723: data_o = 32'h00000000 /* 0x2a8c */;
2724: data_o = 32'h00000000 /* 0x2a90 */;
2725: data_o = 32'h00000000 /* 0x2a94 */;
2726: data_o = 32'h00000000 /* 0x2a98 */;
2727: data_o = 32'h00000000 /* 0x2a9c */;
2728: data_o = 32'h00000000 /* 0x2aa0 */;
2729: data_o = 32'h00000000 /* 0x2aa4 */;
2730: data_o = 32'h00000000 /* 0x2aa8 */;
2731: data_o = 32'h00000000 /* 0x2aac */;
2732: data_o = 32'h00000000 /* 0x2ab0 */;
2733: data_o = 32'h00000000 /* 0x2ab4 */;
2734: data_o = 32'h00000000 /* 0x2ab8 */;
2735: data_o = 32'h00000000 /* 0x2abc */;
2736: data_o = 32'h00000000 /* 0x2ac0 */;
2737: data_o = 32'h00000000 /* 0x2ac4 */;
2738: data_o = 32'h00000000 /* 0x2ac8 */;
2739: data_o = 32'h00000000 /* 0x2acc */;
2740: data_o = 32'h00000000 /* 0x2ad0 */;
2741: data_o = 32'h00000000 /* 0x2ad4 */;
2742: data_o = 32'h00000000 /* 0x2ad8 */;
2743: data_o = 32'h00000000 /* 0x2adc */;
2744: data_o = 32'h00000000 /* 0x2ae0 */;
2745: data_o = 32'h00000000 /* 0x2ae4 */;
2746: data_o = 32'h00000000 /* 0x2ae8 */;
2747: data_o = 32'h00000000 /* 0x2aec */;
2748: data_o = 32'h00000000 /* 0x2af0 */;
2749: data_o = 32'h00000000 /* 0x2af4 */;
2750: data_o = 32'h00000000 /* 0x2af8 */;
2751: data_o = 32'h00000000 /* 0x2afc */;
2752: data_o = 32'h00000000 /* 0x2b00 */;
2753: data_o = 32'h00000000 /* 0x2b04 */;
2754: data_o = 32'h00000000 /* 0x2b08 */;
2755: data_o = 32'h00000000 /* 0x2b0c */;
2756: data_o = 32'h00000000 /* 0x2b10 */;
2757: data_o = 32'h00000000 /* 0x2b14 */;
2758: data_o = 32'h00000000 /* 0x2b18 */;
2759: data_o = 32'h00000000 /* 0x2b1c */;
2760: data_o = 32'h00000000 /* 0x2b20 */;
2761: data_o = 32'h00000000 /* 0x2b24 */;
2762: data_o = 32'h00000000 /* 0x2b28 */;
2763: data_o = 32'h00000000 /* 0x2b2c */;
2764: data_o = 32'h00000000 /* 0x2b30 */;
2765: data_o = 32'h00000000 /* 0x2b34 */;
2766: data_o = 32'h00000000 /* 0x2b38 */;
2767: data_o = 32'h00000000 /* 0x2b3c */;
2768: data_o = 32'h00000000 /* 0x2b40 */;
2769: data_o = 32'h00000000 /* 0x2b44 */;
2770: data_o = 32'h00000000 /* 0x2b48 */;
2771: data_o = 32'h00000000 /* 0x2b4c */;
2772: data_o = 32'h00000000 /* 0x2b50 */;
2773: data_o = 32'h00000000 /* 0x2b54 */;
2774: data_o = 32'h00000000 /* 0x2b58 */;
2775: data_o = 32'h00000000 /* 0x2b5c */;
2776: data_o = 32'h00000000 /* 0x2b60 */;
2777: data_o = 32'h00000000 /* 0x2b64 */;
2778: data_o = 32'h00000000 /* 0x2b68 */;
2779: data_o = 32'h00000000 /* 0x2b6c */;
2780: data_o = 32'h00000000 /* 0x2b70 */;
2781: data_o = 32'h00000000 /* 0x2b74 */;
2782: data_o = 32'h00000000 /* 0x2b78 */;
2783: data_o = 32'h00000000 /* 0x2b7c */;
2784: data_o = 32'h00000000 /* 0x2b80 */;
2785: data_o = 32'h00000000 /* 0x2b84 */;
2786: data_o = 32'h00000000 /* 0x2b88 */;
2787: data_o = 32'h00000000 /* 0x2b8c */;
2788: data_o = 32'h00000000 /* 0x2b90 */;
2789: data_o = 32'h00000000 /* 0x2b94 */;
2790: data_o = 32'h00000000 /* 0x2b98 */;
2791: data_o = 32'h00000000 /* 0x2b9c */;
2792: data_o = 32'h00000000 /* 0x2ba0 */;
2793: data_o = 32'h00000000 /* 0x2ba4 */;
2794: data_o = 32'h00000000 /* 0x2ba8 */;
2795: data_o = 32'h00000000 /* 0x2bac */;
2796: data_o = 32'h00000000 /* 0x2bb0 */;
2797: data_o = 32'h00000000 /* 0x2bb4 */;
2798: data_o = 32'h00000000 /* 0x2bb8 */;
2799: data_o = 32'h00000000 /* 0x2bbc */;
2800: data_o = 32'h00000000 /* 0x2bc0 */;
2801: data_o = 32'h00000000 /* 0x2bc4 */;
2802: data_o = 32'h00000000 /* 0x2bc8 */;
2803: data_o = 32'h00000000 /* 0x2bcc */;
2804: data_o = 32'h00000000 /* 0x2bd0 */;
2805: data_o = 32'h00000000 /* 0x2bd4 */;
2806: data_o = 32'h00000000 /* 0x2bd8 */;
2807: data_o = 32'h00000000 /* 0x2bdc */;
2808: data_o = 32'h00000000 /* 0x2be0 */;
2809: data_o = 32'h00000000 /* 0x2be4 */;
2810: data_o = 32'h00000000 /* 0x2be8 */;
2811: data_o = 32'h00000000 /* 0x2bec */;
2812: data_o = 32'h00000000 /* 0x2bf0 */;
2813: data_o = 32'h00000000 /* 0x2bf4 */;
2814: data_o = 32'h00000000 /* 0x2bf8 */;
2815: data_o = 32'h00000000 /* 0x2bfc */;
2816: data_o = 32'h00000000 /* 0x2c00 */;
2817: data_o = 32'h00000000 /* 0x2c04 */;
2818: data_o = 32'h00000000 /* 0x2c08 */;
2819: data_o = 32'h00000000 /* 0x2c0c */;
2820: data_o = 32'h00000000 /* 0x2c10 */;
2821: data_o = 32'h00000000 /* 0x2c14 */;
2822: data_o = 32'h00000000 /* 0x2c18 */;
2823: data_o = 32'h00000000 /* 0x2c1c */;
2824: data_o = 32'h00000000 /* 0x2c20 */;
2825: data_o = 32'h00000000 /* 0x2c24 */;
2826: data_o = 32'h00000000 /* 0x2c28 */;
2827: data_o = 32'h00000000 /* 0x2c2c */;
2828: data_o = 32'h00000000 /* 0x2c30 */;
2829: data_o = 32'h00000000 /* 0x2c34 */;
2830: data_o = 32'h00000000 /* 0x2c38 */;
2831: data_o = 32'h00000000 /* 0x2c3c */;
2832: data_o = 32'h00000000 /* 0x2c40 */;
2833: data_o = 32'h00000000 /* 0x2c44 */;
2834: data_o = 32'h00000000 /* 0x2c48 */;
2835: data_o = 32'h00000000 /* 0x2c4c */;
2836: data_o = 32'h00000000 /* 0x2c50 */;
2837: data_o = 32'h00000000 /* 0x2c54 */;
2838: data_o = 32'h00000000 /* 0x2c58 */;
2839: data_o = 32'h00000000 /* 0x2c5c */;
2840: data_o = 32'h00000000 /* 0x2c60 */;
2841: data_o = 32'h00000000 /* 0x2c64 */;
2842: data_o = 32'h00000000 /* 0x2c68 */;
2843: data_o = 32'h00000000 /* 0x2c6c */;
2844: data_o = 32'h00000000 /* 0x2c70 */;
2845: data_o = 32'h00000000 /* 0x2c74 */;
2846: data_o = 32'h00000000 /* 0x2c78 */;
2847: data_o = 32'h00000000 /* 0x2c7c */;
2848: data_o = 32'h00000000 /* 0x2c80 */;
2849: data_o = 32'h00000000 /* 0x2c84 */;
2850: data_o = 32'h00000000 /* 0x2c88 */;
2851: data_o = 32'h00000000 /* 0x2c8c */;
2852: data_o = 32'h00000000 /* 0x2c90 */;
2853: data_o = 32'h00000000 /* 0x2c94 */;
2854: data_o = 32'h00000000 /* 0x2c98 */;
2855: data_o = 32'h00000000 /* 0x2c9c */;
2856: data_o = 32'h00000000 /* 0x2ca0 */;
2857: data_o = 32'h00000000 /* 0x2ca4 */;
2858: data_o = 32'h00000000 /* 0x2ca8 */;
2859: data_o = 32'h00000000 /* 0x2cac */;
2860: data_o = 32'h00000000 /* 0x2cb0 */;
2861: data_o = 32'h00000000 /* 0x2cb4 */;
2862: data_o = 32'h00000000 /* 0x2cb8 */;
2863: data_o = 32'h00000000 /* 0x2cbc */;
2864: data_o = 32'h00000000 /* 0x2cc0 */;
2865: data_o = 32'h00000000 /* 0x2cc4 */;
2866: data_o = 32'h00000000 /* 0x2cc8 */;
2867: data_o = 32'h00000000 /* 0x2ccc */;
2868: data_o = 32'h00000000 /* 0x2cd0 */;
2869: data_o = 32'h00000000 /* 0x2cd4 */;
2870: data_o = 32'h00000000 /* 0x2cd8 */;
2871: data_o = 32'h00000000 /* 0x2cdc */;
2872: data_o = 32'h00000000 /* 0x2ce0 */;
2873: data_o = 32'h00000000 /* 0x2ce4 */;
2874: data_o = 32'h00000000 /* 0x2ce8 */;
2875: data_o = 32'h00000000 /* 0x2cec */;
2876: data_o = 32'h00000000 /* 0x2cf0 */;
2877: data_o = 32'h00000000 /* 0x2cf4 */;
2878: data_o = 32'h00000000 /* 0x2cf8 */;
2879: data_o = 32'h00000000 /* 0x2cfc */;
2880: data_o = 32'h00000000 /* 0x2d00 */;
2881: data_o = 32'h00000000 /* 0x2d04 */;
2882: data_o = 32'h00000000 /* 0x2d08 */;
2883: data_o = 32'h00000000 /* 0x2d0c */;
2884: data_o = 32'h00000000 /* 0x2d10 */;
2885: data_o = 32'h00000000 /* 0x2d14 */;
2886: data_o = 32'h00000000 /* 0x2d18 */;
2887: data_o = 32'h00000000 /* 0x2d1c */;
2888: data_o = 32'h00000000 /* 0x2d20 */;
2889: data_o = 32'h00000000 /* 0x2d24 */;
2890: data_o = 32'h00000000 /* 0x2d28 */;
2891: data_o = 32'h00000000 /* 0x2d2c */;
2892: data_o = 32'h00000000 /* 0x2d30 */;
2893: data_o = 32'h00000000 /* 0x2d34 */;
2894: data_o = 32'h00000000 /* 0x2d38 */;
2895: data_o = 32'h00000000 /* 0x2d3c */;
2896: data_o = 32'h00000000 /* 0x2d40 */;
2897: data_o = 32'h00000000 /* 0x2d44 */;
2898: data_o = 32'h00000000 /* 0x2d48 */;
2899: data_o = 32'h00000000 /* 0x2d4c */;
2900: data_o = 32'h00000000 /* 0x2d50 */;
2901: data_o = 32'h00000000 /* 0x2d54 */;
2902: data_o = 32'h00000000 /* 0x2d58 */;
2903: data_o = 32'h00000000 /* 0x2d5c */;
2904: data_o = 32'h00000000 /* 0x2d60 */;
2905: data_o = 32'h00000000 /* 0x2d64 */;
2906: data_o = 32'h00000000 /* 0x2d68 */;
2907: data_o = 32'h00000000 /* 0x2d6c */;
2908: data_o = 32'h00000000 /* 0x2d70 */;
2909: data_o = 32'h00000000 /* 0x2d74 */;
2910: data_o = 32'h00000000 /* 0x2d78 */;
2911: data_o = 32'h00000000 /* 0x2d7c */;
2912: data_o = 32'h00000000 /* 0x2d80 */;
2913: data_o = 32'h00000000 /* 0x2d84 */;
2914: data_o = 32'h00000000 /* 0x2d88 */;
2915: data_o = 32'h00000000 /* 0x2d8c */;
2916: data_o = 32'h00000000 /* 0x2d90 */;
2917: data_o = 32'h00000000 /* 0x2d94 */;
2918: data_o = 32'h00000000 /* 0x2d98 */;
2919: data_o = 32'h00000000 /* 0x2d9c */;
2920: data_o = 32'h00000000 /* 0x2da0 */;
2921: data_o = 32'h00000000 /* 0x2da4 */;
2922: data_o = 32'h00000000 /* 0x2da8 */;
2923: data_o = 32'h00000000 /* 0x2dac */;
2924: data_o = 32'h00000000 /* 0x2db0 */;
2925: data_o = 32'h00000000 /* 0x2db4 */;
2926: data_o = 32'h00000000 /* 0x2db8 */;
2927: data_o = 32'h00000000 /* 0x2dbc */;
2928: data_o = 32'h00000000 /* 0x2dc0 */;
2929: data_o = 32'h00000000 /* 0x2dc4 */;
2930: data_o = 32'h00000000 /* 0x2dc8 */;
2931: data_o = 32'h00000000 /* 0x2dcc */;
2932: data_o = 32'h00000000 /* 0x2dd0 */;
2933: data_o = 32'h00000000 /* 0x2dd4 */;
2934: data_o = 32'h00000000 /* 0x2dd8 */;
2935: data_o = 32'h00000000 /* 0x2ddc */;
2936: data_o = 32'h00000000 /* 0x2de0 */;
2937: data_o = 32'h00000000 /* 0x2de4 */;
2938: data_o = 32'h00000000 /* 0x2de8 */;
2939: data_o = 32'h00000000 /* 0x2dec */;
2940: data_o = 32'h00000000 /* 0x2df0 */;
2941: data_o = 32'h00000000 /* 0x2df4 */;
2942: data_o = 32'h00000000 /* 0x2df8 */;
2943: data_o = 32'h00000000 /* 0x2dfc */;
2944: data_o = 32'h00000000 /* 0x2e00 */;
2945: data_o = 32'h00000000 /* 0x2e04 */;
2946: data_o = 32'h00000000 /* 0x2e08 */;
2947: data_o = 32'h00000000 /* 0x2e0c */;
2948: data_o = 32'h00000000 /* 0x2e10 */;
2949: data_o = 32'h00000000 /* 0x2e14 */;
2950: data_o = 32'h00000000 /* 0x2e18 */;
2951: data_o = 32'h00000000 /* 0x2e1c */;
2952: data_o = 32'h00000000 /* 0x2e20 */;
2953: data_o = 32'h00000000 /* 0x2e24 */;
2954: data_o = 32'h00000000 /* 0x2e28 */;
2955: data_o = 32'h00000000 /* 0x2e2c */;
2956: data_o = 32'h00000000 /* 0x2e30 */;
2957: data_o = 32'h00000000 /* 0x2e34 */;
2958: data_o = 32'h00000000 /* 0x2e38 */;
2959: data_o = 32'h00000000 /* 0x2e3c */;
2960: data_o = 32'h00000000 /* 0x2e40 */;
2961: data_o = 32'h00000000 /* 0x2e44 */;
2962: data_o = 32'h00000000 /* 0x2e48 */;
2963: data_o = 32'h00000000 /* 0x2e4c */;
2964: data_o = 32'h00000000 /* 0x2e50 */;
2965: data_o = 32'h00000000 /* 0x2e54 */;
2966: data_o = 32'h00000000 /* 0x2e58 */;
2967: data_o = 32'h00000000 /* 0x2e5c */;
2968: data_o = 32'h00000000 /* 0x2e60 */;
2969: data_o = 32'h00000000 /* 0x2e64 */;
2970: data_o = 32'h00000000 /* 0x2e68 */;
2971: data_o = 32'h00000000 /* 0x2e6c */;
2972: data_o = 32'h00000000 /* 0x2e70 */;
2973: data_o = 32'h00000000 /* 0x2e74 */;
2974: data_o = 32'h00000000 /* 0x2e78 */;
2975: data_o = 32'h00000000 /* 0x2e7c */;
2976: data_o = 32'h00000000 /* 0x2e80 */;
2977: data_o = 32'h00000000 /* 0x2e84 */;
2978: data_o = 32'h00000000 /* 0x2e88 */;
2979: data_o = 32'h00000000 /* 0x2e8c */;
2980: data_o = 32'h00000000 /* 0x2e90 */;
2981: data_o = 32'h00000000 /* 0x2e94 */;
2982: data_o = 32'h00000000 /* 0x2e98 */;
2983: data_o = 32'h00000000 /* 0x2e9c */;
2984: data_o = 32'h00000000 /* 0x2ea0 */;
2985: data_o = 32'h00000000 /* 0x2ea4 */;
2986: data_o = 32'h00000000 /* 0x2ea8 */;
2987: data_o = 32'h00000000 /* 0x2eac */;
2988: data_o = 32'h00000000 /* 0x2eb0 */;
2989: data_o = 32'h00000000 /* 0x2eb4 */;
2990: data_o = 32'h00000000 /* 0x2eb8 */;
2991: data_o = 32'h00000000 /* 0x2ebc */;
2992: data_o = 32'h00000000 /* 0x2ec0 */;
2993: data_o = 32'h00000000 /* 0x2ec4 */;
2994: data_o = 32'h00000000 /* 0x2ec8 */;
2995: data_o = 32'h00000000 /* 0x2ecc */;
2996: data_o = 32'h00000000 /* 0x2ed0 */;
2997: data_o = 32'h00000000 /* 0x2ed4 */;
2998: data_o = 32'h00000000 /* 0x2ed8 */;
2999: data_o = 32'h00000000 /* 0x2edc */;
3000: data_o = 32'h00000000 /* 0x2ee0 */;
3001: data_o = 32'h00000000 /* 0x2ee4 */;
3002: data_o = 32'h00000000 /* 0x2ee8 */;
3003: data_o = 32'h00000000 /* 0x2eec */;
3004: data_o = 32'h00000000 /* 0x2ef0 */;
3005: data_o = 32'h00000000 /* 0x2ef4 */;
3006: data_o = 32'h00000000 /* 0x2ef8 */;
3007: data_o = 32'h00000000 /* 0x2efc */;
3008: data_o = 32'h00000000 /* 0x2f00 */;
3009: data_o = 32'h00000000 /* 0x2f04 */;
3010: data_o = 32'h00000000 /* 0x2f08 */;
3011: data_o = 32'h00000000 /* 0x2f0c */;
3012: data_o = 32'h00000000 /* 0x2f10 */;
3013: data_o = 32'h00000000 /* 0x2f14 */;
3014: data_o = 32'h00000000 /* 0x2f18 */;
3015: data_o = 32'h00000000 /* 0x2f1c */;
3016: data_o = 32'h00000000 /* 0x2f20 */;
3017: data_o = 32'h00000000 /* 0x2f24 */;
3018: data_o = 32'h00000000 /* 0x2f28 */;
3019: data_o = 32'h00000000 /* 0x2f2c */;
3020: data_o = 32'h00000000 /* 0x2f30 */;
3021: data_o = 32'h00000000 /* 0x2f34 */;
3022: data_o = 32'h00000000 /* 0x2f38 */;
3023: data_o = 32'h00000000 /* 0x2f3c */;
3024: data_o = 32'h00000000 /* 0x2f40 */;
3025: data_o = 32'h00000000 /* 0x2f44 */;
3026: data_o = 32'h00000000 /* 0x2f48 */;
3027: data_o = 32'h00000000 /* 0x2f4c */;
3028: data_o = 32'h00000000 /* 0x2f50 */;
3029: data_o = 32'h00000000 /* 0x2f54 */;
3030: data_o = 32'h00000000 /* 0x2f58 */;
3031: data_o = 32'h00000000 /* 0x2f5c */;
3032: data_o = 32'h00000000 /* 0x2f60 */;
3033: data_o = 32'h00000000 /* 0x2f64 */;
3034: data_o = 32'h00000000 /* 0x2f68 */;
3035: data_o = 32'h00000000 /* 0x2f6c */;
3036: data_o = 32'h00000000 /* 0x2f70 */;
3037: data_o = 32'h00000000 /* 0x2f74 */;
3038: data_o = 32'h00000000 /* 0x2f78 */;
3039: data_o = 32'h00000000 /* 0x2f7c */;
3040: data_o = 32'h00000000 /* 0x2f80 */;
3041: data_o = 32'h00000000 /* 0x2f84 */;
3042: data_o = 32'h00000000 /* 0x2f88 */;
3043: data_o = 32'h00000000 /* 0x2f8c */;
3044: data_o = 32'h00000000 /* 0x2f90 */;
3045: data_o = 32'h00000000 /* 0x2f94 */;
3046: data_o = 32'h00000000 /* 0x2f98 */;
3047: data_o = 32'h00000000 /* 0x2f9c */;
3048: data_o = 32'h00000000 /* 0x2fa0 */;
3049: data_o = 32'h00000000 /* 0x2fa4 */;
3050: data_o = 32'h00000000 /* 0x2fa8 */;
3051: data_o = 32'h00000000 /* 0x2fac */;
3052: data_o = 32'h00000000 /* 0x2fb0 */;
3053: data_o = 32'h00000000 /* 0x2fb4 */;
3054: data_o = 32'h00000000 /* 0x2fb8 */;
3055: data_o = 32'h00000000 /* 0x2fbc */;
3056: data_o = 32'h00000000 /* 0x2fc0 */;
3057: data_o = 32'h00000000 /* 0x2fc4 */;
3058: data_o = 32'h00000000 /* 0x2fc8 */;
3059: data_o = 32'h00000000 /* 0x2fcc */;
3060: data_o = 32'h00000000 /* 0x2fd0 */;
3061: data_o = 32'h00000000 /* 0x2fd4 */;
3062: data_o = 32'h00000000 /* 0x2fd8 */;
3063: data_o = 32'h00000000 /* 0x2fdc */;
3064: data_o = 32'h00000000 /* 0x2fe0 */;
3065: data_o = 32'h00000000 /* 0x2fe4 */;
3066: data_o = 32'h00000000 /* 0x2fe8 */;
3067: data_o = 32'h00000000 /* 0x2fec */;
3068: data_o = 32'h00000000 /* 0x2ff0 */;
3069: data_o = 32'h00000000 /* 0x2ff4 */;
3070: data_o = 32'h00000000 /* 0x2ff8 */;
3071: data_o = 32'h00000000 /* 0x2ffc */;
3072: data_o = 32'h00000000 /* 0x3000 */;
3073: data_o = 32'h00000000 /* 0x3004 */;
3074: data_o = 32'h00000000 /* 0x3008 */;
3075: data_o = 32'h00000000 /* 0x300c */;
3076: data_o = 32'h00000000 /* 0x3010 */;
3077: data_o = 32'h00000000 /* 0x3014 */;
3078: data_o = 32'h00000000 /* 0x3018 */;
3079: data_o = 32'h00000000 /* 0x301c */;
3080: data_o = 32'h00000000 /* 0x3020 */;
3081: data_o = 32'h00000000 /* 0x3024 */;
3082: data_o = 32'h00000000 /* 0x3028 */;
3083: data_o = 32'h00000000 /* 0x302c */;
3084: data_o = 32'h00000000 /* 0x3030 */;
3085: data_o = 32'h00000000 /* 0x3034 */;
3086: data_o = 32'h00000000 /* 0x3038 */;
3087: data_o = 32'h00000000 /* 0x303c */;
3088: data_o = 32'h00000000 /* 0x3040 */;
3089: data_o = 32'h00000000 /* 0x3044 */;
3090: data_o = 32'h00000000 /* 0x3048 */;
3091: data_o = 32'h00000000 /* 0x304c */;
3092: data_o = 32'h00000000 /* 0x3050 */;
3093: data_o = 32'h00000000 /* 0x3054 */;
3094: data_o = 32'h00000000 /* 0x3058 */;
3095: data_o = 32'h00000000 /* 0x305c */;
3096: data_o = 32'h00000000 /* 0x3060 */;
3097: data_o = 32'h00000000 /* 0x3064 */;
3098: data_o = 32'h00000000 /* 0x3068 */;
3099: data_o = 32'h00000000 /* 0x306c */;
3100: data_o = 32'h00000000 /* 0x3070 */;
3101: data_o = 32'h00000000 /* 0x3074 */;
3102: data_o = 32'h00000000 /* 0x3078 */;
3103: data_o = 32'h00000000 /* 0x307c */;
3104: data_o = 32'h00000000 /* 0x3080 */;
3105: data_o = 32'h00000000 /* 0x3084 */;
3106: data_o = 32'h00000000 /* 0x3088 */;
3107: data_o = 32'h00000000 /* 0x308c */;
3108: data_o = 32'h00000000 /* 0x3090 */;
3109: data_o = 32'h00000000 /* 0x3094 */;
3110: data_o = 32'h00000000 /* 0x3098 */;
3111: data_o = 32'h00000000 /* 0x309c */;
3112: data_o = 32'h00000000 /* 0x30a0 */;
3113: data_o = 32'h00000000 /* 0x30a4 */;
3114: data_o = 32'h00000000 /* 0x30a8 */;
3115: data_o = 32'h00000000 /* 0x30ac */;
3116: data_o = 32'h00000000 /* 0x30b0 */;
3117: data_o = 32'h00000000 /* 0x30b4 */;
3118: data_o = 32'h00000000 /* 0x30b8 */;
3119: data_o = 32'h00000000 /* 0x30bc */;
3120: data_o = 32'h00000000 /* 0x30c0 */;
3121: data_o = 32'h00000000 /* 0x30c4 */;
3122: data_o = 32'h00000000 /* 0x30c8 */;
3123: data_o = 32'h00000000 /* 0x30cc */;
3124: data_o = 32'h00000000 /* 0x30d0 */;
3125: data_o = 32'h00000000 /* 0x30d4 */;
3126: data_o = 32'h00000000 /* 0x30d8 */;
3127: data_o = 32'h00000000 /* 0x30dc */;
3128: data_o = 32'h00000000 /* 0x30e0 */;
3129: data_o = 32'h00000000 /* 0x30e4 */;
3130: data_o = 32'h00000000 /* 0x30e8 */;
3131: data_o = 32'h00000000 /* 0x30ec */;
3132: data_o = 32'h00000000 /* 0x30f0 */;
3133: data_o = 32'h00000000 /* 0x30f4 */;
3134: data_o = 32'h00000000 /* 0x30f8 */;
3135: data_o = 32'h00000000 /* 0x30fc */;
3136: data_o = 32'h00000000 /* 0x3100 */;
3137: data_o = 32'h00000000 /* 0x3104 */;
3138: data_o = 32'h00000000 /* 0x3108 */;
3139: data_o = 32'h00000000 /* 0x310c */;
3140: data_o = 32'h00000000 /* 0x3110 */;
3141: data_o = 32'h00000000 /* 0x3114 */;
3142: data_o = 32'h00000000 /* 0x3118 */;
3143: data_o = 32'h00000000 /* 0x311c */;
3144: data_o = 32'h00000000 /* 0x3120 */;
3145: data_o = 32'h00000000 /* 0x3124 */;
3146: data_o = 32'h00000000 /* 0x3128 */;
3147: data_o = 32'h00000000 /* 0x312c */;
3148: data_o = 32'h00000000 /* 0x3130 */;
3149: data_o = 32'h00000000 /* 0x3134 */;
3150: data_o = 32'h00000000 /* 0x3138 */;
3151: data_o = 32'h00000000 /* 0x313c */;
3152: data_o = 32'h00000000 /* 0x3140 */;
3153: data_o = 32'h00000000 /* 0x3144 */;
3154: data_o = 32'h00000000 /* 0x3148 */;
3155: data_o = 32'h00000000 /* 0x314c */;
3156: data_o = 32'h00000000 /* 0x3150 */;
3157: data_o = 32'h00000000 /* 0x3154 */;
3158: data_o = 32'h00000000 /* 0x3158 */;
3159: data_o = 32'h00000000 /* 0x315c */;
3160: data_o = 32'h00000000 /* 0x3160 */;
3161: data_o = 32'h00000000 /* 0x3164 */;
3162: data_o = 32'h00000000 /* 0x3168 */;
3163: data_o = 32'h00000000 /* 0x316c */;
3164: data_o = 32'h00000000 /* 0x3170 */;
3165: data_o = 32'h00000000 /* 0x3174 */;
3166: data_o = 32'h00000000 /* 0x3178 */;
3167: data_o = 32'h00000000 /* 0x317c */;
3168: data_o = 32'h00000000 /* 0x3180 */;
3169: data_o = 32'h00000000 /* 0x3184 */;
3170: data_o = 32'h00000000 /* 0x3188 */;
3171: data_o = 32'h00000000 /* 0x318c */;
3172: data_o = 32'h00000000 /* 0x3190 */;
3173: data_o = 32'h00000000 /* 0x3194 */;
3174: data_o = 32'h00000000 /* 0x3198 */;
3175: data_o = 32'h00000000 /* 0x319c */;
3176: data_o = 32'h00000000 /* 0x31a0 */;
3177: data_o = 32'h00000000 /* 0x31a4 */;
3178: data_o = 32'h00000000 /* 0x31a8 */;
3179: data_o = 32'h00000000 /* 0x31ac */;
3180: data_o = 32'h00000000 /* 0x31b0 */;
3181: data_o = 32'h00000000 /* 0x31b4 */;
3182: data_o = 32'h00000000 /* 0x31b8 */;
3183: data_o = 32'h00000000 /* 0x31bc */;
3184: data_o = 32'h00000000 /* 0x31c0 */;
3185: data_o = 32'h00000000 /* 0x31c4 */;
3186: data_o = 32'h00000000 /* 0x31c8 */;
3187: data_o = 32'h00000000 /* 0x31cc */;
3188: data_o = 32'h00000000 /* 0x31d0 */;
3189: data_o = 32'h00000000 /* 0x31d4 */;
3190: data_o = 32'h00000000 /* 0x31d8 */;
3191: data_o = 32'h00000000 /* 0x31dc */;
3192: data_o = 32'h00000000 /* 0x31e0 */;
3193: data_o = 32'h00000000 /* 0x31e4 */;
3194: data_o = 32'h00000000 /* 0x31e8 */;
3195: data_o = 32'h00000000 /* 0x31ec */;
3196: data_o = 32'h00000000 /* 0x31f0 */;
3197: data_o = 32'h00000000 /* 0x31f4 */;
3198: data_o = 32'h00000000 /* 0x31f8 */;
3199: data_o = 32'h00000000 /* 0x31fc */;
3200: data_o = 32'h00000000 /* 0x3200 */;
3201: data_o = 32'h00000000 /* 0x3204 */;
3202: data_o = 32'h00000000 /* 0x3208 */;
3203: data_o = 32'h00000000 /* 0x320c */;
3204: data_o = 32'h00000000 /* 0x3210 */;
3205: data_o = 32'h00000000 /* 0x3214 */;
3206: data_o = 32'h00000000 /* 0x3218 */;
3207: data_o = 32'h00000000 /* 0x321c */;
3208: data_o = 32'h00000000 /* 0x3220 */;
3209: data_o = 32'h00000000 /* 0x3224 */;
3210: data_o = 32'h00000000 /* 0x3228 */;
3211: data_o = 32'h00000000 /* 0x322c */;
3212: data_o = 32'h00000000 /* 0x3230 */;
3213: data_o = 32'h00000000 /* 0x3234 */;
3214: data_o = 32'h00000000 /* 0x3238 */;
3215: data_o = 32'h00000000 /* 0x323c */;
3216: data_o = 32'h00000000 /* 0x3240 */;
3217: data_o = 32'h00000000 /* 0x3244 */;
3218: data_o = 32'h00000000 /* 0x3248 */;
3219: data_o = 32'h00000000 /* 0x324c */;
3220: data_o = 32'h00000000 /* 0x3250 */;
3221: data_o = 32'h00000000 /* 0x3254 */;
3222: data_o = 32'h00000000 /* 0x3258 */;
3223: data_o = 32'h00000000 /* 0x325c */;
3224: data_o = 32'h00000000 /* 0x3260 */;
3225: data_o = 32'h00000000 /* 0x3264 */;
3226: data_o = 32'h00000000 /* 0x3268 */;
3227: data_o = 32'h00000000 /* 0x326c */;
3228: data_o = 32'h00000000 /* 0x3270 */;
3229: data_o = 32'h00000000 /* 0x3274 */;
3230: data_o = 32'h00000000 /* 0x3278 */;
3231: data_o = 32'h00000000 /* 0x327c */;
3232: data_o = 32'h00000000 /* 0x3280 */;
3233: data_o = 32'h00000000 /* 0x3284 */;
3234: data_o = 32'h00000000 /* 0x3288 */;
3235: data_o = 32'h00000000 /* 0x328c */;
3236: data_o = 32'h00000000 /* 0x3290 */;
3237: data_o = 32'h00000000 /* 0x3294 */;
3238: data_o = 32'h00000000 /* 0x3298 */;
3239: data_o = 32'h00000000 /* 0x329c */;
3240: data_o = 32'h00000000 /* 0x32a0 */;
3241: data_o = 32'h00000000 /* 0x32a4 */;
3242: data_o = 32'h00000000 /* 0x32a8 */;
3243: data_o = 32'h00000000 /* 0x32ac */;
3244: data_o = 32'h00000000 /* 0x32b0 */;
3245: data_o = 32'h00000000 /* 0x32b4 */;
3246: data_o = 32'h00000000 /* 0x32b8 */;
3247: data_o = 32'h00000000 /* 0x32bc */;
3248: data_o = 32'h00000000 /* 0x32c0 */;
3249: data_o = 32'h00000000 /* 0x32c4 */;
3250: data_o = 32'h00000000 /* 0x32c8 */;
3251: data_o = 32'h00000000 /* 0x32cc */;
3252: data_o = 32'h00000000 /* 0x32d0 */;
3253: data_o = 32'h00000000 /* 0x32d4 */;
3254: data_o = 32'h00000000 /* 0x32d8 */;
3255: data_o = 32'h00000000 /* 0x32dc */;
3256: data_o = 32'h00000000 /* 0x32e0 */;
3257: data_o = 32'h00000000 /* 0x32e4 */;
3258: data_o = 32'h00000000 /* 0x32e8 */;
3259: data_o = 32'h00000000 /* 0x32ec */;
3260: data_o = 32'h00000000 /* 0x32f0 */;
3261: data_o = 32'h00000000 /* 0x32f4 */;
3262: data_o = 32'h00000000 /* 0x32f8 */;
3263: data_o = 32'h00000000 /* 0x32fc */;
3264: data_o = 32'h00000000 /* 0x3300 */;
3265: data_o = 32'h00000000 /* 0x3304 */;
3266: data_o = 32'h00000000 /* 0x3308 */;
3267: data_o = 32'h00000000 /* 0x330c */;
3268: data_o = 32'h00000000 /* 0x3310 */;
3269: data_o = 32'h00000000 /* 0x3314 */;
3270: data_o = 32'h00000000 /* 0x3318 */;
3271: data_o = 32'h00000000 /* 0x331c */;
3272: data_o = 32'h00000000 /* 0x3320 */;
3273: data_o = 32'h00000000 /* 0x3324 */;
3274: data_o = 32'h00000000 /* 0x3328 */;
3275: data_o = 32'h00000000 /* 0x332c */;
3276: data_o = 32'h00000000 /* 0x3330 */;
3277: data_o = 32'h00000000 /* 0x3334 */;
3278: data_o = 32'h00000000 /* 0x3338 */;
3279: data_o = 32'h00000000 /* 0x333c */;
3280: data_o = 32'h00000000 /* 0x3340 */;
3281: data_o = 32'h00000000 /* 0x3344 */;
3282: data_o = 32'h00000000 /* 0x3348 */;
3283: data_o = 32'h00000000 /* 0x334c */;
3284: data_o = 32'h00000000 /* 0x3350 */;
3285: data_o = 32'h00000000 /* 0x3354 */;
3286: data_o = 32'h00000000 /* 0x3358 */;
3287: data_o = 32'h00000000 /* 0x335c */;
3288: data_o = 32'h00000000 /* 0x3360 */;
3289: data_o = 32'h00000000 /* 0x3364 */;
3290: data_o = 32'h00000000 /* 0x3368 */;
3291: data_o = 32'h00000000 /* 0x336c */;
3292: data_o = 32'h00000000 /* 0x3370 */;
3293: data_o = 32'h00000000 /* 0x3374 */;
3294: data_o = 32'h00000000 /* 0x3378 */;
3295: data_o = 32'h00000000 /* 0x337c */;
3296: data_o = 32'h00000000 /* 0x3380 */;
3297: data_o = 32'h00000000 /* 0x3384 */;
3298: data_o = 32'h00000000 /* 0x3388 */;
3299: data_o = 32'h00000000 /* 0x338c */;
3300: data_o = 32'h00000000 /* 0x3390 */;
3301: data_o = 32'h00000000 /* 0x3394 */;
3302: data_o = 32'h00000000 /* 0x3398 */;
3303: data_o = 32'h00000000 /* 0x339c */;
3304: data_o = 32'h00000000 /* 0x33a0 */;
3305: data_o = 32'h00000000 /* 0x33a4 */;
3306: data_o = 32'h00000000 /* 0x33a8 */;
3307: data_o = 32'h00000000 /* 0x33ac */;
3308: data_o = 32'h00000000 /* 0x33b0 */;
3309: data_o = 32'h00000000 /* 0x33b4 */;
3310: data_o = 32'h00000000 /* 0x33b8 */;
3311: data_o = 32'h00000000 /* 0x33bc */;
3312: data_o = 32'h00000000 /* 0x33c0 */;
3313: data_o = 32'h00000000 /* 0x33c4 */;
3314: data_o = 32'h00000000 /* 0x33c8 */;
3315: data_o = 32'h00000000 /* 0x33cc */;
3316: data_o = 32'h00000000 /* 0x33d0 */;
3317: data_o = 32'h00000000 /* 0x33d4 */;
3318: data_o = 32'h00000000 /* 0x33d8 */;
3319: data_o = 32'h00000000 /* 0x33dc */;
3320: data_o = 32'h00000000 /* 0x33e0 */;
3321: data_o = 32'h00000000 /* 0x33e4 */;
3322: data_o = 32'h00000000 /* 0x33e8 */;
3323: data_o = 32'h00000000 /* 0x33ec */;
3324: data_o = 32'h00000000 /* 0x33f0 */;
3325: data_o = 32'h00000000 /* 0x33f4 */;
3326: data_o = 32'h00000000 /* 0x33f8 */;
3327: data_o = 32'h00000000 /* 0x33fc */;
3328: data_o = 32'h00000000 /* 0x3400 */;
3329: data_o = 32'h00000000 /* 0x3404 */;
3330: data_o = 32'h00000000 /* 0x3408 */;
3331: data_o = 32'h00000000 /* 0x340c */;
3332: data_o = 32'h00000000 /* 0x3410 */;
3333: data_o = 32'h00000000 /* 0x3414 */;
3334: data_o = 32'h00000000 /* 0x3418 */;
3335: data_o = 32'h00000000 /* 0x341c */;
3336: data_o = 32'h00000000 /* 0x3420 */;
3337: data_o = 32'h00000000 /* 0x3424 */;
3338: data_o = 32'h00000000 /* 0x3428 */;
3339: data_o = 32'h00000000 /* 0x342c */;
3340: data_o = 32'h00000000 /* 0x3430 */;
3341: data_o = 32'h00000000 /* 0x3434 */;
3342: data_o = 32'h00000000 /* 0x3438 */;
3343: data_o = 32'h00000000 /* 0x343c */;
3344: data_o = 32'h00000000 /* 0x3440 */;
3345: data_o = 32'h00000000 /* 0x3444 */;
3346: data_o = 32'h00000000 /* 0x3448 */;
3347: data_o = 32'h00000000 /* 0x344c */;
3348: data_o = 32'h00000000 /* 0x3450 */;
3349: data_o = 32'h00000000 /* 0x3454 */;
3350: data_o = 32'h00000000 /* 0x3458 */;
3351: data_o = 32'h00000000 /* 0x345c */;
3352: data_o = 32'h00000000 /* 0x3460 */;
3353: data_o = 32'h00000000 /* 0x3464 */;
3354: data_o = 32'h00000000 /* 0x3468 */;
3355: data_o = 32'h00000000 /* 0x346c */;
3356: data_o = 32'h00000000 /* 0x3470 */;
3357: data_o = 32'h00000000 /* 0x3474 */;
3358: data_o = 32'h00000000 /* 0x3478 */;
3359: data_o = 32'h00000000 /* 0x347c */;
3360: data_o = 32'h00000000 /* 0x3480 */;
3361: data_o = 32'h00000000 /* 0x3484 */;
3362: data_o = 32'h00000000 /* 0x3488 */;
3363: data_o = 32'h00000000 /* 0x348c */;
3364: data_o = 32'h00000000 /* 0x3490 */;
3365: data_o = 32'h00000000 /* 0x3494 */;
3366: data_o = 32'h00000000 /* 0x3498 */;
3367: data_o = 32'h00000000 /* 0x349c */;
3368: data_o = 32'h00000000 /* 0x34a0 */;
3369: data_o = 32'h00000000 /* 0x34a4 */;
3370: data_o = 32'h00000000 /* 0x34a8 */;
3371: data_o = 32'h00000000 /* 0x34ac */;
3372: data_o = 32'h00000000 /* 0x34b0 */;
3373: data_o = 32'h00000000 /* 0x34b4 */;
3374: data_o = 32'h00000000 /* 0x34b8 */;
3375: data_o = 32'h00000000 /* 0x34bc */;
3376: data_o = 32'h00000000 /* 0x34c0 */;
3377: data_o = 32'h00000000 /* 0x34c4 */;
3378: data_o = 32'h00000000 /* 0x34c8 */;
3379: data_o = 32'h00000000 /* 0x34cc */;
3380: data_o = 32'h00000000 /* 0x34d0 */;
3381: data_o = 32'h00000000 /* 0x34d4 */;
3382: data_o = 32'h00000000 /* 0x34d8 */;
3383: data_o = 32'h00000000 /* 0x34dc */;
3384: data_o = 32'h00000000 /* 0x34e0 */;
3385: data_o = 32'h00000000 /* 0x34e4 */;
3386: data_o = 32'h00000000 /* 0x34e8 */;
3387: data_o = 32'h00000000 /* 0x34ec */;
3388: data_o = 32'h00000000 /* 0x34f0 */;
3389: data_o = 32'h00000000 /* 0x34f4 */;
3390: data_o = 32'h00000000 /* 0x34f8 */;
3391: data_o = 32'h00000000 /* 0x34fc */;
3392: data_o = 32'h00000000 /* 0x3500 */;
3393: data_o = 32'h00000000 /* 0x3504 */;
3394: data_o = 32'h00000000 /* 0x3508 */;
3395: data_o = 32'h00000000 /* 0x350c */;
3396: data_o = 32'h00000000 /* 0x3510 */;
3397: data_o = 32'h00000000 /* 0x3514 */;
3398: data_o = 32'h00000000 /* 0x3518 */;
3399: data_o = 32'h00000000 /* 0x351c */;
3400: data_o = 32'h00000000 /* 0x3520 */;
3401: data_o = 32'h00000000 /* 0x3524 */;
3402: data_o = 32'h00000000 /* 0x3528 */;
3403: data_o = 32'h00000000 /* 0x352c */;
3404: data_o = 32'h00000000 /* 0x3530 */;
3405: data_o = 32'h00000000 /* 0x3534 */;
3406: data_o = 32'h00000000 /* 0x3538 */;
3407: data_o = 32'h00000000 /* 0x353c */;
3408: data_o = 32'h00000000 /* 0x3540 */;
3409: data_o = 32'h00000000 /* 0x3544 */;
3410: data_o = 32'h00000000 /* 0x3548 */;
3411: data_o = 32'h00000000 /* 0x354c */;
3412: data_o = 32'h00000000 /* 0x3550 */;
3413: data_o = 32'h00000000 /* 0x3554 */;
3414: data_o = 32'h00000000 /* 0x3558 */;
3415: data_o = 32'h00000000 /* 0x355c */;
3416: data_o = 32'h00000000 /* 0x3560 */;
3417: data_o = 32'h00000000 /* 0x3564 */;
3418: data_o = 32'h00000000 /* 0x3568 */;
3419: data_o = 32'h00000000 /* 0x356c */;
3420: data_o = 32'h00000000 /* 0x3570 */;
3421: data_o = 32'h00000000 /* 0x3574 */;
3422: data_o = 32'h00000000 /* 0x3578 */;
3423: data_o = 32'h00000000 /* 0x357c */;
3424: data_o = 32'h00000000 /* 0x3580 */;
3425: data_o = 32'h00000000 /* 0x3584 */;
3426: data_o = 32'h00000000 /* 0x3588 */;
3427: data_o = 32'h00000000 /* 0x358c */;
3428: data_o = 32'h00000000 /* 0x3590 */;
3429: data_o = 32'h00000000 /* 0x3594 */;
3430: data_o = 32'h00000000 /* 0x3598 */;
3431: data_o = 32'h00000000 /* 0x359c */;
3432: data_o = 32'h00000000 /* 0x35a0 */;
3433: data_o = 32'h00000000 /* 0x35a4 */;
3434: data_o = 32'h00000000 /* 0x35a8 */;
3435: data_o = 32'h00000000 /* 0x35ac */;
3436: data_o = 32'h00000000 /* 0x35b0 */;
3437: data_o = 32'h00000000 /* 0x35b4 */;
3438: data_o = 32'h00000000 /* 0x35b8 */;
3439: data_o = 32'h00000000 /* 0x35bc */;
3440: data_o = 32'h00000000 /* 0x35c0 */;
3441: data_o = 32'h00000000 /* 0x35c4 */;
3442: data_o = 32'h00000000 /* 0x35c8 */;
3443: data_o = 32'h00000000 /* 0x35cc */;
3444: data_o = 32'h00000000 /* 0x35d0 */;
3445: data_o = 32'h00000000 /* 0x35d4 */;
3446: data_o = 32'h00000000 /* 0x35d8 */;
3447: data_o = 32'h00000000 /* 0x35dc */;
3448: data_o = 32'h00000000 /* 0x35e0 */;
3449: data_o = 32'h00000000 /* 0x35e4 */;
3450: data_o = 32'h00000000 /* 0x35e8 */;
3451: data_o = 32'h00000000 /* 0x35ec */;
3452: data_o = 32'h00000000 /* 0x35f0 */;
3453: data_o = 32'h00000000 /* 0x35f4 */;
3454: data_o = 32'h00000000 /* 0x35f8 */;
3455: data_o = 32'h00000000 /* 0x35fc */;
3456: data_o = 32'h00000000 /* 0x3600 */;
3457: data_o = 32'h00000000 /* 0x3604 */;
3458: data_o = 32'h00000000 /* 0x3608 */;
3459: data_o = 32'h00000000 /* 0x360c */;
3460: data_o = 32'h00000000 /* 0x3610 */;
3461: data_o = 32'h00000000 /* 0x3614 */;
3462: data_o = 32'h00000000 /* 0x3618 */;
3463: data_o = 32'h00000000 /* 0x361c */;
3464: data_o = 32'h00000000 /* 0x3620 */;
3465: data_o = 32'h00000000 /* 0x3624 */;
3466: data_o = 32'h00000000 /* 0x3628 */;
3467: data_o = 32'h00000000 /* 0x362c */;
3468: data_o = 32'h00000000 /* 0x3630 */;
3469: data_o = 32'h00000000 /* 0x3634 */;
3470: data_o = 32'h00000000 /* 0x3638 */;
3471: data_o = 32'h00000000 /* 0x363c */;
3472: data_o = 32'h00000000 /* 0x3640 */;
3473: data_o = 32'h00000000 /* 0x3644 */;
3474: data_o = 32'h00000000 /* 0x3648 */;
3475: data_o = 32'h00000000 /* 0x364c */;
3476: data_o = 32'h00000000 /* 0x3650 */;
3477: data_o = 32'h00000000 /* 0x3654 */;
3478: data_o = 32'h00000000 /* 0x3658 */;
3479: data_o = 32'h00000000 /* 0x365c */;
3480: data_o = 32'h00000000 /* 0x3660 */;
3481: data_o = 32'h00000000 /* 0x3664 */;
3482: data_o = 32'h00000000 /* 0x3668 */;
3483: data_o = 32'h00000000 /* 0x366c */;
3484: data_o = 32'h00000000 /* 0x3670 */;
3485: data_o = 32'h00000000 /* 0x3674 */;
3486: data_o = 32'h00000000 /* 0x3678 */;
3487: data_o = 32'h00000000 /* 0x367c */;
3488: data_o = 32'h00000000 /* 0x3680 */;
3489: data_o = 32'h00000000 /* 0x3684 */;
3490: data_o = 32'h00000000 /* 0x3688 */;
3491: data_o = 32'h00000000 /* 0x368c */;
3492: data_o = 32'h00000000 /* 0x3690 */;
3493: data_o = 32'h00000000 /* 0x3694 */;
3494: data_o = 32'h00000000 /* 0x3698 */;
3495: data_o = 32'h00000000 /* 0x369c */;
3496: data_o = 32'h00000000 /* 0x36a0 */;
3497: data_o = 32'h00000000 /* 0x36a4 */;
3498: data_o = 32'h00000000 /* 0x36a8 */;
3499: data_o = 32'h00000000 /* 0x36ac */;
3500: data_o = 32'h00000000 /* 0x36b0 */;
3501: data_o = 32'h00000000 /* 0x36b4 */;
3502: data_o = 32'h00000000 /* 0x36b8 */;
3503: data_o = 32'h00000000 /* 0x36bc */;
3504: data_o = 32'h00000000 /* 0x36c0 */;
3505: data_o = 32'h00000000 /* 0x36c4 */;
3506: data_o = 32'h00000000 /* 0x36c8 */;
3507: data_o = 32'h00000000 /* 0x36cc */;
3508: data_o = 32'h00000000 /* 0x36d0 */;
3509: data_o = 32'h00000000 /* 0x36d4 */;
3510: data_o = 32'h00000000 /* 0x36d8 */;
3511: data_o = 32'h00000000 /* 0x36dc */;
3512: data_o = 32'h00000000 /* 0x36e0 */;
3513: data_o = 32'h00000000 /* 0x36e4 */;
3514: data_o = 32'h00000000 /* 0x36e8 */;
3515: data_o = 32'h00000000 /* 0x36ec */;
3516: data_o = 32'h00000000 /* 0x36f0 */;
3517: data_o = 32'h00000000 /* 0x36f4 */;
3518: data_o = 32'h00000000 /* 0x36f8 */;
3519: data_o = 32'h00000000 /* 0x36fc */;
3520: data_o = 32'h00000000 /* 0x3700 */;
3521: data_o = 32'h00000000 /* 0x3704 */;
3522: data_o = 32'h00000000 /* 0x3708 */;
3523: data_o = 32'h00000000 /* 0x370c */;
3524: data_o = 32'h00000000 /* 0x3710 */;
3525: data_o = 32'h00000000 /* 0x3714 */;
3526: data_o = 32'h00000000 /* 0x3718 */;
3527: data_o = 32'h00000000 /* 0x371c */;
3528: data_o = 32'h00000000 /* 0x3720 */;
3529: data_o = 32'h00000000 /* 0x3724 */;
3530: data_o = 32'h00000000 /* 0x3728 */;
3531: data_o = 32'h00000000 /* 0x372c */;
3532: data_o = 32'h00000000 /* 0x3730 */;
3533: data_o = 32'h00000000 /* 0x3734 */;
3534: data_o = 32'h00000000 /* 0x3738 */;
3535: data_o = 32'h00000000 /* 0x373c */;
3536: data_o = 32'h00000000 /* 0x3740 */;
3537: data_o = 32'h00000000 /* 0x3744 */;
3538: data_o = 32'h00000000 /* 0x3748 */;
3539: data_o = 32'h00000000 /* 0x374c */;
3540: data_o = 32'h00000000 /* 0x3750 */;
3541: data_o = 32'h00000000 /* 0x3754 */;
3542: data_o = 32'h00000000 /* 0x3758 */;
3543: data_o = 32'h00000000 /* 0x375c */;
3544: data_o = 32'h00000000 /* 0x3760 */;
3545: data_o = 32'h00000000 /* 0x3764 */;
3546: data_o = 32'h00000000 /* 0x3768 */;
3547: data_o = 32'h00000000 /* 0x376c */;
3548: data_o = 32'h00000000 /* 0x3770 */;
3549: data_o = 32'h00000000 /* 0x3774 */;
3550: data_o = 32'h00000000 /* 0x3778 */;
3551: data_o = 32'h00000000 /* 0x377c */;
3552: data_o = 32'h00000000 /* 0x3780 */;
3553: data_o = 32'h00000000 /* 0x3784 */;
3554: data_o = 32'h00000000 /* 0x3788 */;
3555: data_o = 32'h00000000 /* 0x378c */;
3556: data_o = 32'h00000000 /* 0x3790 */;
3557: data_o = 32'h00000000 /* 0x3794 */;
3558: data_o = 32'h00000000 /* 0x3798 */;
3559: data_o = 32'h00000000 /* 0x379c */;
3560: data_o = 32'h00000000 /* 0x37a0 */;
3561: data_o = 32'h00000000 /* 0x37a4 */;
3562: data_o = 32'h00000000 /* 0x37a8 */;
3563: data_o = 32'h00000000 /* 0x37ac */;
3564: data_o = 32'h00000000 /* 0x37b0 */;
3565: data_o = 32'h00000000 /* 0x37b4 */;
3566: data_o = 32'h00000000 /* 0x37b8 */;
3567: data_o = 32'h00000000 /* 0x37bc */;
3568: data_o = 32'h00000000 /* 0x37c0 */;
3569: data_o = 32'h00000000 /* 0x37c4 */;
3570: data_o = 32'h00000000 /* 0x37c8 */;
3571: data_o = 32'h00000000 /* 0x37cc */;
3572: data_o = 32'h00000000 /* 0x37d0 */;
3573: data_o = 32'h00000000 /* 0x37d4 */;
3574: data_o = 32'h00000000 /* 0x37d8 */;
3575: data_o = 32'h00000000 /* 0x37dc */;
3576: data_o = 32'h00000000 /* 0x37e0 */;
3577: data_o = 32'h00000000 /* 0x37e4 */;
3578: data_o = 32'h00000000 /* 0x37e8 */;
3579: data_o = 32'h00000000 /* 0x37ec */;
3580: data_o = 32'h00000000 /* 0x37f0 */;
3581: data_o = 32'h00000000 /* 0x37f4 */;
3582: data_o = 32'h00000000 /* 0x37f8 */;
3583: data_o = 32'h00000000 /* 0x37fc */;
3584: data_o = 32'h00000000 /* 0x3800 */;
3585: data_o = 32'h00000000 /* 0x3804 */;
3586: data_o = 32'h00000000 /* 0x3808 */;
3587: data_o = 32'h00000000 /* 0x380c */;
3588: data_o = 32'h00000000 /* 0x3810 */;
3589: data_o = 32'h00000000 /* 0x3814 */;
3590: data_o = 32'h00000000 /* 0x3818 */;
3591: data_o = 32'h00000000 /* 0x381c */;
3592: data_o = 32'h00000000 /* 0x3820 */;
3593: data_o = 32'h00000000 /* 0x3824 */;
3594: data_o = 32'h00000000 /* 0x3828 */;
3595: data_o = 32'h00000000 /* 0x382c */;
3596: data_o = 32'h00000000 /* 0x3830 */;
3597: data_o = 32'h00000000 /* 0x3834 */;
3598: data_o = 32'h00000000 /* 0x3838 */;
3599: data_o = 32'h00000000 /* 0x383c */;
3600: data_o = 32'h00000000 /* 0x3840 */;
3601: data_o = 32'h00000000 /* 0x3844 */;
3602: data_o = 32'h00000000 /* 0x3848 */;
3603: data_o = 32'h00000000 /* 0x384c */;
3604: data_o = 32'h00000000 /* 0x3850 */;
3605: data_o = 32'h00000000 /* 0x3854 */;
3606: data_o = 32'h00000000 /* 0x3858 */;
3607: data_o = 32'h00000000 /* 0x385c */;
3608: data_o = 32'h00000000 /* 0x3860 */;
3609: data_o = 32'h00000000 /* 0x3864 */;
3610: data_o = 32'h00000000 /* 0x3868 */;
3611: data_o = 32'h00000000 /* 0x386c */;
3612: data_o = 32'h00000000 /* 0x3870 */;
3613: data_o = 32'h00000000 /* 0x3874 */;
3614: data_o = 32'h00000000 /* 0x3878 */;
3615: data_o = 32'h00000000 /* 0x387c */;
3616: data_o = 32'h00000000 /* 0x3880 */;
3617: data_o = 32'h00000000 /* 0x3884 */;
3618: data_o = 32'h00000000 /* 0x3888 */;
3619: data_o = 32'h00000000 /* 0x388c */;
3620: data_o = 32'h00000000 /* 0x3890 */;
3621: data_o = 32'h00000000 /* 0x3894 */;
3622: data_o = 32'h00000000 /* 0x3898 */;
3623: data_o = 32'h00000000 /* 0x389c */;
3624: data_o = 32'h00000000 /* 0x38a0 */;
3625: data_o = 32'h00000000 /* 0x38a4 */;
3626: data_o = 32'h00000000 /* 0x38a8 */;
3627: data_o = 32'h00000000 /* 0x38ac */;
3628: data_o = 32'h00000000 /* 0x38b0 */;
3629: data_o = 32'h00000000 /* 0x38b4 */;
3630: data_o = 32'h00000000 /* 0x38b8 */;
3631: data_o = 32'h00000000 /* 0x38bc */;
3632: data_o = 32'h00000000 /* 0x38c0 */;
3633: data_o = 32'h00000000 /* 0x38c4 */;
3634: data_o = 32'h00000000 /* 0x38c8 */;
3635: data_o = 32'h00000000 /* 0x38cc */;
3636: data_o = 32'h00000000 /* 0x38d0 */;
3637: data_o = 32'h00000000 /* 0x38d4 */;
3638: data_o = 32'h00000000 /* 0x38d8 */;
3639: data_o = 32'h00000000 /* 0x38dc */;
3640: data_o = 32'h00000000 /* 0x38e0 */;
3641: data_o = 32'h00000000 /* 0x38e4 */;
3642: data_o = 32'h00000000 /* 0x38e8 */;
3643: data_o = 32'h00000000 /* 0x38ec */;
3644: data_o = 32'h00000000 /* 0x38f0 */;
3645: data_o = 32'h00000000 /* 0x38f4 */;
3646: data_o = 32'h00000000 /* 0x38f8 */;
3647: data_o = 32'h00000000 /* 0x38fc */;
3648: data_o = 32'h00000000 /* 0x3900 */;
3649: data_o = 32'h00000000 /* 0x3904 */;
3650: data_o = 32'h00000000 /* 0x3908 */;
3651: data_o = 32'h00000000 /* 0x390c */;
3652: data_o = 32'h00000000 /* 0x3910 */;
3653: data_o = 32'h00000000 /* 0x3914 */;
3654: data_o = 32'h00000000 /* 0x3918 */;
3655: data_o = 32'h00000000 /* 0x391c */;
3656: data_o = 32'h00000000 /* 0x3920 */;
3657: data_o = 32'h00000000 /* 0x3924 */;
3658: data_o = 32'h00000000 /* 0x3928 */;
3659: data_o = 32'h00000000 /* 0x392c */;
3660: data_o = 32'h00000000 /* 0x3930 */;
3661: data_o = 32'h00000000 /* 0x3934 */;
3662: data_o = 32'h00000000 /* 0x3938 */;
3663: data_o = 32'h00000000 /* 0x393c */;
3664: data_o = 32'h00000000 /* 0x3940 */;
3665: data_o = 32'h00000000 /* 0x3944 */;
3666: data_o = 32'h00000000 /* 0x3948 */;
3667: data_o = 32'h00000000 /* 0x394c */;
3668: data_o = 32'h00000000 /* 0x3950 */;
3669: data_o = 32'h00000000 /* 0x3954 */;
3670: data_o = 32'h00000000 /* 0x3958 */;
3671: data_o = 32'h00000000 /* 0x395c */;
3672: data_o = 32'h00000000 /* 0x3960 */;
3673: data_o = 32'h00000000 /* 0x3964 */;
3674: data_o = 32'h00000000 /* 0x3968 */;
3675: data_o = 32'h00000000 /* 0x396c */;
3676: data_o = 32'h00000000 /* 0x3970 */;
3677: data_o = 32'h00000000 /* 0x3974 */;
3678: data_o = 32'h00000000 /* 0x3978 */;
3679: data_o = 32'h00000000 /* 0x397c */;
3680: data_o = 32'h00000000 /* 0x3980 */;
3681: data_o = 32'h00000000 /* 0x3984 */;
3682: data_o = 32'h00000000 /* 0x3988 */;
3683: data_o = 32'h00000000 /* 0x398c */;
3684: data_o = 32'h00000000 /* 0x3990 */;
3685: data_o = 32'h00000000 /* 0x3994 */;
3686: data_o = 32'h00000000 /* 0x3998 */;
3687: data_o = 32'h00000000 /* 0x399c */;
3688: data_o = 32'h00000000 /* 0x39a0 */;
3689: data_o = 32'h00000000 /* 0x39a4 */;
3690: data_o = 32'h00000000 /* 0x39a8 */;
3691: data_o = 32'h00000000 /* 0x39ac */;
3692: data_o = 32'h00000000 /* 0x39b0 */;
3693: data_o = 32'h00000000 /* 0x39b4 */;
3694: data_o = 32'h00000000 /* 0x39b8 */;
3695: data_o = 32'h00000000 /* 0x39bc */;
3696: data_o = 32'h00000000 /* 0x39c0 */;
3697: data_o = 32'h00000000 /* 0x39c4 */;
3698: data_o = 32'h00000000 /* 0x39c8 */;
3699: data_o = 32'h00000000 /* 0x39cc */;
3700: data_o = 32'h00000000 /* 0x39d0 */;
3701: data_o = 32'h00000000 /* 0x39d4 */;
3702: data_o = 32'h00000000 /* 0x39d8 */;
3703: data_o = 32'h00000000 /* 0x39dc */;
3704: data_o = 32'h00000000 /* 0x39e0 */;
3705: data_o = 32'h00000000 /* 0x39e4 */;
3706: data_o = 32'h00000000 /* 0x39e8 */;
3707: data_o = 32'h00000000 /* 0x39ec */;
3708: data_o = 32'h00000000 /* 0x39f0 */;
3709: data_o = 32'h00000000 /* 0x39f4 */;
3710: data_o = 32'h00000000 /* 0x39f8 */;
3711: data_o = 32'h00000000 /* 0x39fc */;
3712: data_o = 32'h00000000 /* 0x3a00 */;
3713: data_o = 32'h00000000 /* 0x3a04 */;
3714: data_o = 32'h00000000 /* 0x3a08 */;
3715: data_o = 32'h00000000 /* 0x3a0c */;
3716: data_o = 32'h00000000 /* 0x3a10 */;
3717: data_o = 32'h00000000 /* 0x3a14 */;
3718: data_o = 32'h00000000 /* 0x3a18 */;
3719: data_o = 32'h00000000 /* 0x3a1c */;
3720: data_o = 32'h00000000 /* 0x3a20 */;
3721: data_o = 32'h00000000 /* 0x3a24 */;
3722: data_o = 32'h00000000 /* 0x3a28 */;
3723: data_o = 32'h00000000 /* 0x3a2c */;
3724: data_o = 32'h00000000 /* 0x3a30 */;
3725: data_o = 32'h00000000 /* 0x3a34 */;
3726: data_o = 32'h00000000 /* 0x3a38 */;
3727: data_o = 32'h00000000 /* 0x3a3c */;
3728: data_o = 32'h00000000 /* 0x3a40 */;
3729: data_o = 32'h00000000 /* 0x3a44 */;
3730: data_o = 32'h00000000 /* 0x3a48 */;
3731: data_o = 32'h00000000 /* 0x3a4c */;
3732: data_o = 32'h00000000 /* 0x3a50 */;
3733: data_o = 32'h00000000 /* 0x3a54 */;
3734: data_o = 32'h00000000 /* 0x3a58 */;
3735: data_o = 32'h00000000 /* 0x3a5c */;
3736: data_o = 32'h00000000 /* 0x3a60 */;
3737: data_o = 32'h00000000 /* 0x3a64 */;
3738: data_o = 32'h00000000 /* 0x3a68 */;
3739: data_o = 32'h00000000 /* 0x3a6c */;
3740: data_o = 32'h00000000 /* 0x3a70 */;
3741: data_o = 32'h00000000 /* 0x3a74 */;
3742: data_o = 32'h00000000 /* 0x3a78 */;
3743: data_o = 32'h00000000 /* 0x3a7c */;
3744: data_o = 32'h00000000 /* 0x3a80 */;
3745: data_o = 32'h00000000 /* 0x3a84 */;
3746: data_o = 32'h00000000 /* 0x3a88 */;
3747: data_o = 32'h00000000 /* 0x3a8c */;
3748: data_o = 32'h00000000 /* 0x3a90 */;
3749: data_o = 32'h00000000 /* 0x3a94 */;
3750: data_o = 32'h00000000 /* 0x3a98 */;
3751: data_o = 32'h00000000 /* 0x3a9c */;
3752: data_o = 32'h00000000 /* 0x3aa0 */;
3753: data_o = 32'h00000000 /* 0x3aa4 */;
3754: data_o = 32'h00000000 /* 0x3aa8 */;
3755: data_o = 32'h00000000 /* 0x3aac */;
3756: data_o = 32'h00000000 /* 0x3ab0 */;
3757: data_o = 32'h00000000 /* 0x3ab4 */;
3758: data_o = 32'h00000000 /* 0x3ab8 */;
3759: data_o = 32'h00000000 /* 0x3abc */;
3760: data_o = 32'h00000000 /* 0x3ac0 */;
3761: data_o = 32'h00000000 /* 0x3ac4 */;
3762: data_o = 32'h00000000 /* 0x3ac8 */;
3763: data_o = 32'h00000000 /* 0x3acc */;
3764: data_o = 32'h00000000 /* 0x3ad0 */;
3765: data_o = 32'h00000000 /* 0x3ad4 */;
3766: data_o = 32'h00000000 /* 0x3ad8 */;
3767: data_o = 32'h00000000 /* 0x3adc */;
3768: data_o = 32'h00000000 /* 0x3ae0 */;
3769: data_o = 32'h00000000 /* 0x3ae4 */;
3770: data_o = 32'h00000000 /* 0x3ae8 */;
3771: data_o = 32'h00000000 /* 0x3aec */;
3772: data_o = 32'h00000000 /* 0x3af0 */;
3773: data_o = 32'h00000000 /* 0x3af4 */;
3774: data_o = 32'h00000000 /* 0x3af8 */;
3775: data_o = 32'h00000000 /* 0x3afc */;
3776: data_o = 32'h00000000 /* 0x3b00 */;
3777: data_o = 32'h00000000 /* 0x3b04 */;
3778: data_o = 32'h00000000 /* 0x3b08 */;
3779: data_o = 32'h00000000 /* 0x3b0c */;
3780: data_o = 32'h00000000 /* 0x3b10 */;
3781: data_o = 32'h00000000 /* 0x3b14 */;
3782: data_o = 32'h00000000 /* 0x3b18 */;
3783: data_o = 32'h00000000 /* 0x3b1c */;
3784: data_o = 32'h00000000 /* 0x3b20 */;
3785: data_o = 32'h00000000 /* 0x3b24 */;
3786: data_o = 32'h00000000 /* 0x3b28 */;
3787: data_o = 32'h00000000 /* 0x3b2c */;
3788: data_o = 32'h00000000 /* 0x3b30 */;
3789: data_o = 32'h00000000 /* 0x3b34 */;
3790: data_o = 32'h00000000 /* 0x3b38 */;
3791: data_o = 32'h00000000 /* 0x3b3c */;
3792: data_o = 32'h00000000 /* 0x3b40 */;
3793: data_o = 32'h00000000 /* 0x3b44 */;
3794: data_o = 32'h00000000 /* 0x3b48 */;
3795: data_o = 32'h00000000 /* 0x3b4c */;
3796: data_o = 32'h00000000 /* 0x3b50 */;
3797: data_o = 32'h00000000 /* 0x3b54 */;
3798: data_o = 32'h00000000 /* 0x3b58 */;
3799: data_o = 32'h00000000 /* 0x3b5c */;
3800: data_o = 32'h00000000 /* 0x3b60 */;
3801: data_o = 32'h00000000 /* 0x3b64 */;
3802: data_o = 32'h00000000 /* 0x3b68 */;
3803: data_o = 32'h00000000 /* 0x3b6c */;
3804: data_o = 32'h00000000 /* 0x3b70 */;
3805: data_o = 32'h00000000 /* 0x3b74 */;
3806: data_o = 32'h00000000 /* 0x3b78 */;
3807: data_o = 32'h00000000 /* 0x3b7c */;
3808: data_o = 32'h00000000 /* 0x3b80 */;
3809: data_o = 32'h00000000 /* 0x3b84 */;
3810: data_o = 32'h00000000 /* 0x3b88 */;
3811: data_o = 32'h00000000 /* 0x3b8c */;
3812: data_o = 32'h00000000 /* 0x3b90 */;
3813: data_o = 32'h00000000 /* 0x3b94 */;
3814: data_o = 32'h00000000 /* 0x3b98 */;
3815: data_o = 32'h00000000 /* 0x3b9c */;
3816: data_o = 32'h00000000 /* 0x3ba0 */;
3817: data_o = 32'h00000000 /* 0x3ba4 */;
3818: data_o = 32'h00000000 /* 0x3ba8 */;
3819: data_o = 32'h00000000 /* 0x3bac */;
3820: data_o = 32'h00000000 /* 0x3bb0 */;
3821: data_o = 32'h00000000 /* 0x3bb4 */;
3822: data_o = 32'h00000000 /* 0x3bb8 */;
3823: data_o = 32'h00000000 /* 0x3bbc */;
3824: data_o = 32'h00000000 /* 0x3bc0 */;
3825: data_o = 32'h00000000 /* 0x3bc4 */;
3826: data_o = 32'h00000000 /* 0x3bc8 */;
3827: data_o = 32'h00000000 /* 0x3bcc */;
3828: data_o = 32'h00000000 /* 0x3bd0 */;
3829: data_o = 32'h00000000 /* 0x3bd4 */;
3830: data_o = 32'h00000000 /* 0x3bd8 */;
3831: data_o = 32'h00000000 /* 0x3bdc */;
3832: data_o = 32'h00000000 /* 0x3be0 */;
3833: data_o = 32'h00000000 /* 0x3be4 */;
3834: data_o = 32'h00000000 /* 0x3be8 */;
3835: data_o = 32'h00000000 /* 0x3bec */;
3836: data_o = 32'h00000000 /* 0x3bf0 */;
3837: data_o = 32'h00000000 /* 0x3bf4 */;
3838: data_o = 32'h00000000 /* 0x3bf8 */;
3839: data_o = 32'h00000000 /* 0x3bfc */;
3840: data_o = 32'h00000000 /* 0x3c00 */;
3841: data_o = 32'h00000000 /* 0x3c04 */;
3842: data_o = 32'h00000000 /* 0x3c08 */;
3843: data_o = 32'h00000000 /* 0x3c0c */;
3844: data_o = 32'h00000000 /* 0x3c10 */;
3845: data_o = 32'h00000000 /* 0x3c14 */;
3846: data_o = 32'h00000000 /* 0x3c18 */;
3847: data_o = 32'h00000000 /* 0x3c1c */;
3848: data_o = 32'h00000000 /* 0x3c20 */;
3849: data_o = 32'h00000000 /* 0x3c24 */;
3850: data_o = 32'h00000000 /* 0x3c28 */;
3851: data_o = 32'h00000000 /* 0x3c2c */;
3852: data_o = 32'h00000000 /* 0x3c30 */;
3853: data_o = 32'h00000000 /* 0x3c34 */;
3854: data_o = 32'h00000000 /* 0x3c38 */;
3855: data_o = 32'h00000000 /* 0x3c3c */;
3856: data_o = 32'h00000000 /* 0x3c40 */;
3857: data_o = 32'h00000000 /* 0x3c44 */;
3858: data_o = 32'h00000000 /* 0x3c48 */;
3859: data_o = 32'h00000000 /* 0x3c4c */;
3860: data_o = 32'h00000000 /* 0x3c50 */;
3861: data_o = 32'h00000000 /* 0x3c54 */;
3862: data_o = 32'h00000000 /* 0x3c58 */;
3863: data_o = 32'h00000000 /* 0x3c5c */;
3864: data_o = 32'h00000000 /* 0x3c60 */;
3865: data_o = 32'h00000000 /* 0x3c64 */;
3866: data_o = 32'h00000000 /* 0x3c68 */;
3867: data_o = 32'h00000000 /* 0x3c6c */;
3868: data_o = 32'h00000000 /* 0x3c70 */;
3869: data_o = 32'h00000000 /* 0x3c74 */;
3870: data_o = 32'h00000000 /* 0x3c78 */;
3871: data_o = 32'h00000000 /* 0x3c7c */;
3872: data_o = 32'h00000000 /* 0x3c80 */;
3873: data_o = 32'h00000000 /* 0x3c84 */;
3874: data_o = 32'h00000000 /* 0x3c88 */;
3875: data_o = 32'h00000000 /* 0x3c8c */;
3876: data_o = 32'h00000000 /* 0x3c90 */;
3877: data_o = 32'h00000000 /* 0x3c94 */;
3878: data_o = 32'h00000000 /* 0x3c98 */;
3879: data_o = 32'h00000000 /* 0x3c9c */;
3880: data_o = 32'h00000000 /* 0x3ca0 */;
3881: data_o = 32'h00000000 /* 0x3ca4 */;
3882: data_o = 32'h00000000 /* 0x3ca8 */;
3883: data_o = 32'h00000000 /* 0x3cac */;
3884: data_o = 32'h00000000 /* 0x3cb0 */;
3885: data_o = 32'h00000000 /* 0x3cb4 */;
3886: data_o = 32'h00000000 /* 0x3cb8 */;
3887: data_o = 32'h00000000 /* 0x3cbc */;
3888: data_o = 32'h00000000 /* 0x3cc0 */;
3889: data_o = 32'h00000000 /* 0x3cc4 */;
3890: data_o = 32'h00000000 /* 0x3cc8 */;
3891: data_o = 32'h00000000 /* 0x3ccc */;
3892: data_o = 32'h00000000 /* 0x3cd0 */;
3893: data_o = 32'h00000000 /* 0x3cd4 */;
3894: data_o = 32'h00000000 /* 0x3cd8 */;
3895: data_o = 32'h00000000 /* 0x3cdc */;
3896: data_o = 32'h00000000 /* 0x3ce0 */;
3897: data_o = 32'h00000000 /* 0x3ce4 */;
3898: data_o = 32'h00000000 /* 0x3ce8 */;
3899: data_o = 32'h00000000 /* 0x3cec */;
3900: data_o = 32'h00000000 /* 0x3cf0 */;
3901: data_o = 32'h00000000 /* 0x3cf4 */;
3902: data_o = 32'h00000000 /* 0x3cf8 */;
3903: data_o = 32'h00000000 /* 0x3cfc */;
3904: data_o = 32'h00000000 /* 0x3d00 */;
3905: data_o = 32'h00000000 /* 0x3d04 */;
3906: data_o = 32'h00000000 /* 0x3d08 */;
3907: data_o = 32'h00000000 /* 0x3d0c */;
3908: data_o = 32'h00000000 /* 0x3d10 */;
3909: data_o = 32'h00000000 /* 0x3d14 */;
3910: data_o = 32'h00000000 /* 0x3d18 */;
3911: data_o = 32'h00000000 /* 0x3d1c */;
3912: data_o = 32'h00000000 /* 0x3d20 */;
3913: data_o = 32'h00000000 /* 0x3d24 */;
3914: data_o = 32'h00000000 /* 0x3d28 */;
3915: data_o = 32'h00000000 /* 0x3d2c */;
3916: data_o = 32'h00000000 /* 0x3d30 */;
3917: data_o = 32'h00000000 /* 0x3d34 */;
3918: data_o = 32'h00000000 /* 0x3d38 */;
3919: data_o = 32'h00000000 /* 0x3d3c */;
3920: data_o = 32'h00000000 /* 0x3d40 */;
3921: data_o = 32'h00000000 /* 0x3d44 */;
3922: data_o = 32'h00000000 /* 0x3d48 */;
3923: data_o = 32'h00000000 /* 0x3d4c */;
3924: data_o = 32'h00000000 /* 0x3d50 */;
3925: data_o = 32'h00000000 /* 0x3d54 */;
3926: data_o = 32'h00000000 /* 0x3d58 */;
3927: data_o = 32'h00000000 /* 0x3d5c */;
3928: data_o = 32'h00000000 /* 0x3d60 */;
3929: data_o = 32'h00000000 /* 0x3d64 */;
3930: data_o = 32'h00000000 /* 0x3d68 */;
3931: data_o = 32'h00000000 /* 0x3d6c */;
3932: data_o = 32'h00000000 /* 0x3d70 */;
3933: data_o = 32'h00000000 /* 0x3d74 */;
3934: data_o = 32'h00000000 /* 0x3d78 */;
3935: data_o = 32'h00000000 /* 0x3d7c */;
3936: data_o = 32'h00000000 /* 0x3d80 */;
3937: data_o = 32'h00000000 /* 0x3d84 */;
3938: data_o = 32'h00000000 /* 0x3d88 */;
3939: data_o = 32'h00000000 /* 0x3d8c */;
3940: data_o = 32'h00000000 /* 0x3d90 */;
3941: data_o = 32'h00000000 /* 0x3d94 */;
3942: data_o = 32'h00000000 /* 0x3d98 */;
3943: data_o = 32'h00000000 /* 0x3d9c */;
3944: data_o = 32'h00000000 /* 0x3da0 */;
3945: data_o = 32'h00000000 /* 0x3da4 */;
3946: data_o = 32'h00000000 /* 0x3da8 */;
3947: data_o = 32'h00000000 /* 0x3dac */;
3948: data_o = 32'h00000000 /* 0x3db0 */;
3949: data_o = 32'h00000000 /* 0x3db4 */;
3950: data_o = 32'h00000000 /* 0x3db8 */;
3951: data_o = 32'h00000000 /* 0x3dbc */;
3952: data_o = 32'h00000000 /* 0x3dc0 */;
3953: data_o = 32'h00000000 /* 0x3dc4 */;
3954: data_o = 32'h00000000 /* 0x3dc8 */;
3955: data_o = 32'h00000000 /* 0x3dcc */;
3956: data_o = 32'h00000000 /* 0x3dd0 */;
3957: data_o = 32'h00000000 /* 0x3dd4 */;
3958: data_o = 32'h00000000 /* 0x3dd8 */;
3959: data_o = 32'h00000000 /* 0x3ddc */;
3960: data_o = 32'h00000000 /* 0x3de0 */;
3961: data_o = 32'h00000000 /* 0x3de4 */;
3962: data_o = 32'h00000000 /* 0x3de8 */;
3963: data_o = 32'h00000000 /* 0x3dec */;
3964: data_o = 32'h00000000 /* 0x3df0 */;
3965: data_o = 32'h00000000 /* 0x3df4 */;
3966: data_o = 32'h00000000 /* 0x3df8 */;
3967: data_o = 32'h00000000 /* 0x3dfc */;
3968: data_o = 32'h00000000 /* 0x3e00 */;
3969: data_o = 32'h00000000 /* 0x3e04 */;
3970: data_o = 32'h00000000 /* 0x3e08 */;
3971: data_o = 32'h00000000 /* 0x3e0c */;
3972: data_o = 32'h00000000 /* 0x3e10 */;
3973: data_o = 32'h00000000 /* 0x3e14 */;
3974: data_o = 32'h00000000 /* 0x3e18 */;
3975: data_o = 32'h00000000 /* 0x3e1c */;
3976: data_o = 32'h00000000 /* 0x3e20 */;
3977: data_o = 32'h00000000 /* 0x3e24 */;
3978: data_o = 32'h00000000 /* 0x3e28 */;
3979: data_o = 32'h00000000 /* 0x3e2c */;
3980: data_o = 32'h00000000 /* 0x3e30 */;
3981: data_o = 32'h00000000 /* 0x3e34 */;
3982: data_o = 32'h00000000 /* 0x3e38 */;
3983: data_o = 32'h00000000 /* 0x3e3c */;
3984: data_o = 32'h00000000 /* 0x3e40 */;
3985: data_o = 32'h00000000 /* 0x3e44 */;
3986: data_o = 32'h00000000 /* 0x3e48 */;
3987: data_o = 32'h00000000 /* 0x3e4c */;
3988: data_o = 32'h00000000 /* 0x3e50 */;
3989: data_o = 32'h00000000 /* 0x3e54 */;
3990: data_o = 32'h00000000 /* 0x3e58 */;
3991: data_o = 32'h00000000 /* 0x3e5c */;
3992: data_o = 32'h00000000 /* 0x3e60 */;
3993: data_o = 32'h00000000 /* 0x3e64 */;
3994: data_o = 32'h00000000 /* 0x3e68 */;
3995: data_o = 32'h00000000 /* 0x3e6c */;
3996: data_o = 32'h00000000 /* 0x3e70 */;
3997: data_o = 32'h00000000 /* 0x3e74 */;
3998: data_o = 32'h00000000 /* 0x3e78 */;
3999: data_o = 32'h00000000 /* 0x3e7c */;
4000: data_o = 32'h00000000 /* 0x3e80 */;
4001: data_o = 32'h00000000 /* 0x3e84 */;
4002: data_o = 32'h00000000 /* 0x3e88 */;
4003: data_o = 32'h00000000 /* 0x3e8c */;
4004: data_o = 32'h00000000 /* 0x3e90 */;
4005: data_o = 32'h00000000 /* 0x3e94 */;
4006: data_o = 32'h00000000 /* 0x3e98 */;
4007: data_o = 32'h00000000 /* 0x3e9c */;
4008: data_o = 32'h00000000 /* 0x3ea0 */;
4009: data_o = 32'h00000000 /* 0x3ea4 */;
4010: data_o = 32'h00000000 /* 0x3ea8 */;
4011: data_o = 32'h00000000 /* 0x3eac */;
4012: data_o = 32'h00000000 /* 0x3eb0 */;
4013: data_o = 32'h00000000 /* 0x3eb4 */;
4014: data_o = 32'h00000000 /* 0x3eb8 */;
4015: data_o = 32'h00000000 /* 0x3ebc */;
4016: data_o = 32'h00000000 /* 0x3ec0 */;
4017: data_o = 32'h00000000 /* 0x3ec4 */;
4018: data_o = 32'h00000000 /* 0x3ec8 */;
4019: data_o = 32'h00000000 /* 0x3ecc */;
4020: data_o = 32'h00000000 /* 0x3ed0 */;
4021: data_o = 32'h00000000 /* 0x3ed4 */;
4022: data_o = 32'h00000000 /* 0x3ed8 */;
4023: data_o = 32'h00000000 /* 0x3edc */;
4024: data_o = 32'h00000000 /* 0x3ee0 */;
4025: data_o = 32'h00000000 /* 0x3ee4 */;
4026: data_o = 32'h00000000 /* 0x3ee8 */;
4027: data_o = 32'h00000000 /* 0x3eec */;
4028: data_o = 32'h00000000 /* 0x3ef0 */;
4029: data_o = 32'h00000000 /* 0x3ef4 */;
4030: data_o = 32'h00000000 /* 0x3ef8 */;
4031: data_o = 32'h00000000 /* 0x3efc */;
4032: data_o = 32'h00000000 /* 0x3f00 */;
4033: data_o = 32'h00000000 /* 0x3f04 */;
4034: data_o = 32'h00000000 /* 0x3f08 */;
4035: data_o = 32'h00000000 /* 0x3f0c */;
4036: data_o = 32'h00000000 /* 0x3f10 */;
4037: data_o = 32'h00000000 /* 0x3f14 */;
4038: data_o = 32'h00000000 /* 0x3f18 */;
4039: data_o = 32'h00000000 /* 0x3f1c */;
4040: data_o = 32'h00000000 /* 0x3f20 */;
4041: data_o = 32'h00000000 /* 0x3f24 */;
4042: data_o = 32'h00000000 /* 0x3f28 */;
4043: data_o = 32'h00000000 /* 0x3f2c */;
4044: data_o = 32'h00000000 /* 0x3f30 */;
4045: data_o = 32'h00000000 /* 0x3f34 */;
4046: data_o = 32'h00000000 /* 0x3f38 */;
4047: data_o = 32'h00000000 /* 0x3f3c */;
4048: data_o = 32'h00000000 /* 0x3f40 */;
4049: data_o = 32'h00000000 /* 0x3f44 */;
4050: data_o = 32'h00000000 /* 0x3f48 */;
4051: data_o = 32'h00000000 /* 0x3f4c */;
4052: data_o = 32'h00000000 /* 0x3f50 */;
4053: data_o = 32'h00000000 /* 0x3f54 */;
4054: data_o = 32'h00000000 /* 0x3f58 */;
4055: data_o = 32'h00000000 /* 0x3f5c */;
4056: data_o = 32'h00000000 /* 0x3f60 */;
4057: data_o = 32'h00000000 /* 0x3f64 */;
4058: data_o = 32'h00000000 /* 0x3f68 */;
4059: data_o = 32'h00000000 /* 0x3f6c */;
4060: data_o = 32'h00000000 /* 0x3f70 */;
4061: data_o = 32'h00000000 /* 0x3f74 */;
4062: data_o = 32'h00000000 /* 0x3f78 */;
4063: data_o = 32'h00000000 /* 0x3f7c */;
4064: data_o = 32'h00000000 /* 0x3f80 */;
4065: data_o = 32'h00000000 /* 0x3f84 */;
4066: data_o = 32'h00000000 /* 0x3f88 */;
4067: data_o = 32'h00000000 /* 0x3f8c */;
4068: data_o = 32'h00000000 /* 0x3f90 */;
4069: data_o = 32'h00000000 /* 0x3f94 */;
4070: data_o = 32'h00000000 /* 0x3f98 */;
4071: data_o = 32'h00000000 /* 0x3f9c */;
4072: data_o = 32'h00000000 /* 0x3fa0 */;
4073: data_o = 32'h00000000 /* 0x3fa4 */;
4074: data_o = 32'h00000000 /* 0x3fa8 */;
4075: data_o = 32'h00000000 /* 0x3fac */;
4076: data_o = 32'h00000000 /* 0x3fb0 */;
4077: data_o = 32'h00000000 /* 0x3fb4 */;
4078: data_o = 32'h00000000 /* 0x3fb8 */;
4079: data_o = 32'h00000000 /* 0x3fbc */;
4080: data_o = 32'h00000000 /* 0x3fc0 */;
4081: data_o = 32'h00000000 /* 0x3fc4 */;
4082: data_o = 32'h00000000 /* 0x3fc8 */;
4083: data_o = 32'h00000000 /* 0x3fcc */;
4084: data_o = 32'h00000000 /* 0x3fd0 */;
4085: data_o = 32'h00000000 /* 0x3fd4 */;
4086: data_o = 32'h00000000 /* 0x3fd8 */;
4087: data_o = 32'h00000000 /* 0x3fdc */;
4088: data_o = 32'h00000000 /* 0x3fe0 */;
4089: data_o = 32'h00000000 /* 0x3fe4 */;
4090: data_o = 32'h00000000 /* 0x3fe8 */;
4091: data_o = 32'h00000000 /* 0x3fec */;
4092: data_o = 32'h00000000 /* 0x3ff0 */;
4093: data_o = 32'h00000000 /* 0x3ff4 */;
4094: data_o = 32'h00000000 /* 0x3ff8 */;
4095: data_o = 32'h00000000 /* 0x3ffc */;
default: data_o = '0;
endcase
end
endmodule
// Copyright 2022 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Nicole Narr <[email protected]>
// Christopher Reinwardt <[email protected]>
/// Contains the structs and configurations necessary for the Cheshire Platform
package cheshire_pkg;
// Copyright (c) 2019 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Andreas Kurth <[email protected]>
// - Florian Zaruba <[email protected]>
// - Wolfgang Roenninger <[email protected]>
// Macros to define AXI and AXI-Lite Channel and Request/Response Structs
////////////////////////////////////////////////////////////////////////////////////////////////////
// AXI4+ATOP Channel and Request/Response Structs
//
// Usage Example:
// `AXI_TYPEDEF_AW_CHAN_T(axi_aw_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t)
// `AXI_TYPEDEF_B_CHAN_T(axi_b_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_AR_CHAN_T(axi_ar_t, axi_addr_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_R_CHAN_T(axi_r_t, axi_data_t, axi_id_t, axi_user_t)
// `AXI_TYPEDEF_REQ_T(axi_req_t, axi_aw_t, axi_w_t, axi_ar_t)
// `AXI_TYPEDEF_RESP_T(axi_resp_t, axi_b_t, axi_r_t)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4+ATOP Channels and Request/Response Structs in One Macro - Custom Type Name Version
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_TYPEDEF_ALL_CT(axi, axi_req_t, axi_rsp_t, addr_t, id_t, data_t, strb_t, user_t)
//
// This defines `axi_req_t` and `axi_rsp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4+ATOP Channels and Request/Response Structs in One Macro
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t)
//
// This defines `axi_req_t` and `axi_resp_t` request/response structs as well as `axi_aw_chan_t`,
// `axi_w_chan_t`, `axi_b_chan_t`, `axi_ar_chan_t`, and `axi_r_chan_t` channel structs.
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Channel and Request/Response Structs
//
// Usage Example:
// `AXI_LITE_TYPEDEF_AW_CHAN_T(axi_lite_aw_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_W_CHAN_T(axi_lite_w_t, axi_lite_data_t, axi_lite_strb_t)
// `AXI_LITE_TYPEDEF_B_CHAN_T(axi_lite_b_t)
// `AXI_LITE_TYPEDEF_AR_CHAN_T(axi_lite_ar_t, axi_lite_addr_t)
// `AXI_LITE_TYPEDEF_R_CHAN_T(axi_lite_r_t, axi_lite_data_t)
// `AXI_LITE_TYPEDEF_REQ_T(axi_lite_req_t, axi_lite_aw_t, axi_lite_w_t, axi_lite_ar_t)
// `AXI_LITE_TYPEDEF_RESP_T(axi_lite_resp_t, axi_lite_b_t, axi_lite_r_t)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4-Lite Channels and Request/Response Structs in One Macro - Custom Type Name Version
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_LITE_TYPEDEF_ALL_CT(axi_lite, axi_lite_req_t, axi_lite_rsp_t, addr_t, data_t, strb_t)
//
// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as
// `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and
// `axi_lite_r_chan_t` channel structs.
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// All AXI4-Lite Channels and Request/Response Structs in One Macro
//
// This can be used whenever the user is not interested in "precise" control of the naming of the
// individual channels.
//
// Usage Example:
// `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t)
//
// This defines `axi_lite_req_t` and `axi_lite_resp_t` request/response structs as well as
// `axi_lite_aw_chan_t`, `axi_lite_w_chan_t`, `axi_lite_b_chan_t`, `axi_lite_ar_chan_t`, and
// `axi_lite_r_chan_t` channel structs.
////////////////////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014-2018 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Authors:
// - Andreas Kurth <[email protected]>
// - Nils Wistoff <[email protected]>
// Macros to assign AXI Interfaces and Structs
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning one AXI struct or interface to another struct or interface.
// The path to the signals on each side is defined by the `__sep*` arguments. The `__opt_as`
// argument allows to use this standalone (with `__opt_as = assign`) or in assignments inside
// processes (with `__opt_as` void).
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning one AXI4+ATOP interface to another, as if you would do `assign slv = mst;`
//
// The channel assignments `AXI_ASSIGN_XX(dst, src)` assign all payload and the valid signal of the
// `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the
// `src` to the `dst` interface.
// The interface assignment `AXI_ASSIGN(dst, src)` assigns all channels including handshakes as if
// `src` was the master of `dst`.
//
// Usage Example:
// `AXI_ASSIGN(slv, mst)
// `AXI_ASSIGN_AW(dst, src)
// `AXI_ASSIGN_R(dst, src)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning a AXI4+ATOP interface to a monitor modport, as if you would do `assign mon = axi_if;`
//
// The channel assignment `AXI_ASSIGN_MONITOR(mon_dv, axi_if)` assigns all signals from `axi_if`
// to the `mon_dv` interface.
//
// Usage Example:
// `AXI_ASSIGN_MONITOR(mon_dv, axi_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting an interface from channel or request/response structs inside a process.
//
// The channel macros `AXI_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the `axi_if`
// interface from the signals in `xx_struct`. They do not set the handshake signals.
// The request macro `AXI_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W, AR)
// and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the `axi_if`
// interface from the signals in `req_struct`.
// The response macro `AXI_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B and R)
// and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the `axi_if`
// interface from the signals in `resp_struct`.
//
// Usage Example:
// always_comb begin
// `AXI_SET_FROM_REQ(my_if, my_req_struct)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning an interface from channel or request/response structs outside a process.
//
// The channel macros `AXI_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals.
// The request macro `AXI_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels (AW, W,
// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response channels (B
// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the
// `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_ASSIGN_FROM_REQ(my_if, my_req_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from an interface inside a process.
//
// The channel macros `AXI_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not set the handshake
// signals.
// The request macro `AXI_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct` (i.e.,
// request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR valid and
// B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// always_comb begin
// `AXI_SET_TO_REQ(my_req_struct, my_if)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from an interface outside a process.
//
// The channel macros `AXI_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not assign the handshake
// signals.
// The request macro `AXI_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of `req_struct`
// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR
// valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_ASSIGN_TO_REQ(my_req_struct, my_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from another struct inside a process.
//
// The channel macros `AXI_SET_XX_STRUCT(lhs, rhs)` set the fields of the `lhs` channel struct to
// the fields of the `rhs` channel struct. They do not set the handshake signals, which are not
// part of channel structs.
// The request macro `AXI_SET_REQ_STRUCT(lhs, rhs)` sets all fields of the `lhs` request struct to
// the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) payload
// and request-side handshake signals (AW, W, and AR valid and B and R ready).
// The response macro `AXI_SET_RESP_STRUCT(lhs, rhs)` sets all fields of the `lhs` response struct
// to the fields of the `rhs` response struct. This includes all response channel (B and R) payload
// and response-side handshake signals (B and R valid and AW, W, and R ready).
//
// Usage Example:
// always_comb begin
// `AXI_SET_REQ_STRUCT(my_req_struct, another_req_struct)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from another struct outside a process.
//
// The channel macros `AXI_ASSIGN_XX_STRUCT(lhs, rhs)` assign the fields of the `lhs` channel struct
// to the fields of the `rhs` channel struct. They do not assign the handshake signals, which are
// not part of the channel structs.
// The request macro `AXI_ASSIGN_REQ_STRUCT(lhs, rhs)` assigns all fields of the `lhs` request
// struct to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR)
// payload and request-side handshake signals (AW, W, and AR valid and B and R ready).
// The response macro `AXI_ASSIGN_RESP_STRUCT(lhs, rhs)` assigns all fields of the `lhs` response
// struct to the fields of the `rhs` response struct. This includes all response channel (B and R)
// payload and response-side handshake signals (B and R valid and AW, W, and R ready).
//
// Usage Example:
// `AXI_ASSIGN_REQ_STRUCT(my_req_struct, another_req_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal implementation for assigning one Lite structs or interface to another struct or
// interface. The path to the signals on each side is defined by the `__sep*` arguments. The
// `__opt_as` argument allows to use this standalne (with `__opt_as = assign`) or in assignments
// inside processes (with `__opt_as` void).
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning one AXI-Lite interface to another, as if you would do `assign slv = mst;`
//
// The channel assignments `AXI_LITE_ASSIGN_XX(dst, src)` assign all payload and the valid signal of
// the `XX` channel from the `src` to the `dst` interface and they assign the ready signal from the
// `src` to the `dst` interface.
// The interface assignment `AXI_LITE_ASSIGN(dst, src)` assigns all channels including handshakes as
// if `src` was the master of `dst`.
//
// Usage Example:
// `AXI_LITE_ASSIGN(slv, mst)
// `AXI_LITE_ASSIGN_AW(dst, src)
// `AXI_LITE_ASSIGN_R(dst, src)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting a Lite interface from channel or request/response structs inside a process.
//
// The channel macros `AXI_LITE_SET_FROM_XX(axi_if, xx_struct)` set the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not set the handshake signals.
// The request macro `AXI_LITE_SET_FROM_REQ(axi_if, req_struct)` sets all request channels (AW, W,
// AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_LITE_SET_FROM_RESP(axi_if, resp_struct)` sets both response channels (B
// and R) and the response-side handshake signals (B and R valid and AW, W, and AR ready) of the
// `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_FROM_REQ(my_if, my_req_struct)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning a Lite interface from channel or request/response structs outside a process.
//
// The channel macros `AXI_LITE_ASSIGN_FROM_XX(axi_if, xx_struct)` assign the payload signals of the
// `axi_if` interface from the signals in `xx_struct`. They do not assign the handshake signals.
// The request macro `AXI_LITE_ASSIGN_FROM_REQ(axi_if, req_struct)` assigns all request channels
// (AW, W, AR) and the request-side handshake signals (AW, W, and AR valid and B and R ready) of the
// `axi_if` interface from the signals in `req_struct`.
// The response macro `AXI_LITE_ASSIGN_FROM_RESP(axi_if, resp_struct)` assigns both response
// channels (B and R) and the response-side handshake signals (B and R valid and AW, W, and AR
// ready) of the `axi_if` interface from the signals in `resp_struct`.
//
// Usage Example:
// `AXI_LITE_ASSIGN_FROM_REQ(my_if, my_req_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from an interface inside a process.
//
// The channel macros `AXI_LITE_SET_TO_XX(xx_struct, axi_if)` set the signals of `xx_struct` to the
// payload signals of that channel in the `axi_if` interface. They do not set the handshake
// signals.
// The request macro `AXI_LITE_SET_TO_REQ(axi_if, req_struct)` sets all signals of `req_struct`
// (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW, W, and AR
// valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_LITE_SET_TO_RESP(axi_if, resp_struct)` sets all signals of `resp_struct`
// (i.e., response channel (B and R) payload and response-side handshake signals (B and R valid and
// AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_TO_REQ(my_req_struct, my_if)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from an interface outside a process.
//
// The channel macros `AXI_LITE_ASSIGN_TO_XX(xx_struct, axi_if)` assign the signals of `xx_struct`
// to the payload signals of that channel in the `axi_if` interface. They do not assign the
// handshake signals.
// The request macro `AXI_LITE_ASSIGN_TO_REQ(axi_if, req_struct)` assigns all signals of
// `req_struct` (i.e., request channel (AW, W, AR) payload and request-side handshake signals (AW,
// W, and AR valid and B and R ready)) to the signals in the `axi_if` interface.
// The response macro `AXI_LITE_ASSIGN_TO_RESP(axi_if, resp_struct)` assigns all signals of
// `resp_struct` (i.e., response channel (B and R) payload and response-side handshake signals (B
// and R valid and AW, W, and AR ready)) to the signals in the `axi_if` interface.
//
// Usage Example:
// `AXI_LITE_ASSIGN_TO_REQ(my_req_struct, my_if)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Setting channel or request/response structs from another struct inside a process.
//
// The channel macros `AXI_LITE_SET_XX_STRUCT(lhs, rhs)` set the fields of the `lhs` channel struct
// to the fields of the `rhs` channel struct. They do not set the handshake signals, which are not
// part of channel structs.
// The request macro `AXI_LITE_SET_REQ_STRUCT(lhs, rhs)` sets all fields of the `lhs` request struct
// to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR) payload
// and request-side handshake signals (AW, W, and AR valid and B and R ready).
// The response macro `AXI_LITE_SET_RESP_STRUCT(lhs, rhs)` sets all fields of the `lhs` response
// struct to the fields of the `rhs` response struct. This includes all response channel (B and R)
// payload and response-side handshake signals (B and R valid and AW, W, and R ready).
//
// Usage Example:
// always_comb begin
// `AXI_LITE_SET_REQ_STRUCT(my_req_struct, another_req_struct)
// end
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Assigning channel or request/response structs from another struct outside a process.
//
// The channel macros `AXI_LITE_ASSIGN_XX_STRUCT(lhs, rhs)` assign the fields of the `lhs` channel
// struct to the fields of the `rhs` channel struct. They do not assign the handshake signals,
// which are not part of the channel structs.
// The request macro `AXI_LITE_ASSIGN_REQ_STRUCT(lhs, rhs)` assigns all fields of the `lhs` request
// struct to the fields of the `rhs` request struct. This includes all request channel (AW, W, AR)
// payload and request-side handshake signals (AW, W, and AR valid and B and R ready).
// The response macro `AXI_LITE_ASSIGN_RESP_STRUCT(lhs, rhs)` assigns all fields of the `lhs`
// response struct to the fields of the `rhs` response struct. This includes all response channel
// (B and R) payload and response-side handshake signals (B and R valid and AW, W, and R ready).
//
// Usage Example:
// `AXI_LITE_ASSIGN_REQ_STRUCT(my_req_struct, another_req_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////
// Macros for assigning flattened AXI ports to req/resp AXI structs
// Flat AXI ports are required by the Vivado IP Integrator. Vivado naming convention is followed.
//
// Usage Example:
// `AXI_ASSIGN_MASTER_TO_FLAT("my_bus", my_req_struct, my_rsp_struct)
////////////////////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2020 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Florian Zaruba <[email protected]>
/// Macros to define register bus request/response structs.
// Copyright (c) 2020 ETH Zurich, University of Bologna
//
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Author:
// Wolfgang Roenninger <[email protected]>
// Macros to define APB4 Request/Response Structs
////////////////////////////////////////////////////////////////////////////////////////////////////
// APB4 (v2.0) Request/Response Structs
//
// Usage Example:
// `APB_TYPEDEF_REQ_T ( apb_req_t, addr_t, data_t, strb_t )
// `APB_TYPEDEF_RESP_T ( apb_resp_t, data_t )
////////////////////////////////////////////////////////////////////////////////////////////////////
/// Inputs of X-Bar
typedef enum int {
AxiXbarInCva6,
AxiXbarInDebug,
AxiXbarInSerialLink,
AxiXbarInVga,
AxiXbarInDma,
AxiXbarNumInputs
} axi_xbar_inputs_e;
/// Outputs of X-Bar
typedef enum int {
AxiXbarOutDebug,
AxiXbarOutRegbus,
AxiXbarOutDmaConf,
AxiXbarOutLlc,
AxiXbarOutSerialLink,
AxiXbarNumOutputs
} axi_xbar_outputs_e;
/// Parameters for AXI types
localparam int unsigned AxiAddrWidth = 48;
localparam int unsigned AxiDataWidth = 64;
localparam int unsigned AxiUserWidth = 1;
localparam int unsigned AxiStrbWidth = AxiDataWidth/8; // Using byte strobes
localparam int unsigned AxiXbarMasterIdWidth = 2;
localparam int unsigned AxiXbarSlaveIdWidth = AxiXbarMasterIdWidth + $clog2(AxiXbarNumInputs);
localparam int unsigned AxiXbarCombs = AxiXbarNumInputs * AxiXbarNumOutputs;
localparam logic [AxiXbarCombs-1:0] AxiXbarConnectivity = {AxiXbarCombs{1'b1}};
/// Configuration struct of X-Bar
localparam axi_pkg::xbar_cfg_t AxiXbarCfg = '{
NoSlvPorts: AxiXbarNumInputs,
NoMstPorts: AxiXbarNumOutputs,
MaxMstTrans: 12,
MaxSlvTrans: 12,
FallThrough: 0,
LatencyMode: axi_pkg::CUT_ALL_PORTS,
PipelineStages: 1,
AxiIdWidthSlvPorts: AxiXbarMasterIdWidth,
AxiIdUsedSlvPorts: AxiXbarMasterIdWidth,
UniqueIds: 0,
AxiAddrWidth: 48,
AxiDataWidth: 64,
NoAddrRules: 6
};
/// Address rule struct
typedef struct packed {
logic [31:0] idx;
logic [47:0] start_addr;
logic [47:0] end_addr;
} address_rule_48_t;
/// Address map of the AXI X-Bar
/// NUM_OUTPUT rules + 1 additional for LLC (SPM and DRAM)
localparam address_rule_48_t [AxiXbarNumOutputs:0] AxiXbarAddrmap = '{
'{ idx: AxiXbarOutSerialLink, start_addr: 48'h100000000000, end_addr: 48'h200000000000},
'{ idx: AxiXbarOutLlc, start_addr: 48'h000080000000, end_addr: 48'h000100000000},
'{ idx: AxiXbarOutLlc, start_addr: 48'h000070000000, end_addr: 48'h000070020000},
'{ idx: AxiXbarOutDmaConf, start_addr: 48'h000060000000, end_addr: 48'h000060001000},
'{ idx: AxiXbarOutRegbus, start_addr: 48'h000001000000, end_addr: 48'h000060000000},
'{ idx: AxiXbarOutDebug, start_addr: 48'h000000000000, end_addr: 48'h000000001000}
};
/// Inputs of the Regbus Demux
typedef enum int {
RegbusInXbar,
RegbusNumInputs
} regbus_inputs_e;
/// Outputs of the Regbus Demux
typedef enum int {
RegbusOutBootrom,
RegbusOutCsr,
RegbusOutLlc,
RegbusOutSerialLink,
RegbusOutUart,
RegbusOutI2c,
RegbusOutSpim,
RegbusOutVga,
RegbusOutClint,
RegbusOutPlic,
RegbusOutExternal,
RegbusNumOutputs
} regbus_outputs_e;
/// Address map of the Regbus Demux
localparam address_rule_48_t [RegbusNumOutputs-1:0] RegbusAddrmap = '{
'{ idx: RegbusOutExternal, start_addr: 48'h10000000, end_addr: 48'h60000000 }, // EXTERNAL - 1.25 GiB
'{ idx: RegbusOutPlic, start_addr: 48'h0c000000, end_addr: 48'h10000000 }, // PLIC - 64 MiB
'{ idx: RegbusOutClint, start_addr: 48'h04000000, end_addr: 48'h04100000 }, // CLINT - 1 MiB
'{ idx: RegbusOutVga, start_addr: 48'h02006000, end_addr: 48'h02007000 }, // VGA - 4 KiB
'{ idx: RegbusOutSpim, start_addr: 48'h02005000, end_addr: 48'h02006000 }, // SPIM - 4 KiB
'{ idx: RegbusOutI2c, start_addr: 48'h02004000, end_addr: 48'h02005000 }, // I2C - 4 KiB
'{ idx: RegbusOutUart, start_addr: 48'h02003000, end_addr: 48'h02004000 }, // UART - 4 KiB
'{ idx: RegbusOutSerialLink, start_addr: 48'h02002000, end_addr: 48'h02003000 }, // Serial Link - 4 KiB
'{ idx: RegbusOutLlc, start_addr: 48'h02001000, end_addr: 48'h02002000 }, // LLC - 4 KiB
'{ idx: RegbusOutCsr, start_addr: 48'h02000000, end_addr: 48'h02001000 }, // CSR - 4 KiB
'{ idx: RegbusOutBootrom, start_addr: 48'h01000000, end_addr: 48'h01020000 } // Bootrom - 128 KiB
};
/// Type definitions
///
/// Register bus with 48 bit address and 32 bit data
typedef struct packed {
logic [47:0] addr;
logic write;
logic [31:0] wdata;
logic [3:0] wstrb;
logic valid;
} reg_a48_d32_req_t;
typedef struct packed {
logic [31:0] rdata;
logic error;
logic ready;
} reg_a48_d32_rsp_t;
/// Register bus with 48 bit address and 64 bit data
typedef struct packed {
logic [47:0] addr;
logic write;
logic [63:0] wdata;
logic [7:0] wstrb;
logic valid;
} reg_a48_d64_req_t;
typedef struct packed {
logic [63:0] rdata;
logic error;
logic ready;
} reg_a48_d64_rsp_t;
/// AXI bus with 48 bit address and 64 bit data
typedef struct packed {
logic [AxiXbarMasterIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
logic [0:0] user;
} axi_a48_d64_mst_u0_aw_chan_t;
typedef struct packed {
logic [63:0] data;
logic [7:0] strb;
logic last;
logic [0:0] user;
} axi_a48_d64_mst_u0_w_chan_t;
typedef struct packed {
logic [AxiXbarMasterIdWidth-1:0] id;
axi_pkg::resp_t resp;
logic [0:0] user;
} axi_a48_d64_mst_u0_b_chan_t;
typedef struct packed {
logic [AxiXbarMasterIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
logic [0:0] user;
} axi_a48_d64_mst_u0_ar_chan_t;
typedef struct packed {
logic [AxiXbarMasterIdWidth-1:0] id;
logic [63:0] data;
axi_pkg::resp_t resp;
logic last;
logic [0:0] user;
} axi_a48_d64_mst_u0_r_chan_t;
typedef struct packed {
axi_a48_d64_mst_u0_aw_chan_t aw;
logic aw_valid;
axi_a48_d64_mst_u0_w_chan_t w;
logic w_valid;
logic b_ready;
axi_a48_d64_mst_u0_ar_chan_t ar;
logic ar_valid;
logic r_ready;
} axi_a48_d64_mst_u0_req_t;
typedef struct packed {
logic aw_ready;
logic ar_ready;
logic w_ready;
logic b_valid;
axi_a48_d64_mst_u0_b_chan_t b;
logic r_valid;
axi_a48_d64_mst_u0_r_chan_t r;
} axi_a48_d64_mst_u0_resp_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
logic [0:0] user;
} axi_a48_d64_slv_u0_aw_chan_t;
typedef struct packed {
logic [63:0] data;
logic [7:0] strb;
logic last;
logic [0:0] user;
} axi_a48_d64_slv_u0_w_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
axi_pkg::resp_t resp;
logic [0:0] user;
} axi_a48_d64_slv_u0_b_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
logic [0:0] user;
} axi_a48_d64_slv_u0_ar_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [63:0] data;
axi_pkg::resp_t resp;
logic last;
logic [0:0] user;
} axi_a48_d64_slv_u0_r_chan_t;
typedef struct packed {
axi_a48_d64_slv_u0_aw_chan_t aw;
logic aw_valid;
axi_a48_d64_slv_u0_w_chan_t w;
logic w_valid;
logic b_ready;
axi_a48_d64_slv_u0_ar_chan_t ar;
logic ar_valid;
logic r_ready;
} axi_a48_d64_slv_u0_req_t;
typedef struct packed {
logic aw_ready;
logic ar_ready;
logic w_ready;
logic b_valid;
axi_a48_d64_slv_u0_b_chan_t b;
logic r_valid;
axi_a48_d64_slv_u0_r_chan_t r;
} axi_a48_d64_slv_u0_resp_t;
/// Same AXI bus with 48 bit address and 64 bit data but with CVA6s 4 bit ID
typedef struct packed {
logic [3:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
logic [0:0] user;
} axi_cva6_aw_chan_t;
typedef struct packed {
logic [63:0] data;
logic [7:0] strb;
logic last;
logic [0:0] user;
} axi_cva6_w_chan_t;
typedef struct packed {
logic [3:0] id;
axi_pkg::resp_t resp;
logic [0:0] user;
} axi_cva6_b_chan_t;
typedef struct packed {
logic [3:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
logic [0:0] user;
} axi_cva6_ar_chan_t;
typedef struct packed {
logic [3:0] id;
logic [63:0] data;
axi_pkg::resp_t resp;
logic last;
logic [0:0] user;
} axi_cva6_r_chan_t;
typedef struct packed {
axi_cva6_aw_chan_t aw;
logic aw_valid;
axi_cva6_w_chan_t w;
logic w_valid;
logic b_ready;
axi_cva6_ar_chan_t ar;
logic ar_valid;
logic r_ready;
} axi_cva6_req_t;
typedef struct packed {
logic aw_ready;
logic ar_ready;
logic w_ready;
logic b_valid;
axi_cva6_b_chan_t b;
logic r_valid;
axi_cva6_r_chan_t r;
} axi_cva6_resp_t;
/// AXI bus for LLC (one additional ID bit)
typedef struct packed {
logic [AxiXbarSlaveIdWidth:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
logic [0:0] user;
} axi_a48_d64_mst_u0_llc_aw_chan_t;
typedef struct packed {
logic [63:0] data;
logic [7:0] strb;
logic last;
logic [0:0] user;
} axi_a48_d64_mst_u0_llc_w_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth:0] id;
axi_pkg::resp_t resp;
logic [0:0] user;
} axi_a48_d64_mst_u0_llc_b_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
logic [0:0] user;
} axi_a48_d64_mst_u0_llc_ar_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth:0] id;
logic [63:0] data;
axi_pkg::resp_t resp;
logic last;
logic [0:0] user;
} axi_a48_d64_mst_u0_llc_r_chan_t;
typedef struct packed {
axi_a48_d64_mst_u0_llc_aw_chan_t aw;
logic aw_valid;
axi_a48_d64_mst_u0_llc_w_chan_t w;
logic w_valid;
logic b_ready;
axi_a48_d64_mst_u0_llc_ar_chan_t ar;
logic ar_valid;
logic r_ready;
} axi_a48_d64_mst_u0_llc_req_t;
typedef struct packed {
logic aw_ready;
logic ar_ready;
logic w_ready;
logic b_valid;
axi_a48_d64_mst_u0_llc_b_chan_t b;
logic r_valid;
axi_a48_d64_mst_u0_llc_r_chan_t r;
} axi_a48_d64_mst_u0_llc_resp_t;
/// AXI bus with 48 bit address and 32 bit data
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
axi_pkg::atop_t atop;
logic [0:0] user;
} axi_a48_d32_slv_u0_aw_chan_t;
typedef struct packed {
logic [31:0] data;
logic [3:0] strb;
logic last;
logic [0:0] user;
} axi_a48_d32_slv_u0_w_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
axi_pkg::resp_t resp;
logic [0:0] user;
} axi_a48_d32_slv_u0_b_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [47:0] addr;
axi_pkg::len_t len;
axi_pkg::size_t size;
axi_pkg::burst_t burst;
logic lock;
axi_pkg::cache_t cache;
axi_pkg::prot_t prot;
axi_pkg::qos_t qos;
axi_pkg::region_t region;
logic [0:0] user;
} axi_a48_d32_slv_u0_ar_chan_t;
typedef struct packed {
logic [AxiXbarSlaveIdWidth-1:0] id;
logic [31:0] data;
axi_pkg::resp_t resp;
logic last;
logic [0:0] user;
} axi_a48_d32_slv_u0_r_chan_t;
typedef struct packed {
axi_a48_d32_slv_u0_aw_chan_t aw;
logic aw_valid;
axi_a48_d32_slv_u0_w_chan_t w;
logic w_valid;
logic b_ready;
axi_a48_d32_slv_u0_ar_chan_t ar;
logic ar_valid;
logic r_ready;
} axi_a48_d32_slv_u0_req_t;
typedef struct packed {
logic aw_ready;
logic ar_ready;
logic w_ready;
logic b_valid;
axi_a48_d32_slv_u0_b_chan_t b;
logic r_valid;
axi_a48_d32_slv_u0_r_chan_t r;
} axi_a48_d32_slv_u0_resp_t;
/// Identifier used for user-signal based ATOPs by CVA6
localparam logic [0:0] Cva6Identifier = 1'b1;
/// CVA6 Configuration struct
localparam ariane_pkg::ariane_cfg_t CheshireArianeConfig = '{
/// Default config
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
/// Non idempotent regions
NrNonIdempotentRules: 1,
NonIdempotentAddrBase: {
64'h0100_0000
},
// Everything up until the SPM is assumed non idempotent
NonIdempotentLength: {
64'h6F00_0000
},
/// DRAM, SPM, Boot ROM, Debug Module
NrExecuteRegionRules: 4,
ExecuteRegionAddrBase: {
64'h8000_0000, 64'h7000_0000, 64'h0100_0000, 64'h0
},
ExecuteRegionLength: {
64'h8000_0000, 64'h0002_0000, 64'h0002_0000, 64'h1000
},
/// Cached regions: DRAM, Upper half of SPM
NrCachedRegionRules: 2,
CachedRegionAddrBase: {
64'h8000_0000, 64'h7001_0000
},
CachedRegionLength: {
64'h8000_0000, 64'h0001_0000
},
Axi64BitCompliant: 1'b1,
SwapEndianess: 1'b0,
/// Debug
DmBaseAddress: 64'h0,
NrPMPEntries: 0
};
/// Interrupts
typedef struct packed {
logic uart;
logic spim_spi_event;
logic spim_error;
logic i2c_host_timeout;
logic i2c_ack_stop;
logic i2c_acq_overflow;
logic i2c_tx_overflow;
logic i2c_tx_nonempty;
logic i2c_tx_empty;
logic i2c_trans_complete;
logic i2c_sda_unstable;
logic i2c_stretch_timeout;
logic i2c_sda_interference;
logic i2c_scl_interference;
logic i2c_nak;
logic i2c_rx_overflow;
logic i2c_fmt_overflow;
logic i2c_rx_watermark;
logic i2c_fmt_watermark;
logic zero;
} cheshire_interrupt_t;
/// Debug Module parameter
localparam logic [15:0] PartNum = 1012;
localparam logic [31:0] IDCode = (dm::DbgVersion013 << 28) | (PartNum << 12) | 32'h1;
/// Testbench start adresses
localparam logic [47:0] SpmBase = AxiXbarAddrmap[AxiXbarOutLlc].start_addr;
localparam logic [47:0] ScratchRegsBase = RegbusAddrmap[RegbusOutCsr].start_addr;
/// Cheshire Config
/// Can be used to exclude parts of the system
typedef struct packed {
bit Uart;
bit Spim;
bit I2c;
bit Dma;
bit SerialLink;
bit Dram;
bit Vga;
/// Width of the VGA red channel, ignored if VGA set to 0
logic [31:0] VgaRedWidth;
/// Width of the VGA green channel, ignored if VGA set to 0
logic [31:0] VgaGreenWidth;
/// Width of the VGA blue channel, ignored if VGA set to 0
logic [31:0] VgaBlueWidth;
/// The Clock frequency after coming out of reset
logic [31:0] ResetFreq;
} cheshire_cfg_t;
/// Default FPGA config for Cheshire Platform
localparam cheshire_cfg_t CheshireCfgFPGADefault = '{
Uart: 1'b1,
Spim: 1'b1,
I2c: 1'b1,
Dma: 1'b1,
SerialLink: 1'b0,
Dram: 1'b1,
Vga: 1'b1,
VgaRedWidth: 32'd5,
VgaGreenWidth: 32'd6,
VgaBlueWidth: 32'd5,
ResetFreq: 32'd50000000
};
/// Default ASIC config for Cheshire Platform
localparam cheshire_cfg_t CheshireCfgASICDefault = '{
Uart: 1'b1,
Spim: 1'b1,
I2c: 1'b1,
Dma: 1'b1,
SerialLink: 1'b1,
Dram: 1'b1,
Vga: 1'b1,
VgaRedWidth: 32'd2,
VgaGreenWidth: 32'd3,
VgaBlueWidth: 32'd3,
ResetFreq: 32'd200000000
};
endpackage
// Copyright 2023 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Thomas Benz <[email protected]>
/// Top-level implementation of Baby Iguana <3
module baby_iguana import cheshire_pkg::*;#(
) (
input logic clk_i,
input logic rst_ni,
input logic testmode_i,
// JTAG Interface
input logic jtag_tck_i,
input logic jtag_trst_ni,
input logic jtag_tms_i,
input logic jtag_tdi_i,
output logic jtag_tdo_o
);
axi_a48_d64_slv_u0_req_t axi_req;
axi_a48_d64_slv_u0_resp_t axi_rsp;
axi_a48_d32_slv_u0_req_t axi_narrow_req;
axi_a48_d32_slv_u0_resp_t axi_narrow_rsp;
// Regbus Peripherals
reg_a48_d32_req_t reg_req;
reg_a48_d32_rsp_t reg_rsp;
/////////////
// Debug //
/////////////
// DMI signals for JTAG DMI <-> DM communication
logic dmi_rst_n;
dm::dmi_req_t dmi_req;
logic dmi_req_ready;
logic dmi_req_valid;
dm::dmi_resp_t dmi_resp;
logic dmi_resp_ready;
logic dmi_resp_valid;
// System Bus Access for the debug module
logic sba_req;
logic [15:0] sba_addr;
logic [63:0] sba_addr_long;
logic [31:0] sba_rdata, sba_rdata_q;
logic sba_rvalid;
// Ignore the upper 16 bits
assign sba_addr = sba_addr_long[47:0];
dm::hartinfo_t [0:0] hartinfo;
assign hartinfo[0] = ariane_pkg::DebugHartInfo;
// Debug Module
dm_top #(
.NrHarts ( 1 ),
.BusWidth ( 64 ),
.DmBaseAddress ( 'h0 )
) i_dm_top (
.clk_i,
.rst_ni,
.testmode_i,
.ndmreset_o ( ),
.dmactive_o ( ),
.debug_req_o ( /* NC */ ),
.unavailable_i ( '0 ),
.hartinfo_i ( hartinfo ),
.slave_req_i ( '0 ),
.slave_we_i ( '0 ),
.slave_addr_i ( '0 ),
.slave_be_i ( '0 ),
.slave_wdata_i ( '0 ),
.slave_rdata_o ( /* NC */ ),
.master_req_o ( sba_req ),
.master_add_o ( sba_addr_long ),
.master_we_o ( /* NC */ ),
.master_wdata_o ( /* NC */ ),
.master_be_o ( /* NC */ ),
.master_gnt_i ( sba_req ),
.master_r_valid_i ( sba_rvalid ),
.master_r_rdata_i ( {32'd0, sba_rdata_q} ),
.master_r_err_i ( 1'b0 ),
.master_r_other_err_i ( 1'b0 ),
.dmi_rst_ni ( dmi_rst_n ),
.dmi_req_valid_i ( dmi_req_valid ),
.dmi_req_ready_o ( dmi_req_ready ),
.dmi_req_i ( dmi_req ),
.dmi_resp_valid_o ( dmi_resp_valid ),
.dmi_resp_ready_i ( dmi_resp_ready ),
.dmi_resp_o ( dmi_resp )
);
// Debug Transfer Module + Debug Module Interface
dmi_jtag #(
.IdcodeValue ( IDCode )
) i_dmi_jtag (
.clk_i,
.rst_ni,
.testmode_i,
.dmi_rst_no ( dmi_rst_n ),
.dmi_req_o ( dmi_req ),
.dmi_req_ready_i ( dmi_req_ready ),
.dmi_req_valid_o ( dmi_req_valid ),
.dmi_resp_i ( dmi_resp ),
.dmi_resp_ready_o ( dmi_resp_ready ),
.dmi_resp_valid_i ( dmi_resp_valid ),
.tck_i ( jtag_tck_i ),
.tms_i ( jtag_tms_i ),
.trst_ni ( jtag_trst_ni ),
.td_i ( jtag_tdi_i ),
.td_o ( jtag_tdo_o ),
.tdo_oe_o ( )
);
///////////////
// Bootrom //
///////////////
cheshire_bootrom #(
.AddrWidth ( 16 ),
.DataWidth ( 32 )
) i_bootrom (
.clk_i,
.rst_ni,
.req_i ( sba_req ),
.addr_i ( sba_addr ),
.data_o ( sba_rdata )
);
// State
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_state
if(~rst_ni) begin
sba_rdata_q <= '0;
sba_rvalid <= '0;
end else begin
sba_rdata_q <= sba_rdata;
sba_rvalid <= sba_req;
end
end
endmodule
Raw
baby_iguana.v
This file has been truncated, but you can view the full file.
/* Generated by Yosys 0.27+3 (git sha1 b58664d44, gcc 11.2.0 -fPIC -Os) */
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:631.1-752.10" *)
module \$paramod$188f56f715bf7113e85efc07128579a48c3ed873\cdc_4phase_dst (rst_ni, clk_i, data_o, valid_o, ready_i, async_req_i, async_ack_o, async_data_i);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire _00_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire _01_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire [1:0] _02_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire [1:0] _03_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire [1:0] _04_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:670.3-708.6" *)
wire [1:0] _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:647.10-647.19" *)
wire ack_dst_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:647.21-647.30" *)
reg ack_dst_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:642.16-642.27" *)
output async_ack_o;
wire async_ack_o;
(* enum_value_00 = "\\CLEAR_PHASE_IDLE" *)
(* enum_value_01 = "\\CLEAR_PHASE_ISOLATE" *)
(* enum_value_10 = "\\CLEAR_PHASE_CLEAR" *)
(* enum_value_11 = "\\CLEAR_PHASE_POST_CLEAR" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:643.16-643.28" *)
(* wiretype = "\\clear_seq_phase_e" *)
input [1:0] async_data_i;
wire [1:0] async_data_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:641.16-641.27" *)
input async_req_i;
wire async_req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:637.16-637.21" *)
input clk_i;
wire clk_i;
(* enum_value_00 = "\\CLEAR_PHASE_IDLE" *)
(* enum_value_01 = "\\CLEAR_PHASE_ISOLATE" *)
(* enum_value_10 = "\\CLEAR_PHASE_CLEAR" *)
(* enum_value_11 = "\\CLEAR_PHASE_POST_CLEAR" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:638.16-638.22" *)
(* wiretype = "\\clear_seq_phase_e" *)
output [1:0] data_o;
wire [1:0] data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:651.10-651.20" *)
wire data_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:653.10-653.22" *)
wire output_ready;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:640.16-640.23" *)
input ready_i;
wire ready_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:649.10-649.20" *)
wire req_synced;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:636.16-636.22" *)
input rst_ni;
wire rst_ni;
(* enum_value_00 = "\\IDLE" *)
(* enum_value_01 = "\\WAIT_DOWNSTREAM_ACK" *)
(* enum_value_10 = "\\WAIT_REQ_DEASSERT" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:657.11-657.18" *)
(* wiretype = "\\state_e" *)
wire [1:0] state_d;
(* enum_value_00 = "\\IDLE" *)
(* enum_value_01 = "\\WAIT_DOWNSTREAM_ACK" *)
(* enum_value_10 = "\\WAIT_REQ_DEASSERT" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:657.20-657.27" *)
(* wiretype = "\\state_e" *)
reg [1:0] state_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:639.16-639.23" *)
output valid_o;
wire valid_o;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:710.3-716.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) state_q <= 2'h0;
else if (_09_) state_q <= state_d;
assign _06_ = { _11_, ready_i } != 2'h2;
assign _07_ = { _12_, req_synced } != 2'h2;
assign _08_ = { _10_, req_synced } != 2'h3;
assign _09_ = & { _07_, _06_, _08_ };
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:719.3-725.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) ack_dst_q <= 1'h0;
else ack_dst_q <= ack_dst_d;
assign _05_ = req_synced ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:698.9-701.12" *) 2'hx : 2'h0;
assign _10_ = state_q == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:696.7-702.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *) 2'h2;
assign _00_ = ready_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:690.9-693.12" *) 1'h1 : 1'h0;
assign _11_ = state_q == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:688.7-694.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *) 2'h1;
assign _04_ = ready_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:690.9-693.12" *) 2'h2 : 2'hx;
assign _03_ = ready_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:680.11-684.14" *) 2'h2 : 2'h1;
assign _12_ = ! (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:676.7-686.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *) state_q;
assign _02_ = req_synced ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:678.9-685.12" *) _03_ : 2'hx;
assign _01_ = req_synced ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:678.9-685.12" *) 1'h1 : 1'h0;
function [0:0] _28_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:688.7-694.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *)
(* parallel_case *)
casez (s)
2'b?1:
_28_ = b[0:0];
2'b1?:
_28_ = b[1:1];
default:
_28_ = a;
endcase
endfunction
assign valid_o = _28_(1'h0, { _01_, 1'h1 }, { _12_, _11_ });
function [1:0] _29_;
input [1:0] a;
input [5:0] b;
input [2:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:696.7-702.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *)
(* parallel_case *)
casez (s)
3'b??1:
_29_ = b[1:0];
3'b?1?:
_29_ = b[3:2];
3'b1??:
_29_ = b[5:4];
default:
_29_ = a;
endcase
endfunction
assign state_d = _29_(2'h0, { _02_, _04_, _05_ }, { _12_, _11_, _10_ });
function [0:0] _30_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:696.7-702.10|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:675.5-707.12" *)
(* parallel_case *)
casez (s)
2'b?1:
_30_ = b[0:0];
2'b1?:
_30_ = b[1:1];
default:
_30_ = a;
endcase
endfunction
assign ack_dst_d = _30_(1'h0, { _00_, _01_ }, { _11_, _10_ });
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:660.3-667.5" *)
\$paramod$252136d4adf4135cccabc504f7353066b499cb78\sync i_sync (
.clk_i(clk_i),
.rst_ni(rst_ni),
.serial_i(async_req_i),
.serial_o(req_synced)
);
assign async_ack_o = ack_dst_q;
assign data_o = async_data_i;
assign data_valid = valid_o;
assign output_ready = ready_i;
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:375.1-399.10" *)
module \$paramod$252136d4adf4135cccabc504f7353066b499cb78\sync (clk_i, rst_ni, serial_i, serial_o);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:379.18-379.23" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:387.23-387.28" *)
reg [1:0] reg_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:380.18-380.24" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:381.18-381.26" *)
input serial_i;
wire serial_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:382.18-382.26" *)
output serial_o;
wire serial_o;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:389.5-395.8" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) reg_q <= 2'h0;
else reg_q <= { reg_q[0], serial_i };
assign serial_o = reg_q[1];
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1826.1-1887.10" *)
module \$paramod$2ae3818c383ec9e4b5fcbe86cfd2b09270f9b0c9\fifo_v2 (clk_i, rst_ni, flush_i, testmode_i, full_o, empty_o, alm_full_o, alm_empty_o, data_i, push_i, data_o, pop_i);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1844.19-1844.30" *)
output alm_empty_o;
wire alm_empty_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1843.19-1843.29" *)
output alm_full_o;
wire alm_full_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1836.19-1836.24" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1846.19-1846.25" *)
input [33:0] data_i;
wire [33:0] data_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1849.19-1849.25" *)
output [33:0] data_o;
wire [33:0] data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1842.19-1842.26" *)
output empty_o;
wire empty_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1838.19-1838.26" *)
input flush_i;
wire flush_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1841.19-1841.25" *)
output full_o;
wire full_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1850.19-1850.24" *)
input pop_i;
wire pop_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1847.19-1847.25" *)
input push_i;
wire push_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1837.19-1837.25" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1839.19-1839.29" *)
input testmode_i;
wire testmode_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1853.28-1853.33" *)
wire usage;
assign alm_full_o = usage >= (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1860.32-1860.68" *) 1'h1;
assign alm_empty_o = usage <= (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1861.32-1861.69" *) 1'h1;
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1864.5-1881.7" *)
\$paramod$e494a19f6a2dfa4742b0f2a81ce288d4c04acfe9\fifo_v3 i_fifo_v3 (
.clk_i(clk_i),
.data_i(data_i),
.data_o(data_o),
.empty_o(empty_o),
.flush_i(flush_i),
.full_o(full_o),
.pop_i(pop_i),
.push_i(push_i),
.rst_ni(rst_ni),
.testmode_i(testmode_i),
.usage_o(usage)
);
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3013.1-3658.20" *)
module \$paramod$347fe71c49e01963bcd82bfabe5c4311a43ce920\dm_csrs (clk_i, rst_ni, testmode_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_resp_valid_o, dmi_resp_ready_i, ndmreset_o, dmactive_o, halted_i, unavailable_i, resumeack_i, hartsel_o, haltreq_o, resumereq_o, clear_resumeack_o, cmd_valid_o, cmderror_valid_i, cmderror_i, cmdbusy_i
, progbuf_o, data_o, data_i, data_valid_i, sbaddress_o, sbaddress_i, sbaddress_write_valid_o, sbreadonaddr_o, sbautoincrement_o, sbaccess_o, sbreadondata_o, sbdata_o, sbdata_read_valid_o, sbdata_write_valid_o, sbdata_i, sbdata_valid_i, sbbusy_i, sberror_valid_i, sberror_i, hartinfo_i, dmi_req_i
, dmi_resp_o, cmd_o);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [31:0] _000_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire _001_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [2:0] _002_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [31:0] _003_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [63:0] _004_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
(* unused_bits = "0" *)
wire [31:0] _005_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [255:0] _006_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [63:0] _007_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [31:0] _008_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
wire [63:0] _009_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _010_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _011_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _012_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _013_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _014_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _015_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _016_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _017_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _018_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _019_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _020_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
(* unused_bits = "0 2 3 4 5 26 27 28 29" *)
wire [31:0] _021_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
(* unused_bits = "1" *)
wire [1:0] _022_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [33:0] _023_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _024_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _025_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _026_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _027_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _028_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _029_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _030_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _031_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _032_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [255:0] _033_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [33:0] _034_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _035_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _036_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _037_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _038_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _039_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _040_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _041_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _042_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _043_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [63:0] _044_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _045_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [255:0] _046_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _047_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _048_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _049_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _050_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _051_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _052_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _053_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _054_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [33:0] _055_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
(* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 21 29 30 31" *)
wire [31:0] _056_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _057_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [33:0] _058_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _059_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _060_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _061_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [31:0] _062_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [2:0] _063_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire [1:0] _064_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3220.3-3557.6" *)
wire _065_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _066_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [63:0] _067_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [1:0] _068_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [255:0] _069_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3399.38-3399.69" *)
wire [2:0] _070_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3460.34-3460.74" *)
wire _071_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.34-3461.83" *)
wire [2:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.47-3289.69" *)
wire _112_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3299.17-3299.43" *)
wire _113_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3345.36-3345.56" *)
wire _114_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.47-3363.70" *)
wire _115_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.60-3461.80" *)
wire _116_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3565.9-3565.48" *)
wire _117_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.9-3289.43" *)
wire _118_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.9-3289.69" *)
wire _119_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.9-3363.70" *)
wire _120_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3542.9-3542.56" *)
wire _121_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3545.9-3545.45" *)
wire _122_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3542.9-3542.31" *)
wire _123_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3341.15-3341.45" *)
wire _124_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3109.9-3109.47" *)
wire _125_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3126.9-3126.50" *)
wire _126_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3143.9-3143.49" *)
wire _127_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [32:0] _128_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _129_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [32:0] _130_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [63:0] _131_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [1:0] _132_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [255:0] _133_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3248.61-3248.96" *)
wire _134_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3251.29-3251.59" *)
wire _135_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3399.38-3399.58" *)
wire [2:0] _136_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3460.56-3460.73" *)
wire _137_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.58-3461.81" *)
wire _138_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3588.25-3588.36" *)
wire _139_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [63:0] _140_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [1:0] _141_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [255:0] _142_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire _143_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire [7:0] _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire [1:0] _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [63:0] _164_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [63:0] _165_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [1:0] _166_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [1:0] _167_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [255:0] _168_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [255:0] _169_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _170_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _171_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _172_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire _173_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _174_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire _175_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _176_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire [31:0] _177_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *)
wire _178_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3218.32-3218.59" *)
(* unused_bits = "4 5 6 7" *)
wire [7:0] _179_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3164.23-3164.37" *)
(* wiretype = "\\abstractauto_t" *)
wire [31:0] abstractauto_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3164.39-3164.53" *)
(* wiretype = "\\abstractauto_t" *)
wire [31:0] abstractauto_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3160.23-3160.33" *)
(* wiretype = "\\abstractcs_t" *)
wire [31:0] abstractcs;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3212.15-3212.31" *)
wire [3:0] autoexecdata_idx;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3043.45-3043.62" *)
output clear_resumeack_o;
wire clear_resumeack_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3018.45-3018.50" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3046.45-3046.50" *)
(* wiretype = "\\command_t" *)
output [31:0] cmd_o;
wire [31:0] cmd_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3163.23-3163.34" *)
wire cmd_valid_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3045.45-3045.56" *)
output cmd_valid_o;
wire cmd_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3163.36-3163.47" *)
reg cmd_valid_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3049.45-3049.54" *)
input cmdbusy_i;
wire cmdbusy_i;
(* enum_value_000 = "\\CmdErrNone" *)
(* enum_value_001 = "\\CmdErrBusy" *)
(* enum_value_010 = "\\CmdErrNotSupported" *)
(* enum_value_011 = "\\CmdErrorException" *)
(* enum_value_100 = "\\CmdErrorHaltResume" *)
(* enum_value_101 = "\\CmdErrorBus" *)
(* enum_value_111 = "\\CmdErrorOther" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3161.23-3161.31" *)
(* wiretype = "\\cmderr_e" *)
wire [2:0] cmderr_d;
(* enum_value_000 = "\\CmdErrNone" *)
(* enum_value_001 = "\\CmdErrBusy" *)
(* enum_value_010 = "\\CmdErrNotSupported" *)
(* enum_value_011 = "\\CmdErrorException" *)
(* enum_value_100 = "\\CmdErrorHaltResume" *)
(* enum_value_101 = "\\CmdErrorBus" *)
(* enum_value_111 = "\\CmdErrorOther" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3161.33-3161.41" *)
(* wiretype = "\\cmderr_e" *)
reg [2:0] cmderr_q;
(* enum_value_000 = "\\CmdErrNone" *)
(* enum_value_001 = "\\CmdErrBusy" *)
(* enum_value_010 = "\\CmdErrNotSupported" *)
(* enum_value_011 = "\\CmdErrorException" *)
(* enum_value_100 = "\\CmdErrorHaltResume" *)
(* enum_value_101 = "\\CmdErrorBus" *)
(* enum_value_111 = "\\CmdErrorOther" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3048.45-3048.55" *)
(* wiretype = "\\cmderr_e" *)
input [2:0] cmderror_i;
wire [2:0] cmderror_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3047.45-3047.61" *)
input cmderror_valid_i;
wire cmderror_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3162.23-3162.32" *)
(* wiretype = "\\command_t" *)
wire [31:0] command_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3162.34-3162.43" *)
(* wiretype = "\\command_t" *)
reg [31:0] command_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3172.35-3172.41" *)
wire [63:0] data_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3054.45-3054.51" *)
input [63:0] data_i;
wire [63:0] data_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3052.45-3052.51" *)
output [63:0] data_o;
wire [63:0] data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3172.43-3172.49" *)
reg [63:0] data_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3055.45-3055.57" *)
input data_valid_i;
wire data_valid_i;
(* enum_value_00000100 = "\\Data0" *)
(* enum_value_00000101 = "\\Data1" *)
(* enum_value_00000110 = "\\Data2" *)
(* enum_value_00000111 = "\\Data3" *)
(* enum_value_00001000 = "\\Data4" *)
(* enum_value_00001001 = "\\Data5" *)
(* enum_value_00001010 = "\\Data6" *)
(* enum_value_00001011 = "\\Data7" *)
(* enum_value_00001100 = "\\Data8" *)
(* enum_value_00001101 = "\\Data9" *)
(* enum_value_00001110 = "\\Data10" *)
(* enum_value_00001111 = "\\Data11" *)
(* enum_value_00010000 = "\\DMControl" *)
(* enum_value_00010001 = "\\DMStatus" *)
(* enum_value_00010010 = "\\Hartinfo" *)
(* enum_value_00010011 = "\\HaltSum1" *)
(* enum_value_00010100 = "\\HAWindowSel" *)
(* enum_value_00010101 = "\\HAWindow" *)
(* enum_value_00010110 = "\\AbstractCS" *)
(* enum_value_00010111 = "\\Command" *)
(* enum_value_00011000 = "\\AbstractAuto" *)
(* enum_value_00011001 = "\\DevTreeAddr0" *)
(* enum_value_00011010 = "\\DevTreeAddr1" *)
(* enum_value_00011011 = "\\DevTreeAddr2" *)
(* enum_value_00011100 = "\\DevTreeAddr3" *)
(* enum_value_00011101 = "\\NextDM" *)
(* enum_value_00100000 = "\\ProgBuf0" *)
(* enum_value_00100001 = "\\ProgBuf1" *)
(* enum_value_00100010 = "\\ProgBuf2" *)
(* enum_value_00100011 = "\\ProgBuf3" *)
(* enum_value_00100100 = "\\ProgBuf4" *)
(* enum_value_00100101 = "\\ProgBuf5" *)
(* enum_value_00100110 = "\\ProgBuf6" *)
(* enum_value_00100111 = "\\ProgBuf7" *)
(* enum_value_00101000 = "\\ProgBuf8" *)
(* enum_value_00101001 = "\\ProgBuf9" *)
(* enum_value_00101010 = "\\ProgBuf10" *)
(* enum_value_00101011 = "\\ProgBuf11" *)
(* enum_value_00101100 = "\\ProgBuf12" *)
(* enum_value_00101101 = "\\ProgBuf13" *)
(* enum_value_00101110 = "\\ProgBuf14" *)
(* enum_value_00101111 = "\\ProgBuf15" *)
(* enum_value_00110000 = "\\AuthData" *)
(* enum_value_00110100 = "\\HaltSum2" *)
(* enum_value_00110101 = "\\HaltSum3" *)
(* enum_value_00110111 = "\\SBAddress3" *)
(* enum_value_00111000 = "\\SBCS" *)
(* enum_value_00111001 = "\\SBAddress0" *)
(* enum_value_00111010 = "\\SBAddress1" *)
(* enum_value_00111011 = "\\SBAddress2" *)
(* enum_value_00111100 = "\\SBData0" *)
(* enum_value_00111101 = "\\SBData1" *)
(* enum_value_00111110 = "\\SBData2" *)
(* enum_value_00111111 = "\\SBData3" *)
(* enum_value_01000000 = "\\HaltSum0" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3209.16-3209.27" *)
(* wiretype = "\\dm_csr_e" *)
wire [7:0] dm_csr_addr;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3032.45-3032.55" *)
output dmactive_o;
wire dmactive_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3159.23-3159.34" *)
(* unused_bits = "0" *)
(* wiretype = "\\dmcontrol_t" *)
wire [31:0] dmcontrol_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3159.36-3159.47" *)
(* wiretype = "\\dmcontrol_t" *)
wire [31:0] dmcontrol_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3025.45-3025.54" *)
(* wiretype = "\\dmi_req_t" *)
input [40:0] dmi_req_i;
wire [40:0] dmi_req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3024.45-3024.60" *)
output dmi_req_ready_o;
wire dmi_req_ready_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3023.45-3023.60" *)
input dmi_req_valid_i;
wire dmi_req_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3029.45-3029.55" *)
(* wiretype = "\\dmi_resp_t" *)
output [33:0] dmi_resp_o;
wire [33:0] dmi_resp_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3028.45-3028.61" *)
input dmi_resp_ready_i;
wire dmi_resp_ready_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3027.45-3027.61" *)
output dmi_resp_valid_o;
wire dmi_resp_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3021.45-3021.55" *)
input dmi_rst_ni;
wire dmi_rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3158.23-3158.31" *)
(* wiretype = "\\dmstatus_t" *)
wire [31:0] dmstatus;
(* enum_value_00 = "\\DTM_NOP" *)
(* enum_value_01 = "\\DTM_READ" *)
(* enum_value_10 = "\\DTM_WRITE" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3081.16-3081.22" *)
(* wiretype = "\\dtm_op_e" *)
wire [1:0] dtm_op;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3093.47-3093.53" *)
wire [31:0] halted;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3194.30-3194.44" *)
wire [1:0] halted_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3097.40-3097.52" *)
wire [31:0] halted_flat1;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3098.40-3098.52" *)
wire [31:0] halted_flat2;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3099.16-3099.28" *)
wire [31:0] halted_flat3;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3036.45-3036.53" *)
input halted_i;
wire halted_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3094.36-3094.52" *)
wire [31:0] halted_reshaped0;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3095.37-3095.53" *)
wire [31:0] halted_reshaped1;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3096.37-3096.53" *)
wire [31:0] halted_reshaped2;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3041.45-3041.54" *)
output haltreq_o;
wire haltreq_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3092.16-3092.24" *)
wire [31:0] haltsum0;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3092.26-3092.34" *)
wire [31:0] haltsum1;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3092.36-3092.44" *)
wire [31:0] haltsum2;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3092.46-3092.54" *)
wire [31:0] haltsum3;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3202.39-3202.55" *)
(* wiretype = "\\hartinfo_t" *)
wire [63:0] hartinfo_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3035.45-3035.55" *)
(* wiretype = "\\hartinfo_t" *)
input [31:0] hartinfo_i;
wire [31:0] hartinfo_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3102.16-3102.28" *)
wire [14:0] hartsel_idx0;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3115.15-3115.27" *)
wire [9:0] hartsel_idx1;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3132.15-3132.27" *)
wire [4:0] hartsel_idx2;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3040.45-3040.54" *)
output [19:0] hartsel_o;
wire [19:0] hartsel_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3169.23-3169.34" *)
wire havereset_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3192.30-3192.49" *)
(* unused_bits = "1" *)
wire [1:0] havereset_d_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3169.36-3169.47" *)
reg havereset_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3192.51-3192.70" *)
wire [1:0] havereset_q_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3031.45-3031.55" *)
output ndmreset_o;
wire ndmreset_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3171.37-3171.46" *)
wire [255:0] progbuf_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3051.45-3051.54" *)
output [255:0] progbuf_o;
wire [255:0] progbuf_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3171.48-3171.57" *)
reg [255:0] progbuf_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3085.16-3085.32" *)
wire resp_queue_empty;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3084.16-3084.31" *)
wire resp_queue_full;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3176.18-3176.32" *)
(* wiretype = "\\dmi_resp_t" *)
wire [33:0] resp_queue_inp;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3087.16-3087.30" *)
wire resp_queue_pop;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3086.16-3086.31" *)
wire resp_queue_push;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3193.30-3193.47" *)
wire [1:0] resumeack_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3038.45-3038.56" *)
input resumeack_i;
wire resumeack_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3042.45-3042.56" *)
output resumereq_o;
wire resumereq_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3019.45-3019.51" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3063.45-3063.55" *)
output [2:0] sbaccess_o;
wire [2:0] sbaccess_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3166.23-3166.31" *)
wire [63:0] sbaddr_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3166.33-3166.41" *)
reg [63:0] sbaddr_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3058.45-3058.56" *)
input [63:0] sbaddress_i;
wire [63:0] sbaddress_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3057.45-3057.56" *)
output [63:0] sbaddress_o;
wire [63:0] sbaddress_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3059.45-3059.68" *)
output sbaddress_write_valid_o;
wire sbaddress_write_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3062.45-3062.62" *)
output sbautoincrement_o;
wire sbautoincrement_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3073.45-3073.53" *)
input sbbusy_i;
wire sbbusy_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3165.23-3165.29" *)
(* wiretype = "\\sbcs_t" *)
wire [31:0] sbcs_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3165.31-3165.37" *)
(* wiretype = "\\sbcs_t" *)
wire [31:0] sbcs_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3167.23-3167.31" *)
wire [63:0] sbdata_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3070.45-3070.53" *)
input [63:0] sbdata_i;
wire [63:0] sbdata_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3066.45-3066.53" *)
output [63:0] sbdata_o;
wire [63:0] sbdata_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3167.33-3167.41" *)
reg [63:0] sbdata_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3067.45-3067.64" *)
output sbdata_read_valid_o;
wire sbdata_read_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3071.45-3071.59" *)
input sbdata_valid_i;
wire sbdata_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3068.45-3068.65" *)
output sbdata_write_valid_o;
wire sbdata_write_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3075.45-3075.54" *)
input [2:0] sberror_i;
wire [2:0] sberror_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3074.45-3074.60" *)
input sberror_valid_i;
wire sberror_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3061.45-3061.59" *)
output sbreadonaddr_o;
wire sbreadonaddr_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3065.45-3065.59" *)
output sbreadondata_o;
wire sbreadondata_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3174.26-3174.39" *)
wire selected_hart;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3020.45-3020.55" *)
input testmode_i;
wire testmode_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3193.49-3193.68" *)
wire [1:0] unavailable_aligned;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3037.45-3037.58" *)
input unavailable_i;
wire unavailable_i;
assign _066_ = 32'd16 + (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) { 28'h0000001, dmi_req_i[37:34] };
assign _067_ = data_q & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _131_;
assign _068_ = { 1'h0, havereset_q } & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _132_;
assign _069_ = progbuf_q & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _133_;
assign resp_queue_push = dmi_req_valid_i & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3180.33-3180.66" *) dmi_req_ready_o;
assign dmstatus[9] = _173_ & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3248.29-3248.96" *) _134_;
assign dmstatus[11] = _135_ & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3251.29-3251.97" *) _134_;
assign _070_ = _136_ & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3399.38-3399.69" *) cmderr_q;
assign _071_ = sbcs_q[22] & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3460.34-3460.74" *) _137_;
assign _072_ = sbcs_q[14:12] & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.34-3461.83" *) { _138_, _138_, _138_ };
assign resp_queue_pop = dmi_resp_ready_i & (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3577.27-3577.63" *) dmi_resp_valid_o;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) progbuf_q <= 256'h0000000000000000000000000000000000000000000000000000000000000000;
else if (_097_) progbuf_q <= _006_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) sbdata_q[63:32] <= 32'd0;
else if (_098_) sbdata_q[63:32] <= _009_[63:32];
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) sbdata_q[31:0] <= 32'd0;
else if (_099_) sbdata_q[31:0] <= _009_[31:0];
reg [2:0] _194_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _194_ <= 3'h0;
else if (_100_) _194_ <= _008_[14:12];
assign sbcs_q[14:12] = _194_;
reg [11:0] _195_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _195_ <= 12'h000;
else if (_101_) _195_ <= { _008_[28:23], _008_[20:15] };
assign { sbcs_q[28:23], sbcs_q[20:15] } = _195_;
reg [16:0] _196_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _196_ <= 17'h00000;
else _196_ <= { _008_[31:29], _008_[22:21], _008_[11:0] };
assign { sbcs_q[31:29], sbcs_q[22:21], sbcs_q[11:0] } = _196_;
reg [27:0] _197_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _197_ <= 28'h0000000;
else if (_102_) _197_ <= { _000_[31:16], _000_[11:0] };
assign { abstractauto_q[31:16], abstractauto_q[11:0] } = _197_;
reg [3:0] _198_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _198_ <= 4'h0;
else _198_ <= _000_[15:12];
assign abstractauto_q[15:12] = _198_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) command_q <= 32'd0;
else if (_103_) command_q <= _003_;
reg \dmcontrol_q_reg[0] ;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) \dmcontrol_q_reg[0] <= 1'h0;
else if (_120_) \dmcontrol_q_reg[0] <= _031_[0];
assign dmcontrol_q[0] = \dmcontrol_q_reg[0] ;
reg [21:0] _201_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) _201_ <= 22'h000000;
else if (_104_) _201_ <= { _005_[31], _005_[25:6], _005_[1] };
assign { dmcontrol_q[31], dmcontrol_q[25:6], dmcontrol_q[1] } = _201_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) data_q <= 64'h0000000000000000;
else if (_105_) data_q <= _004_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) havereset_q <= 1'h1;
else if (_106_) havereset_q <= havereset_d;
reg \dmcontrol_q_reg[30] ;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) \dmcontrol_q_reg[30] <= 1'h0;
else \dmcontrol_q_reg[30] <= _005_[30];
assign dmcontrol_q[30] = \dmcontrol_q_reg[30] ;
assign _073_ = { _151_, _120_, dmcontrol_q[0], cmdbusy_i } != 4'hf;
assign _074_ = { _120_, dmcontrol_q[0] } != 2'h1;
assign _075_ = { _151_, _120_, dmcontrol_q[0] } != 3'h3;
assign _076_ = { _145_, _120_, _124_, dmcontrol_q[0], sbdata_valid_i } != 5'h1e;
assign _077_ = { _120_, dmcontrol_q[0], sbdata_valid_i } != 3'h2;
assign _078_ = { _145_, _120_, dmcontrol_q[0], sbdata_valid_i } != 4'h6;
assign _079_ = { _147_, _120_, _124_, dmcontrol_q[0], sbdata_valid_i } != 5'h1e;
assign _080_ = { _147_, _120_, dmcontrol_q[0], sbdata_valid_i } != 4'h6;
assign _081_ = { _149_, _120_, dmcontrol_q[0], sberror_valid_i, sbbusy_i } != 5'h1d;
assign _082_ = { _120_, dmcontrol_q[0], sberror_valid_i } != 3'h2;
assign _083_ = { _149_, _120_, dmcontrol_q[0], sberror_valid_i } != 4'h6;
assign _084_ = { _149_, _120_, dmcontrol_q[0], sbbusy_i } != 4'hf;
assign _085_ = { _149_, _120_, dmcontrol_q[0] } != 3'h3;
assign _086_ = { _152_, _120_, dmcontrol_q[0], cmdbusy_i } != 4'hf;
assign _087_ = { _152_, _120_, dmcontrol_q[0] } != 3'h3;
assign _088_ = { _153_, _120_, dmcontrol_q[0], cmdbusy_i } != 4'hf;
assign _089_ = { _153_, _120_, dmcontrol_q[0] } != 3'h3;
assign _090_ = { _155_, _120_, dmcontrol_q[0] } != 3'h3;
assign _091_ = { _157_, _120_, dmcontrol_q[0], data_valid_i, cmdbusy_i } != 5'h1d;
assign _092_ = { _120_, dmcontrol_q[0], data_valid_i } != 3'h2;
assign _093_ = { _157_, _120_, dmcontrol_q[0], data_valid_i } != 4'h6;
assign _094_ = { _155_, _120_, dmcontrol_q[1], dmi_req_i[28] } != 4'hc;
assign _095_ = | { _120_, dmcontrol_q[1] };
assign _096_ = { _155_, _120_, dmcontrol_q[1] } != 3'h2;
assign _097_ = & { _073_, _074_, _075_ };
assign _098_ = & { _076_, _077_, _078_ };
assign _099_ = & { _077_, _079_, _080_ };
assign _100_ = & { _082_, _083_, _081_ };
assign _101_ = & { _084_, _085_, _074_ };
assign _102_ = & { _086_, _087_, _074_ };
assign _103_ = & { _089_, _088_, _074_ };
assign _104_ = & { _090_, _074_ };
assign _105_ = & { _091_, _092_, _093_ };
assign _106_ = & { _096_, _094_, _095_ };
assign _107_ = | { _148_, _147_, _146_, _145_ };
assign _108_ = | { _156_, _154_, _153_, _152_, _150_ };
assign _109_ = | { _156_, _153_, _152_, _150_ };
assign _111_ = | { _156_, _150_ };
assign _110_ = | { _147_, _145_ };
assign _112_ = dmi_req_i[33:32] == (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.47-3289.69" *) 2'h1;
assign _113_ = ! (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3299.17-3299.43" *) cmderr_q;
assign _114_ = ! (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3345.36-3345.56" *) sbcs_q[14:12];
assign _115_ = dmi_req_i[33:32] == (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.47-3363.70" *) 2'h2;
assign _116_ = dmi_req_i[14:12] == (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.60-3461.80" *) 3'h1;
assign dmstatus[15] = { dmcontrol_q[15:6], dmcontrol_q[25:16] } > (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3243.38-3243.68" *) 32'd0;
assign _117_ = dmcontrol_q[16] <= (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3565.9-3565.48" *) 32'd0;
assign _118_ = dmi_req_ready_o && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.9-3289.43" *) dmi_req_valid_i;
assign _119_ = _118_ && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.9-3289.69" *) _112_;
assign _120_ = _118_ && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.9-3363.70" *) _115_;
assign _121_ = _123_ && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3542.9-3542.56" *) _021_[30];
assign _122_ = dmcontrol_q[30] && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3545.9-3545.45" *) resumeack_i;
assign _123_ = ! (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3542.9-3542.31" *) dmcontrol_q[30];
assign _124_ = sbbusy_i || (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3341.15-3341.45" *) sbcs_q[22];
assign _125_ = { dmcontrol_q[15:6], dmcontrol_q[25:21] } < (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3109.9-3109.47" *) 32'd1;
assign _126_ = dmcontrol_q[15:6] < (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3126.9-3126.50" *) 32'd1;
assign _127_ = dmcontrol_q[15:11] < (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3143.9-3143.49" *) 32'd1;
assign _128_ = - (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) $signed({ 27'h0000000, dmi_req_i[34], 5'h00 });
assign _129_ = - (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) $signed({ 31'h00000000, dmcontrol_q[16] });
assign _130_ = - (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) $signed({ 25'h0000000, dmi_req_i[36:34], 5'h00 });
assign _131_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _164_;
assign _132_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _166_;
assign _133_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _168_;
assign dmi_resp_valid_o = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3178.33-3178.50" *) resp_queue_empty;
assign dmi_req_ready_o = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3179.33-3179.49" *) resp_queue_full;
assign _134_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3248.61-3248.96" *) dmstatus[13];
assign _135_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3251.29-3251.59" *) _173_;
assign _136_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3399.38-3399.58" *) dmi_req_i[10:8];
assign _137_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3460.56-3460.73" *) dmi_req_i[22];
assign _138_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3461.58-3461.81" *) _116_;
assign _139_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3588.25-3588.36" *) dmi_rst_ni;
assign _140_ = _067_ | (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _165_;
assign _141_ = _068_ | (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _167_;
assign _142_ = _069_ | (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:0.0-0.0" *) _169_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) cmderr_q <= 3'h0;
else cmderr_q <= _002_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) cmd_valid_q <= 1'h0;
else cmd_valid_q <= _001_;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3601.3-3656.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) sbaddr_q <= 64'h0000000000000000;
else sbaddr_q <= _007_;
assign _005_[31] = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) dmcontrol_d[31] : 1'h0;
assign _007_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) sbaddr_d : 64'h0000000000000000;
assign _008_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) { 3'h1, sbcs_d[28:22], sbbusy_i, sbcs_d[20:12], 12'h80f } : 32'd0;
assign _004_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) data_d : 64'h0000000000000000;
assign _006_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) progbuf_d : 256'h0000000000000000000000000000000000000000000000000000000000000000;
assign _000_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) abstractauto_d : 32'd0;
assign _001_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) cmd_valid_d : 1'h0;
assign _003_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) command_d : 32'd0;
assign _002_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) cmderr_d : 3'h0;
assign _009_ = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) sbdata_d : 64'h0000000000000000;
assign _005_[1] = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) dmcontrol_d[1] : 1'h0;
assign _005_[15:6] = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) dmcontrol_d[15:6] : 10'h000;
assign _005_[25:16] = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) dmcontrol_d[25:16] : 10'h000;
assign _005_[30] = dmcontrol_q[0] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3619.7-3654.10" *) dmcontrol_d[30] : 1'h0;
assign resumereq_o = _117_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3565.5-3568.8" *) _144_ : 1'h0;
assign haltreq_o = _117_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3565.5-3568.8" *) _143_ : 1'h0;
assign dmcontrol_d[30] = _122_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3545.5-3547.8" *) 1'h0 : _021_[30];
assign clear_resumeack_o = _121_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3542.5-3544.8" *) 1'h1 : 1'h0;
assign sbdata_d = sbdata_valid_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3527.5-3529.8" *) sbdata_i : _025_;
assign sbcs_d[14:12] = sberror_valid_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3523.5-3525.8" *) sberror_i : _056_[14:12];
assign havereset_d = dmcontrol_q[1] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3516.5-3518.8" *) 1'h1 : _022_[0];
assign data_d = data_valid_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3511.5-3513.8" *) data_i : _020_;
assign cmderr_d = cmderror_valid_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3506.5-3508.8" *) cmderror_i : _061_;
assign _038_[63:32] = _145_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3493.9-3501.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _051_ : 32'hxxxxxxxx;
assign _145_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3493.9-3501.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h3d;
assign _051_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3495.11-3500.14" *) 32'hxxxxxxxx : dmi_req_i[31:0];
assign _035_[31:0] = _146_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3464.9-3473.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _048_ : sbaddress_i[31:0];
assign _146_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3464.9-3473.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h39;
assign _147_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3483.9-3492.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h3c;
assign _038_[31:0] = _147_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3483.9-3492.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _051_ : 32'hxxxxxxxx;
assign _035_[63:32] = _148_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3474.9-3482.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _054_ : sbaddress_i[63:32];
assign _148_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3474.9-3482.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h3a;
assign _013_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3476.11-3481.14" *) 1'h1 : _024_;
assign _054_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3476.11-3481.14" *) sbaddress_i[63:32] : dmi_req_i[31:0];
assign _017_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3485.11-3491.14" *) 2'h3 : _023_[1:0];
assign _048_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3466.11-3472.14" *) sbaddress_i[31:0] : dmi_req_i[31:0];
function [0:0] _317_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3493.9-3501.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *)
(* parallel_case *)
casez (s)
2'b?1:
_317_ = b[0:0];
2'b1?:
_317_ = b[1:1];
default:
_317_ = a;
endcase
endfunction
assign _059_[22] = _317_(_024_, { _062_[22], _013_ }, { _149_, _107_ });
assign _149_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3451.9-3463.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h38;
assign _059_[21:0] = _149_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3451.9-3463.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _062_[21:0] : { sbcs_q[21], 9'hxxx, sbcs_q[11:0] };
assign _062_[14:12] = sbbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3453.11-3462.14" *) 3'hx : _072_;
assign _062_[11:0] = sbbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3453.11-3462.14" *) sbcs_q[11:0] : dmi_req_i[11:0];
assign _062_[22] = sbbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3453.11-3462.14" *) 1'h1 : _071_;
assign _016_ = sbbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3453.11-3462.14" *) 2'h3 : _023_[1:0];
assign _150_[0] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h20;
assign _150_[1] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h21;
assign _150_[2] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h22;
assign _150_[3] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h23;
assign _150_[4] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h24;
assign _150_[5] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h25;
assign _150_[6] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h26;
assign _150_[7] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h27;
assign _010_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3436.11-3449.14" *) _018_ : _178_;
assign _046_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3436.11-3449.14" *) 256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : _142_;
assign _152_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3421.9-3433.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h18;
assign _040_[31:16] = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3423.11-3432.14" *) 16'hxxxx : { 8'h00, dmi_req_i[23:16] };
assign _040_[11:0] = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3423.11-3432.14" *) 12'hxxx : { 10'h000, dmi_req_i[1:0] };
assign _153_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3407.9-3420.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h17;
assign _043_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3409.11-3419.14" *) 32'hxxxxxxxx : dmi_req_i[31:0];
assign _065_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3409.11-3419.14" *) _018_ : 1'h1;
assign _011_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3409.11-3419.14" *) _014_ : _019_;
assign _154_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3391.9-3406.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h16;
assign _015_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3398.11-3405.14" *) _014_ : _070_;
assign _012_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3398.11-3405.14" *) 2'h3 : _023_[1:0];
assign _045_ = dmi_req_i[28] ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3384.11-3386.14" *) _141_ : 2'b0x;
assign _155_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3381.9-3387.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h10;
assign _014_ = _113_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3375.15-3377.18" *) 3'h1 : _019_;
assign _157_ = | (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3365.9-3380.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _156_;
assign _156_[0] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3365.9-3380.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h04;
assign _156_[1] = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3365.9-3380.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) 7'h05;
assign _060_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3368.13-3378.16" *) _018_ : _175_;
assign _044_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3368.13-3378.16" *) 64'hxxxxxxxxxxxxxxxx : _140_;
function [1:0] _352_;
input [1:0] a;
input [5:0] b;
input [2:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3493.9-3501.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *)
(* parallel_case *)
casez (s)
3'b??1:
_352_ = b[1:0];
3'b?1?:
_352_ = b[3:2];
3'b1??:
_352_ = b[5:4];
default:
_352_ = a;
endcase
endfunction
assign _064_ = _352_(_023_[1:0], { _012_, _016_, _017_ }, { _108_, _149_, _107_ });
assign _151_ = | (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _150_;
function [0:0] _354_;
input [0:0] a;
input [2:0] b;
input [2:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *)
(* parallel_case *)
casez (s)
3'b??1:
_354_ = b[0:0];
3'b?1?:
_354_ = b[1:1];
3'b1??:
_354_ = b[2:2];
default:
_354_ = a;
endcase
endfunction
assign _057_ = _354_(_018_, { _060_, _065_, _010_ }, { _157_, _153_, _151_ });
function [2:0] _355_;
input [2:0] a;
input [5:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *)
(* parallel_case *)
casez (s)
2'b?1:
_355_ = b[2:0];
2'b1?:
_355_ = b[5:3];
default:
_355_ = a;
endcase
endfunction
assign _063_ = _355_(_019_, { _015_, _011_ }, { _154_, _109_ });
assign _030_ = _157_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3365.9-3380.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _044_ : 64'hxxxxxxxxxxxxxxxx;
assign _032_ = _155_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3381.9-3387.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _045_ : 2'b0x;
assign _033_ = _151_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3434.9-3450.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _046_ : 256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign _059_[31:23] = _149_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3451.9-3463.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _062_[31:23] : { sbcs_q[31:29], 6'hxx };
assign { _062_[31:23], _062_[21:15] } = sbbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3453.11-3462.14" *) { sbcs_q[31:29], 6'hxx, sbcs_q[21], 6'hxx } : { dmi_req_i[31:23], dmi_req_i[21:15] };
assign _026_ = _152_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3421.9-3433.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) { _040_[31:16], 4'h0, _040_[11:0] } : 32'hxxxx0xxx;
assign _029_ = _153_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3407.9-3420.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _043_ : 32'hxxxxxxxx;
assign _031_ = _155_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3381.9-3387.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) dmi_req_i[31:0] : { 1'hx, dmcontrol_q[30], 29'b0000xxxxxxxxxxxxxxxxxxxx0000x, dmcontrol_q[0] };
assign _039_ = _147_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3483.9-3492.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _049_ : 1'h0;
assign _036_ = _146_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3464.9-3473.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3364.7-3503.14" *) _049_ : 1'h0;
assign { havereset_d_aligned[1], _022_[0] } = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _032_ : 2'b0x;
assign resp_queue_inp[1:0] = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _064_ : _023_[1:0];
assign progbuf_d = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _033_ : 256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
assign _025_ = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _038_ : 64'hxxxxxxxxxxxxxxxx;
assign sbaddr_d = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _035_ : sbaddress_i;
assign { _056_[31:29], sbcs_d[28:22], _056_[21], sbcs_d[20:15], _056_[14:0] } = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _059_ : { sbcs_q[31:29], 6'hxx, _024_, sbcs_q[21], 9'hxxx, sbcs_q[11:0] };
assign abstractauto_d = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _026_ : 32'hxxxx0xxx;
assign cmd_valid_d = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _057_ : _018_;
assign command_d = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _029_ : 32'hxxxxxxxx;
assign _061_ = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _063_ : _019_;
assign { dmcontrol_d[31], _021_[30:26], dmcontrol_d[25:6], _021_[5:2], dmcontrol_d[1:0] } = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _031_ : { 1'hx, dmcontrol_q[30], 29'b0000xxxxxxxxxxxxxxxxxxxx0000x, dmcontrol_q[0] };
assign sbdata_write_valid_o = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _039_ : 1'h0;
assign sbaddress_write_valid_o = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _036_ : 1'h0;
assign _020_ = _120_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3363.5-3504.8" *) _030_ : 64'hxxxxxxxxxxxxxxxx;
function [31:0] _380_;
input [31:0] a;
input [511:0] b;
input [15:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3349.9-3357.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *)
(* parallel_case *)
casez (s)
16'b???????????????1:
_380_ = b[31:0];
16'b??????????????1?:
_380_ = b[63:32];
16'b?????????????1??:
_380_ = b[95:64];
16'b????????????1???:
_380_ = b[127:96];
16'b???????????1????:
_380_ = b[159:128];
16'b??????????1?????:
_380_ = b[191:160];
16'b?????????1??????:
_380_ = b[223:192];
16'b????????1???????:
_380_ = b[255:224];
16'b???????1????????:
_380_ = b[287:256];
16'b??????1?????????:
_380_ = b[319:288];
16'b?????1??????????:
_380_ = b[351:320];
16'b????1???????????:
_380_ = b[383:352];
16'b???1????????????:
_380_ = b[415:384];
16'b??1?????????????:
_380_ = b[447:416];
16'b?1??????????????:
_380_ = b[479:448];
16'b1???????????????:
_380_ = b[511:480];
default:
_380_ = a;
endcase
endfunction
assign _034_[33:2] = _380_(32'd0, { _174_, dmcontrol_q[31:30], 4'h0, dmcontrol_q[25:6], 4'h0, dmcontrol_q[1:0], 12'h000, dmstatus[19], dmstatus[19], dmstatus[17], dmstatus[17], dmstatus[15], dmstatus[15], dmstatus[13], dmstatus[13], dmstatus[11], dmstatus[11], dmstatus[9], dmstatus[9], 8'h82, _176_, 19'h04000, cmdbusy_i, 1'h0, cmderr_q, 8'h02, abstractauto_q, _177_, haltsum0, haltsum1, haltsum2, 31'h00000000, halted_i, sbcs_q, sbaddr_q[31:0], sbaddr_q[63:32], _055_[33:2], _058_[33:2] }, { _157_, _155_, _163_, _162_, _154_, _152_, _151_, _161_, _160_, _159_, _158_, _149_, _146_, _148_, _147_, _145_ });
assign _158_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3329.9-3329.54|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h35;
assign _159_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3328.9-3328.54|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h34;
assign _160_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3327.9-3327.54|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h13;
assign _161_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3326.9-3326.54|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h40;
assign _162_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3306.9-3306.81|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h12;
assign _163_ = dmi_req_i[40:34] == (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3305.9-3305.58|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) 7'h11;
assign _050_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3351.11-3356.14" *) 1'h1 : sbcs_q[22];
assign _058_[33:2] = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3351.11-3356.14" *) 32'd0 : sbdata_q[63:32];
function [1:0] _389_;
input [1:0] a;
input [3:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3349.9-3357.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *)
(* parallel_case *)
casez (s)
2'b?1:
_389_ = b[1:0];
2'b1?:
_389_ = b[3:2];
default:
_389_ = a;
endcase
endfunction
assign _034_[1:0] = _389_(2'h0, { _047_, _055_[1:0] }, { _111_, _110_ });
assign _055_[33:2] = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3341.11-3347.14" *) 32'd0 : sbdata_q[31:0];
assign _049_ = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3341.11-3347.14" *) 1'h0 : _114_;
assign _055_[1:0] = _124_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3351.11-3356.14" *) 2'h3 : 2'h0;
assign _052_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3313.11-3324.14" *) 1'h0 : _178_;
assign _047_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3313.11-3324.14" *) 2'h3 : 2'h0;
assign _042_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3313.11-3324.14" *) _053_ : cmderr_q;
assign _053_ = _113_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3299.13-3301.16" *) 3'h1 : cmderr_q;
assign _041_ = cmdbusy_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3293.11-3302.14" *) 1'h0 : _175_;
function [0:0] _398_;
input [0:0] a;
input [1:0] b;
input [1:0] s;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3311.9-3325.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *)
(* parallel_case *)
casez (s)
2'b?1:
_398_ = b[0:0];
2'b1?:
_398_ = b[1:1];
default:
_398_ = a;
endcase
endfunction
assign _027_ = _398_(1'h0, { _041_, _052_ }, { _157_, _151_ });
assign _028_ = _111_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3311.9-3325.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) _042_ : cmderr_q;
assign _037_ = _110_ ? (* full_case = 32'd1 *) (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3349.9-3357.12|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3290.7-3359.14" *) _050_ : sbcs_q[22];
assign { resp_queue_inp[33:2], _023_[1:0] } = _119_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.5-3360.8" *) _034_ : 34'h000000000;
assign _024_ = _119_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.5-3360.8" *) _037_ : sbcs_q[22];
assign _018_ = _119_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.5-3360.8" *) _027_ : 1'h0;
assign _019_ = _119_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.5-3360.8" *) _028_ : cmderr_q;
assign sbdata_read_valid_o = _119_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3289.5-3360.8" *) _039_ : 1'h0;
assign haltsum2 = _127_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3143.5-3145.8" *) _172_ : 32'd0;
assign haltsum1 = _126_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3126.5-3128.8" *) _171_ : 32'd0;
assign haltsum0 = _125_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3109.5-3111.8" *) _170_ : 32'd0;
assign _164_ = $signed(_128_) < 0 ? 32'd4294967295 << - _128_ : 32'd4294967295 >> _128_;
assign _165_ = $signed(_128_) < 0 ? dmi_req_i[31:0] << - _128_ : dmi_req_i[31:0] >> _128_;
assign _166_ = $signed(_129_) < 0 ? 1'h1 << - _129_ : 1'h1 >> _129_;
assign _167_ = $signed(_129_) < 0 ? 1'h0 << - _129_ : 1'h0 >> _129_;
assign _168_ = $signed(_130_) < 0 ? 32'd4294967295 << - _130_ : 32'd4294967295 >> _130_;
assign _169_ = $signed(_130_) < 0 ? dmi_req_i[31:0] << - _130_ : dmi_req_i[31:0] >> _130_;
assign _143_ = $signed(_129_) < 0 ? dmcontrol_q[31] << - _129_ : dmcontrol_q[31] >> _129_;
assign _144_ = $signed(_129_) < 0 ? dmcontrol_q[30] << - _129_ : dmcontrol_q[30] >> _129_;
wire [31:0] _430_ = { 31'h00000000, halted_i };
assign _170_ = _430_[$signed({ 12'h000, dmcontrol_q[15:6], dmcontrol_q[25:21], 5'h00 }) +: 32];
wire [31:0] _431_ = { 31'h00000000, halted_i };
assign _171_ = _431_[$signed({ 17'h00000, dmcontrol_q[15:6], 5'h00 }) +: 32];
wire [31:0] _432_ = { 31'h00000000, halted_i };
assign _172_ = _432_[$signed({ 22'h000000, dmcontrol_q[15:11], 5'h00 }) +: 32];
wire [1:0] _433_ = { 1'h0, havereset_q };
assign dmstatus[19] = _433_[dmcontrol_q[16] +: 1];
wire [1:0] _434_ = { 1'h0, resumeack_i };
assign dmstatus[17] = _434_[dmcontrol_q[16] +: 1];
wire [1:0] _435_ = { 1'h0, unavailable_i };
assign dmstatus[13] = _435_[dmcontrol_q[16] +: 1];
wire [1:0] _436_ = { 1'h0, halted_i };
assign _173_ = _436_[dmcontrol_q[16] +: 1];
wire [63:0] _437_ = data_q;
assign _174_ = _437_[$signed({ 23'h000000, autoexecdata_idx, 5'h00 }) +: 32];
wire [31:0] _438_ = abstractauto_q;
assign _175_ = _438_[$signed({ 28'h0000000, autoexecdata_idx }) +: 1];
wire [63:0] _439_ = { 32'h00000000, hartinfo_i };
assign _176_ = _439_[$signed({ 26'h0000000, dmcontrol_q[16], 5'h00 }) +: 32];
wire [255:0] _440_ = progbuf_q;
assign _177_ = _440_[$signed({ 24'h000000, dmi_req_i[36:34], 5'h00 }) +: 32];
wire [31:0] _441_ = abstractauto_q;
assign _178_ = _441_[$signed(_066_) +: 1];
assign { _179_[7:4], autoexecdata_idx } = { 1'h0, dmi_req_i[40:34] } - (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3218.32-3218.59" *) 8'h04;
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:3582.3-3599.5" *)
\$paramod$2ae3818c383ec9e4b5fcbe86cfd2b09270f9b0c9\fifo_v2 i_fifo (
.clk_i(clk_i),
.data_i(resp_queue_inp),
.data_o(dmi_resp_o),
.empty_o(resp_queue_empty),
.flush_i(_139_),
.full_o(resp_queue_full),
.pop_i(resp_queue_pop),
.push_i(resp_queue_push),
.rst_ni(rst_ni),
.testmode_i(testmode_i)
);
assign { _005_[29:26], _005_[5:2], _005_[0] } = { 8'h00, dmcontrol_d[0] };
assign { _021_[31], _021_[25:6], _021_[1:0] } = { dmcontrol_d[31], dmcontrol_d[25:6], dmcontrol_d[1:0] };
assign _022_[1] = havereset_d_aligned[1];
assign _023_[33:2] = resp_queue_inp[33:2];
assign _040_[15:12] = 4'h0;
assign { _056_[28:22], _056_[20:15] } = { sbcs_d[28:22], sbcs_d[20:15] };
assign _058_[1:0] = _055_[1:0];
assign _179_[3:0] = autoexecdata_idx;
assign abstractcs = { 19'h04000, cmdbusy_i, 1'h0, cmderr_q, 8'h02 };
assign cmd_o = command_q;
assign cmd_valid_o = cmd_valid_q;
assign data_o = data_q;
assign dm_csr_addr = { 1'h0, dmi_req_i[40:34] };
assign dmactive_o = dmcontrol_q[0];
assign { dmcontrol_d[29:26], dmcontrol_d[5:2] } = 8'h00;
assign { dmcontrol_q[29:26], dmcontrol_q[5:2] } = 8'h00;
assign { dmstatus[31:20], dmstatus[18], dmstatus[16], dmstatus[14], dmstatus[12], dmstatus[10], dmstatus[8:0] } = { 12'h000, dmstatus[19], dmstatus[17], dmstatus[15], dmstatus[13], dmstatus[11], dmstatus[9], 8'h82 };
assign dtm_op = dmi_req_i[33:32];
assign halted = { 31'h00000000, halted_i };
assign halted_aligned = { 1'h0, halted_i };
assign halted_flat1 = { 31'h00000000, halted_i };
assign halted_flat2 = { 31'h00000000, halted_i };
assign halted_flat3 = { 31'h00000000, halted_i };
assign halted_reshaped0 = { 31'h00000000, halted_i };
assign halted_reshaped1 = { 31'h00000000, halted_i };
assign halted_reshaped2 = { 31'h00000000, halted_i };
assign haltsum3 = { 31'h00000000, halted_i };
assign hartinfo_aligned = { 32'h00000000, hartinfo_i };
assign hartsel_idx0 = { dmcontrol_q[15:6], dmcontrol_q[25:21] };
assign hartsel_idx1 = dmcontrol_q[15:6];
assign hartsel_idx2 = dmcontrol_q[15:11];
assign hartsel_o = { dmcontrol_q[15:6], dmcontrol_q[25:16] };
assign havereset_d_aligned[0] = havereset_d;
assign havereset_q_aligned = { 1'h0, havereset_q };
assign ndmreset_o = dmcontrol_q[1];
assign progbuf_o = progbuf_q;
assign resumeack_aligned = { 1'h0, resumeack_i };
assign sbaccess_o = sbcs_q[19:17];
assign sbaddress_o = sbaddr_q;
assign sbautoincrement_o = sbcs_q[16];
assign { sbcs_d[31:29], sbcs_d[21], sbcs_d[11:0] } = { 3'h1, sbbusy_i, 12'h80f };
assign sbdata_o = sbdata_q;
assign sbreadonaddr_o = sbcs_q[20];
assign sbreadondata_o = sbcs_q[15];
assign selected_hart = dmcontrol_q[16];
assign unavailable_aligned = { 1'h0, unavailable_i };
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1740.1-1812.10" *)
module \$paramod$38ced3394f1fba8e40a3783f4da982c2eea9558c\cdc_2phase_dst_clearable (rst_ni, clk_i, clear_i, valid_o, ready_i, async_req_i, async_ack_o, data_o, async_data_i);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1773.3-1780.6" *)
wire _00_;
wire _01_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1777.18-1777.36" *)
wire _02_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.9-1786.48" *)
wire _03_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.40-1786.48" *)
wire _04_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.9-1786.36" *)
wire _05_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1778.19-1778.29" *)
wire _06_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1757.8-1757.17" *)
wire ack_dst_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1757.19-1757.28" *)
reg ack_dst_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1751.16-1751.27" *)
output async_ack_o;
wire async_ack_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1752.16-1752.28" *)
(* wiretype = "\\dmi_resp_t" *)
input [33:0] async_data_i;
wire [33:0] async_data_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1750.16-1750.27" *)
input async_req_i;
wire async_req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1746.16-1746.23" *)
input clear_i;
wire clear_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1745.16-1745.21" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1759.17-1759.27" *)
(* wiretype = "\\dmi_resp_t" *)
reg [33:0] data_dst_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1747.16-1747.22" *)
(* wiretype = "\\dmi_resp_t" *)
output [33:0] data_o;
wire [33:0] data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1749.16-1749.23" *)
input ready_i;
wire ready_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1757.30-1757.40" *)
wire req_synced;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1757.42-1757.55" *)
reg req_synced_q1;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1744.16-1744.22" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1748.16-1748.23" *)
output valid_o;
wire valid_o;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1791.5-1793.6" *)
always @(posedge clk_i)
if (_03_) data_dst_q <= async_data_i;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1795.3-1805.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) ack_dst_q <= 1'h0;
else if (_01_) ack_dst_q <= ack_dst_d;
assign _01_ = | { _02_, clear_i };
assign _02_ = valid_o && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1777.18-1777.36" *) ready_i;
assign _03_ = _05_ && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.9-1786.48" *) _04_;
assign _04_ = ! (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.40-1786.48" *) valid_o;
assign _05_ = req_synced != (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1786.9-1786.36" *) req_synced_q1;
assign valid_o = ack_dst_q != (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1808.21-1808.47" *) req_synced_q1;
assign _06_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1778.19-1778.29" *) ack_dst_q;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1795.3-1805.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) req_synced_q1 <= 1'h0;
else req_synced_q1 <= req_synced;
assign _00_ = _02_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1777.14-1779.8" *) _06_ : 1'hx;
assign ack_dst_d = clear_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1775.5-1779.8" *) 1'h0 : _00_;
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1763.3-1770.5" *)
\$paramod$f7f58dd6ce736fb4beabd5397d315fdd90d5df9e\sync i_sync (
.clk_i(clk_i),
.rst_ni(rst_ni),
.serial_i(async_req_i),
.serial_o(req_synced)
);
assign async_ack_o = ack_dst_q;
assign data_o = data_dst_q;
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1671.1-1735.10" *)
module \$paramod$38ced3394f1fba8e40a3783f4da982c2eea9558c\cdc_2phase_src_clearable (rst_ni, clk_i, clear_i, valid_i, ready_o, async_req_o, async_ack_i, data_i, async_data_o);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1703.3-1713.6" *)
wire _00_;
wire _01_;
wire _02_;
wire _03_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1709.18-1709.36" *)
wire _04_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1710.20-1710.30" *)
wire _05_;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1687.32-1687.42" *)
wire ack_synced;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1682.16-1682.27" *)
input async_ack_i;
wire async_ack_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1683.16-1683.28" *)
(* wiretype = "\\dmi_resp_t" *)
output [33:0] async_data_o;
wire [33:0] async_data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1681.16-1681.27" *)
output async_req_o;
wire async_req_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1677.16-1677.23" *)
input clear_i;
wire clear_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1676.16-1676.21" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1678.16-1678.22" *)
(* wiretype = "\\dmi_resp_t" *)
input [33:0] data_i;
wire [33:0] data_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1689.17-1689.27" *)
(* wiretype = "\\dmi_resp_t" *)
reg [33:0] data_src_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1680.16-1680.23" *)
output ready_o;
wire ready_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1687.10-1687.19" *)
wire req_src_d;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1687.21-1687.30" *)
reg req_src_q;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1675.16-1675.22" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1679.16-1679.23" *)
input valid_i;
wire valid_i;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1719.3-1725.6" *)
always @(posedge clk_i, negedge rst_ni)
if (!rst_ni) req_src_q <= 1'h0;
else if (_01_) req_src_q <= req_src_d;
(* \always_ff = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1715.5-1717.6" *)
always @(posedge clk_i)
if (_02_) data_src_q <= data_i;
assign _01_ = | { _04_, clear_i };
assign _03_ = ~ clear_i;
assign _02_ = & { _03_, _04_ };
assign ready_o = req_src_q == (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1728.21-1728.44" *) ack_synced;
assign _04_ = valid_i && (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1709.18-1709.36" *) ready_o;
assign _05_ = ~ (* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1710.20-1710.30" *) req_src_q;
assign _00_ = _04_ ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1709.14-1712.8" *) _05_ : 1'hx;
assign req_src_d = clear_i ? (* full_case = 32'd1 *) (* src = "build/baby_iguana_top.pickle.sv:0.0-0.0|/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1706.5-1712.8" *) 1'h0 : _00_;
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:1692.3-1699.5" *)
\$paramod$f7f58dd6ce736fb4beabd5397d315fdd90d5df9e\sync i_sync (
.clk_i(clk_i),
.rst_ni(rst_ni),
.serial_i(async_ack_i),
.serial_o(ack_synced)
);
assign async_data_o = data_src_q;
assign async_req_o = req_src_q;
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4873.1-5083.19" *)
module \$paramod$3cf1bba3ee2aa7c1453982cd2e859db4b0334b1e\dm_top (clk_i, rst_ni, testmode_i, ndmreset_o, dmactive_o, debug_req_o, unavailable_i, slave_req_i, slave_we_i, slave_addr_i, slave_be_i, slave_wdata_i, slave_rdata_o, master_req_o, master_add_o, master_we_o, master_wdata_o, master_be_o, master_gnt_i, master_r_valid_i, master_r_err_i
, master_r_other_err_i, master_r_rdata_i, dmi_rst_ni, dmi_req_valid_i, dmi_req_ready_o, dmi_resp_valid_o, dmi_resp_ready_i, hartinfo_i, dmi_req_i, dmi_resp_o);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4931.37-4931.52" *)
wire clear_resumeack;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4883.33-4883.38" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4933.37-4933.40" *)
(* wiretype = "\\command_t" *)
wire [31:0] cmd;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4932.37-4932.46" *)
wire cmd_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4937.37-4937.44" *)
wire cmdbusy;
(* enum_value_000 = "\\CmdErrNone" *)
(* enum_value_001 = "\\CmdErrBusy" *)
(* enum_value_010 = "\\CmdErrNotSupported" *)
(* enum_value_011 = "\\CmdErrorException" *)
(* enum_value_100 = "\\CmdErrorHaltResume" *)
(* enum_value_101 = "\\CmdErrorBus" *)
(* enum_value_111 = "\\CmdErrorOther" *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4936.37-4936.45" *)
(* wiretype = "\\cmderr_e" *)
wire [2:0] cmderror;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4935.37-4935.51" *)
wire cmderror_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4939.37-4939.50" *)
wire [63:0] data_csrs_mem;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4940.37-4940.50" *)
wire [63:0] data_mem_csrs;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4941.37-4941.47" *)
wire data_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4889.33-4889.44" *)
output debug_req_o;
wire debug_req_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4888.33-4888.43" *)
output dmactive_o;
wire dmactive_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4918.33-4918.42" *)
(* wiretype = "\\dmi_req_t" *)
input [40:0] dmi_req_i;
wire [40:0] dmi_req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4917.33-4917.48" *)
output dmi_req_ready_o;
wire dmi_req_ready_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4916.33-4916.48" *)
input dmi_req_valid_i;
wire dmi_req_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4922.33-4922.43" *)
(* wiretype = "\\dmi_resp_t" *)
output [33:0] dmi_resp_o;
wire [33:0] dmi_resp_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4921.33-4921.49" *)
input dmi_resp_ready_i;
wire dmi_resp_ready_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4920.33-4920.49" *)
output dmi_resp_valid_o;
wire dmi_resp_valid_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4913.33-4913.43" *)
input dmi_rst_ni;
wire dmi_rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4926.37-4926.43" *)
wire halted;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4929.37-4929.44" *)
wire haltreq;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4892.39-4892.49" *)
(* wiretype = "\\hartinfo_t" *)
input [31:0] hartinfo_i;
wire [31:0] hartinfo_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4943.37-4943.44" *)
wire [19:0] hartsel;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4902.33-4902.45" *)
output [63:0] master_add_o;
wire [63:0] master_add_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4905.33-4905.44" *)
output [7:0] master_be_o;
wire [7:0] master_be_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4906.33-4906.45" *)
input master_gnt_i;
wire master_gnt_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4908.33-4908.47" *)
input master_r_err_i;
wire master_r_err_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4909.33-4909.53" *)
input master_r_other_err_i;
wire master_r_other_err_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4910.33-4910.49" *)
input [63:0] master_r_rdata_i;
wire [63:0] master_r_rdata_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4907.33-4907.49" *)
input master_r_valid_i;
wire master_r_valid_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4901.33-4901.45" *)
output master_req_o;
wire master_req_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4904.33-4904.47" *)
output [63:0] master_wdata_o;
wire [63:0] master_wdata_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4903.33-4903.44" *)
output master_we_o;
wire master_we_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4942.37-4942.45" *)
wire ndmreset;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4887.33-4887.43" *)
output ndmreset_o;
wire ndmreset_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4938.37-4938.44" *)
wire [255:0] progbuf;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4928.37-4928.46" *)
wire resumeack;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4930.37-4930.46" *)
wire resumereq;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4885.33-4885.39" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4950.37-4950.45" *)
wire [2:0] sbaccess;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4945.37-4945.55" *)
wire [63:0] sbaddress_csrs_sba;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4946.37-4946.55" *)
wire [63:0] sbaddress_sba_csrs;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4947.37-4947.58" *)
wire sbaddress_write_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4949.37-4949.52" *)
wire sbautoincrement;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4957.37-4957.43" *)
wire sbbusy;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4955.37-4955.48" *)
wire [63:0] sbdata_read;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4953.37-4953.54" *)
wire sbdata_read_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4956.37-4956.49" *)
wire sbdata_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4952.37-4952.49" *)
wire [63:0] sbdata_write;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4954.37-4954.55" *)
wire sbdata_write_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4959.37-4959.44" *)
wire [2:0] sberror;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4958.37-4958.50" *)
wire sberror_valid;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4948.37-4948.49" *)
wire sbreadonaddr;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4951.37-4951.49" *)
wire sbreadondata;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4896.33-4896.45" *)
input [63:0] slave_addr_i;
wire [63:0] slave_addr_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4897.33-4897.43" *)
input [7:0] slave_be_i;
wire [7:0] slave_be_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4899.33-4899.46" *)
output [63:0] slave_rdata_o;
wire [63:0] slave_rdata_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4894.33-4894.44" *)
input slave_req_i;
wire slave_req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4898.33-4898.46" *)
input [63:0] slave_wdata_i;
wire [63:0] slave_wdata_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4895.33-4895.43" *)
input slave_we_i;
wire slave_we_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4886.33-4886.43" *)
input testmode_i;
wire testmode_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4891.33-4891.46" *)
input unavailable_i;
wire unavailable_i;
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:4963.3-5012.5" *)
\$paramod$347fe71c49e01963bcd82bfabe5c4311a43ce920\dm_csrs i_dm_csrs (
.clear_resumeack_o(clear_resumeack),
.clk_i(clk_i),
.cmd_o(cmd),
.cmd_valid_o(cmd_valid),
.cmdbusy_i(cmdbusy),
.cmderror_i(cmderror),
.cmderror_valid_i(cmderror_valid),
.data_i(data_mem_csrs),
.data_o(data_csrs_mem),
.data_valid_i(data_valid),
.dmactive_o(dmactive_o),
.dmi_req_i(dmi_req_i),
.dmi_req_ready_o(dmi_req_ready_o),
.dmi_req_valid_i(dmi_req_valid_i),
.dmi_resp_o(dmi_resp_o),
.dmi_resp_ready_i(dmi_resp_ready_i),
.dmi_resp_valid_o(dmi_resp_valid_o),
.dmi_rst_ni(dmi_rst_ni),
.halted_i(halted),
.haltreq_o(haltreq),
.hartinfo_i(hartinfo_i),
.hartsel_o(hartsel),
.ndmreset_o(ndmreset),
.progbuf_o(progbuf),
.resumeack_i(resumeack),
.resumereq_o(resumereq),
.rst_ni(rst_ni),
.sbaccess_o(sbaccess),
.sbaddress_i(sbaddress_sba_csrs),
.sbaddress_o(sbaddress_csrs_sba),
.sbaddress_write_valid_o(sbaddress_write_valid),
.sbautoincrement_o(sbautoincrement),
.sbbusy_i(sbbusy),
.sbdata_i(sbdata_read),
.sbdata_o(sbdata_write),
.sbdata_read_valid_o(sbdata_read_valid),
.sbdata_valid_i(sbdata_valid),
.sbdata_write_valid_o(sbdata_write_valid),
.sberror_i(sberror),
.sberror_valid_i(sberror_valid),
.sbreadonaddr_o(sbreadonaddr),
.sbreadondata_o(sbreadondata),
.testmode_i(testmode_i),
.unavailable_i(unavailable_i)
);
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:5050.3-5081.5" *)
\$paramod$e22adeaf5eb5338a46d8ba81a9e74d8e3d4962e1\dm_mem i_dm_mem (
.addr_i(slave_addr_i),
.be_i(slave_be_i),
.clear_resumeack_i(clear_resumeack),
.clk_i(clk_i),
.cmd_i(cmd),
.cmd_valid_i(cmd_valid),
.cmdbusy_o(cmdbusy),
.cmderror_o(cmderror),
.cmderror_valid_o(cmderror_valid),
.data_i(data_csrs_mem),
.data_o(data_mem_csrs),
.data_valid_o(data_valid),
.debug_req_o(debug_req_o),
.halted_o(halted),
.haltreq_i(haltreq),
.hartsel_i(hartsel),
.ndmreset_i(ndmreset),
.progbuf_i(progbuf),
.rdata_o(slave_rdata_o),
.req_i(slave_req_i),
.resumereq_i(resumereq),
.resuming_o(resumeack),
.rst_ni(rst_ni),
.wdata_i(slave_wdata_i),
.we_i(slave_we_i)
);
(* module_not_derived = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:5014.3-5048.5" *)
\$paramod$578d4d815db3db7bef3f8d5ed31ac23e3db5d81b\dm_sba i_dm_sba (
.clk_i(clk_i),
.dmactive_i(dmactive_o),
.master_add_o(master_add_o),
.master_be_o(master_be_o),
.master_gnt_i(master_gnt_i),
.master_r_err_i(master_r_err_i),
.master_r_other_err_i(master_r_other_err_i),
.master_r_rdata_i(master_r_rdata_i),
.master_r_valid_i(master_r_valid_i),
.master_req_o(master_req_o),
.master_wdata_o(master_wdata_o),
.master_we_o(master_we_o),
.rst_ni(rst_ni),
.sbaccess_i(sbaccess),
.sbaddress_i(sbaddress_csrs_sba),
.sbaddress_o(sbaddress_sba_csrs),
.sbaddress_write_valid_i(sbaddress_write_valid),
.sbautoincrement_i(sbautoincrement),
.sbbusy_o(sbbusy),
.sbdata_i(sbdata_write),
.sbdata_o(sbdata_read),
.sbdata_read_valid_i(sbdata_read_valid),
.sbdata_valid_o(sbdata_valid),
.sbdata_write_valid_i(sbdata_write_valid),
.sberror_o(sberror),
.sberror_valid_o(sberror_valid),
.sbreadonaddr_i(sbreadonaddr),
.sbreadondata_i(sbreadondata)
);
assign ndmreset_o = ndmreset;
endmodule
(* cells_not_processed = 1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7063.1-11181.10" *)
module \$paramod$4dc9cd64b1a21a9d65f5fcbc72f43abe868eb8aa\cheshire_bootrom (clk_i, rst_ni, req_i, addr_i, data_o);
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7070.34-7070.40" *)
input [15:0] addr_i;
wire [15:0] addr_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7067.34-7067.39" *)
input clk_i;
wire clk_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7071.34-7071.40" *)
output [31:0] data_o;
wire [31:0] data_o;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7069.34-7069.39" *)
input req_i;
wire req_i;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7068.34-7068.40" *)
input rst_ni;
wire rst_ni;
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7074.34-7074.38" *)
wire [11:0] word;
(* full_case = 32'd1 *)
(* src = "/home/janniss/Documents/iguana/build/baby_iguana_top.pickle.sv:7080.9-11178.16" *)
reg [31:0] \$auto$proc_rom.cc:150:do_switch$987 [4095:0];
initial begin
\$auto$proc_rom.cc:150:do_switch$987 [0] = 32'd1862402327;
\$auto$proc_rom.cc:150:do_switch$987 [1] = 32'd4286644499;
\$auto$proc_rom.cc:150:do_switch$987 [2] = 32'd8599;
\$auto$proc_rom.cc:150:do_switch$987 [3] = 32'd1392607635;
\$auto$proc_rom.cc:150:do_switch$987 [4] = 32'd1107378305;
\$auto$proc_rom.cc:150:do_switch$987 [5] = 32'd1124156033;
\$auto$proc_rom.cc:150:do_switch$987 [6] = 32'd1140933505;
\$auto$proc_rom.cc:150:do_switch$987 [7] = 32'd1157710977;
\$auto$proc_rom.cc:150:do_switch$987 [8] = 32'd1174488449;
\$auto$proc_rom.cc:150:do_switch$987 [9] = 32'd1191265921;
\$auto$proc_rom.cc:150:do_switch$987 [10] = 32'd1208043393;
\$auto$proc_rom.cc:150:do_switch$987 [11] = 32'd1224820865;
\$auto$proc_rom.cc:150:do_switch$987 [12] = 32'd1241598337;
\$auto$proc_rom.cc:150:do_switch$987 [13] = 32'd1258375809;
\$auto$proc_rom.cc:150:do_switch$987 [14] = 32'd1275153281;
\$auto$proc_rom.cc:150:do_switch$987 [15] = 32'd1291930753;
\$auto$proc_rom.cc:150:do_switch$987 [16] = 32'd1308708225;
\$auto$proc_rom.cc:150:do_switch$987 [17] = 32'd1325485697;
\$auto$proc_rom.cc:150:do_switch$987 [18] = 32'd16781975;
\$auto$proc_rom.cc:150:do_switch$987 [19] = 32'd4219634323;
\$auto$proc_rom.cc:150:do_switch$987 [20] = 32'd2686669693;
\$auto$proc_rom.cc:150:do_switch$987 [21] = 32'd2720202850;
\$auto$proc_rom.cc:150:do_switch$987 [22] = 32'd1124401250;
\$auto$proc_rom.cc:150:do_switch$987 [23] = 32'd6465571;
\$auto$proc_rom.cc:150:do_switch$987 [24] = 32'd1124156033;
\$auto$proc_rom.cc:150:do_switch$987 [25] = 32'd4111;
\$auto$proc_rom.cc:150:do_switch$987 [26] = 32'd333447407;
\$auto$proc_rom.cc:150:do_switch$987 [27] = 32'd84320265;
\$auto$proc_rom.cc:150:do_switch$987 [28] = 32'd1402131;
\$auto$proc_rom.cc:150:do_switch$987 [29] = 32'd16777879;
\$auto$proc_rom.cc:150:do_switch$987 [30] = 32'd4173496979;
\$auto$proc_rom.cc:150:do_switch$987 [31] = 32'd10658339;
\$auto$proc_rom.cc:150:do_switch$987 [32] = 32'd273678451;
\$auto$proc_rom.cc:150:do_switch$987 [33] = 32'd289521653;
\$auto$proc_rom.cc:150:do_switch$987 [34] = 32'd3760382982;
\$auto$proc_rom.cc:150:do_switch$987 [35] = 32'd15696938;
\$auto$proc_rom.cc:150:do_switch$987 [36] = 32'd2242518208;
\$auto$proc_rom.cc:150:do_switch$987 [37] = 32'd3154216211;
\$auto$proc_rom.cc:150:do_switch$987 [38] = 32'd562041071;
\$auto$proc_rom.cc:150:do_switch$987 [39] = 32'd15697186;
\$auto$proc_rom.cc:150:do_switch$987 [40] = 32'd2242517280;
\$auto$proc_rom.cc:150:do_switch$987 [41] = 32'd3204547859;
\$auto$proc_rom.cc:150:do_switch$987 [42] = 32'd545263855;
\$auto$proc_rom.cc:150:do_switch$987 [43] = 32'd15697186;
\$auto$proc_rom.cc:150:do_switch$987 [44] = 32'd2242517472;
\$auto$proc_rom.cc:150:do_switch$987 [45] = 32'd3254879507;
\$auto$proc_rom.cc:150:do_switch$987 [46] = 32'd528486639;
\$auto$proc_rom.cc:150:do_switch$987 [47] = 32'd15697186;
\$auto$proc_rom.cc:150:do_switch$987 [48] = 32'd2242516992;
\$auto$proc_rom.cc:150:do_switch$987 [49] = 32'd3305211155;
\$auto$proc_rom.cc:150:do_switch$987 [50] = 32'd511709423;
\$auto$proc_rom.cc:150:do_switch$987 [51] = 32'd15697186;
\$auto$proc_rom.cc:150:do_switch$987 [52] = 32'd1677858112;
\$auto$proc_rom.cc:150:do_switch$987 [53] = 32'd2242535586;
\$auto$proc_rom.cc:150:do_switch$987 [54] = 32'd3355542803;
\$auto$proc_rom.cc:150:do_switch$987 [55] = 32'd275710273;
\$auto$proc_rom.cc:150:do_switch$987 [56] = 32'd1899568416;
\$auto$proc_rom.cc:150:do_switch$987 [57] = 32'd1444644266;
\$auto$proc_rom.cc:150:do_switch$987 [58] = 32'd1429667861;
\$auto$proc_rom.cc:150:do_switch$987 [59] = 32'd3408384;
\$auto$proc_rom.cc:150:do_switch$987 [60] = 32'd328979;
\$auto$proc_rom.cc:150:do_switch$987 [61] = 32'd4163042310;
\$auto$proc_rom.cc:150:do_switch$987 [62] = 32'd3221419046;
\$auto$proc_rom.cc:150:do_switch$987 [63] = 32'd284148226;
\$auto$proc_rom.cc:150:do_switch$987 [64] = 32'd2649888;
\$auto$proc_rom.cc:150:do_switch$987 [65] = 32'd1904218351;
\$auto$proc_rom.cc:150:do_switch$987 [66] = 32'd402871;
\$auto$proc_rom.cc:150:do_switch$987 [67] = 32'd2818934163;
\$auto$proc_rom.cc:150:do_switch$987 [68] = 32'd284098600;
\$auto$proc_rom.cc:150:do_switch$987 [69] = 32'd1166082864;
\$auto$proc_rom.cc:150:do_switch$987 [70] = 32'd284098600;
\$auto$proc_rom.cc:150:do_switch$987 [71] = 32'd2623248;
\$auto$proc_rom.cc:150:do_switch$987 [72] = 32'd1072697583;
\$auto$proc_rom.cc:150:do_switch$987 [73] = 32'd3317169517;
\$auto$proc_rom.cc:150:do_switch$987 [74] = 32'd2241003710;
\$auto$proc_rom.cc:150:do_switch$987 [75] = 32'd2671109;
\$auto$proc_rom.cc:150:do_switch$987 [76] = 32'd22024431;
\$auto$proc_rom.cc:150:do_switch$987 [77] = 32'd284098600;
\$auto$proc_rom.cc:150:do_switch$987 [78] = 32'd2248804144;
\$auto$proc_rom.cc:150:do_switch$987 [79] = 32'd2639233;
\$auto$proc_rom.cc:150:do_switch$987 [80] = 32'd506466543;
\$auto$proc_rom.cc:150:do_switch$987 [81] = 32'd1166344272;
\$auto$proc_rom.cc:150:do_switch$987 [82] = 32'd284098600;
\$auto$proc_rom.cc:150:do_switch$987 [83] = 32'd1166155152;
\$auto$proc_rom.cc:150:do_switch$987 [84] = 32'd1879049399;
\$auto$proc_rom.cc:150:do_switch$987 [85] = 32'd296467;
\$auto$proc_rom.cc:150:do_switch$987 [86] = 32'd2639521;
\$auto$proc_rom.cc:150:do_switch$987 [87] = 32'd1460670703;
\$auto$proc_rom.cc:150:do_switch$987 [88] = 32'd296339;
\$auto$proc_rom.cc:150:do_switch$987 [89] = 32'd3405874451;
\$auto$proc_rom.cc:150:do_switch$987 [90] = 32'd343937263;
\$auto$proc_rom.cc:150:do_switch$987 [91] = 32'd1141196178;
\$auto$proc_rom.cc:150:do_switch$987 [92] = 32'd2257806985;
\$auto$proc_rom.cc:150:do_switch$987 [93] = 32'd370376710;
\$auto$proc_rom.cc:150:do_switch$987 [94] = 32'd2621940;
\$auto$proc_rom.cc:150:do_switch$987 [95] = 32'd1427116271;
\$auto$proc_rom.cc:150:do_switch$987 [96] = 32'd32773523;
\$auto$proc_rom.cc:150:do_switch$987 [97] = 32'd3439428883;
\$auto$proc_rom.cc:150:do_switch$987 [98] = 32'd310382831;
\$auto$proc_rom.cc:150:do_switch$987 [99] = 32'd4111;
\$auto$proc_rom.cc:150:do_switch$987 [100] = 32'd75384321;
\$auto$proc_rom.cc:150:do_switch$987 [101] = 32'd296339;
\$auto$proc_rom.cc:150:do_switch$987 [102] = 32'd2483176705;
\$auto$proc_rom.cc:150:do_switch$987 [103] = 32'd1950511330;
\$auto$proc_rom.cc:150:do_switch$987 [104] = 32'd1629582498;
\$auto$proc_rom.cc:150:do_switch$987 [105] = 32'd289505410;
\$auto$proc_rom.cc:150:do_switch$987 [106] = 32'd70770722;
\$auto$proc_rom.cc:150:do_switch$987 [107] = 32'd68354560;
\$auto$proc_rom.cc:150:do_switch$987 [108] = 32'd1409810436;
\$auto$proc_rom.cc:150:do_switch$987 [109] = 32'd2241029617;
\$auto$proc_rom.cc:150:do_switch$987 [110] = 32'd3825606661;
\$auto$proc_rom.cc:150:do_switch$987 [111] = 32'd341840111;
\$auto$proc_rom.cc:150:do_switch$987 [112] = 32'd33559863;
\$auto$proc_rom.cc:150:do_switch$987 [113] = 32'd328979;
\$auto$proc_rom.cc:150:do_switch$987 [114] = 32'd3959419119;
\$auto$proc_rom.cc:150:do_switch$987 [115] = 32'd1191790676;
\$auto$proc_rom.cc:150:do_switch$987 [116] = 32'd48662115;
\$auto$proc_rom.cc:150:do_switch$987 [117] = 32'd427931;
\$auto$proc_rom.cc:150:do_switch$987 [118] = 32'd16214627;
\$auto$proc_rom.cc:150:do_switch$987 [119] = 32'd2232667037;
\$auto$proc_rom.cc:150:do_switch$987 [120] = 32'd284152193;
\$auto$proc_rom.cc:150:do_switch$987 [121] = 32'd7539936;
\$auto$proc_rom.cc:150:do_switch$987 [122] = 32'd3220508752;
\$auto$proc_rom.cc:150:do_switch$987 [123] = 32'd2623751949;
\$auto$proc_rom.cc:150:do_switch$987 [124] = 32'd2232615143;
\$auto$proc_rom.cc:150:do_switch$987 [125] = 32'd284153217;
\$auto$proc_rom.cc:150:do_switch$987 [126] = 32'd3086289824;
\$auto$proc_rom.cc:150:do_switch$987 [127] = 32'd3548480787;
\$auto$proc_rom.cc:150:do_switch$987 [128] = 32'd184553711;
\$auto$proc_rom.cc:150:do_switch$987 [129] = 32'd1212987341;
\$auto$proc_rom.cc:150:do_switch$987 [130] = 32'd3615589651;
\$auto$proc_rom.cc:150:do_switch$987 [131] = 32'd171970799;
\$auto$proc_rom.cc:150:do_switch$987 [132] = 32'd2232664025;
\$auto$proc_rom.cc:150:do_switch$987 [133] = 32'd284151553;
\$auto$proc_rom.cc:150:do_switch$987 [134] = 32'd1409812896;
\$auto$proc_rom.cc:150:do_switch$987 [135] = 32'd3967807727;
\$auto$proc_rom.cc:150:do_switch$987 [136] = 32'd1365030873;
\$auto$proc_rom.cc:150:do_switch$987 [137] = 32'd394416392;
\$auto$proc_rom.cc:150:do_switch$987 [138] = 32'd2432767234;
\$auto$proc_rom.cc:150:do_switch$987 [139] = 32'd2156039517;
\$auto$proc_rom.cc:150:do_switch$987 [140] = 32'd1426609500;
\$auto$proc_rom.cc:150:do_switch$987 [141] = 32'd352458626;
\$auto$proc_rom.cc:150:do_switch$987 [142] = 32'd2371719425;
\$auto$proc_rom.cc:150:do_switch$987 [143] = 32'd1499234434;
\$auto$proc_rom.cc:150:do_switch$987 [144] = 32'd394418440;
\$auto$proc_rom.cc:150:do_switch$987 [145] = 32'd2432767234;
\$auto$proc_rom.cc:150:do_switch$987 [146] = 32'd2156039517;
\$auto$proc_rom.cc:150:do_switch$987 [147] = 32'd1560829276;
\$auto$proc_rom.cc:150:do_switch$987 [148] = 32'd352458626;
\$auto$proc_rom.cc:150:do_switch$987 [149] = 32'd2371719425;
\$auto$proc_rom.cc:150:do_switch$987 [150] = 32'd1098678402;
\$auto$proc_rom.cc:150:do_switch$987 [151] = 32'd394412328;
\$auto$proc_rom.cc:150:do_switch$987 [152] = 32'd2432767234;
\$auto$proc_rom.cc:150:do_switch$987 [153] = 32'd2156039517;
\$auto$proc_rom.cc:150:do_switch$987 [154] = 32'd1897758850;
\$auto$proc_rom.cc:150:do_switch$987 [155] = 32'd3771393190;
\$auto$proc_rom.cc:150:do_switch$987 [156] = 32'd4166188110;
\$auto$proc_rom.cc:150:do_switch$987 [157] = 32'd4032492630;
\$auto$proc_rom.cc:150:do_switch$987 [158] = 32'd3898772146;
\$auto$proc_rom.cc:150:do_switch$987 [159] = 32'd3765101670;
\$auto$proc_rom.cc:150:do_switch$987 [160] = 32'd3902991494;
\$auto$proc_rom.cc:150:do_switch$987 [161] = 32'd4128500830;
\$auto$proc_rom.cc:150:do_switch$987 [162] = 32'd2361786424;
\$auto$proc_rom.cc:150:do_switch$987 [163] = 32'd2309916970;
\$auto$proc_rom.cc:150:do_switch$987 [164] = 32'd2335869494;
\$auto$proc_rom.cc:150:do_switch$987 [165] = 32'd2353171774;
\$auto$proc_rom.cc:150:do_switch$987 [166] = 32'd3793585366;
\$auto$proc_rom.cc:150:do_switch$987 [167] = 32'd34084755;
\$auto$proc_rom.cc:150:do_switch$987 [168] = 32'd2226361217;
\$auto$proc_rom.cc:150:do_switch$987 [169] = 32'd2497069479;
\$auto$proc_rom.cc:150:do_switch$987 [170] = 32'd1885570134;
\$auto$proc_rom.cc:150:do_switch$987 [171] = 32'd2250377469;
\$auto$proc_rom.cc:150:do_switch$987 [172] = 32'd67471058;
\$auto$proc_rom.cc:150:do_switch$987 [173] = 32'd85165518;
\$auto$proc_rom.cc:150:do_switch$987 [174] = 32'd2567045632;
\$auto$proc_rom.cc:150:do_switch$987 [175] = 32'd4271118819;
\$auto$proc_rom.cc:150:do_switch$987 [176] = 32'd27984947;
\$auto$proc_rom.cc:150:do_switch$987 [177] = 32'd8686515;
\$auto$proc_rom.cc:150:do_switch$987 [178] = 32'd855395;
\$auto$proc_rom.cc:150:do_switch$987 [179] = 32'd4294198531;
\$auto$proc_rom.cc:150:do_switch$987 [180] = 32'd1082885683;
\$auto$proc_rom.cc:150:do_switch$987 [181] = 32'd343770834;
\$auto$proc_rom.cc:150:do_switch$987 [182] = 32'd2567079374;
\$auto$proc_rom.cc:150:do_switch$987 [183] = 32'd4270528739;
\$auto$proc_rom.cc:150:do_switch$987 [184] = 32'd4237530346;
\$auto$proc_rom.cc:150:do_switch$987 [185] = 32'd2204303404;
\$auto$proc_rom.cc:150:do_switch$987 [186] = 32'd469893644;
\$auto$proc_rom.cc:150:do_switch$987 [187] = 32'd1096059571;
\$auto$proc_rom.cc:150:do_switch$987 [188] = 32'd34364435;
\$auto$proc_rom.cc:150:do_switch$987 [189] = 32'd25885795;
\$auto$proc_rom.cc:150:do_switch$987 [190] = 32'd176522790;
\$auto$proc_rom.cc:150:do_switch$987 [191] = 32'd2244904658;
\$auto$proc_rom.cc:150:do_switch$987 [192] = 32'd33555731;
\$auto$proc_rom.cc:150:do_switch$987 [193] = 32'd2567046277;
\$auto$proc_rom.cc:150:do_switch$987 [194] = 32'd4287293667;
\$auto$proc_rom.cc:150:do_switch$987 [195] = 32'd1682333926;
\$auto$proc_rom.cc:150:do_switch$987 [196] = 32'd2044881158;
\$auto$proc_rom.cc:150:do_switch$987 [197] = 32'd2057468482;
\$auto$proc_rom.cc:150:do_switch$987 [198] = 32'd1810004738;
\$auto$proc_rom.cc:150:do_switch$987 [199] = 32'd1822583874;
\$auto$proc_rom.cc:150:do_switch$987 [200] = 32'd2233888002;
\$auto$proc_rom.cc:150:do_switch$987 [201] = 32'd1629840550;
\$auto$proc_rom.cc:150:do_switch$987 [202] = 32'd2228650114;
\$auto$proc_rom.cc:150:do_switch$987 [203] = 32'd1901969233;
\$auto$proc_rom.cc:150:do_switch$987 [204] = 32'd1088873606;
\$auto$proc_rom.cc:150:do_switch$987 [205] = 32'd4098817062;
\$auto$proc_rom.cc:150:do_switch$987 [206] = 32'd4165656738;
\$auto$proc_rom.cc:150:do_switch$987 [207] = 32'd2386202306;
\$auto$proc_rom.cc:150:do_switch$987 [208] = 32'd2227062854;
\$auto$proc_rom.cc:150:do_switch$987 [209] = 32'd1073805715;
\$auto$proc_rom.cc:150:do_switch$987 [210] = 32'd2298931029;
\$auto$proc_rom.cc:150:do_switch$987 [211] = 32'd4277203091;
\$auto$proc_rom.cc:150:do_switch$987 [212] = 32'd168402019;
\$auto$proc_rom.cc:150:do_switch$987 [213] = 32'd33617811;
\$auto$proc_rom.cc:150:do_switch$987 [214] = 32'd43206913;
\$auto$proc_rom.cc:150:do_switch$987 [215] = 32'd3822388752;
\$auto$proc_rom.cc:150:do_switch$987 [216] = 32'd2265597825;
\$auto$proc_rom.cc:150:do_switch$987 [217] = 32'd853099429;
\$auto$proc_rom.cc:150:do_switch$987 [218] = 32'd33555475;
\$auto$proc_rom.cc:150:do_switch$987 [219] = 32'd2321784865;
\$auto$proc_rom.cc:150:do_switch$987 [220] = 32'd2384069255;
\$auto$proc_rom.cc:150:do_switch$987 [221] = 32'd64913203;
\$auto$proc_rom.cc:150:do_switch$987 [222] = 32'd268399379;
\$auto$proc_rom.cc:150:do_switch$987 [223] = 32'd50532251;
\$auto$proc_rom.cc:150:do_switch$987 [224] = 32'd6456123;
\$auto$proc_rom.cc:150:do_switch$987 [225] = 32'd267612947;
\$auto$proc_rom.cc:150:do_switch$987 [226] = 32'd31712355;
\$auto$proc_rom.cc:150:do_switch$987 [227] = 32'd268432147;
\$auto$proc_rom.cc:150:do_switch$987 [228] = 32'd255002501;
\$auto$proc_rom.cc:150:do_switch$987 [229] = 32'd262340855;
\$auto$proc_rom.cc:150:do_switch$987 [230] = 32'd1395916399;
\$auto$proc_rom.cc:150:do_switch$987 [231] = 32'd2028143582;
\$auto$proc_rom.cc:150:do_switch$987 [232] = 32'd4078173662;
\$auto$proc_rom.cc:150:do_switch$987 [233] = 32'd123928608;
\$auto$proc_rom.cc:150:do_switch$987 [234] = 32'd241370627;
\$auto$proc_rom.cc:150:do_switch$987 [235] = 32'd2539851785;
\$auto$proc_rom.cc:150:do_switch$987 [236] = 32'd3957919241;
\$auto$proc_rom.cc:150:do_switch$987 [237] = 32'd2221098945;
\$auto$proc_rom.cc:150:do_switch$987 [238] = 32'd1200169214;
\$auto$proc_rom.cc:150:do_switch$987 [239] = 32'd587104355;
\$auto$proc_rom.cc:150:do_switch$987 [240] = 32'd50333587;
\$auto$proc_rom.cc:150:do_switch$987 [241] = 32'd15794211;
\$auto$proc_rom.cc:150:do_switch$987 [242] = 32'd2338539397;
\$auto$proc_rom.cc:150:do_switch$987 [243] = 32'd2215842308;
\$auto$proc_rom.cc:150:do_switch$987 [244] = 32'd145949191;
\$auto$proc_rom.cc:150:do_switch$987 [245] = 32'd51576868;
\$auto$proc_rom.cc:150:do_switch$987 [246] = 32'd2149778128;
\$auto$proc_rom.cc:150:do_switch$987 [247] = 32'd126221928;
\$auto$proc_rom.cc:150:do_switch$987 [248] = 32'd4042229894;
\$auto$proc_rom.cc:150:do_switch$987 [249] = 32'd1621551263;
\$auto$proc_rom.cc:150:do_switch$987 [250] = 32'd1960993798;
\$auto$proc_rom.cc:150:do_switch$987 [251] = 32'd2040691010;
\$auto$proc_rom.cc:150:do_switch$987 [252] = 32'd2156028257;
\$auto$proc_rom.cc:150:do_switch$987 [253] = 32'd33617811;
\$auto$proc_rom.cc:150:do_switch$987 [254] = 32'd16840979;
\$auto$proc_rom.cc:150:do_switch$987 [255] = 32'd101712531;
\$auto$proc_rom.cc:150:do_switch$987 [256] = 32'd43242405;
\$auto$proc_rom.cc:150:do_switch$987 [257] = 32'd3215524880;
\$auto$proc_rom.cc:150:do_switch$987 [258] = 32'd2717971;
\$auto$proc_rom.cc:150:do_switch$987 [259] = 32'd2265597825;
\$auto$proc_rom.cc:150:do_switch$987 [260] = 32'd4194901475;
\$auto$proc_rom.cc:150:do_switch$987 [261] = 32'd34119187;
\$auto$proc_rom.cc:150:do_switch$987 [262] = 32'd34496019;
\$auto$proc_rom.cc:150:do_switch$987 [263] = 32'd4069753606;
\$auto$proc_rom.cc:150:do_switch$987 [264] = 32'd425918480;
\$auto$proc_rom.cc:150:do_switch$987 [265] = 32'd4100131336;
\$auto$proc_rom.cc:150:do_switch$987 [266] = 32'd51577799;
\$auto$proc_rom.cc:150:do_switch$987 [267] = 32'd2153972224;
\$auto$proc_rom.cc:150:do_switch$987 [268] = 32'd252904039;
\$auto$proc_rom.cc:150:do_switch$987 [269] = 32'd261292800;
\$auto$proc_rom.cc:150:do_switch$987 [270] = 32'd2685993472;
\$auto$proc_rom.cc:150:do_switch$987 [271] = 32'd32999779;
\$auto$proc_rom.cc:150:do_switch$987 [272] = 32'd53675909;
\$auto$proc_rom.cc:150:do_switch$987 [273] = 32'd262340855;
\$auto$proc_rom.cc:150:do_switch$987 [274] = 32'd3924033507;
\$auto$proc_rom.cc:150:do_switch$987 [275] = 32'd2397306823;
\$auto$proc_rom.cc:150:do_switch$987 [276] = 32'd521401346;
\$auto$proc_rom.cc:150:do_switch$987 [277] = 32'd1595081224;
\$auto$proc_rom.cc:150:do_switch$987 [278] = 32'd4175626767;
\$auto$proc_rom.cc:150:do_switch$987 [279] = 32'd51639783;
\$auto$proc_rom.cc:150:do_switch$987 [280] = 32'd261292544;
\$auto$proc_rom.cc:150:do_switch$987 [281] = 32'd43188992;
\$auto$proc_rom.cc:150:do_switch$987 [282] = 32'd2506293760;
\$auto$proc_rom.cc:150:do_switch$987 [283] = 32'd2689663079;
\$auto$proc_rom.cc:150:do_switch$987 [284] = 32'd139952483;
\$auto$proc_rom.cc:150:do_switch$987 [285] = 32'd53675909;
\$auto$proc_rom.cc:150:do_switch$987 [286] = 32'd262340855;
\$auto$proc_rom.cc:150:do_switch$987 [287] = 32'd2581856243;
\$auto$proc_rom.cc:150:do_switch$987 [288] = 32'd3072720871;
\$auto$proc_rom.cc:150:do_switch$987 [289] = 32'd34119187;
\$auto$proc_rom.cc:150:do_switch$987 [290] = 32'd34496019;
\$auto$proc_rom.cc:150:do_switch$987 [291] = 32'd217975651;
\$auto$proc_rom.cc:150:do_switch$987 [292] = 32'd34085011;
\$auto$proc_rom.cc:150:do_switch$987 [293] = 32'd34134163;
\$auto$proc_rom.cc:150:do_switch$987 [294] = 32'd217613667;
\$auto$proc_rom.cc:150:do_switch$987 [295] = 32'd2187544769;
\$auto$proc_rom.cc:150:do_switch$987 [296] = 32'd1216941854;
\$auto$proc_rom.cc:150:do_switch$987 [297] = 32'd186549603;
\$auto$proc_rom.cc:150:do_switch$987 [298] = 32'd33556627;
\$auto$proc_rom.cc:150:do_switch$987 [299] = 32'd4078406371;
\$auto$proc_rom.cc:150:do_switch$987 [300] = 32'd2274592958;
\$auto$proc_rom.cc:150:do_switch$987 [301] = 32'd2201158152;
\$auto$proc_rom.cc:150:do_switch$987 [302] = 32'd2274557991;
\$auto$proc_rom.cc:150:do_switch$987 [303] = 32'd143851544;
\$auto$proc_rom.cc:150:do_switch$987 [304] = 32'd2294528;
\$auto$proc_rom.cc:150:do_switch$987 [305] = 32'd143916819;
\$auto$proc_rom.cc:150:do_switch$987 [306] = 32'd2430796288;
\$auto$proc_rom.cc:150:do_switch$987 [307] = 32'd127136023;
\$auto$proc_rom.cc:150:do_switch$987 [308] = 32'd3073966592;
\$auto$proc_rom.cc:150:do_switch$987 [309] = 32'd67274851;
\$auto$proc_rom.cc:150:do_switch$987 [310] = 32'd1930682585;
\$auto$proc_rom.cc:150:do_switch$987 [311] = 32'd274923715;
\$auto$proc_rom.cc:150:do_switch$987 [312] = 32'd4175628291;
\$auto$proc_rom.cc:150:do_switch$987 [313] = 32'd51640263;
\$auto$proc_rom.cc:150:do_switch$987 [314] = 32'd2497905152;
\$auto$proc_rom.cc:150:do_switch$987 [315] = 32'd4276352103;
\$auto$proc_rom.cc:150:do_switch$987 [316] = 32'd249817863;
\$auto$proc_rom.cc:150:do_switch$987 [317] = 32'd127138825;
\$auto$proc_rom.cc:150:do_switch$987 [318] = 32'd2313355776;
\$auto$proc_rom.cc:150:do_switch$987 [319] = 32'd3212441609;
\$auto$proc_rom.cc:150:do_switch$987 [320] = 32'd4257939;
\$auto$proc_rom.cc:150:do_switch$987 [321] = 32'd34118499;
\$auto$proc_rom.cc:150:do_switch$987 [322] = 32'd8452243;
\$auto$proc_rom.cc:150:do_switch$987 [323] = 32'd3959982819;
\$auto$proc_rom.cc:150:do_switch$987 [324] = 32'd34046995;
\$auto$proc_rom.cc:150:do_switch$987 [325] = 32'd2361523;
\$auto$proc_rom.cc:150:do_switch$987 [326] = 32'd33555219;
\$auto$proc_rom.cc:150:do_switch$987 [327] = 32'd4268261411;
\$auto$proc_rom.cc:150:do_switch$987 [328] = 32'd3179087749;
\$auto$proc_rom.cc:150:do_switch$987 [329] = 32'd3922195427;
\$auto$proc_rom.cc:150:do_switch$987 [330] = 32'd33555219;
\$auto$proc_rom.cc:150:do_switch$987 [331] = 32'd4033319907;
\$auto$proc_rom.cc:150:do_switch$987 [332] = 32'd3859357667;
\$auto$proc_rom.cc:150:do_switch$987 [333] = 32'd33556371;
\$auto$proc_rom.cc:150:do_switch$987 [334] = 32'd2215884133;
\$auto$proc_rom.cc:150:do_switch$987 [335] = 32'd145949191;
\$auto$proc_rom.cc:150:do_switch$987 [336] = 32'd51576868;
\$auto$proc_rom.cc:150:do_switch$987 [337] = 32'd2149778096;
\$auto$proc_rom.cc:150:do_switch$987 [338] = 32'd126221928;
\$auto$proc_rom.cc:150:do_switch$987 [339] = 32'd143899985;
\$auto$proc_rom.cc:150:do_switch$987 [340] = 32'd2279801344;
\$auto$proc_rom.cc:150:do_switch$987 [341] = 32'd146008343;
\$auto$proc_rom.cc:150:do_switch$987 [342] = 32'd126157047;
\$auto$proc_rom.cc:150:do_switch$987 [343] = 32'd947759153;
\$auto$proc_rom.cc:150:do_switch$987 [344] = 32'd2291382089;
\$auto$proc_rom.cc:150:do_switch$987 [345] = 32'd2279866359;
\$auto$proc_rom.cc:150:do_switch$987 [346] = 32'd1128391688;
\$auto$proc_rom.cc:150:do_switch$987 [347] = 32'd107908707;
\$auto$proc_rom.cc:150:do_switch$987 [348] = 32'd2430812937;
\$auto$proc_rom.cc:150:do_switch$987 [349] = 32'd2562389102;
\$auto$proc_rom.cc:150:do_switch$987 [350] = 32'd102761235;
\$auto$proc_rom.cc:150:do_switch$987 [351] = 32'd6848547;
\$auto$proc_rom.cc:150:do_switch$987 [352] = 32'd4170430245;
\$auto$proc_rom.cc:150:do_switch$987 [353] = 32'd2657288704;
\$auto$proc_rom.cc:150:do_switch$987 [354] = 32'd143851528;
\$auto$proc_rom.cc:150:do_switch$987 [355] = 32'd2313355776;
\$auto$proc_rom.cc:150:do_switch$987 [356] = 32'd53732631;
\$auto$proc_rom.cc:150:do_switch$987 [357] = 32'd126157047;
\$auto$proc_rom.cc:150:do_switch$987 [358] = 32'd125831315;
\$auto$proc_rom.cc:150:do_switch$987 [359] = 32'd18022435;
\$auto$proc_rom.cc:150:do_switch$987 [360] = 32'd143898401;
\$auto$proc_rom.cc:150:do_switch$987 [361] = 32'd2380464640;
\$auto$proc_rom.cc:150:do_switch$987 [362] = 32'd2215895831;
\$auto$proc_rom.cc:150:do_switch$987 [363] = 32'd145949191;
\$auto$proc_rom.cc:150:do_switch$987 [364] = 32'd51576868;
\$auto$proc_rom.cc:150:do_switch$987 [365] = 32'd2149778816;
\$auto$proc_rom.cc:150:do_switch$987 [366] = 32'd126221928;
\$auto$proc_rom.cc:150:do_switch$987 [367] = 32'd4153652725;
\$auto$proc_rom.cc:150:do_switch$987 [368] = 32'd3885564416;
\$auto$proc_rom.cc:150:do_switch$987 [369] = 32'd125831059;
\$auto$proc_rom.cc:150:do_switch$987 [370] = 32'd15794211;
\$auto$proc_rom.cc:150:do_switch$987 [371] = 32'd3050653829;
\$auto$proc_rom.cc:150:do_switch$987 [372] = 32'd92276627;
\$auto$proc_rom.cc:150:do_switch$987 [373] = 32'd15794211;
\$auto$proc_rom.cc:150:do_switch$987 [374] = 32'd3185657989;
\$auto$proc_rom.cc:150:do_switch$987 [375] = 32'd102762387;
\$auto$proc_rom.cc:150:do_switch$987 [376] = 32'd15794211;
\$auto$proc_rom.cc:150:do_switch$987 [377] = 32'd3052488837;
\$auto$proc_rom.cc:150:do_switch$987 [378] = 32'd33616659;
\$auto$proc_rom.cc:150:do_switch$987 [379] = 32'd518199289;
\$auto$proc_rom.cc:150:do_switch$987 [380] = 32'd53737987;
\$auto$proc_rom.cc:150:do_switch$987 [381] = 32'd2277900535;
\$auto$proc_rom.cc:150:do_switch$987 [382] = 32'd684963653;
\$auto$proc_rom.cc:150:do_switch$987 [383] = 32'd1901699749;
\$auto$proc_rom.cc:150:do_switch$987 [384] = 32'd3970363554;
\$auto$proc_rom.cc:150:do_switch$987 [385] = 32'd3838765258;
\$auto$proc_rom.cc:150:do_switch$987 [386] = 32'd4233552082;
\$auto$proc_rom.cc:150:do_switch$987 [387] = 32'd4166710406;
\$auto$proc_rom.cc:150:do_switch$987 [388] = 32'd4033016926;
\$auto$proc_rom.cc:150:do_switch$987 [389] = 32'd2309680230;
\$auto$proc_rom.cc:150:do_switch$987 [390] = 32'd2217904686;
\$auto$proc_rom.cc:150:do_switch$987 [391] = 32'd2302577334;
\$auto$proc_rom.cc:150:do_switch$987 [392] = 32'd2372109506;
\$auto$proc_rom.cc:150:do_switch$987 [393] = 32'd664217096;
\$auto$proc_rom.cc:150:do_switch$987 [394] = 32'd3079077888;
\$auto$proc_rom.cc:150:do_switch$987 [395] = 32'd2547198503;
\$auto$proc_rom.cc:150:do_switch$987 [396] = 32'd2506334887;
\$auto$proc_rom.cc:150:do_switch$987 [397] = 32'd664217095;
\$auto$proc_rom.cc:150:do_switch$987 [398] = 32'd3079077888;
\$auto$proc_rom.cc:150:do_switch$987 [399] = 32'd399714727;
\$auto$proc_rom.cc:150:do_switch$987 [400] = 32'd2640552693;
\$auto$proc_rom.cc:150:do_switch$987 [401] = 32'd131277831;
\$auto$proc_rom.cc:150:do_switch$987 [402] = 32'd114553344;
\$auto$proc_rom.cc:150:do_switch$987 [403] = 32'd399761925;
\$auto$proc_rom.cc:150:do_switch$987 [404] = 32'd3347686133;
\$auto$proc_rom.cc:150:do_switch$987 [405] = 32'd581244883;
\$auto$proc_rom.cc:150:do_switch$987 [406] = 32'd3792144083;
\$auto$proc_rom.cc:150:do_switch$987 [407] = 32'd1074066963;
\$auto$proc_rom.cc:150:do_switch$987 [408] = 32'd1192878609;
\$auto$proc_rom.cc:150:do_switch$987 [409] = 32'd54974355;
\$auto$proc_rom.cc:150:do_switch$987 [410] = 32'd2146957203;
\$auto$proc_rom.cc:150:do_switch$987 [411] = 32'd3222767515;
\$auto$proc_rom.cc:150:do_switch$987 [412] = 32'd3523708755;
\$auto$proc_rom.cc:150:do_switch$987 [413] = 32'd1072694675;
\$auto$proc_rom.cc:150:do_switch$987 [414] = 32'd13014931;
\$auto$proc_rom.cc:150:do_switch$987 [415] = 32'd2209420754;
\$auto$proc_rom.cc:150:do_switch$987 [416] = 32'd630689741;
\$auto$proc_rom.cc:150:do_switch$987 [417] = 32'd3062300672;
\$auto$proc_rom.cc:150:do_switch$987 [418] = 32'd630662501;
\$auto$proc_rom.cc:150:do_switch$987 [419] = 32'd3079077888;
\$auto$proc_rom.cc:150:do_switch$987 [420] = 32'd630662501;
\$auto$proc_rom.cc:150:do_switch$987 [421] = 32'd622264320;
\$auto$proc_rom.cc:150:do_switch$987 [422] = 32'd2000879616;
\$auto$proc_rom.cc:150:do_switch$987 [423] = 32'd2262006487;
\$auto$proc_rom.cc:150:do_switch$987 [424] = 32'd3079139847;
\$auto$proc_rom.cc:150:do_switch$987 [425] = 32'd664216933;
\$auto$proc_rom.cc:150:do_switch$987 [426] = 32'd4157800448;
\$auto$proc_rom.cc:150:do_switch$987 [427] = 32'd3062303478;
\$auto$proc_rom.cc:150:do_switch$987 [428] = 32'd664216743;
\$auto$proc_rom.cc:150:do_switch$987 [429] = 32'd3045523456;
\$auto$proc_rom.cc:150:do_switch$987 [430] = 32'd664217319;
\$auto$proc_rom.cc:150:do_switch$987 [431] = 32'd4156751872;
\$auto$proc_rom.cc:150:do_switch$987 [432] = 32'd3070718679;
\$auto$proc_rom.cc:150:do_switch$987 [433] = 32'd664216551;
\$auto$proc_rom.cc:150:do_switch$987 [434] = 32'd3062300672;
\$auto$proc_rom.cc:150:do_switch$987 [435] = 32'd2513642407;
\$auto$proc_rom.cc:150:do_switch$987 [436] = 32'd2278801927;
\$auto$proc_rom.cc:150:do_switch$987 [437] = 32'd2350633477;
\$auto$proc_rom.cc:150:do_switch$987 [438] = 32'd4148363269;
\$auto$proc_rom.cc:150:do_switch$987 [439] = 32'd914844391;
\$auto$proc_rom.cc:150:do_switch$987 [440] = 32'd622274341;
\$auto$proc_rom.cc:150:do_switch$987 [441] = 32'd399704064;
\$auto$proc_rom.cc:150:do_switch$987 [442] = 32'd2270413319;
\$auto$proc_rom.cc:150:do_switch$987 [443] = 32'd2275136007;
\$auto$proc_rom.cc:150:do_switch$987 [444] = 32'd399654903;
\$auto$proc_rom.cc:150:do_switch$987 [445] = 32'd316110675;
\$auto$proc_rom.cc:150:do_switch$987 [446] = 32'd585447047;
\$auto$proc_rom.cc:150:do_switch$987 [447] = 32'd9495;
\$auto$proc_rom.cc:150:do_switch$987 [448] = 32'd591738375;
\$auto$proc_rom.cc:150:do_switch$987 [449] = 32'd9495;
\$auto$proc_rom.cc:150:do_switch$987 [450] = 32'd1926756295;
\$auto$proc_rom.cc:150:do_switch$987 [451] = 32'd558184199;
\$auto$proc_rom.cc:150:do_switch$987 [452] = 32'd9495;
\$auto$proc_rom.cc:150:do_switch$987 [453] = 32'd562376711;
\$auto$proc_rom.cc:150:do_switch$987 [454] = 32'd9495;
\$auto$proc_rom.cc:150:do_switch$987 [455] = 32'd318240467;
\$auto$proc_rom.cc:150:do_switch$987 [456] = 32'd183924307;
\$auto$proc_rom.cc:150:do_switch$987 [457] = 32'd49805267;
\$auto$proc_rom.cc:150:do_switch$987 [458] = 32'd451344211;
\$auto$proc_rom.cc:150:do_switch$987 [459] = 32'd45578067;
\$auto$proc_rom.cc:150:do_switch$987 [460] = 32'd451344211;
\$auto$proc_rom.cc:150:do_switch$987 [461] = 32'd34043731;
\$auto$proc_rom.cc:150:do_switch$987 [462] = 32'd451344083;
\$auto$proc_rom.cc:150:do_switch$987 [463] = 32'd570767111;
\$auto$proc_rom.cc:150:do_switch$987 [464] = 32'd46593747;
\$auto$proc_rom.cc:150:do_switch$987 [465] = 32'd450361299;
\$auto$proc_rom.cc:150:do_switch$987 [466] = 32'd48756691;
\$auto$proc_rom.cc:150:do_switch$987 [467] = 32'd4060579667;
\$auto$proc_rom.cc:150:do_switch$987 [468] = 32'd317192147;
\$auto$proc_rom.cc:150:do_switch$987 [469] = 32'd4060514131;
\$auto$proc_rom.cc:150:do_switch$987 [470] = 32'd2734102483;
\$auto$proc_rom.cc:150:do_switch$987 [471] = 32'd3792144595;
\$auto$proc_rom.cc:150:do_switch$987 [472] = 32'd4157851545;
\$auto$proc_rom.cc:150:do_switch$987 [473] = 32'd2350586551;
\$auto$proc_rom.cc:150:do_switch$987 [474] = 32'd2295594997;
\$auto$proc_rom.cc:150:do_switch$987 [475] = 32'd211542535;
\$auto$proc_rom.cc:150:do_switch$987 [476] = 32'd3616736828;
\$auto$proc_rom.cc:150:do_switch$987 [477] = 32'd93520052;
\$auto$proc_rom.cc:150:do_switch$987 [478] = 32'd3165850720;
\$auto$proc_rom.cc:150:do_switch$987 [479] = 32'd2340749717;
\$auto$proc_rom.cc:150:do_switch$987 [480] = 32'd3282111633;
\$auto$proc_rom.cc:150:do_switch$987 [481] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [482] = 32'd466073479;
\$auto$proc_rom.cc:150:do_switch$987 [483] = 32'd4060514131;
\$auto$proc_rom.cc:150:do_switch$987 [484] = 32'd2733082579;
\$auto$proc_rom.cc:150:do_switch$987 [485] = 32'd336035939;
\$auto$proc_rom.cc:150:do_switch$987 [486] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [487] = 32'd453490567;
\$auto$proc_rom.cc:150:do_switch$987 [488] = 32'd2734102483;
\$auto$proc_rom.cc:150:do_switch$987 [489] = 32'd302483555;
\$auto$proc_rom.cc:150:do_switch$987 [490] = 32'd460699;
\$auto$proc_rom.cc:150:do_switch$987 [491] = 32'd1449346817;
\$auto$proc_rom.cc:150:do_switch$987 [492] = 32'd2277179644;
\$auto$proc_rom.cc:150:do_switch$987 [493] = 32'd2266710407;
\$auto$proc_rom.cc:150:do_switch$987 [494] = 32'd3834904567;
\$auto$proc_rom.cc:150:do_switch$987 [495] = 32'd1283538948;
\$auto$proc_rom.cc:150:do_switch$987 [496] = 32'd1199655937;
\$auto$proc_rom.cc:150:do_switch$987 [497] = 32'd19723363;
\$auto$proc_rom.cc:150:do_switch$987 [498] = 32'd1100548027;
\$auto$proc_rom.cc:150:do_switch$987 [499] = 32'd2423699;
\$auto$proc_rom.cc:150:do_switch$987 [500] = 32'd755555;
\$auto$proc_rom.cc:150:do_switch$987 [501] = 32'd1881619;
\$auto$proc_rom.cc:150:do_switch$987 [502] = 32'd1086326323;
\$auto$proc_rom.cc:150:do_switch$987 [503] = 32'd308514801;
\$auto$proc_rom.cc:150:do_switch$987 [504] = 32'd131272204;
\$auto$proc_rom.cc:150:do_switch$987 [505] = 32'd374600192;
\$auto$proc_rom.cc:150:do_switch$987 [506] = 32'd3323568885;
\$auto$proc_rom.cc:150:do_switch$987 [507] = 32'd4060514259;
\$auto$proc_rom.cc:150:do_switch$987 [508] = 32'd586651603;
\$auto$proc_rom.cc:150:do_switch$987 [509] = 32'd3792144083;
\$auto$proc_rom.cc:150:do_switch$987 [510] = 32'd4060513619;
\$auto$proc_rom.cc:150:do_switch$987 [511] = 32'd135493757;
\$auto$proc_rom.cc:150:do_switch$987 [512] = 32'd4164124664;
\$auto$proc_rom.cc:150:do_switch$987 [513] = 32'd2262171908;
\$auto$proc_rom.cc:150:do_switch$987 [514] = 32'd2245166626;
\$auto$proc_rom.cc:150:do_switch$987 [515] = 32'd15697230;
\$auto$proc_rom.cc:150:do_switch$987 [516] = 32'd2334788896;
\$auto$proc_rom.cc:150:do_switch$987 [517] = 32'd101484131;
\$auto$proc_rom.cc:150:do_switch$987 [518] = 32'd33879187;
\$auto$proc_rom.cc:150:do_switch$987 [519] = 32'd72353043;
\$auto$proc_rom.cc:150:do_switch$987 [520] = 32'd85188761;
\$auto$proc_rom.cc:150:do_switch$987 [521] = 32'd2254046800;
\$auto$proc_rom.cc:150:do_switch$987 [522] = 32'd2245166806;
\$auto$proc_rom.cc:150:do_switch$987 [523] = 32'd1461426562;
\$auto$proc_rom.cc:150:do_switch$987 [524] = 32'd1186152956;
\$auto$proc_rom.cc:150:do_switch$987 [525] = 32'd1200947436;
\$auto$proc_rom.cc:150:do_switch$987 [526] = 32'd101924093;
\$auto$proc_rom.cc:150:do_switch$987 [527] = 32'd3829268507;
\$auto$proc_rom.cc:150:do_switch$987 [528] = 32'd1088849723;
\$auto$proc_rom.cc:150:do_switch$987 [529] = 32'd1216471142;
\$auto$proc_rom.cc:150:do_switch$987 [530] = 32'd1469794345;
\$auto$proc_rom.cc:150:do_switch$987 [531] = 32'd2262172156;
\$auto$proc_rom.cc:150:do_switch$987 [532] = 32'd2236515794;
\$auto$proc_rom.cc:150:do_switch$987 [533] = 32'd2915037423;
\$auto$proc_rom.cc:150:do_switch$987 [534] = 32'd2204338986;
\$auto$proc_rom.cc:150:do_switch$987 [535] = 32'd419561995;
\$auto$proc_rom.cc:150:do_switch$987 [536] = 32'd1082459187;
\$auto$proc_rom.cc:150:do_switch$987 [537] = 32'd34167059;
\$auto$proc_rom.cc:150:do_switch$987 [538] = 32'd19168355;
\$auto$proc_rom.cc:150:do_switch$987 [539] = 32'd67470938;
\$auto$proc_rom.cc:150:do_switch$987 [540] = 32'd2245166806;
\$auto$proc_rom.cc:150:do_switch$987 [541] = 32'd33555731;
\$auto$proc_rom.cc:150:do_switch$987 [542] = 32'd2575436549;
\$auto$proc_rom.cc:150:do_switch$987 [543] = 32'd4280576227;
\$auto$proc_rom.cc:150:do_switch$987 [544] = 32'd1946579110;
\$auto$proc_rom.cc:150:do_switch$987 [545] = 32'd1766221030;
\$auto$proc_rom.cc:150:do_switch$987 [546] = 32'd1778805158;
\$auto$proc_rom.cc:150:do_switch$987 [547] = 32'd2074245858;
\$auto$proc_rom.cc:150:do_switch$987 [548] = 32'd1826782210;
\$auto$proc_rom.cc:150:do_switch$987 [549] = 32'd2067957082;
\$auto$proc_rom.cc:150:do_switch$987 [550] = 32'd2156028261;
\$auto$proc_rom.cc:150:do_switch$987 [551] = 32'd1946584610;
\$auto$proc_rom.cc:150:do_switch$987 [552] = 32'd2067951782;
\$auto$proc_rom.cc:150:do_switch$987 [553] = 32'd2080537506;
\$auto$proc_rom.cc:150:do_switch$987 [554] = 32'd2284219618;
\$auto$proc_rom.cc:150:do_switch$987 [555] = 32'd1692829642;
\$auto$proc_rom.cc:150:do_switch$987 [556] = 32'd2262198598;
\$auto$proc_rom.cc:150:do_switch$987 [557] = 32'd2061665746;
\$auto$proc_rom.cc:150:do_switch$987 [558] = 32'd2236508678;
\$auto$proc_rom.cc:150:do_switch$987 [559] = 32'd1634036134;
\$auto$proc_rom.cc:150:do_switch$987 [560] = 32'd2278793221;
\$auto$proc_rom.cc:150:do_switch$987 [561] = 32'd2270425606;
\$auto$proc_rom.cc:150:do_switch$987 [562] = 32'd4157862408;
\$auto$proc_rom.cc:150:do_switch$987 [563] = 32'd2261981927;
\$auto$proc_rom.cc:150:do_switch$987 [564] = 32'd3204571655;
\$auto$proc_rom.cc:150:do_switch$987 [565] = 32'd3993438179;
\$auto$proc_rom.cc:150:do_switch$987 [566] = 32'd3993372131;
\$auto$proc_rom.cc:150:do_switch$987 [567] = 32'd3050649469;
\$auto$proc_rom.cc:150:do_switch$987 [568] = 32'd2728731475;
\$auto$proc_rom.cc:150:do_switch$987 [569] = 32'd2294452158;
\$auto$proc_rom.cc:150:do_switch$987 [570] = 32'd402851683;
\$auto$proc_rom.cc:150:do_switch$987 [571] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [572] = 32'd4266112903;
\$auto$proc_rom.cc:150:do_switch$987 [573] = 32'd2733971411;
\$auto$proc_rom.cc:150:do_switch$987 [574] = 32'd604477027;
\$auto$proc_rom.cc:150:do_switch$987 [575] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [576] = 32'd4240947079;
\$auto$proc_rom.cc:150:do_switch$987 [577] = 32'd4163006777;
\$auto$proc_rom.cc:150:do_switch$987 [578] = 32'd2728892371;
\$auto$proc_rom.cc:150:do_switch$987 [579] = 32'd4228314150;
\$auto$proc_rom.cc:150:do_switch$987 [580] = 32'd2209252010;
\$auto$proc_rom.cc:150:do_switch$987 [581] = 32'd2226553906;
\$auto$proc_rom.cc:150:do_switch$987 [582] = 32'd302488675;
\$auto$proc_rom.cc:150:do_switch$987 [583] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [584] = 32'd55031687;
\$auto$proc_rom.cc:150:do_switch$987 [585] = 32'd2728892371;
\$auto$proc_rom.cc:150:do_switch$987 [586] = 32'd537367395;
\$auto$proc_rom.cc:150:do_switch$987 [587] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [588] = 32'd46643079;
\$auto$proc_rom.cc:150:do_switch$987 [589] = 32'd2733971411;
\$auto$proc_rom.cc:150:do_switch$987 [590] = 32'd503815011;
\$auto$proc_rom.cc:150:do_switch$987 [591] = 32'd4060088275;
\$auto$proc_rom.cc:150:do_switch$987 [592] = 32'd399721857;
\$auto$proc_rom.cc:150:do_switch$987 [593] = 32'd2422448885;
\$auto$proc_rom.cc:150:do_switch$987 [594] = 32'd4153613831;
\$auto$proc_rom.cc:150:do_switch$987 [595] = 32'd3817947144;
\$auto$proc_rom.cc:150:do_switch$987 [596] = 32'd1124157209;
\$auto$proc_rom.cc:150:do_switch$987 [597] = 32'd101926821;
\$auto$proc_rom.cc:150:do_switch$987 [598] = 32'd110297856;
\$auto$proc_rom.cc:150:do_switch$987 [599] = 32'd4200792576;
\$auto$proc_rom.cc:150:do_switch$987 [600] = 32'd50659559;
\$auto$proc_rom.cc:150:do_switch$987 [601] = 32'd6360627;
\$auto$proc_rom.cc:150:do_switch$987 [602] = 32'd4274917283;
\$auto$proc_rom.cc:150:do_switch$987 [603] = 32'd417544061;
\$auto$proc_rom.cc:150:do_switch$987 [604] = 32'd382992083;
\$auto$proc_rom.cc:150:do_switch$987 [605] = 32'd353616389;
\$auto$proc_rom.cc:150:do_switch$987 [606] = 32'd2278752775;
\$auto$proc_rom.cc:150:do_switch$987 [607] = 32'd2274611718;
\$auto$proc_rom.cc:150:do_switch$987 [608] = 32'd1444148609;
\$auto$proc_rom.cc:150:do_switch$987 [609] = 32'd2010317269;
\$auto$proc_rom.cc:150:do_switch$987 [610] = 32'd2545027829;
\$auto$proc_rom.cc:150:do_switch$987 [611] = 32'd664216468;
\$auto$proc_rom.cc:150:do_switch$987 [612] = 32'd3070689280;
\$auto$proc_rom.cc:150:do_switch$987 [613] = 32'd2384197415;
\$auto$proc_rom.cc:150:do_switch$987 [614] = 32'd4157800454;
\$auto$proc_rom.cc:150:do_switch$987 [615] = 32'd2673021655;
\$auto$proc_rom.cc:150:do_switch$987 [616] = 32'd1985200695;
\$auto$proc_rom.cc:150:do_switch$987 [617] = 32'd4157854271;
\$auto$proc_rom.cc:150:do_switch$987 [618] = 32'd399706823;
\$auto$proc_rom.cc:150:do_switch$987 [619] = 32'd3487671031;
\$auto$proc_rom.cc:150:do_switch$987 [620] = 32'd2010320645;
\$auto$proc_rom.cc:150:do_switch$987 [621] = 32'd2278806079;
\$auto$proc_rom.cc:150:do_switch$987 [622] = 32'd3347161846;
\$auto$proc_rom.cc:150:do_switch$987 [623] = 32'd1478171;
\$auto$proc_rom.cc:150:do_switch$987 [624] = 32'd3949547265;
\$auto$proc_rom.cc:150:do_switch$987 [625] = 32'd3524134867;
\$auto$proc_rom.cc:150:do_switch$987 [626] = 32'd10135;
\$auto$proc_rom.cc:150:do_switch$987 [627] = 32'd4085757703;
\$auto$proc_rom.cc:150:do_switch$987 [628] = 32'd183858515;
\$auto$proc_rom.cc:150:do_switch$987 [629] = 32'd2732922835;
\$auto$proc_rom.cc:150:do_switch$987 [630] = 32'd399755137;
\$auto$proc_rom.cc:150:do_switch$987 [631] = 32'd3347686055;
\$auto$proc_rom.cc:150:do_switch$987 [632] = 32'd1996691;
\$auto$proc_rom.cc:150:do_switch$987 [633] = 32'd772129681;
\$auto$proc_rom.cc:150:do_switch$987 [634] = 32'd33555987;
\$auto$proc_rom.cc:150:do_switch$987 [635] = 32'd258164649;
\$auto$proc_rom.cc:150:do_switch$987 [636] = 32'd1731923139;
\$auto$proc_rom.cc:150:do_switch$987 [637] = 32'd50660094;
\$auto$proc_rom.cc:150:do_switch$987 [638] = 32'd6358707;
\$auto$proc_rom.cc:150:do_switch$987 [639] = 32'd50220603;
\$auto$proc_rom.cc:150:do_switch$987 [640] = 32'd50792219;
\$auto$proc_rom.cc:150:do_switch$987 [641] = 32'd4276522915;
\$auto$proc_rom.cc:150:do_switch$987 [642] = 32'd4262335459;
\$auto$proc_rom.cc:150:do_switch$987 [643] = 32'd3733395;
\$auto$proc_rom.cc:150:do_switch$987 [644] = 32'd2304984837;
\$auto$proc_rom.cc:150:do_switch$987 [645] = 32'd118693095;
\$auto$proc_rom.cc:150:do_switch$987 [646] = 32'd241369600;
\$auto$proc_rom.cc:150:do_switch$987 [647] = 32'd2338527971;
\$auto$proc_rom.cc:150:do_switch$987 [648] = 32'd127078917;
\$auto$proc_rom.cc:150:do_switch$987 [649] = 32'd2268267011;
\$auto$proc_rom.cc:150:do_switch$987 [650] = 32'd110297127;
\$auto$proc_rom.cc:150:do_switch$987 [651] = 32'd127075024;
\$auto$proc_rom.cc:150:do_switch$987 [652] = 32'd2293779;
\$auto$proc_rom.cc:150:do_switch$987 [653] = 32'd2265644759;
\$auto$proc_rom.cc:150:do_switch$987 [654] = 32'd2250409638;
\$auto$proc_rom.cc:150:do_switch$987 [655] = 32'd2241759358;
\$auto$proc_rom.cc:150:do_switch$987 [656] = 32'd4042229014;
\$auto$proc_rom.cc:150:do_switch$987 [657] = 32'd1893892767;
\$auto$proc_rom.cc:150:do_switch$987 [658] = 32'd1956803650;
\$auto$proc_rom.cc:150:do_switch$987 [659] = 32'd2156028193;
\$auto$proc_rom.cc:150:do_switch$987 [660] = 32'd4749203;
\$auto$proc_rom.cc:150:do_switch$987 [661] = 32'd655877113;
\$auto$proc_rom.cc:150:do_switch$987 [662] = 32'd118685696;
\$auto$proc_rom.cc:150:do_switch$987 [663] = 32'd1200457767;
\$auto$proc_rom.cc:150:do_switch$987 [664] = 32'd1950516770;
\$auto$proc_rom.cc:150:do_switch$987 [665] = 32'd2259054818;
\$auto$proc_rom.cc:150:do_switch$987 [666] = 32'd2289988770;
\$auto$proc_rom.cc:150:do_switch$987 [667] = 32'd2232845726;
\$auto$proc_rom.cc:150:do_switch$987 [668] = 32'd4033831201;
\$auto$proc_rom.cc:150:do_switch$987 [669] = 32'd655884175;
\$auto$proc_rom.cc:150:do_switch$987 [670] = 32'd2285764608;
\$auto$proc_rom.cc:150:do_switch$987 [671] = 32'd2259093267;
\$auto$proc_rom.cc:150:do_switch$987 [672] = 32'd4033824653;
\$auto$proc_rom.cc:150:do_switch$987 [673] = 32'd2547252879;
\$auto$proc_rom.cc:150:do_switch$987 [674] = 32'd4286948071;
\$auto$proc_rom.cc:150:do_switch$987 [675] = 32'd302980963;
\$auto$proc_rom.cc:150:do_switch$987 [676] = 32'd3675066117;
\$auto$proc_rom.cc:150:do_switch$987 [677] = 32'd4261873691;
\$auto$proc_rom.cc:150:do_switch$987 [678] = 32'd6817851;
\$auto$proc_rom.cc:150:do_switch$987 [679] = 32'd1084573353;
\$auto$proc_rom.cc:150:do_switch$987 [680] = 32'd2008260613;
\$auto$proc_rom.cc:150:do_switch$987 [681] = 32'd85656287;
\$auto$proc_rom.cc:150:do_switch$987 [682] = 32'd2275147767;
\$auto$proc_rom.cc:150:do_switch$987 [683] = 32'd262341383;
\$auto$proc_rom.cc:150:do_switch$987 [684] = 32'd1471414006;
\$auto$proc_rom.cc:150:do_switch$987 [685] = 32'd4284678879;
\$auto$proc_rom.cc:150:do_switch$987 [686] = 32'd2267679712;
\$auto$proc_rom.cc:150:do_switch$987 [687] = 32'd2403238774;
\$auto$proc_rom.cc:150:do_switch$987 [688] = 32'd1248915;
\$auto$proc_rom.cc:150:do_switch$987 [689] = 32'd30475827;
\$auto$proc_rom.cc:150:do_switch$987 [690] = 32'd4245102051;
\$auto$proc_rom.cc:150:do_switch$987 [691] = 32'd3733395;
\$auto$proc_rom.cc:150:do_switch$987 [692] = 32'd2455979781;
\$auto$proc_rom.cc:150:do_switch$987 [693] = 32'd127078631;
\$auto$proc_rom.cc:150:do_switch$987 [694] = 32'd2397241856;
\$auto$proc_rom.cc:150:do_switch$987 [695] = 32'd2674127887;
\$auto$proc_rom.cc:150:do_switch$987 [696] = 32'd4145221125;
\$auto$proc_rom.cc:150:do_switch$987 [697] = 32'd3676373192;
\$auto$proc_rom.cc:150:do_switch$987 [698] = 32'd2467512317;
\$auto$proc_rom.cc:150:do_switch$987 [699] = 32'd1393754639;
\$auto$proc_rom.cc:150:do_switch$987 [700] = 32'd4066574851;
\$auto$proc_rom.cc:150:do_switch$987 [701] = 32'd118689895;
\$auto$proc_rom.cc:150:do_switch$987 [702] = 32'd101908992;
\$auto$proc_rom.cc:150:do_switch$987 [703] = 32'd110297856;
\$auto$proc_rom.cc:150:do_switch$987 [704] = 32'd2330132992;
\$auto$proc_rom.cc:150:do_switch$987 [705] = 32'd126218983;
\$auto$proc_rom.cc:150:do_switch$987 [706] = 32'd15796019;
\$auto$proc_rom.cc:150:do_switch$987 [707] = 32'd4274458531;
\$auto$proc_rom.cc:150:do_switch$987 [708] = 32'd4033315811;
\$auto$proc_rom.cc:150:do_switch$987 [709] = 32'd4275542499;
\$auto$proc_rom.cc:150:do_switch$987 [710] = 32'd387432249;
\$auto$proc_rom.cc:150:do_switch$987 [711] = 32'd118685696;
\$auto$proc_rom.cc:150:do_switch$987 [712] = 32'd1200716647;
\$auto$proc_rom.cc:150:do_switch$987 [713] = 32'd4115906357;
\$auto$proc_rom.cc:150:do_switch$987 [714] = 32'd1166346919;
\$auto$proc_rom.cc:150:do_switch$987 [715] = 32'd2250423609;
\$auto$proc_rom.cc:150:do_switch$987 [716] = 32'd1893889090;
\$auto$proc_rom.cc:150:do_switch$987 [717] = 32'd1956808358;
\$auto$proc_rom.cc:150:do_switch$987 [718] = 32'd2281605190;
\$auto$proc_rom.cc:150:do_switch$987 [719] = 32'd2232845726;
\$auto$proc_rom.cc:150:do_switch$987 [720] = 32'd3160760609;
\$auto$proc_rom.cc:150:do_switch$987 [721] = 32'd5911;
\$auto$proc_rom.cc:150:do_switch$987 [722] = 32'd1200719998;
\$auto$proc_rom.cc:150:do_switch$987 [723] = 32'd2051475219;
\$auto$proc_rom.cc:150:do_switch$987 [724] = 32'd4054839407;
\$auto$proc_rom.cc:150:do_switch$987 [725] = 32'd4781971;
\$auto$proc_rom.cc:150:do_switch$987 [726] = 32'd4136890289;
\$auto$proc_rom.cc:150:do_switch$987 [727] = 32'd2275016840;
\$auto$proc_rom.cc:150:do_switch$987 [728] = 32'd3959852003;
\$auto$proc_rom.cc:150:do_switch$987 [729] = 32'd33752723;
\$auto$proc_rom.cc:150:do_switch$987 [730] = 32'd2523955;
\$auto$proc_rom.cc:150:do_switch$987 [731] = 32'd2295685;
\$auto$proc_rom.cc:150:do_switch$987 [732] = 32'd3050438371;
\$auto$proc_rom.cc:150:do_switch$987 [733] = 32'd33556371;
\$auto$proc_rom.cc:150:do_switch$987 [734] = 32'd4110322403;
\$auto$proc_rom.cc:150:do_switch$987 [735] = 32'd3240966009;
\$auto$proc_rom.cc:150:do_switch$987 [736] = 32'd2466322178;
\$auto$proc_rom.cc:150:do_switch$987 [737] = 32'd2470052617;
\$auto$proc_rom.cc:150:do_switch$987 [738] = 32'd50333331;
\$auto$proc_rom.cc:150:do_switch$987 [739] = 32'd33556243;
\$auto$proc_rom.cc:150:do_switch$987 [740] = 32'd129175173;
\$auto$proc_rom.cc:150:do_switch$987 [741] = 32'd2409824721;
\$auto$proc_rom.cc:150:do_switch$987 [742] = 32'd2313420503;
\$auto$proc_rom.cc:150:do_switch$987 [743] = 32'd2581852910;
\$auto$proc_rom.cc:150:do_switch$987 [744] = 32'd127139438;
\$auto$proc_rom.cc:150:do_switch$987 [745] = 32'd2542404099;
\$auto$proc_rom.cc:150:do_switch$987 [746] = 32'd48236307;
\$auto$proc_rom.cc:150:do_switch$987 [747] = 32'd2149778181;
\$auto$proc_rom.cc:150:do_switch$987 [748] = 32'd3172859623;
\$auto$proc_rom.cc:150:do_switch$987 [749] = 32'd33752979;
\$auto$proc_rom.cc:150:do_switch$987 [750] = 32'd2590515;
\$auto$proc_rom.cc:150:do_switch$987 [751] = 32'd45090451;
\$auto$proc_rom.cc:150:do_switch$987 [752] = 32'd1247123;
\$auto$proc_rom.cc:150:do_switch$987 [753] = 32'd4275503139;
\$auto$proc_rom.cc:150:do_switch$987 [754] = 32'd2006169021;
\$auto$proc_rom.cc:150:do_switch$987 [755] = 32'd2330132511;
\$auto$proc_rom.cc:150:do_switch$987 [756] = 32'd252042759;
\$auto$proc_rom.cc:150:do_switch$987 [757] = 32'd127122813;
\$auto$proc_rom.cc:150:do_switch$987 [758] = 32'd3182494208;
\$auto$proc_rom.cc:150:do_switch$987 [759] = 32'd3181461501;
\$auto$proc_rom.cc:150:do_switch$987 [760] = 32'd3082912630;
\$auto$proc_rom.cc:150:do_switch$987 [761] = 32'd3792669155;
\$auto$proc_rom.cc:150:do_switch$987 [762] = 32'd4145277321;
\$auto$proc_rom.cc:150:do_switch$987 [763] = 32'd2275016904;
\$auto$proc_rom.cc:150:do_switch$987 [764] = 32'd3993439715;
\$auto$proc_rom.cc:150:do_switch$987 [765] = 32'd2201927125;
\$auto$proc_rom.cc:150:do_switch$987 [766] = 32'd2275065145;
\$auto$proc_rom.cc:150:do_switch$987 [767] = 32'd3776034293;
\$auto$proc_rom.cc:150:do_switch$987 [768] = 32'd2781708418;
\$auto$proc_rom.cc:150:do_switch$987 [769] = 32'd3978719601;
\$auto$proc_rom.cc:150:do_switch$987 [770] = 32'd3847153994;
\$auto$proc_rom.cc:150:do_switch$987 [771] = 32'd4041406682;
\$auto$proc_rom.cc:150:do_switch$987 [772] = 32'd4294965655;
\$auto$proc_rom.cc:150:do_switch$987 [773] = 32'd4045600006;
\$auto$proc_rom.cc:150:do_switch$987 [774] = 32'd4241940818;
\$auto$proc_rom.cc:150:do_switch$987 [775] = 32'd3974558942;
\$auto$proc_rom.cc:150:do_switch$987 [776] = 32'd3840862442;
\$auto$proc_rom.cc:150:do_switch$987 [777] = 32'd2226293038;
\$auto$proc_rom.cc:150:do_switch$987 [778] = 32'd2352646966;
\$auto$proc_rom.cc:150:do_switch$987 [779] = 32'd1703512467;
\$auto$proc_rom.cc:150:do_switch$987 [780] = 32'd2309669265;
\$auto$proc_rom.cc:150:do_switch$987 [781] = 32'd738563;
\$auto$proc_rom.cc:150:do_switch$987 [782] = 32'd23284609;
\$auto$proc_rom.cc:150:do_switch$987 [783] = 32'd1740722693;
\$auto$proc_rom.cc:150:do_switch$987 [784] = 32'd1789204477;
\$auto$proc_rom.cc:150:do_switch$987 [785] = 32'd2274621502;
\$auto$proc_rom.cc:150:do_switch$987 [786] = 32'd3963487258;
\$auto$proc_rom.cc:150:do_switch$987 [787] = 32'd2274584453;
\$auto$proc_rom.cc:150:do_switch$987 [788] = 32'd169050119;
\$auto$proc_rom.cc:150:do_switch$987 [789] = 32'd4097704528;
\$auto$proc_rom.cc:150:do_switch$987 [790] = 32'd2254350353;
\$auto$proc_rom.cc:150:do_switch$987 [791] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [792] = 32'd2575436677;
\$auto$proc_rom.cc:150:do_switch$987 [793] = 32'd738563;
\$auto$proc_rom.cc:150:do_switch$987 [794] = 32'd302318179;
\$auto$proc_rom.cc:150:do_switch$987 [795] = 32'd383978245;
\$auto$proc_rom.cc:150:do_switch$987 [796] = 32'd1208090437;
\$auto$proc_rom.cc:150:do_switch$987 [797] = 32'd1157842497;
\$auto$proc_rom.cc:150:do_switch$987 [798] = 32'd110297099;
\$auto$proc_rom.cc:150:do_switch$987 [799] = 32'd127598619;
\$auto$proc_rom.cc:150:do_switch$987 [800] = 32'd4153671173;
\$auto$proc_rom.cc:150:do_switch$987 [801] = 32'd1768099831;
\$auto$proc_rom.cc:150:do_switch$987 [802] = 32'd2266169590;
\$auto$proc_rom.cc:150:do_switch$987 [803] = 32'd126540673;
\$auto$proc_rom.cc:150:do_switch$987 [804] = 32'd1134335930;
\$auto$proc_rom.cc:150:do_switch$987 [805] = 32'd2273482682;
\$auto$proc_rom.cc:150:do_switch$987 [806] = 32'd4244965275;
\$auto$proc_rom.cc:150:do_switch$987 [807] = 32'd267909011;
\$auto$proc_rom.cc:150:do_switch$987 [808] = 32'd1935886117;
\$auto$proc_rom.cc:150:do_switch$987 [809] = 32'd118691063;
\$auto$proc_rom.cc:150:do_switch$987 [810] = 32'd1249968800;
\$auto$proc_rom.cc:150:do_switch$987 [811] = 32'd384107619;
\$auto$proc_rom.cc:150:do_switch$987 [812] = 32'd48236307;
\$auto$proc_rom.cc:150:do_switch$987 [813] = 32'd107168769;
\$auto$proc_rom.cc:150:do_switch$987 [814] = 32'd119214309;
\$auto$proc_rom.cc:150:do_switch$987 [815] = 32'd1997797765;
\$auto$proc_rom.cc:150:do_switch$987 [816] = 32'd1179193335;
\$auto$proc_rom.cc:150:do_switch$987 [817] = 32'd15101539;
\$auto$proc_rom.cc:150:do_switch$987 [818] = 32'd3754001939;
\$auto$proc_rom.cc:150:do_switch$987 [819] = 32'd2536638218;
\$auto$proc_rom.cc:150:do_switch$987 [820] = 32'd2536653592;
\$auto$proc_rom.cc:150:do_switch$987 [821] = 32'd1157859074;
\$auto$proc_rom.cc:150:do_switch$987 [822] = 32'd1746075675;
\$auto$proc_rom.cc:150:do_switch$987 [823] = 32'd109383688;
\$auto$proc_rom.cc:150:do_switch$987 [824] = 32'd108005139;
\$auto$proc_rom.cc:150:do_switch$987 [825] = 32'd1768131382;
\$auto$proc_rom.cc:150:do_switch$987 [826] = 32'd118686887;
\$auto$proc_rom.cc:150:do_switch$987 [827] = 32'd1994588736;
\$auto$proc_rom.cc:150:do_switch$987 [828] = 32'd119273127;
\$auto$proc_rom.cc:150:do_switch$987 [829] = 32'd1997798837;
\$auto$proc_rom.cc:150:do_switch$987 [830] = 32'd110301175;
\$auto$proc_rom.cc:150:do_switch$987 [831] = 32'd4007855136;
\$auto$proc_rom.cc:150:do_switch$987 [832] = 32'd2257843430;
\$auto$proc_rom.cc:150:do_switch$987 [833] = 32'd118154369;
\$auto$proc_rom.cc:150:do_switch$987 [834] = 32'd1125685046;
\$auto$proc_rom.cc:150:do_switch$987 [835] = 32'd2265093942;
\$auto$proc_rom.cc:150:do_switch$987 [836] = 32'd1599507;
\$auto$proc_rom.cc:150:do_switch$987 [837] = 32'd3078982454;
\$auto$proc_rom.cc:150:do_switch$987 [838] = 32'd2648083;
\$auto$proc_rom.cc:150:do_switch$987 [839] = 32'd3215035190;
\$auto$proc_rom.cc:150:do_switch$987 [840] = 32'd4745235;
\$auto$proc_rom.cc:150:do_switch$987 [841] = 32'd3212938038;
\$auto$proc_rom.cc:150:do_switch$987 [842] = 32'd17328147;
\$auto$proc_rom.cc:150:do_switch$987 [843] = 32'd3080817462;
\$auto$proc_rom.cc:150:do_switch$987 [844] = 32'd8939539;
\$auto$proc_rom.cc:150:do_switch$987 [845] = 32'd3078720310;
\$auto$proc_rom.cc:150:do_switch$987 [846] = 32'd4185196315;
\$auto$proc_rom.cc:150:do_switch$987 [847] = 32'd267876115;
\$auto$proc_rom.cc:150:do_switch$987 [848] = 32'd3974317757;
\$auto$proc_rom.cc:150:do_switch$987 [849] = 32'd1742926054;
\$auto$proc_rom.cc:150:do_switch$987 [850] = 32'd2528331397;
\$auto$proc_rom.cc:150:do_switch$987 [851] = 32'd2398945510;
\$auto$proc_rom.cc:150:do_switch$987 [852] = 32'd839293283;
\$auto$proc_rom.cc:150:do_switch$987 [853] = 32'd140723881;
\$auto$proc_rom.cc:150:do_switch$987 [854] = 32'd1201477847;
\$auto$proc_rom.cc:150:do_switch$987 [855] = 32'd4009172963;
\$auto$proc_rom.cc:150:do_switch$987 [856] = 32'd800515;
\$auto$proc_rom.cc:150:do_switch$987 [857] = 32'd35153811;
\$auto$proc_rom.cc:150:do_switch$987 [858] = 32'd1203889214;
\$auto$proc_rom.cc:150:do_switch$987 [859] = 32'd3762194014;
\$auto$proc_rom.cc:150:do_switch$987 [860] = 32'd1212254370;
\$auto$proc_rom.cc:150:do_switch$987 [861] = 32'd2259044225;
\$auto$proc_rom.cc:150:do_switch$987 [862] = 32'd2236515786;
\$auto$proc_rom.cc:150:do_switch$987 [863] = 32'd3677352175;
\$auto$proc_rom.cc:150:do_switch$987 [864] = 32'd1157860266;
\$auto$proc_rom.cc:150:do_switch$987 [865] = 32'd203489291;
\$auto$proc_rom.cc:150:do_switch$987 [866] = 32'd3993309923;
\$auto$proc_rom.cc:150:do_switch$987 [867] = 32'd754715;
\$auto$proc_rom.cc:150:do_switch$987 [868] = 32'd10216547;
\$auto$proc_rom.cc:150:do_switch$987 [869] = 32'd4294216595;
\$auto$proc_rom.cc:150:do_switch$987 [870] = 32'd2254341798;
\$auto$proc_rom.cc:150:do_switch$987 [871] = 32'd1157727690;
\$auto$proc_rom.cc:150:do_switch$987 [872] = 32'd1890228610;
\$auto$proc_rom.cc:150:do_switch$987 [873] = 32'd1946846498;
\$auto$proc_rom.cc:150:do_switch$987 [874] = 32'd1766483178;
\$auto$proc_rom.cc:150:do_switch$987 [875] = 32'd1779067306;
\$auto$proc_rom.cc:150:do_switch$987 [876] = 32'd2068216550;
\$auto$proc_rom.cc:150:do_switch$987 [877] = 32'd2080799654;
\$auto$proc_rom.cc:150:do_switch$987 [878] = 32'd1833331942;
\$auto$proc_rom.cc:150:do_switch$987 [879] = 32'd1632464294;
\$auto$proc_rom.cc:150:do_switch$987 [880] = 32'd1157857410;
\$auto$proc_rom.cc:150:do_switch$987 [881] = 32'd1168441371;
\$auto$proc_rom.cc:150:do_switch$987 [882] = 32'd119244342;
\$auto$proc_rom.cc:150:do_switch$987 [883] = 32'd1997798661;
\$auto$proc_rom.cc:150:do_switch$987 [884] = 32'd1746079735;
\$auto$proc_rom.cc:150:do_switch$987 [885] = 32'd4184031240;
\$auto$proc_rom.cc:150:do_switch$987 [886] = 32'd118692069;
\$auto$proc_rom.cc:150:do_switch$987 [887] = 32'd191038112;
\$auto$proc_rom.cc:150:do_switch$987 [888] = 32'd2335578853;
\$auto$proc_rom.cc:150:do_switch$987 [889] = 32'd3184592517;
\$auto$proc_rom.cc:150:do_switch$987 [890] = 32'd1176849025;
\$auto$proc_rom.cc:150:do_switch$987 [891] = 32'd2791195;
\$auto$proc_rom.cc:150:do_switch$987 [892] = 32'd22480699;
\$auto$proc_rom.cc:150:do_switch$987 [893] = 32'd1513243;
\$auto$proc_rom.cc:150:do_switch$987 [894] = 32'd3305348905;
\$auto$proc_rom.cc:150:do_switch$987 [895] = 32'd177930246;
\$auto$proc_rom.cc:150:do_switch$987 [896] = 32'd2335636743;
\$auto$proc_rom.cc:150:do_switch$987 [897] = 32'd4244965147;
\$auto$proc_rom.cc:150:do_switch$987 [898] = 32'd267876115;
\$auto$proc_rom.cc:150:do_switch$987 [899] = 32'd2145584773;
\$auto$proc_rom.cc:150:do_switch$987 [900] = 32'd3178888422;
\$auto$proc_rom.cc:150:do_switch$987 [901] = 32'd796419;
\$auto$proc_rom.cc:150:do_switch$987 [902] = 32'd177933345;
\$auto$proc_rom.cc:150:do_switch$987 [903] = 32'd1197670407;
\$auto$proc_rom.cc:150:do_switch$987 [904] = 32'd1157824519;
\$auto$proc_rom.cc:150:do_switch$987 [905] = 32'd2335571995;
\$auto$proc_rom.cc:150:do_switch$987 [906] = 32'd3042510469;
\$auto$proc_rom.cc:150:do_switch$987 [907] = 32'd1787139;
\$auto$proc_rom.cc:150:do_switch$987 [908] = 32'd2648083;
\$auto$proc_rom.cc:150:do_switch$987 [909] = 32'd180063030;
\$auto$proc_rom.cc:150:do_switch$987 [910] = 32'd109396192;
\$auto$proc_rom.cc:150:do_switch$987 [911] = 32'd1157873045;
\$auto$proc_rom.cc:150:do_switch$987 [912] = 32'd118685723;
\$auto$proc_rom.cc:150:do_switch$987 [913] = 32'd451086016;
\$auto$proc_rom.cc:150:do_switch$987 [914] = 32'd1157884133;
\$auto$proc_rom.cc:150:do_switch$987 [915] = 32'd1746075691;
\$auto$proc_rom.cc:150:do_switch$987 [916] = 32'd110309384;
\$auto$proc_rom.cc:150:do_switch$987 [917] = 32'd3043557435;
\$auto$proc_rom.cc:150:do_switch$987 [918] = 32'd1787139;
\$auto$proc_rom.cc:150:do_switch$987 [919] = 32'd109053715;
\$auto$proc_rom.cc:150:do_switch$987 [920] = 32'd786760547;
\$auto$proc_rom.cc:150:do_switch$987 [921] = 32'd134768659;
\$auto$proc_rom.cc:150:do_switch$987 [922] = 32'd3181184645;
\$auto$proc_rom.cc:150:do_switch$987 [923] = 32'd73402131;
\$auto$proc_rom.cc:150:do_switch$987 [924] = 32'd551880291;
\$auto$proc_rom.cc:150:do_switch$987 [925] = 32'd800007;
\$auto$proc_rom.cc:150:do_switch$987 [926] = 32'd2278983262;
\$auto$proc_rom.cc:150:do_switch$987 [927] = 32'd2259060514;
\$auto$proc_rom.cc:150:do_switch$987 [928] = 32'd2236515786;
\$auto$proc_rom.cc:150:do_switch$987 [929] = 32'd2782916847;
\$auto$proc_rom.cc:150:do_switch$987 [930] = 32'd2343177249;
\$auto$proc_rom.cc:150:do_switch$987 [931] = 32'd1947450337;
\$auto$proc_rom.cc:150:do_switch$987 [932] = 32'd210960424;
\$auto$proc_rom.cc:150:do_switch$987 [933] = 32'd56819852;
\$auto$proc_rom.cc:150:do_switch$987 [934] = 32'd1157837316;
\$auto$proc_rom.cc:150:do_switch$987 [935] = 32'd2259025932;
\$auto$proc_rom.cc:150:do_switch$987 [936] = 32'd2244642398;
\$auto$proc_rom.cc:150:do_switch$987 [937] = 32'd1191549314;
\$auto$proc_rom.cc:150:do_switch$987 [938] = 32'd1803283;
\$auto$proc_rom.cc:150:do_switch$987 [939] = 32'd995586659;
\$auto$proc_rom.cc:150:do_switch$987 [940] = 32'd4293560219;
\$auto$proc_rom.cc:150:do_switch$987 [941] = 32'd2383615874;
\$auto$proc_rom.cc:150:do_switch$987 [942] = 32'd2474704939;
\$auto$proc_rom.cc:150:do_switch$987 [943] = 32'd16649139;
\$auto$proc_rom.cc:150:do_switch$987 [944] = 32'd2259060258;
\$auto$proc_rom.cc:150:do_switch$987 [945] = 32'd2244609029;
\$auto$proc_rom.cc:150:do_switch$987 [946] = 32'd33555731;
\$auto$proc_rom.cc:150:do_switch$987 [947] = 32'd2581830018;
\$auto$proc_rom.cc:150:do_switch$987 [948] = 32'd2355560075;
\$auto$proc_rom.cc:150:do_switch$987 [949] = 32'd2254355265;
\$auto$proc_rom.cc:150:do_switch$987 [950] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [951] = 32'd38798611;
\$auto$proc_rom.cc:150:do_switch$987 [952] = 32'd2575436677;
\$auto$proc_rom.cc:150:do_switch$987 [953] = 32'd1023652673;
\$auto$proc_rom.cc:150:do_switch$987 [954] = 32'd127074316;
\$auto$proc_rom.cc:150:do_switch$987 [955] = 32'd4231921804;
\$auto$proc_rom.cc:150:do_switch$987 [956] = 32'd869891;
\$auto$proc_rom.cc:150:do_switch$987 [957] = 32'd3965027634;
\$auto$proc_rom.cc:150:do_switch$987 [958] = 32'd90397945;
\$auto$proc_rom.cc:150:do_switch$987 [959] = 32'd210057734;
\$auto$proc_rom.cc:150:do_switch$987 [960] = 32'd2271911146;
\$auto$proc_rom.cc:150:do_switch$987 [961] = 32'd2271453209;
\$auto$proc_rom.cc:150:do_switch$987 [962] = 32'd1182999788;
\$auto$proc_rom.cc:150:do_switch$987 [963] = 32'd117768215;
\$auto$proc_rom.cc:150:do_switch$987 [964] = 32'd129759997;
\$auto$proc_rom.cc:150:do_switch$987 [965] = 32'd4030611879;
\$auto$proc_rom.cc:150:do_switch$987 [966] = 32'd1074298259;
\$auto$proc_rom.cc:150:do_switch$987 [967] = 32'd887395;
\$auto$proc_rom.cc:150:do_switch$987 [968] = 32'd2267182978;
\$auto$proc_rom.cc:150:do_switch$987 [969] = 32'd8909667;
\$auto$proc_rom.cc:150:do_switch$987 [970] = 32'd127633214;
\$auto$proc_rom.cc:150:do_switch$987 [971] = 32'd4030595079;
\$auto$proc_rom.cc:150:do_switch$987 [972] = 32'd2653203;
\$auto$proc_rom.cc:150:do_switch$987 [973] = 32'd571215459;
\$auto$proc_rom.cc:150:do_switch$987 [974] = 32'd436604259;
\$auto$proc_rom.cc:150:do_switch$987 [975] = 32'd2271446622;
\$auto$proc_rom.cc:150:do_switch$987 [976] = 32'd119209997;
\$auto$proc_rom.cc:150:do_switch$987 [977] = 32'd40108020;
\$auto$proc_rom.cc:150:do_switch$987 [978] = 32'd2218400260;
\$auto$proc_rom.cc:150:do_switch$987 [979] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [980] = 32'd1445011;
\$auto$proc_rom.cc:150:do_switch$987 [981] = 32'd2268305794;
\$auto$proc_rom.cc:150:do_switch$987 [982] = 32'd2540323196;
\$auto$proc_rom.cc:150:do_switch$987 [983] = 32'd476419;
\$auto$proc_rom.cc:150:do_switch$987 [984] = 32'd402982499;
\$auto$proc_rom.cc:150:do_switch$987 [985] = 32'd3219228262;
\$auto$proc_rom.cc:150:do_switch$987 [986] = 32'd387663525;
\$auto$proc_rom.cc:150:do_switch$987 [987] = 32'd2669740068;
\$auto$proc_rom.cc:150:do_switch$987 [988] = 32'd387646981;
\$auto$proc_rom.cc:150:do_switch$987 [989] = 32'd2670264343;
\$auto$proc_rom.cc:150:do_switch$987 [990] = 32'd410883;
\$auto$proc_rom.cc:150:do_switch$987 [991] = 32'd4245095451;
\$auto$proc_rom.cc:150:do_switch$987 [992] = 32'd4244965147;
\$auto$proc_rom.cc:150:do_switch$987 [993] = 32'd267876115;
\$auto$proc_rom.cc:150:do_switch$987 [994] = 32'd4276548067;
\$auto$proc_rom.cc:150:do_switch$987 [995] = 32'd110332722;
\$auto$proc_rom.cc:150:do_switch$987 [996] = 32'd3005546518;
\$auto$proc_rom.cc:150:do_switch$987 [997] = 32'd796419;
\$auto$proc_rom.cc:150:do_switch$987 [998] = 32'd2835715;
\$auto$proc_rom.cc:150:do_switch$987 [999] = 32'd1217596169;
\$auto$proc_rom.cc:150:do_switch$987 [1000] = 32'd3633577975;
\$auto$proc_rom.cc:150:do_switch$987 [1001] = 32'd4097000440;
\$auto$proc_rom.cc:150:do_switch$987 [1002] = 32'd203489512;
\$auto$proc_rom.cc:150:do_switch$987 [1003] = 32'd1771155;
\$auto$proc_rom.cc:150:do_switch$987 [1004] = 32'd479441705;
\$auto$proc_rom.cc:150:do_switch$987 [1005] = 32'd3700621828;
\$auto$proc_rom.cc:150:do_switch$987 [1006] = 32'd90374668;
\$auto$proc_rom.cc:150:do_switch$987 [1007] = 32'd486354438;
\$auto$proc_rom.cc:150:do_switch$987 [1008] = 32'd1997782845;
\$auto$proc_rom.cc:150:do_switch$987 [1009] = 32'd110300661;
\$auto$proc_rom.cc:150:do_switch$987 [1010] = 32'd40043632;
\$auto$proc_rom.cc:150:do_switch$987 [1011] = 32'd118691543;
\$auto$proc_rom.cc:150:do_switch$987 [1012] = 32'd123929680;
\$auto$proc_rom.cc:150:do_switch$987 [1013] = 32'd889657061;
\$auto$proc_rom.cc:150:do_switch$987 [1014] = 32'd2254307340;
\$auto$proc_rom.cc:150:do_switch$987 [1015] = 32'd2267187158;
\$auto$proc_rom.cc:150:do_switch$987 [1016] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [1017] = 32'd4042229070;
\$auto$proc_rom.cc:150:do_switch$987 [1018] = 32'd203546959;
\$auto$proc_rom.cc:150:do_switch$987 [1019] = 32'd3114109866;
\$auto$proc_rom.cc:150:do_switch$987 [1020] = 32'd102762259;
\$auto$proc_rom.cc:150:do_switch$987 [1021] = 32'd551880035;
\$auto$proc_rom.cc:150:do_switch$987 [1022] = 32'd116393747;
\$auto$proc_rom.cc:150:do_switch$987 [1023] = 32'd551881571;
\$auto$proc_rom.cc:150:do_switch$987 [1024] = 32'd92276499;
\$auto$proc_rom.cc:150:do_switch$987 [1025] = 32'd384106595;
\$auto$proc_rom.cc:150:do_switch$987 [1026] = 32'd4277696531;
\$auto$proc_rom.cc:150:do_switch$987 [1027] = 32'd1997751977;
\$auto$proc_rom.cc:150:do_switch$987 [1028] = 32'd101924872;
\$auto$proc_rom.cc:150:do_switch$987 [1029] = 32'd2243561104;
\$auto$proc_rom.cc:150:do_switch$987 [1030] = 32'd516232803;
\$auto$proc_rom.cc:150:do_switch$987 [1031] = 32'd211021229;
\$auto$proc_rom.cc:150:do_switch$987 [1032] = 32'd1997734028;
\$auto$proc_rom.cc:150:do_switch$987 [1033] = 32'd2252480520;
\$auto$proc_rom.cc:150:do_switch$987 [1034] = 32'd503781219;
\$auto$proc_rom.cc:150:do_switch$987 [1035] = 32'd268990227;
\$auto$proc_rom.cc:150:do_switch$987 [1036] = 32'd570891363;
\$auto$proc_rom.cc:150:do_switch$987 [1037] = 32'd67532563;
\$auto$proc_rom.cc:150:do_switch$987 [1038] = 32'd796035;
\$auto$proc_rom.cc:150:do_switch$987 [1039] = 32'd537334627;
\$auto$proc_rom.cc:150:do_switch$987 [1040] = 32'd134641171;
\$auto$proc_rom.cc:150:do_switch$987 [1041] = 32'd604375651;
\$auto$proc_rom.cc:150:do_switch$987 [1042] = 32'd17143195;
\$auto$proc_rom.cc:150:do_switch$987 [1043] = 32'd1090901403;
\$auto$proc_rom.cc:150:do_switch$987 [1044] = 32'd1089852955;
\$auto$proc_rom.cc:150:do_switch$987 [1045] = 32'd12961587;
\$auto$proc_rom.cc:150:do_switch$987 [1046] = 32'd390242065;
\$auto$proc_rom.cc:150:do_switch$987 [1047] = 32'd3829568321;
\$auto$proc_rom.cc:150:do_switch$987 [1048] = 32'd3763766878;
\$auto$proc_rom.cc:150:do_switch$987 [1049] = 32'd2285275298;
\$auto$proc_rom.cc:150:do_switch$987 [1050] = 32'd32888731;
\$auto$proc_rom.cc:150:do_switch$987 [1051] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [1052] = 32'd4042229070;
\$auto$proc_rom.cc:150:do_switch$987 [1053] = 32'd2343218127;
\$auto$proc_rom.cc:150:do_switch$987 [1054] = 32'd3069021286;
\$auto$proc_rom.cc:150:do_switch$987 [1055] = 32'd34105363;
\$auto$proc_rom.cc:150:do_switch$987 [1056] = 32'd118733781;
\$auto$proc_rom.cc:150:do_switch$987 [1057] = 32'd367200128;
\$auto$proc_rom.cc:150:do_switch$987 [1058] = 32'd1187116773;
\$auto$proc_rom.cc:150:do_switch$987 [1059] = 32'd1074296595;
\$auto$proc_rom.cc:150:do_switch$987 [1060] = 32'd4281890835;
\$auto$proc_rom.cc:150:do_switch$987 [1061] = 32'd2014562049;
\$auto$proc_rom.cc:150:do_switch$987 [1062] = 32'd671219688;
\$auto$proc_rom.cc:150:do_switch$987 [1063] = 32'd110102291;
\$auto$proc_rom.cc:150:do_switch$987 [1064] = 32'd9178259;
\$auto$proc_rom.cc:150:do_switch$987 [1065] = 32'd4142206947;
\$auto$proc_rom.cc:150:do_switch$987 [1066] = 32'd104859411;
\$auto$proc_rom.cc:150:do_switch$987 [1067] = 32'd4142205923;
\$auto$proc_rom.cc:150:do_switch$987 [1068] = 32'd537425683;
\$auto$proc_rom.cc:150:do_switch$987 [1069] = 32'd274957890;
\$auto$proc_rom.cc:150:do_switch$987 [1070] = 32'd1997740551;
\$auto$proc_rom.cc:150:do_switch$987 [1071] = 32'd342036488;
\$auto$proc_rom.cc:150:do_switch$987 [1072] = 32'd1997741063;
\$auto$proc_rom.cc:150:do_switch$987 [1073] = 32'd308478982;
\$auto$proc_rom.cc:150:do_switch$987 [1074] = 32'd1980962823;
\$auto$proc_rom.cc:150:do_switch$987 [1075] = 32'd654510086;
\$auto$proc_rom.cc:150:do_switch$987 [1076] = 32'd3256418316;
\$auto$proc_rom.cc:150:do_switch$987 [1077] = 32'd2407364546;
\$auto$proc_rom.cc:150:do_switch$987 [1078] = 32'd3829536514;
\$auto$proc_rom.cc:150:do_switch$987 [1079] = 32'd3763766878;
\$auto$proc_rom.cc:150:do_switch$987 [1080] = 32'd2285275298;
\$auto$proc_rom.cc:150:do_switch$987 [1081] = 32'd2466334593;
\$auto$proc_rom.cc:150:do_switch$987 [1082] = 32'd2360522577;
\$auto$proc_rom.cc:150:do_switch$987 [1083] = 32'd34344547;
\$auto$proc_rom.cc:150:do_switch$987 [1084] = 32'd2005044198;
\$auto$proc_rom.cc:150:do_switch$987 [1085] = 32'd223867491;
\$auto$proc_rom.cc:150:do_switch$987 [1086] = 32'd4294608923;
\$auto$proc_rom.cc:150:do_switch$987 [1087] = 32'd1089996859;
\$auto$proc_rom.cc:150:do_switch$987 [1088] = 32'd1477646338;
\$auto$proc_rom.cc:150:do_switch$987 [1089] = 32'd2266169864;
\$auto$proc_rom.cc:150:do_switch$987 [1090] = 32'd213057563;
\$auto$proc_rom.cc:150:do_switch$987 [1091] = 32'd2685468904;
\$auto$proc_rom.cc:150:do_switch$987 [1092] = 32'd2254309125;
\$auto$proc_rom.cc:150:do_switch$987 [1093] = 32'd2259087418;
\$auto$proc_rom.cc:150:do_switch$987 [1094] = 32'd85165514;
\$auto$proc_rom.cc:150:do_switch$987 [1095] = 32'd2344223232;
\$auto$proc_rom.cc:150:do_switch$987 [1096] = 32'd1996659074;
\$auto$proc_rom.cc:150:do_switch$987 [1097] = 32'd4276917987;
\$auto$proc_rom.cc:150:do_switch$987 [1098] = 32'd2347138146;
\$auto$proc_rom.cc:150:do_switch$987 [1099] = 32'd2007154213;
\$auto$proc_rom.cc:150:do_switch$987 [1100] = 32'd265647379;
\$auto$proc_rom.cc:150:do_switch$987 [1101] = 32'd72353555;
\$auto$proc_rom.cc:150:do_switch$987 [1102] = 32'd16279603;
\$auto$proc_rom.cc:150:do_switch$987 [1103] = 32'd3907329507;
\$auto$proc_rom.cc:150:do_switch$987 [1104] = 32'd34105363;
\$auto$proc_rom.cc:150:do_switch$987 [1105] = 32'd1157872969;
\$auto$proc_rom.cc:150:do_switch$987 [1106] = 32'd1746075691;
\$auto$proc_rom.cc:150:do_switch$987 [1107] = 32'd110300168;
\$auto$proc_rom.cc:150:do_switch$987 [1108] = 32'd3061383227;
\$auto$proc_rom.cc:150:do_switch$987 [1109] = 32'd1101825979;
\$auto$proc_rom.cc:150:do_switch$987 [1110] = 32'd3145592894;
\$auto$proc_rom.cc:150:do_switch$987 [1111] = 32'd3991094273;
\$auto$proc_rom.cc:150:do_switch$987 [1112] = 32'd3104686747;
\$auto$proc_rom.cc:150:do_switch$987 [1113] = 32'd34105363;
\$auto$proc_rom.cc:150:do_switch$987 [1114] = 32'd1997752001;
\$auto$proc_rom.cc:150:do_switch$987 [1115] = 32'd3071098888;
\$auto$proc_rom.cc:150:do_switch$987 [1116] = 32'd2266724226;
\$auto$proc_rom.cc:150:do_switch$987 [1117] = 32'd4217569303;
\$auto$proc_rom.cc:150:do_switch$987 [1118] = 32'd2266698583;
\$auto$proc_rom.cc:150:do_switch$987 [1119] = 32'd213647354;
\$auto$proc_rom.cc:150:do_switch$987 [1120] = 32'd478298359;
\$auto$proc_rom.cc:150:do_switch$987 [1121] = 32'd34397331;
\$auto$proc_rom.cc:150:do_switch$987 [1122] = 32'd1804051;
\$auto$proc_rom.cc:150:do_switch$987 [1123] = 32'd2686033082;
\$auto$proc_rom.cc:150:do_switch$987 [1124] = 32'd117798658;
\$auto$proc_rom.cc:150:do_switch$987 [1125] = 32'd2259060318;
\$auto$proc_rom.cc:150:do_switch$987 [1126] = 32'd4030368698;
\$auto$proc_rom.cc:150:do_switch$987 [1127] = 32'd85165514;
\$auto$proc_rom.cc:150:do_switch$987 [1128] = 32'd2575434240;
\$auto$proc_rom.cc:150:do_switch$987 [1129] = 32'd4286355171;
\$auto$proc_rom.cc:150:do_switch$987 [1130] = 32'd869891;
\$auto$proc_rom.cc:150:do_switch$987 [1131] = 32'd1738651;
\$auto$proc_rom.cc:150:do_switch$987 [1132] = 32'd2234708030;
\$auto$proc_rom.cc:150:do_switch$987 [1133] = 32'd3624277219;
\$auto$proc_rom.cc:150:do_switch$987 [1134] = 32'd3082652894;
\$auto$proc_rom.cc:150:do_switch$987 [1135] = 32'd1969440517;
\$auto$proc_rom.cc:150:do_switch$987 [1136] = 32'd2216365911;
\$auto$proc_rom.cc:150:do_switch$987 [1137] = 32'd335740906;
\$auto$proc_rom.cc:150:do_switch$987 [1138] = 32'd1804051;
\$auto$proc_rom.cc:150:do_switch$987 [1139] = 32'd2486865921;
\$auto$proc_rom.cc:150:do_switch$987 [1140] = 32'd117809169;
\$auto$proc_rom.cc:150:do_switch$987 [1141] = 32'd4030367326;
\$auto$proc_rom.cc:150:do_switch$987 [1142] = 32'd2244642470;
\$auto$proc_rom.cc:150:do_switch$987 [1143] = 32'd33555731;
\$auto$proc_rom.cc:150:do_switch$987 [1144] = 32'd2575469498;
\$auto$proc_rom.cc:150:do_switch$987 [1145] = 32'd384005890;
\$auto$proc_rom.cc:150:do_switch$987 [1146] = 32'd1157889671;
\$auto$proc_rom.cc:150:do_switch$987 [1147] = 32'd2259025932;
\$auto$proc_rom.cc:150:do_switch$987 [1148] = 32'd2244642338;
\$auto$proc_rom.cc:150:do_switch$987 [1149] = 32'd1313683;
\$auto$proc_rom.cc:150:do_switch$987 [1150] = 32'd2355534210;
\$auto$proc_rom.cc:150:do_switch$987 [1151] = 32'd1183429797;
\$auto$proc_rom.cc:150:do_switch$987 [1152] = 32'd1074296595;
\$auto$proc_rom.cc:150:do_switch$987 [1153] = 32'd104859155;
\$auto$proc_rom.cc:150:do_switch$987 [1154] = 32'd3905230051;
\$auto$proc_rom.cc:150:do_switch$987 [1155] = 32'd3758557667;
\$auto$proc_rom.cc:150:do_switch$987 [1156] = 32'd1185002841;
\$auto$proc_rom.cc:150:do_switch$987 [1157] = 32'd931380205;
\$auto$proc_rom.cc:150:do_switch$987 [1158] = 32'd2254307340;
\$auto$proc_rom.cc:150:do_switch$987 [1159] = 32'd3608405058;
\$auto$proc_rom.cc:150:do_switch$987 [1160] = 32'd1160987639;
\$auto$proc_rom.cc:150:do_switch$987 [1161] = 32'd3763732727;
\$auto$proc_rom.cc:150:do_switch$987 [1162] = 32'd2285275298;
\$auto$proc_rom.cc:150:do_switch$987 [1163] = 32'd120820733;
\$auto$proc_rom.cc:150:do_switch$987 [1164] = 32'd2259042533;
\$auto$proc_rom.cc:150:do_switch$987 [1165] = 32'd2236515786;
\$auto$proc_rom.cc:150:do_switch$987 [1166] = 32'd2406478063;
\$auto$proc_rom.cc:150:do_switch$987 [1167] = 32'd2355530666;
\$auto$proc_rom.cc:150:do_switch$987 [1168] = 32'd4120097813;
\$auto$proc_rom.cc:150:do_switch$987 [1169] = 32'd2267942901;
\$auto$proc_rom.cc:150:do_switch$987 [1170] = 32'd1191427353;
\$auto$proc_rom.cc:150:do_switch$987 [1171] = 32'd3043557388;
\$auto$proc_rom.cc:150:do_switch$987 [1172] = 32'd2355530658;
\$auto$proc_rom.cc:150:do_switch$987 [1173] = 32'd922991617;
\$auto$proc_rom.cc:150:do_switch$987 [1174] = 32'd2254307340;
\$auto$proc_rom.cc:150:do_switch$987 [1175] = 32'd3763790914;
\$auto$proc_rom.cc:150:do_switch$987 [1176] = 32'd2285275298;
\$auto$proc_rom.cc:150:do_switch$987 [1177] = 32'd3086043009;
\$auto$proc_rom.cc:150:do_switch$987 [1178] = 32'd800643;
\$auto$proc_rom.cc:150:do_switch$987 [1179] = 32'd3829565022;
\$auto$proc_rom.cc:150:do_switch$987 [1180] = 32'd1140315923;
\$auto$proc_rom.cc:150:do_switch$987 [1181] = 32'd16205107;
\$auto$proc_rom.cc:150:do_switch$987 [1182] = 32'd2292375638;
\$auto$proc_rom.cc:150:do_switch$987 [1183] = 32'd2482866230;
\$auto$proc_rom.cc:150:do_switch$987 [1184] = 32'd1088751411;
\$auto$proc_rom.cc:150:do_switch$987 [1185] = 32'd922989541;
\$auto$proc_rom.cc:150:do_switch$987 [1186] = 32'd2254307340;
\$auto$proc_rom.cc:150:do_switch$987 [1187] = 32'd3763790914;
\$auto$proc_rom.cc:150:do_switch$987 [1188] = 32'd2285275298;
\$auto$proc_rom.cc:150:do_switch$987 [1189] = 32'd3151579009;
\$auto$proc_rom.cc:150:do_switch$987 [1190] = 32'd1106630171;
\$auto$proc_rom.cc:150:do_switch$987 [1191] = 32'd12961587;
\$auto$proc_rom.cc:150:do_switch$987 [1192] = 32'd3145047825;
\$auto$proc_rom.cc:150:do_switch$987 [1193] = 32'd3113086978;
\$auto$proc_rom.cc:150:do_switch$987 [1194] = 32'd3078718558;
\$auto$proc_rom.cc:150:do_switch$987 [1195] = 32'd3071406138;
\$auto$proc_rom.cc:150:do_switch$987 [1196] = 32'd51605789;
\$auto$proc_rom.cc:150:do_switch$987 [1197] = 32'd2385117825;
\$auto$proc_rom.cc:150:do_switch$987 [1198] = 32'd1303;
\$auto$proc_rom.cc:150:do_switch$987 [1199] = 32'd4164088878;
\$auto$proc_rom.cc:150:do_switch$987 [1200] = 32'd3770350646;
\$auto$proc_rom.cc:150:do_switch$987 [1201] = 32'd2264040842;
\$auto$proc_rom.cc:150:do_switch$987 [1202] = 32'd1451067162;
\$auto$proc_rom.cc:150:do_switch$987 [1203] = 32'd2489648403;
\$auto$proc_rom.cc:150:do_switch$987 [1204] = 32'd3837717510;
\$auto$proc_rom.cc:150:do_switch$987 [1205] = 32'd3972458690;
\$auto$proc_rom.cc:150:do_switch$987 [1206] = 32'd4042253338;
\$auto$proc_rom.cc:150:do_switch$987 [1207] = 32'd1625461439;
\$auto$proc_rom.cc:150:do_switch$987 [1208] = 32'd2156028197;
\$auto$proc_rom.cc:150:do_switch$987 [1209] = 32'd16787223;
\$auto$proc_rom.cc:150:do_switch$987 [1210] = 32'd3519481619;
\$auto$proc_rom.cc:150:do_switch$987 [1211] = 32'd1199769425;
\$auto$proc_rom.cc:150:do_switch$987 [1212] = 32'd4153606151;
\$auto$proc_rom.cc:150:do_switch$987 [1213] = 32'd3756327431;
\$auto$proc_rom.cc:150:do_switch$987 [1214] = 32'd16787351;
\$auto$proc_rom.cc:150:do_switch$987 [1215] = 32'd3500639267;
\$auto$proc_rom.cc:150:do_switch$987 [1216] = 32'd2509996162;
\$auto$proc_rom.cc:150:do_switch$987 [1217] = 32'd1429930053;
\$auto$proc_rom.cc:150:do_switch$987 [1218] = 32'd664208053;
\$auto$proc_rom.cc:150:do_switch$987 [1219] = 32'd2274558208;
\$auto$proc_rom.cc:150:do_switch$987 [1220] = 32'd2183384935;
\$auto$proc_rom.cc:150:do_switch$987 [1221] = 32'd118685703;
\$auto$proc_rom.cc:150:do_switch$987 [1222] = 32'd2250504192;
\$auto$proc_rom.cc:150:do_switch$987 [1223] = 32'd655818983;
\$auto$proc_rom.cc:150:do_switch$987 [1224] = 32'd1989345536;
\$auto$proc_rom.cc:150:do_switch$987 [1225] = 32'd1427836917;
\$auto$proc_rom.cc:150:do_switch$987 [1226] = 32'd19071109;
\$auto$proc_rom.cc:150:do_switch$987 [1227] = 32'd1964232407;
\$auto$proc_rom.cc:150:do_switch$987 [1228] = 32'd2183335925;
\$auto$proc_rom.cc:150:do_switch$987 [1229] = 32'd1192034471;
\$auto$proc_rom.cc:150:do_switch$987 [1230] = 32'd15173155;
\$auto$proc_rom.cc:150:do_switch$987 [1231] = 32'd4235200275;
\$auto$proc_rom.cc:150:do_switch$987 [1232] = 32'd15172643;
\$auto$proc_rom.cc:150:do_switch$987 [1233] = 32'd33556243;
\$auto$proc_rom.cc:150:do_switch$987 [1234] = 32'd15173667;
\$auto$proc_rom.cc:150:do_switch$987 [1235] = 32'd2022932610;
\$auto$proc_rom.cc:150:do_switch$987 [1236] = 32'd1208025126;
\$auto$proc_rom.cc:150:do_switch$987 [1237] = 32'd2506328581;
\$auto$proc_rom.cc:150:do_switch$987 [1238] = 32'd1226571784;
\$auto$proc_rom.cc:150:do_switch$987 [1239] = 32'd3416868869;
\$auto$proc_rom.cc:150:do_switch$987 [1240] = 32'd1629275665;
\$auto$proc_rom.cc:150:do_switch$987 [1241] = 32'd3373811461;
\$auto$proc_rom.cc:150:do_switch$987 [1242] = 32'd34054179;
\$auto$proc_rom.cc:150:do_switch$987 [1243] = 32'd1737082281;
\$auto$proc_rom.cc:150:do_switch$987 [1244] = 32'd2274582804;
\$auto$proc_rom.cc:150:do_switch$987 [1245] = 32'd2685497607;
\$auto$proc_rom.cc:150:do_switch$987 [1246] = 32'd1255719845;
\$auto$proc_rom.cc:150:do_switch$987 [1247] = 32'd1575172093;
\$auto$proc_rom.cc:150:do_switch$987 [1248] = 32'd4153671175;
\$auto$proc_rom.cc:150:do_switch$987 [1249] = 32'd939335669;
\$auto$proc_rom.cc:150:do_switch$987 [1250] = 32'd9967643;
\$auto$proc_rom.cc:150:do_switch$987 [1251] = 32'd17295283;
\$auto$proc_rom.cc:150:do_switch$987 [1252] = 32'd3537643393;
\$auto$proc_rom.cc:150:do_switch$987 [1253] = 32'd1073743671;
\$auto$proc_rom.cc:150:do_switch$987 [1254] = 32'd2415479516;
\$auto$proc_rom.cc:150:do_switch$987 [1255] = 32'd4293732225;
\$auto$proc_rom.cc:150:do_switch$987 [1256] = 32'd558691;
\$auto$proc_rom.cc:150:do_switch$987 [1257] = 32'd337955;
\$auto$proc_rom.cc:150:do_switch$987 [1258] = 32'd3533457285;
\$auto$proc_rom.cc:150:do_switch$987 [1259] = 32'd2156020993;
\$auto$proc_rom.cc:150:do_switch$987 [1260] = 32'd395291;
\$auto$proc_rom.cc:150:do_switch$987 [1261] = 32'd2346956661;
\$auto$proc_rom.cc:150:do_switch$987 [1262] = 32'd289537544;
\$auto$proc_rom.cc:150:do_switch$987 [1263] = 32'd3825623324;
\$auto$proc_rom.cc:150:do_switch$987 [1264] = 32'd337955;
\$auto$proc_rom.cc:150:do_switch$987 [1265] = 32'd3549972229;
\$auto$proc_rom.cc:150:do_switch$987 [1266] = 32'd1168197121;
\$auto$proc_rom.cc:150:do_switch$987 [1267] = 32'd4164940015;
\$auto$proc_rom.cc:150:do_switch$987 [1268] = 32'd1157718178;
\$auto$proc_rom.cc:150:do_switch$987 [1269] = 32'd2156003649;
\$auto$proc_rom.cc:150:do_switch$987 [1270] = 32'd2156025213;
\$auto$proc_rom.cc:150:do_switch$987 [1271] = 32'd2276362410;
\$auto$proc_rom.cc:150:do_switch$987 [1272] = 32'd436604003;
\$auto$proc_rom.cc:150:do_switch$987 [1273] = 32'd7861523;
\$auto$proc_rom.cc:150:do_switch$987 [1274] = 32'd1074074211;
\$auto$proc_rom.cc:150:do_switch$987 [1275] = 32'd1930654009;
\$auto$proc_rom.cc:150:do_switch$987 [1276] = 32'd4228251687;
\$auto$proc_rom.cc:150:do_switch$987 [1277] = 32'd4096194594;
\$auto$proc_rom.cc:150:do_switch$987 [1278] = 32'd3964596298;
\$auto$proc_rom.cc:150:do_switch$987 [1279] = 32'd1115785989;
\$auto$proc_rom.cc:150:do_switch$987 [1280] = 32'd202851;
\$auto$proc_rom.cc:150:do_switch$987 [1281] = 32'd17343875;
\$auto$proc_rom.cc:150:do_switch$987 [1282] = 32'd3784917637;
\$auto$proc_rom.cc:150:do_switch$987 [1283] = 32'd459419;
\$auto$proc_rom.cc:150:do_switch$987 [1284] = 32'd268898659;
\$auto$proc_rom.cc:150:do_switch$987 [1285] = 32'd268929123;
\$auto$proc_rom.cc:150:do_switch$987 [1286] = 32'd12597043;
\$auto$proc_rom.cc:150:do_switch$987 [1287] = 32'd13645235;
\$auto$proc_rom.cc:150:do_switch$987 [1288] = 32'd1513243;
\$auto$proc_rom.cc:150:do_switch$987 [1289] = 32'd1436258125;
\$auto$proc_rom.cc:150:do_switch$987 [1290] = 32'd521863191;
\$auto$proc_rom.cc:150:do_switch$987 [1291] = 32'd4120052103;
\$auto$proc_rom.cc:150:do_switch$987 [1292] = 32'd3087208437;
\$auto$proc_rom.cc:150:do_switch$987 [1293] = 32'd3734700040;
\$auto$proc_rom.cc:150:do_switch$987 [1294] = 32'd3726311479;
\$auto$proc_rom.cc:150:do_switch$987 [1295] = 32'd1595605047;
\$auto$proc_rom.cc:150:do_switch$987 [1296] = 32'd3316990351;
\$auto$proc_rom.cc:150:do_switch$987 [1297] = 32'd5756699;
\$auto$proc_rom.cc:150:do_switch$987 [1298] = 32'd5756315;
\$auto$proc_rom.cc:150:do_switch$987 [1299] = 32'd2677264185;
\$auto$proc_rom.cc:150:do_switch$987 [1300] = 32'd3750953477;
\$auto$proc_rom.cc:150:do_switch$987 [1301] = 32'd2276590063;
\$auto$proc_rom.cc:150:do_switch$987 [1302] = 32'd2031329202;
\$auto$proc_rom.cc:150:do_switch$987 [1303] = 32'd2039676982;
\$auto$proc_rom.cc:150:do_switch$987 [1304] = 32'd2688352278;
\$auto$proc_rom.cc:150:do_switch$987 [1305] = 32'd3655427;
\$auto$proc_rom.cc:150:do_switch$987 [1306] = 32'd509059;
\$auto$proc_rom.cc:150:do_switch$987 [1307] = 32'd1557507;
\$auto$proc_rom.cc:150:do_switch$987 [1308] = 32'd2605955;
\$auto$proc_rom.cc:150:do_switch$987 [1309] = 32'd9504163;
\$auto$proc_rom.cc:150:do_switch$987 [1310] = 32'd8455459;
\$auto$proc_rom.cc:150:do_switch$987 [1311] = 32'd7406755;
\$auto$proc_rom.cc:150:do_switch$987 [1312] = 32'd14746659;
\$auto$proc_rom.cc:150:do_switch$987 [1313] = 32'd126961442;
\$auto$proc_rom.cc:150:do_switch$987 [1314] = 32'd48768035;
\$auto$proc_rom.cc:150:do_switch$987 [1315] = 32'd33000803;
\$auto$proc_rom.cc:150:do_switch$987 [1316] = 32'd21546755;
\$auto$proc_rom.cc:150:do_switch$987 [1317] = 32'd325311329;
\$auto$proc_rom.cc:150:do_switch$987 [1318] = 32'd1134038025;
\$auto$proc_rom.cc:150:do_switch$987 [1319] = 32'd606275473;
\$auto$proc_rom.cc:150:do_switch$987 [1320] = 32'd2548237032;
\$auto$proc_rom.cc:150:do_switch$987 [1321] = 32'd2535194615;
\$auto$proc_rom.cc:150:do_switch$987 [1322] = 32'd1801650213;
\$auto$proc_rom.cc:150:do_switch$987 [1323] = 32'd4128444359;
\$auto$proc_rom.cc:150:do_switch$987 [1324] = 32'd396042238;
\$auto$proc_rom.cc:150:do_switch$987 [1325] = 32'd914161871;
\$auto$proc_rom.cc:150:do_switch$987 [1326] = 32'd2459668061;
\$auto$proc_rom.cc:150:do_switch$987 [1327] = 32'd1714618514;
\$auto$proc_rom.cc:150:do_switch$987 [1328] = 32'd1737031766;
\$auto$proc_rom.cc:150:do_switch$987 [1329] = 32'd2274567681;
\$auto$proc_rom.cc:150:do_switch$987 [1330] = 32'd2686021895;
\$auto$proc_rom.cc:150:do_switch$987 [1331] = 32'd268929379;
\$auto$proc_rom.cc:150:do_switch$987 [1332] = 32'd21505795;
\$auto$proc_rom.cc:150:do_switch$987 [1333] = 32'd1541617661;
\$auto$proc_rom.cc:150:do_switch$987 [1334] = 32'd572784135;
\$auto$proc_rom.cc:150:do_switch$987 [1335] = 32'd2810381000;
\$auto$proc_rom.cc:150:do_switch$987 [1336] = 32'd3482386696;
\$auto$proc_rom.cc:150:do_switch$987 [1337] = 32'd986467;
\$auto$proc_rom.cc:150:do_switch$987 [1338] = 32'd2062099;
\$auto$proc_rom.cc:150:do_switch$987 [1339] = 32'd302455651;
\$auto$proc_rom.cc:150:do_switch$987 [1340] = 32'd1073743671;
\$auto$proc_rom.cc:150:do_switch$987 [1341] = 32'd21505923;
\$auto$proc_rom.cc:150:do_switch$987 [1342] = 32'd662802425;
\$auto$proc_rom.cc:150:do_switch$987 [1343] = 32'd291766245;
\$auto$proc_rom.cc:150:do_switch$987 [1344] = 32'd1893860355;
\$auto$proc_rom.cc:150:do_switch$987 [1345] = 32'd1956803650;
\$auto$proc_rom.cc:150:do_switch$987 [1346] = 32'd1776449794;
\$auto$proc_rom.cc:150:do_switch$987 [1347] = 32'd1629570305;
\$auto$proc_rom.cc:150:do_switch$987 [1348] = 32'd3070460034;
\$auto$proc_rom.cc:150:do_switch$987 [1349] = 32'd1166344200;
\$auto$proc_rom.cc:150:do_switch$987 [1350] = 32'd12101667;
\$auto$proc_rom.cc:150:do_switch$987 [1351] = 32'd34021411;
\$auto$proc_rom.cc:150:do_switch$987 [1352] = 32'd3993476323;
\$auto$proc_rom.cc:150:do_switch$987 [1353] = 32'd4228059107;
\$auto$proc_rom.cc:150:do_switch$987 [1354] = 32'd571267;
\$auto$proc_rom.cc:150:do_switch$987 [1355] = 32'd567331;
\$auto$proc_rom.cc:150:do_switch$987 [1356] = 32'd3549972229;
\$auto$proc_rom.cc:150:do_switch$987 [1357] = 32'd1168197121;
\$auto$proc_rom.cc:150:do_switch$987 [1358] = 32'd4042229062;
\$auto$proc_rom.cc:150:do_switch$987 [1359] = 32'd3083985247;
\$auto$proc_rom.cc:150:do_switch$987 [1360] = 32'd571267;
\$auto$proc_rom.cc:150:do_switch$987 [1361] = 32'd1950511330;
\$auto$proc_rom.cc:150:do_switch$987 [1362] = 32'd567331;
\$auto$proc_rom.cc:150:do_switch$987 [1363] = 32'd3549972229;
\$auto$proc_rom.cc:150:do_switch$987 [1364] = 32'd2030204066;
\$auto$proc_rom.cc:150:do_switch$987 [1365] = 32'd1157720546;
\$auto$proc_rom.cc:150:do_switch$987 [1366] = 32'd2156028193;
\$auto$proc_rom.cc:150:do_switch$987 [1367] = 32'd629859;
\$auto$proc_rom.cc:150:do_switch$987 [1368] = 32'd2610947;
\$auto$proc_rom.cc:150:do_switch$987 [1369] = 32'd512899;
\$auto$proc_rom.cc:150:do_switch$987 [1370] = 32'd14751011;
\$auto$proc_rom.cc:150:do_switch$987 [1371] = 32'd7410723;
\$auto$proc_rom.cc:150:do_switch$987 [1372] = 32'd3205580578;
\$auto$proc_rom.cc:150:do_switch$987 [1373] = 32'd3655427;
\$auto$proc_rom.cc:150:do_switch$987 [1374] = 32'd509059;
\$auto$proc_rom.cc:150:do_switch$987 [1375] = 32'd1557507;
\$auto$proc_rom.cc:150:do_switch$987 [1376] = 32'd2605955;
\$auto$proc_rom.cc:150:do_switch$987 [1377] = 32'd9503779;
\$auto$proc_rom.cc:150:do_switch$987 [1378] = 32'd8455331;
\$auto$proc_rom.cc:150:do_switch$987 [1379] = 32'd7406883;
\$auto$proc_rom.cc:150:do_switch$987 [1380] = 32'd14747043;
\$auto$proc_rom.cc:150:do_switch$987 [1381] = 32'd3183822626;
\$auto$proc_rom.cc:150:do_switch$987 [1382] = 32'd3825637091;
\$auto$proc_rom.cc:150:do_switch$987 [1383] = 32'd3141895738;
\$auto$proc_rom.cc:150:do_switch$987 [1384] = 32'd21546883;
\$auto$proc_rom.cc:150:do_switch$987 [1385] = 32'd15074739;
\$auto$proc_rom.cc:150:do_switch$987 [1386] = 32'd380803;
\$auto$proc_rom.cc:150:do_switch$987 [1387] = 32'd1089373627;
\$auto$proc_rom.cc:150:do_switch$987 [1388] = 32'd94629789;
\$auto$proc_rom.cc:150:do_switch$987 [1389] = 32'd1334116849;
\$auto$proc_rom.cc:150:do_switch$987 [1390] = 32'd482344035;
\$auto$proc_rom.cc:150:do_switch$987 [1391] = 32'd15077299;
\$auto$proc_rom.cc:150:do_switch$987 [1392] = 32'd2081667;
\$auto$proc_rom.cc:150:do_switch$987 [1393] = 32'd86200205;
\$auto$proc_rom.cc:150:do_switch$987 [1394] = 32'd2506293361;
\$auto$proc_rom.cc:150:do_switch$987 [1395] = 32'd2536636917;
\$auto$proc_rom.cc:150:do_switch$987 [1396] = 32'd2574211;
\$auto$proc_rom.cc:150:do_switch$987 [1397] = 32'd15795363;
\$auto$proc_rom.cc:150:do_switch$987 [1398] = 32'd66595;
\$auto$proc_rom.cc:150:do_switch$987 [1399] = 32'd1893902397;
\$auto$proc_rom.cc:150:do_switch$987 [1400] = 32'd1956803650;
\$auto$proc_rom.cc:150:do_switch$987 [1401] = 32'd1776449794;
\$auto$proc_rom.cc:150:do_switch$987 [1402] = 32'd1629574525;
\$auto$proc_rom.cc:150:do_switch$987 [1403] = 32'd69435522;
\$auto$proc_rom.cc:150:do_switch$987 [1404] = 32'd1199899121;
\$auto$proc_rom.cc:150:do_switch$987 [1405] = 32'd414710371;
\$auto$proc_rom.cc:150:do_switch$987 [1406] = 32'd15075251;
\$auto$proc_rom.cc:150:do_switch$987 [1407] = 32'd1557379;
\$auto$proc_rom.cc:150:do_switch$987 [1408] = 32'd1199656845;
\$auto$proc_rom.cc:150:do_switch$987 [1409] = 32'd7406755;
\$auto$proc_rom.cc:150:do_switch$987 [1410] = 32'd32871779;
\$auto$proc_rom.cc:150:do_switch$987 [1411] = 32'd1199806010;
\$auto$proc_rom.cc:150:do_switch$987 [1412] = 32'd86179878;
\$auto$proc_rom.cc:150:do_switch$987 [1413] = 32'd94568689;
\$auto$proc_rom.cc:150:do_switch$987 [1414] = 32'd1201799169;
\$auto$proc_rom.cc:150:do_switch$987 [1415] = 32'd49816611;
\$auto$proc_rom.cc:150:do_switch$987 [1416] = 32'd104314233;
\$auto$proc_rom.cc:150:do_switch$987 [1417] = 32'd1326268416;
\$auto$proc_rom.cc:150:do_switch$987 [1418] = 32'd662916997;
\$auto$proc_rom.cc:150:do_switch$987 [1419] = 32'd3608871240;
\$auto$proc_rom.cc:150:do_switch$987 [1420] = 32'd1997734023;
\$auto$proc_rom.cc:150:do_switch$987 [1421] = 32'd662769655;
\$auto$proc_rom.cc:150:do_switch$987 [1422] = 32'd662948641;
\$auto$proc_rom.cc:150:do_switch$987 [1423] = 32'd1994588808;
\$auto$proc_rom.cc:150:do_switch$987 [1424] = 32'd121372613;
\$auto$proc_rom.cc:150:do_switch$987 [1425] = 32'd3313713326;
\$auto$proc_rom.cc:150:do_switch$987 [1426] = 32'd662765896;
\$auto$proc_rom.cc:150:do_switch$987 [1427] = 32'd183465571;
\$auto$proc_rom.cc:150:do_switch$987 [1428] = 32'd268800355;
\$auto$proc_rom.cc:150:do_switch$987 [1429] = 32'd8902683;
\$auto$proc_rom.cc:150:do_switch$987 [1430] = 32'd17290651;
\$auto$proc_rom.cc:150:do_switch$987 [1431] = 32'd25679643;
\$auto$proc_rom.cc:150:do_switch$987 [1432] = 32'd16155043;
\$auto$proc_rom.cc:150:do_switch$987 [1433] = 32'd17203491;
\$auto$proc_rom.cc:150:do_switch$987 [1434] = 32'd11960483;
\$auto$proc_rom.cc:150:do_switch$987 [1435] = 32'd15106083;
\$auto$proc_rom.cc:150:do_switch$987 [1436] = 32'd571395;
\$auto$proc_rom.cc:150:do_switch$987 [1437] = 32'd21505923;
\$auto$proc_rom.cc:150:do_switch$987 [1438] = 32'd621872785;
\$auto$proc_rom.cc:150:do_switch$987 [1439] = 32'd8902427;
\$auto$proc_rom.cc:150:do_switch$987 [1440] = 32'd267876115;
\$auto$proc_rom.cc:150:do_switch$987 [1441] = 32'd4216661889;
\$auto$proc_rom.cc:150:do_switch$987 [1442] = 32'd662802417;
\$auto$proc_rom.cc:150:do_switch$987 [1443] = 32'd2028208089;
\$auto$proc_rom.cc:150:do_switch$987 [1444] = 32'd1728702405;
\$auto$proc_rom.cc:150:do_switch$987 [1445] = 32'd1896285971;
\$auto$proc_rom.cc:150:do_switch$987 [1446] = 32'd3543244817;
\$auto$proc_rom.cc:150:do_switch$987 [1447] = 32'd21505923;
\$auto$proc_rom.cc:150:do_switch$987 [1448] = 32'd3617273725;
\$auto$proc_rom.cc:150:do_switch$987 [1449] = 32'd4153606279;
\$auto$proc_rom.cc:150:do_switch$987 [1450] = 32'd3689222135;
\$auto$proc_rom.cc:150:do_switch$987 [1451] = 32'd42477443;
\$auto$proc_rom.cc:150:do_switch$987 [1452] = 32'd21546499;
\$auto$proc_rom.cc:150:do_switch$987 [1453] = 32'd1378075;
\$auto$proc_rom.cc:150:do_switch$987 [1454] = 32'd4000130945;
\$auto$proc_rom.cc:150:do_switch$987 [1455] = 32'd25679387;
\$auto$proc_rom.cc:150:do_switch$987 [1456] = 32'd13008931;
\$auto$proc_rom.cc:150:do_switch$987 [1457] = 32'd3807251939;
\$auto$proc_rom.cc:150:do_switch$987 [1458] = 32'd17291035;
\$auto$proc_rom.cc:150:do_switch$987 [1459] = 32'd15106211;
\$auto$proc_rom.cc:150:do_switch$987 [1460] = 32'd2426651;
\$auto$proc_rom.cc:150:do_switch$987 [1461] = 32'd15599715;
\$auto$proc_rom.cc:150:do_switch$987 [1462] = 32'd8902427;
\$auto$proc_rom.cc:150:do_switch$987 [1463] = 32'd15106339;
\$auto$proc_rom.cc:150:do_switch$987 [1464] = 32'd3475227;
\$auto$proc_rom.cc:150:do_switch$987 [1465] = 32'd1089374011;
\$auto$proc_rom.cc:150:do_switch$987 [1466] = 32'd451102213;
\$auto$proc_rom.cc:150:do_switch$987 [1467] = 32'd2175000775;
\$auto$proc_rom.cc:150:do_switch$987 [1468] = 32'd149094646;
\$auto$proc_rom.cc:150:do_switch$987 [1469] = 32'd3047809027;
\$auto$proc_rom.cc:150:do_switch$987 [1470] = 32'd1378075;
\$auto$proc_rom.cc:150:do_switch$987 [1471] = 32'd3583764877;
\$auto$proc_rom.cc:150:do_switch$987 [1472] = 32'd2149777799;
\$auto$proc_rom.cc:150:do_switch$987 [1473] = 32'd191037622;
\$auto$proc_rom.cc:150:do_switch$987 [1474] = 32'd3583706350;
\$auto$proc_rom.cc:150:do_switch$987 [1475] = 32'd119210247;
\$auto$proc_rom.cc:150:do_switch$987 [1476] = 32'd2158166053;
\$auto$proc_rom.cc:150:do_switch$987 [1477] = 32'd96141494;
\$auto$proc_rom.cc:150:do_switch$987 [1478] = 32'd2556641518;
\$auto$proc_rom.cc:150:do_switch$987 [1479] = 32'd3617260533;
\$auto$proc_rom.cc:150:do_switch$987 [1480] = 32'd2166554759;
\$auto$proc_rom.cc:150:do_switch$987 [1481] = 32'd3087204598;
\$auto$proc_rom.cc:150:do_switch$987 [1482] = 32'd621608968;
\$auto$proc_rom.cc:150:do_switch$987 [1483] = 32'd2149826045;
\$auto$proc_rom.cc:150:do_switch$987 [1484] = 32'd90374390;
\$auto$proc_rom.cc:150:do_switch$987 [1485] = 32'd3583705838;
\$auto$proc_rom.cc:150:do_switch$987 [1486] = 32'd119210119;
\$auto$proc_rom.cc:150:do_switch$987 [1487] = 32'd2158166053;
\$auto$proc_rom.cc:150:do_switch$987 [1488] = 32'd96141494;
\$auto$proc_rom.cc:150:do_switch$987 [1489] = 32'd2304983278;
\$auto$proc_rom.cc:150:do_switch$987 [1490] = 32'd3087205365;
\$auto$proc_rom.cc:150:do_switch$987 [1491] = 32'd2235170824;
\$auto$proc_rom.cc:150:do_switch$987 [1492] = 32'd4145266153;
\$auto$proc_rom.cc:150:do_switch$987 [1493] = 32'd3877175350;
\$auto$proc_rom.cc:150:do_switch$987 [1494] = 32'd3207185052;
\$auto$proc_rom.cc:150:do_switch$987 [1495] = 32'd571395;
\$auto$proc_rom.cc:150:do_switch$987 [1496] = 32'd3051455858;
\$auto$proc_rom.cc:150:do_switch$987 [1497] = 32'd1505043;
\$auto$proc_rom.cc:150:do_switch$987 [1498] = 32'd17290651;
\$auto$proc_rom.cc:150:do_switch$987 [1499] = 32'd2418272013;
\$auto$proc_rom.cc:150:do_switch$987 [1500] = 32'd2434990326;
\$auto$proc_rom.cc:150:do_switch$987 [1501] = 32'd3187474614;
\$auto$proc_rom.cc:150:do_switch$987 [1502] = 32'd17291163;
\$auto$proc_rom.cc:150:do_switch$987 [1503] = 32'd16154915;
\$auto$proc_rom.cc:150:do_switch$987 [1504] = 32'd571395;
\$auto$proc_rom.cc:150:do_switch$987 [1505] = 32'd3042256141;
\$auto$proc_rom.cc:150:do_switch$987 [1506] = 32'd66723;
\$auto$proc_rom.cc:150:do_switch$987 [1507] = 32'd3042002817;
\$auto$proc_rom.cc:150:do_switch$987 [1508] = 32'd66851;
\$auto$proc_rom.cc:150:do_switch$987 [1509] = 32'd3625694593;
\$auto$proc_rom.cc:150:do_switch$987 [1510] = 32'd3608871047;
\$auto$proc_rom.cc:150:do_switch$987 [1511] = 32'd2149777799;
\$auto$proc_rom.cc:150:do_switch$987 [1512] = 32'd2158166262;
\$auto$proc_rom.cc:150:do_switch$987 [1513] = 32'd2166554886;
\$auto$proc_rom.cc:150:do_switch$987 [1514] = 32'd2174943414;
\$auto$proc_rom.cc:150:do_switch$987 [1515] = 32'd3087204582;
\$auto$proc_rom.cc:150:do_switch$987 [1516] = 32'd3049848840;
\$auto$proc_rom.cc:150:do_switch$987 [1517] = 32'd16154659;
\$auto$proc_rom.cc:150:do_switch$987 [1518] = 32'd3572368355;
\$auto$proc_rom.cc:150:do_switch$987 [1519] = 32'd8902427;
\$auto$proc_rom.cc:150:do_switch$987 [1520] = 32'd15106211;
\$auto$proc_rom.cc:150:do_switch$987 [1521] = 32'd2426651;
\$auto$proc_rom.cc:150:do_switch$987 [1522] = 32'd15599715;
\$auto$proc_rom.cc:150:do_switch$987 [1523] = 32'd17291035;
\$auto$proc_rom.cc:150:do_switch$987 [1524] = 32'd15106339;
\$auto$proc_rom.cc:150:do_switch$987 [1525] = 32'd3475227;
\$auto$proc_rom.cc:150:do_switch$987 [1526] = 32'd1089374011;
\$auto$proc_rom.cc:150:do_switch$987 [1527] = 32'd283330053;
\$auto$proc_rom.cc:150:do_switch$987 [1528] = 32'd3617313479;
\$auto$proc_rom.cc:150:do_switch$987 [1529] = 32'd2174943623;
\$auto$proc_rom.cc:150:do_switch$987 [1530] = 32'd3072393462;
\$auto$proc_rom.cc:150:do_switch$987 [1531] = 32'd2156025213;
\$auto$proc_rom.cc:150:do_switch$987 [1532] = 32'd3800614533;
\$auto$proc_rom.cc:150:do_switch$987 [1533] = 32'd3331113237;
\$auto$proc_rom.cc:150:do_switch$987 [1534] = 32'd3389112709;
\$auto$proc_rom.cc:150:do_switch$987 [1535] = 32'd1430939;
\$auto$proc_rom.cc:150:do_switch$987 [1536] = 32'd12969315;
\$auto$proc_rom.cc:150:do_switch$987 [1537] = 32'd1157744336;
\$auto$proc_rom.cc:150:do_switch$987 [1538] = 32'd2813821058;
\$auto$proc_rom.cc:150:do_switch$987 [1539] = 32'd2274557959;
\$auto$proc_rom.cc:150:do_switch$987 [1540] = 32'd3336311303;
\$auto$proc_rom.cc:150:do_switch$987 [1541] = 32'd2156020993;
\$auto$proc_rom.cc:150:do_switch$987 [1542] = 32'd2156025213;
\$auto$proc_rom.cc:150:do_switch$987 [1543] = 32'd129458448;
\$auto$proc_rom.cc:150:do_switch$987 [1544] = 32'd1186414592;
\$auto$proc_rom.cc:150:do_switch$987 [1545] = 32'd572719119;
\$auto$proc_rom.cc:150:do_switch$987 [1546] = 32'd706936838;
\$auto$proc_rom.cc:150:do_switch$987 [1547] = 32'd3390833158;
\$auto$proc_rom.cc:150:do_switch$987 [1548] = 32'd2284472924;
\$auto$proc_rom.cc:150:do_switch$987 [1549] = 32'd603358867;
\$auto$proc_rom.cc:150:do_switch$987 [1550] = 32'd1073743287;
\$auto$proc_rom.cc:150:do_switch$987 [1551] = 32'd2686527361;
\$auto$proc_rom.cc:150:do_switch$987 [1552] = 32'd662784604;
\$auto$proc_rom.cc:150:do_switch$987 [1553] = 32'd4147365525;
\$auto$proc_rom.cc:150:do_switch$987 [1554] = 32'd2543517879;
\$auto$proc_rom.cc:150:do_switch$987 [1555] = 32'd2413363463;
\$auto$proc_rom.cc:150:do_switch$987 [1556] = 32'd922560385;
\$auto$proc_rom.cc:150:do_switch$987 [1557] = 32'd129497077;
\$auto$proc_rom.cc:150:do_switch$987 [1558] = 32'd3390865408;
\$auto$proc_rom.cc:150:do_switch$987 [1559] = 32'd3525068677;
\$auto$proc_rom.cc:150:do_switch$987 [1560] = 32'd1157712476;
\$auto$proc_rom.cc:150:do_switch$987 [1561] = 32'd23582619;
\$auto$proc_rom.cc:150:do_switch$987 [1562] = 32'd170101637;
\$auto$proc_rom.cc:150:do_switch$987 [1563] = 32'd2156003576;
\$auto$proc_rom.cc:150:do_switch$987 [1564] = 32'd403491;
\$auto$proc_rom.cc:150:do_switch$987 [1565] = 32'd2156025213;
\$auto$proc_rom.cc:150:do_switch$987 [1566] = 32'd4099305757;
\$auto$proc_rom.cc:150:do_switch$987 [1567] = 32'd3968232069;
\$auto$proc_rom.cc:150:do_switch$987 [1568] = 32'd3836143778;
\$auto$proc_rom.cc:150:do_switch$987 [1569] = 32'd4233027786;
\$auto$proc_rom.cc:150:do_switch$987 [1570] = 32'd4032493650;
\$auto$proc_rom.cc:150:do_switch$987 [1571] = 32'd3898797150;
\$auto$proc_rom.cc:150:do_switch$987 [1572] = 32'd2324948070;
\$auto$proc_rom.cc:150:do_switch$987 [1573] = 32'd4200824842;
\$auto$proc_rom.cc:150:do_switch$987 [1574] = 32'd2317027514;
\$auto$proc_rom.cc:150:do_switch$987 [1575] = 32'd2335866869;
\$auto$proc_rom.cc:150:do_switch$987 [1576] = 32'd12212123;
\$auto$proc_rom.cc:150:do_switch$987 [1577] = 32'd2332394670;
\$auto$proc_rom.cc:150:do_switch$987 [1578] = 32'd2849555;
\$auto$proc_rom.cc:150:do_switch$987 [1579] = 32'd12212763;
\$auto$proc_rom.cc:150:do_switch$987 [1580] = 32'd981322685;
\$auto$proc_rom.cc:150:do_switch$987 [1581] = 32'd658459;
\$auto$proc_rom.cc:150:do_switch$987 [1582] = 32'd2343180802;
\$auto$proc_rom.cc:150:do_switch$987 [1583] = 32'd2310441266;
\$auto$proc_rom.cc:150:do_switch$987 [1584] = 32'd34232851;
\$auto$proc_rom.cc:150:do_switch$987 [1585] = 32'd2362852353;
\$auto$proc_rom.cc:150:do_switch$987 [1586] = 32'd241412129;
\$auto$proc_rom.cc:150:do_switch$987 [1587] = 32'd127599940;
\$auto$proc_rom.cc:150:do_switch$987 [1588] = 32'd2270822420;
\$auto$proc_rom.cc:150:do_switch$987 [1589] = 32'd25658211;
\$auto$proc_rom.cc:150:do_switch$987 [1590] = 32'd67454721;
\$auto$proc_rom.cc:150:do_switch$987 [1591] = 32'd2147779739;
\$auto$proc_rom.cc:150:do_switch$987 [1592] = 32'd296347;
\$auto$proc_rom.cc:150:do_switch$987 [1593] = 32'd10155107;
\$auto$proc_rom.cc:150:do_switch$987 [1594] = 32'd820635;
\$auto$proc_rom.cc:150:do_switch$987 [1595] = 32'd90392065;
\$auto$proc_rom.cc:150:do_switch$987 [1596] = 32'd370343945;
\$auto$proc_rom.cc:150:do_switch$987 [1597] = 32'd2521432196;
\$auto$proc_rom.cc:150:do_switch$987 [1598] = 32'd2237875841;
\$auto$proc_rom.cc:150:do_switch$987 [1599] = 32'd378732553;
\$auto$proc_rom.cc:150:do_switch$987 [1600] = 32'd2530082948;
\$auto$proc_rom.cc:150:do_switch$987 [1601] = 32'd4042229086;
\$auto$proc_rom.cc:150:do_switch$987 [1602] = 32'd3512839551;
\$auto$proc_rom.cc:150:do_switch$987 [1603] = 32'd1682333926;
\$auto$proc_rom.cc:150:do_switch$987 [1604] = 32'd1762026662;
\$auto$proc_rom.cc:150:do_switch$987 [1605] = 32'd2051176930;
\$auto$proc_rom.cc:150:do_switch$987 [1606] = 32'd2063760034;
\$auto$proc_rom.cc:150:do_switch$987 [1607] = 32'd1816292322;
\$auto$proc_rom.cc:150:do_switch$987 [1608] = 32'd1629842594;
\$auto$proc_rom.cc:150:do_switch$987 [1609] = 32'd1157726338;
\$auto$proc_rom.cc:150:do_switch$987 [1610] = 32'd1682356181;
\$auto$proc_rom.cc:150:do_switch$987 [1611] = 32'd1688625382;
\$auto$proc_rom.cc:150:do_switch$987 [1612] = 32'd2044881158;
\$auto$proc_rom.cc:150:do_switch$987 [1613] = 32'd2057468482;
\$auto$proc_rom.cc:150:do_switch$987 [1614] = 32'd1810004738;
\$auto$proc_rom.cc:150:do_switch$987 [1615] = 32'd1822583874;
\$auto$proc_rom.cc:150:do_switch$987 [1616] = 32'd3161022757;
\$auto$proc_rom.cc:150:do_switch$987 [1617] = 32'd2269005148;
\$auto$proc_rom.cc:150:do_switch$987 [1618] = 32'd16118627;
\$auto$proc_rom.cc:150:do_switch$987 [1619] = 32'd1159497518;
\$auto$proc_rom.cc:150:do_switch$987 [1620] = 32'd1513243;
\$auto$proc_rom.cc:150:do_switch$987 [1621] = 32'd34018963;
\$auto$proc_rom.cc:150:do_switch$987 [1622] = 32'd394436537;
\$auto$proc_rom.cc:150:do_switch$987 [1623] = 32'd2457965441;
\$auto$proc_rom.cc:150:do_switch$987 [1624] = 32'd3618838525;
\$auto$proc_rom.cc:150:do_switch$987 [1625] = 32'd1732313815;
\$auto$proc_rom.cc:150:do_switch$987 [1626] = 32'd402462589;
\$auto$proc_rom.cc:150:do_switch$987 [1627] = 32'd15201971;
\$auto$proc_rom.cc:150:do_switch$987 [1628] = 32'd16155491;
\$auto$proc_rom.cc:150:do_switch$987 [1629] = 32'd1628735418;
\$auto$proc_rom.cc:150:do_switch$987 [1630] = 32'd1157723713;
\$auto$proc_rom.cc:150:do_switch$987 [1631] = 32'd2406567576;
\$auto$proc_rom.cc:150:do_switch$987 [1632] = 32'd662802393;
\$auto$proc_rom.cc:150:do_switch$987 [1633] = 32'd3470577308;
\$auto$proc_rom.cc:150:do_switch$987 [1634] = 32'd1628995714;
\$auto$proc_rom.cc:150:do_switch$987 [1635] = 32'd31823259;
\$auto$proc_rom.cc:150:do_switch$987 [1636] = 32'd268371639;
\$auto$proc_rom.cc:150:do_switch$987 [1637] = 32'd1157713692;
\$auto$proc_rom.cc:150:do_switch$987 [1638] = 32'd2478905282;
\$auto$proc_rom.cc:150:do_switch$987 [1639] = 32'd2413137869;
\$auto$proc_rom.cc:150:do_switch$987 [1640] = 32'd3474728833;
\$auto$proc_rom.cc:150:do_switch$987 [1641] = 32'd2156056412;
\$auto$proc_rom.cc:150:do_switch$987 [1642] = 32'd4163006777;
\$auto$proc_rom.cc:150:do_switch$987 [1643] = 32'd4031444006;
\$auto$proc_rom.cc:150:do_switch$987 [1644] = 32'd3964599302;
\$auto$proc_rom.cc:150:do_switch$987 [1645] = 32'd3830900818;
\$auto$proc_rom.cc:150:do_switch$987 [1646] = 32'd1895891072;
\$auto$proc_rom.cc:150:do_switch$987 [1647] = 32'd1183155338;
\$auto$proc_rom.cc:150:do_switch$987 [1648] = 32'd2250666241;
\$auto$proc_rom.cc:150:do_switch$987 [1649] = 32'd2301248901;
\$auto$proc_rom.cc:150:do_switch$987 [1650] = 32'd1346371823;
\$auto$proc_rom.cc:150:do_switch$987 [1651] = 32'd302324835;
\$auto$proc_rom.cc:150:do_switch$987 [1652] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1653] = 32'd3011839251;
\$auto$proc_rom.cc:150:do_switch$987 [1654] = 32'd2376069359;
\$auto$proc_rom.cc:150:do_switch$987 [1655] = 32'd353853580;
\$auto$proc_rom.cc:150:do_switch$987 [1656] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1657] = 32'd4042241189;
\$auto$proc_rom.cc:150:do_switch$987 [1658] = 32'd1150061759;
\$auto$proc_rom.cc:150:do_switch$987 [1659] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1660] = 32'd3041199379;
\$auto$proc_rom.cc:150:do_switch$987 [1661] = 32'd2346709231;
\$auto$proc_rom.cc:150:do_switch$987 [1662] = 32'd353846476;
\$auto$proc_rom.cc:150:do_switch$987 [1663] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1664] = 32'd4042241509;
\$auto$proc_rom.cc:150:do_switch$987 [1665] = 32'd1221364479;
\$auto$proc_rom.cc:150:do_switch$987 [1666] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1667] = 32'd3062170899;
\$auto$proc_rom.cc:150:do_switch$987 [1668] = 32'd2317349103;
\$auto$proc_rom.cc:150:do_switch$987 [1669] = 32'd353856652;
\$auto$proc_rom.cc:150:do_switch$987 [1670] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1671] = 32'd4042241829;
\$auto$proc_rom.cc:150:do_switch$987 [1672] = 32'd1888258367;
\$auto$proc_rom.cc:150:do_switch$987 [1673] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1674] = 32'd3083142419;
\$auto$proc_rom.cc:150:do_switch$987 [1675] = 32'd2287988975;
\$auto$proc_rom.cc:150:do_switch$987 [1676] = 32'd353854636;
\$auto$proc_rom.cc:150:do_switch$987 [1677] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1678] = 32'd4042242277;
\$auto$proc_rom.cc:150:do_switch$987 [1679] = 32'd1219266431;
\$auto$proc_rom.cc:150:do_switch$987 [1680] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1681] = 32'd3120891155;
\$auto$proc_rom.cc:150:do_switch$987 [1682] = 32'd2258628847;
\$auto$proc_rom.cc:150:do_switch$987 [1683] = 32'd353847532;
\$auto$proc_rom.cc:150:do_switch$987 [1684] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1685] = 32'd4042242981;
\$auto$proc_rom.cc:150:do_switch$987 [1686] = 32'd1152157119;
\$auto$proc_rom.cc:150:do_switch$987 [1687] = 32'd1183155530;
\$auto$proc_rom.cc:150:do_switch$987 [1688] = 32'd15697418;
\$auto$proc_rom.cc:150:do_switch$987 [1689] = 32'd2318026400;
\$auto$proc_rom.cc:150:do_switch$987 [1690] = 32'd134285587;
\$auto$proc_rom.cc:150:do_switch$987 [1691] = 32'd1251035521;
\$auto$proc_rom.cc:150:do_switch$987 [1692] = 32'd353886549;
\$auto$proc_rom.cc:150:do_switch$987 [1693] = 32'd2244870144;
\$auto$proc_rom.cc:150:do_switch$987 [1694] = 32'd3202680083;
\$auto$proc_rom.cc:150:do_switch$987 [1695] = 32'd2204102895;
\$auto$proc_rom.cc:150:do_switch$987 [1696] = 32'd4194907523;
\$auto$proc_rom.cc:150:do_switch$987 [1697] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1698] = 32'd3217360147;
\$auto$proc_rom.cc:150:do_switch$987 [1699] = 32'd2187325679;
\$auto$proc_rom.cc:150:do_switch$987 [1700] = 32'd4203296131;
\$auto$proc_rom.cc:150:do_switch$987 [1701] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1702] = 32'd3225748755;
\$auto$proc_rom.cc:150:do_switch$987 [1703] = 32'd2170548463;
\$auto$proc_rom.cc:150:do_switch$987 [1704] = 32'd4211684739;
\$auto$proc_rom.cc:150:do_switch$987 [1705] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1706] = 32'd3234137363;
\$auto$proc_rom.cc:150:do_switch$987 [1707] = 32'd2153771247;
\$auto$proc_rom.cc:150:do_switch$987 [1708] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1709] = 32'd3246720275;
\$auto$proc_rom.cc:150:do_switch$987 [1710] = 32'd4287623407;
\$auto$proc_rom.cc:150:do_switch$987 [1711] = 32'd4220060819;
\$auto$proc_rom.cc:150:do_switch$987 [1712] = 32'd312707;
\$auto$proc_rom.cc:150:do_switch$987 [1713] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1714] = 32'd85132421;
\$auto$proc_rom.cc:150:do_switch$987 [1715] = 32'd4042244293;
\$auto$proc_rom.cc:150:do_switch$987 [1716] = 32'd2548301359;
\$auto$proc_rom.cc:150:do_switch$987 [1717] = 32'd85458724;
\$auto$proc_rom.cc:150:do_switch$987 [1718] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1719] = 32'd696612645;
\$auto$proc_rom.cc:150:do_switch$987 [1720] = 32'd4245680367;
\$auto$proc_rom.cc:150:do_switch$987 [1721] = 32'd134809875;
\$auto$proc_rom.cc:150:do_switch$987 [1722] = 32'd4183397859;
\$auto$proc_rom.cc:150:do_switch$987 [1723] = 32'd4228120851;
\$auto$proc_rom.cc:150:do_switch$987 [1724] = 32'd2236772578;
\$auto$proc_rom.cc:150:do_switch$987 [1725] = 32'd1956803650;
\$auto$proc_rom.cc:150:do_switch$987 [1726] = 32'd1776449794;
\$auto$proc_rom.cc:150:do_switch$987 [1727] = 32'd1789028930;
\$auto$proc_rom.cc:150:do_switch$987 [1728] = 32'd2156028193;
\$auto$proc_rom.cc:150:do_switch$987 [1729] = 32'd353864234;
\$auto$proc_rom.cc:150:do_switch$987 [1730] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1731] = 32'd4042235301;
\$auto$proc_rom.cc:150:do_switch$987 [1732] = 32'd3219782191;
\$auto$proc_rom.cc:150:do_switch$987 [1733] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1734] = 32'd2982479123;
\$auto$proc_rom.cc:150:do_switch$987 [1735] = 32'd4182765807;
\$auto$proc_rom.cc:150:do_switch$987 [1736] = 32'd1899608049;
\$auto$proc_rom.cc:150:do_switch$987 [1737] = 32'd4031445026;
\$auto$proc_rom.cc:150:do_switch$987 [1738] = 32'd3897748558;
\$auto$proc_rom.cc:150:do_switch$987 [1739] = 32'd4228310102;
\$auto$proc_rom.cc:150:do_switch$987 [1740] = 32'd8451110;
\$auto$proc_rom.cc:150:do_switch$987 [1741] = 32'd2324328705;
\$auto$proc_rom.cc:150:do_switch$987 [1742] = 32'd2318567726;
\$auto$proc_rom.cc:150:do_switch$987 [1743] = 32'd1183150337;
\$auto$proc_rom.cc:150:do_switch$987 [1744] = 32'd1166378582;
\$auto$proc_rom.cc:150:do_switch$987 [1745] = 32'd15698346;
\$auto$proc_rom.cc:150:do_switch$987 [1746] = 32'd3977590880;
\$auto$proc_rom.cc:150:do_switch$987 [1747] = 32'd76195203;
\$auto$proc_rom.cc:150:do_switch$987 [1748] = 32'd2248820357;
\$auto$proc_rom.cc:150:do_switch$987 [1749] = 32'd15697230;
\$auto$proc_rom.cc:150:do_switch$987 [1750] = 32'd2225747808;
\$auto$proc_rom.cc:150:do_switch$987 [1751] = 32'd396094733;
\$auto$proc_rom.cc:150:do_switch$987 [1752] = 32'd394395769;
\$auto$proc_rom.cc:150:do_switch$987 [1753] = 32'd2542441345;
\$auto$proc_rom.cc:150:do_switch$987 [1754] = 32'd539194268;
\$auto$proc_rom.cc:150:do_switch$987 [1755] = 32'd18022650;
\$auto$proc_rom.cc:150:do_switch$987 [1756] = 32'd1893923844;
\$auto$proc_rom.cc:150:do_switch$987 [1757] = 32'd1950516518;
\$auto$proc_rom.cc:150:do_switch$987 [1758] = 32'd2030204066;
\$auto$proc_rom.cc:150:do_switch$987 [1759] = 32'd1782737378;
\$auto$proc_rom.cc:150:do_switch$987 [1760] = 32'd1629579938;
\$auto$proc_rom.cc:150:do_switch$987 [1761] = 32'd2225766530;
\$auto$proc_rom.cc:150:do_switch$987 [1762] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1763] = 32'd2508522771;
\$auto$proc_rom.cc:150:do_switch$987 [1764] = 32'd4061130991;
\$auto$proc_rom.cc:150:do_switch$987 [1765] = 32'd353877993;
\$auto$proc_rom.cc:150:do_switch$987 [1766] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1767] = 32'd4042238373;
\$auto$proc_rom.cc:150:do_switch$987 [1768] = 32'd3086086447;
\$auto$proc_rom.cc:150:do_switch$987 [1769] = 32'd33986323;
\$auto$proc_rom.cc:150:do_switch$987 [1770] = 32'd1132562323;
\$auto$proc_rom.cc:150:do_switch$987 [1771] = 32'd1901695745;
\$auto$proc_rom.cc:150:do_switch$987 [1772] = 32'd4037187514;
\$auto$proc_rom.cc:150:do_switch$987 [1773] = 32'd508931;
\$auto$proc_rom.cc:150:do_switch$987 [1774] = 32'd4102482122;
\$auto$proc_rom.cc:150:do_switch$987 [1775] = 32'd3410203;
\$auto$proc_rom.cc:150:do_switch$987 [1776] = 32'd3838766246;
\$auto$proc_rom.cc:150:do_switch$987 [1777] = 32'd4233552082;
\$auto$proc_rom.cc:150:do_switch$987 [1778] = 32'd4099864666;
\$auto$proc_rom.cc:150:do_switch$987 [1779] = 32'd3966169186;
\$auto$proc_rom.cc:150:do_switch$987 [1780] = 32'd2031347818;
\$auto$proc_rom.cc:150:do_switch$987 [1781] = 32'd1201741769;
\$auto$proc_rom.cc:150:do_switch$987 [1782] = 32'd321383011;
\$auto$proc_rom.cc:150:do_switch$987 [1783] = 32'd17143579;
\$auto$proc_rom.cc:150:do_switch$987 [1784] = 32'd17258267;
\$auto$proc_rom.cc:150:do_switch$987 [1785] = 32'd8755227;
\$auto$proc_rom.cc:150:do_switch$987 [1786] = 32'd8869659;
\$auto$proc_rom.cc:150:do_switch$987 [1787] = 32'd42324755;
\$auto$proc_rom.cc:150:do_switch$987 [1788] = 32'd33937555;
\$auto$proc_rom.cc:150:do_switch$987 [1789] = 32'd17160083;
\$auto$proc_rom.cc:150:do_switch$987 [1790] = 32'd15231027;
\$auto$proc_rom.cc:150:do_switch$987 [1791] = 32'd2368899638;
\$auto$proc_rom.cc:150:do_switch$987 [1792] = 32'd1182877445;
\$auto$proc_rom.cc:150:do_switch$987 [1793] = 32'd93554186;
\$auto$proc_rom.cc:150:do_switch$987 [1794] = 32'd2334786304;
\$auto$proc_rom.cc:150:do_switch$987 [1795] = 32'd6357027;
\$auto$proc_rom.cc:150:do_switch$987 [1796] = 32'd17891491;
\$auto$proc_rom.cc:150:do_switch$987 [1797] = 32'd65827;
\$auto$proc_rom.cc:150:do_switch$987 [1798] = 32'd15794595;
\$auto$proc_rom.cc:150:do_switch$987 [1799] = 32'd16847395;
\$auto$proc_rom.cc:150:do_switch$987 [1800] = 32'd3315593455;
\$auto$proc_rom.cc:150:do_switch$987 [1801] = 32'd3430542637;
\$auto$proc_rom.cc:150:do_switch$987 [1802] = 32'd3742739;
\$auto$proc_rom.cc:150:do_switch$987 [1803] = 32'd1267026305;
\$auto$proc_rom.cc:150:do_switch$987 [1804] = 32'd1250247809;
\$auto$proc_rom.cc:150:do_switch$987 [1805] = 32'd79694995;
\$auto$proc_rom.cc:150:do_switch$987 [1806] = 32'd3426049;
\$auto$proc_rom.cc:150:do_switch$987 [1807] = 32'd2246198785;
\$auto$proc_rom.cc:150:do_switch$987 [1808] = 32'd4042229082;
\$auto$proc_rom.cc:150:do_switch$987 [1809] = 32'd3978412927;
\$auto$proc_rom.cc:150:do_switch$987 [1810] = 32'd4262004963;
\$auto$proc_rom.cc:150:do_switch$987 [1811] = 32'd83331;
\$auto$proc_rom.cc:150:do_switch$987 [1812] = 32'd1199898680;
\$auto$proc_rom.cc:150:do_switch$987 [1813] = 32'd627811;
\$auto$proc_rom.cc:150:do_switch$987 [1814] = 32'd60130659;
\$auto$proc_rom.cc:150:do_switch$987 [1815] = 32'd134472841;
\$auto$proc_rom.cc:150:do_switch$987 [1816] = 32'd1264779271;
\$auto$proc_rom.cc:150:do_switch$987 [1817] = 32'd3358654472;
\$auto$proc_rom.cc:150:do_switch$987 [1818] = 32'd476803;
\$auto$proc_rom.cc:150:do_switch$987 [1819] = 32'd9242675;
\$auto$proc_rom.cc:150:do_switch$987 [1820] = 32'd262358149;
\$auto$proc_rom.cc:150:do_switch$987 [1821] = 32'd880672472;
\$auto$proc_rom.cc:150:do_switch$987 [1822] = 32'd19396707;
\$auto$proc_rom.cc:150:do_switch$987 [1823] = 32'd117778309;
\$auto$proc_rom.cc:150:do_switch$987 [1824] = 32'd1233502161;
\$auto$proc_rom.cc:150:do_switch$987 [1825] = 32'd4280806627;
\$auto$proc_rom.cc:150:do_switch$987 [1826] = 32'd1199962181;
\$auto$proc_rom.cc:150:do_switch$987 [1827] = 32'd83493987;
\$auto$proc_rom.cc:150:do_switch$987 [1828] = 32'd1182877449;
\$auto$proc_rom.cc:150:do_switch$987 [1829] = 32'd1166099969;
\$auto$proc_rom.cc:150:do_switch$987 [1830] = 32'd4042229082;
\$auto$proc_rom.cc:150:do_switch$987 [1831] = 32'd1889975807;
\$auto$proc_rom.cc:150:do_switch$987 [1832] = 32'd1692824582;
\$auto$proc_rom.cc:150:do_switch$987 [1833] = 32'd1772513606;
\$auto$proc_rom.cc:150:do_switch$987 [1834] = 32'd2061658630;
\$auto$proc_rom.cc:150:do_switch$987 [1835] = 32'd2074245954;
\$auto$proc_rom.cc:150:do_switch$987 [1836] = 32'd1826782210;
\$auto$proc_rom.cc:150:do_switch$987 [1837] = 32'd1634037058;
\$auto$proc_rom.cc:150:do_switch$987 [1838] = 32'd107184258;
\$auto$proc_rom.cc:150:do_switch$987 [1839] = 32'd4142072154;
\$auto$proc_rom.cc:150:do_switch$987 [1840] = 32'd1149631783;
\$auto$proc_rom.cc:150:do_switch$987 [1841] = 32'd2363735909;
\$auto$proc_rom.cc:150:do_switch$987 [1842] = 32'd1266941451;
\$auto$proc_rom.cc:150:do_switch$987 [1843] = 32'd3146973191;
\$auto$proc_rom.cc:150:do_switch$987 [1844] = 32'd3086286875;
\$auto$proc_rom.cc:150:do_switch$987 [1845] = 32'd4195061475;
\$auto$proc_rom.cc:150:do_switch$987 [1846] = 32'd2224252041;
\$auto$proc_rom.cc:150:do_switch$987 [1847] = 32'd6320388;
\$auto$proc_rom.cc:150:do_switch$987 [1848] = 32'd3426049;
\$auto$proc_rom.cc:150:do_switch$987 [1849] = 32'd93537793;
\$auto$proc_rom.cc:150:do_switch$987 [1850] = 32'd2237268480;
\$auto$proc_rom.cc:150:do_switch$987 [1851] = 32'd3101683951;
\$auto$proc_rom.cc:150:do_switch$987 [1852] = 32'd3338862652;
\$auto$proc_rom.cc:150:do_switch$987 [1853] = 32'd126156807;
\$auto$proc_rom.cc:150:do_switch$987 [1854] = 32'd484704065;
\$auto$proc_rom.cc:150:do_switch$987 [1855] = 32'd889061108;
\$auto$proc_rom.cc:150:do_switch$987 [1856] = 32'd3078222053;
\$auto$proc_rom.cc:150:do_switch$987 [1857] = 32'd367216517;
\$auto$proc_rom.cc:150:do_switch$987 [1858] = 32'd3086612730;
\$auto$proc_rom.cc:150:do_switch$987 [1859] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1860] = 32'd85165474;
\$auto$proc_rom.cc:150:do_switch$987 [1861] = 32'd4042235077;
\$auto$proc_rom.cc:150:do_switch$987 [1862] = 32'd1434311087;
\$auto$proc_rom.cc:150:do_switch$987 [1863] = 32'd1899607881;
\$auto$proc_rom.cc:150:do_switch$987 [1864] = 32'd1182877441;
\$auto$proc_rom.cc:150:do_switch$987 [1865] = 32'd93537793;
\$auto$proc_rom.cc:150:do_switch$987 [1866] = 32'd4162979072;
\$auto$proc_rom.cc:150:do_switch$987 [1867] = 32'd4228314150;
\$auto$proc_rom.cc:150:do_switch$987 [1868] = 32'd3964596298;
\$auto$proc_rom.cc:150:do_switch$987 [1869] = 32'd3825370282;
\$auto$proc_rom.cc:150:do_switch$987 [1870] = 32'd3021992175;
\$auto$proc_rom.cc:150:do_switch$987 [1871] = 32'd3372844074;
\$auto$proc_rom.cc:150:do_switch$987 [1872] = 32'd2233626850;
\$auto$proc_rom.cc:150:do_switch$987 [1873] = 32'd1956803650;
\$auto$proc_rom.cc:150:do_switch$987 [1874] = 32'd1776449794;
\$auto$proc_rom.cc:150:do_switch$987 [1875] = 32'd2156028193;
\$auto$proc_rom.cc:150:do_switch$987 [1876] = 32'd361974021;
\$auto$proc_rom.cc:150:do_switch$987 [1877] = 32'd1182860009;
\$auto$proc_rom.cc:150:do_switch$987 [1878] = 32'd2241003568;
\$auto$proc_rom.cc:150:do_switch$987 [1879] = 32'd2233862485;
\$auto$proc_rom.cc:150:do_switch$987 [1880] = 32'd3831492847;
\$auto$proc_rom.cc:150:do_switch$987 [1881] = 32'd4251550762;
\$auto$proc_rom.cc:150:do_switch$987 [1882] = 32'd353854882;
\$auto$proc_rom.cc:150:do_switch$987 [1883] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1884] = 32'd4187200101;
\$auto$proc_rom.cc:150:do_switch$987 [1885] = 32'd2216366069;
\$auto$proc_rom.cc:150:do_switch$987 [1886] = 32'd4042194953;
\$auto$proc_rom.cc:150:do_switch$987 [1887] = 32'd2447627119;
\$auto$proc_rom.cc:150:do_switch$987 [1888] = 32'd395836713;
\$auto$proc_rom.cc:150:do_switch$987 [1889] = 32'd3045261312;
\$auto$proc_rom.cc:150:do_switch$987 [1890] = 32'd1184742887;
\$auto$proc_rom.cc:150:do_switch$987 [1891] = 32'd2233860144;
\$auto$proc_rom.cc:150:do_switch$987 [1892] = 32'd4042253314;
\$auto$proc_rom.cc:150:do_switch$987 [1893] = 32'd2217402687;
\$auto$proc_rom.cc:150:do_switch$987 [1894] = 32'd1680012613;
\$auto$proc_rom.cc:150:do_switch$987 [1895] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1896] = 32'd2571437331;
\$auto$proc_rom.cc:150:do_switch$987 [1897] = 32'd4042229154;
\$auto$proc_rom.cc:150:do_switch$987 [1898] = 32'd395563183;
\$auto$proc_rom.cc:150:do_switch$987 [1899] = 32'd427950468;
\$auto$proc_rom.cc:150:do_switch$987 [1900] = 32'd2308146145;
\$auto$proc_rom.cc:150:do_switch$987 [1901] = 32'd1947409065;
\$auto$proc_rom.cc:150:do_switch$987 [1902] = 32'd2481131508;
\$auto$proc_rom.cc:150:do_switch$987 [1903] = 32'd152303927;
\$auto$proc_rom.cc:150:do_switch$987 [1904] = 32'd421660528;
\$auto$proc_rom.cc:150:do_switch$987 [1905] = 32'd3163777;
\$auto$proc_rom.cc:150:do_switch$987 [1906] = 32'd106497427;
\$auto$proc_rom.cc:150:do_switch$987 [1907] = 32'd3825370406;
\$auto$proc_rom.cc:150:do_switch$987 [1908] = 32'd3714052335;
\$auto$proc_rom.cc:150:do_switch$987 [1909] = 32'd4113400874;
\$auto$proc_rom.cc:150:do_switch$987 [1910] = 32'd353854882;
\$auto$proc_rom.cc:150:do_switch$987 [1911] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1912] = 32'd160667493;
\$auto$proc_rom.cc:150:do_switch$987 [1913] = 32'd4042201680;
\$auto$proc_rom.cc:150:do_switch$987 [1914] = 32'd429575343;
\$auto$proc_rom.cc:150:do_switch$987 [1915] = 32'd3163777;
\$auto$proc_rom.cc:150:do_switch$987 [1916] = 32'd125404563;
\$auto$proc_rom.cc:150:do_switch$987 [1917] = 32'd3825370406;
\$auto$proc_rom.cc:150:do_switch$987 [1918] = 32'd3672109295;
\$auto$proc_rom.cc:150:do_switch$987 [1919] = 32'd4046029866;
\$auto$proc_rom.cc:150:do_switch$987 [1920] = 32'd353854498;
\$auto$proc_rom.cc:150:do_switch$987 [1921] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1922] = 32'd2242025189;
\$auto$proc_rom.cc:150:do_switch$987 [1923] = 32'd267678739;
\$auto$proc_rom.cc:150:do_switch$987 [1924] = 32'd3390042351;
\$auto$proc_rom.cc:150:do_switch$987 [1925] = 32'd152291385;
\$auto$proc_rom.cc:150:do_switch$987 [1926] = 32'd2308114009;
\$auto$proc_rom.cc:150:do_switch$987 [1927] = 32'd1182861177;
\$auto$proc_rom.cc:150:do_switch$987 [1928] = 32'd2244608048;
\$auto$proc_rom.cc:150:do_switch$987 [1929] = 32'd3825370406;
\$auto$proc_rom.cc:150:do_switch$987 [1930] = 32'd3621777647;
\$auto$proc_rom.cc:150:do_switch$987 [1931] = 32'd353862698;
\$auto$proc_rom.cc:150:do_switch$987 [1932] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [1933] = 32'd367235621;
\$auto$proc_rom.cc:150:do_switch$987 [1934] = 32'd1705177092;
\$auto$proc_rom.cc:150:do_switch$987 [1935] = 32'd3343905007;
\$auto$proc_rom.cc:150:do_switch$987 [1936] = 32'd3163777;
\$auto$proc_rom.cc:150:do_switch$987 [1937] = 32'd2233894350;
\$auto$proc_rom.cc:150:do_switch$987 [1938] = 32'd4042253314;
\$auto$proc_rom.cc:150:do_switch$987 [1939] = 32'd2217399743;
\$auto$proc_rom.cc:150:do_switch$987 [1940] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1941] = 32'd2449802515;
\$auto$proc_rom.cc:150:do_switch$987 [1942] = 32'd3993244899;
\$auto$proc_rom.cc:150:do_switch$987 [1943] = 32'd2242012194;
\$auto$proc_rom.cc:150:do_switch$987 [1944] = 32'd267678739;
\$auto$proc_rom.cc:150:do_switch$987 [1945] = 32'd3301961967;
\$auto$proc_rom.cc:150:do_switch$987 [1946] = 32'd93583453;
\$auto$proc_rom.cc:150:do_switch$987 [1947] = 32'd363201488;
\$auto$proc_rom.cc:150:do_switch$987 [1948] = 32'd3163789;
\$auto$proc_rom.cc:150:do_switch$987 [1949] = 32'd267748755;
\$auto$proc_rom.cc:150:do_switch$987 [1950] = 32'd3825370406;
\$auto$proc_rom.cc:150:do_switch$987 [1951] = 32'd3533697263;
\$auto$proc_rom.cc:150:do_switch$987 [1952] = 32'd535004202;
\$auto$proc_rom.cc:150:do_switch$987 [1953] = 32'd1705175557;
\$auto$proc_rom.cc:150:do_switch$987 [1954] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1955] = 32'd2424636691;
\$auto$proc_rom.cc:150:do_switch$987 [1956] = 32'd3255824623;
\$auto$proc_rom.cc:150:do_switch$987 [1957] = 32'd6039;
\$auto$proc_rom.cc:150:do_switch$987 [1958] = 32'd2907157891;
\$auto$proc_rom.cc:150:do_switch$987 [1959] = 32'd3163777;
\$auto$proc_rom.cc:150:do_switch$987 [1960] = 32'd3825370406;
\$auto$proc_rom.cc:150:do_switch$987 [1961] = 32'd3491754223;
\$auto$proc_rom.cc:150:do_switch$987 [1962] = 32'd467895338;
\$auto$proc_rom.cc:150:do_switch$987 [1963] = 32'd1688397829;
\$auto$proc_rom.cc:150:do_switch$987 [1964] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [1965] = 32'd2416248083;
\$auto$proc_rom.cc:150:do_switch$987 [1966] = 32'd4103308710;
\$auto$proc_rom.cc:150:do_switch$987 [1967] = 32'd4042199028;
\$auto$proc_rom.cc:150:do_switch$987 [1968] = 32'd2414067503;
\$auto$proc_rom.cc:150:do_switch$987 [1969] = 32'd2216420868;
\$auto$proc_rom.cc:150:do_switch$987 [1970] = 32'd3181182980;
\$auto$proc_rom.cc:150:do_switch$987 [1971] = 32'd4171395353;
\$auto$proc_rom.cc:150:do_switch$987 [1972] = 32'd4104584326;
\$auto$proc_rom.cc:150:do_switch$987 [1973] = 32'd3972985034;
\$auto$proc_rom.cc:150:do_switch$987 [1974] = 32'd3839289554;
\$auto$proc_rom.cc:150:do_switch$987 [1975] = 32'd4234076378;
\$auto$proc_rom.cc:150:do_switch$987 [1976] = 32'd4100388962;
\$auto$proc_rom.cc:150:do_switch$987 [1977] = 32'd3966693482;
\$auto$proc_rom.cc:150:do_switch$987 [1978] = 32'd2153989121;
\$auto$proc_rom.cc:150:do_switch$987 [1979] = 32'd2484802054;
\$auto$proc_rom.cc:150:do_switch$987 [1980] = 32'd335675525;
\$auto$proc_rom.cc:150:do_switch$987 [1981] = 32'd2335590149;
\$auto$proc_rom.cc:150:do_switch$987 [1982] = 32'd2226293034;
\$auto$proc_rom.cc:150:do_switch$987 [1983] = 32'd2254671873;
\$auto$proc_rom.cc:150:do_switch$987 [1984] = 32'd118690534;
\$auto$proc_rom.cc:150:do_switch$987 [1985] = 32'd353829520;
\$auto$proc_rom.cc:150:do_switch$987 [1986] = 32'd395509760;
\$auto$proc_rom.cc:150:do_switch$987 [1987] = 32'd2259813015;
\$auto$proc_rom.cc:150:do_switch$987 [1988] = 32'd2251163525;
\$auto$proc_rom.cc:150:do_switch$987 [1989] = 32'd2418345235;
\$auto$proc_rom.cc:150:do_switch$987 [1990] = 32'd2354939354;
\$auto$proc_rom.cc:150:do_switch$987 [1991] = 32'd3109023983;
\$auto$proc_rom.cc:150:do_switch$987 [1992] = 32'd17061779;
\$auto$proc_rom.cc:150:do_switch$987 [1993] = 32'd42227859;
\$auto$proc_rom.cc:150:do_switch$987 [1994] = 32'd25450515;
\$auto$proc_rom.cc:150:do_switch$987 [1995] = 32'd15794595;
\$auto$proc_rom.cc:150:do_switch$987 [1996] = 32'd1199931425;
\$auto$proc_rom.cc:150:do_switch$987 [1997] = 32'd1182877445;
\$auto$proc_rom.cc:150:do_switch$987 [1998] = 32'd93554186;
\$auto$proc_rom.cc:150:do_switch$987 [1999] = 32'd2236220160;
\$auto$proc_rom.cc:150:do_switch$987 [2000] = 32'd8454691;
\$auto$proc_rom.cc:150:do_switch$987 [2001] = 32'd17891363;
\$auto$proc_rom.cc:150:do_switch$987 [2002] = 32'd65699;
\$auto$proc_rom.cc:150:do_switch$987 [2003] = 32'd16843043;
\$auto$proc_rom.cc:150:do_switch$987 [2004] = 32'd15794851;
\$auto$proc_rom.cc:150:do_switch$987 [2005] = 32'd2455761135;
\$auto$proc_rom.cc:150:do_switch$987 [2006] = 32'd3913647146;
\$auto$proc_rom.cc:150:do_switch$987 [2007] = 32'd202591489;
\$auto$proc_rom.cc:150:do_switch$987 [2008] = 32'd1266753536;
\$auto$proc_rom.cc:150:do_switch$987 [2009] = 32'd1234258433;
\$auto$proc_rom.cc:150:do_switch$987 [2010] = 32'd177425797;
\$auto$proc_rom.cc:150:do_switch$987 [2011] = 32'd1284313056;
\$auto$proc_rom.cc:150:do_switch$987 [2012] = 32'd3426049;
\$auto$proc_rom.cc:150:do_switch$987 [2013] = 32'd93537793;
\$auto$proc_rom.cc:150:do_switch$987 [2014] = 32'd2236219904;
\$auto$proc_rom.cc:150:do_switch$987 [2015] = 32'd2413818095;
\$auto$proc_rom.cc:150:do_switch$987 [2016] = 32'd3846276138;
\$auto$proc_rom.cc:150:do_switch$987 [2017] = 32'd274923580;
\$auto$proc_rom.cc:150:do_switch$987 [2018] = 32'd3313697802;
\$auto$proc_rom.cc:150:do_switch$987 [2019] = 32'd604307463;
\$auto$proc_rom.cc:150:do_switch$987 [2020] = 32'd2535131013;
\$auto$proc_rom.cc:150:do_switch$987 [2021] = 32'd1461387653;
\$auto$proc_rom.cc:150:do_switch$987 [2022] = 32'd1583563143;
\$auto$proc_rom.cc:150:do_switch$987 [2023] = 32'd165871623;
\$auto$proc_rom.cc:150:do_switch$987 [2024] = 32'd3313761588;
\$auto$proc_rom.cc:150:do_switch$987 [2025] = 32'd604307463;
\$auto$proc_rom.cc:150:do_switch$987 [2026] = 32'd2535131013;
\$auto$proc_rom.cc:150:do_switch$987 [2027] = 32'd1461387653;
\$auto$proc_rom.cc:150:do_switch$987 [2028] = 32'd1189298567;
\$auto$proc_rom.cc:150:do_switch$987 [2029] = 32'd353893895;
\$auto$proc_rom.cc:150:do_switch$987 [2030] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [2031] = 32'd4042230181;
\$auto$proc_rom.cc:150:do_switch$987 [2032] = 32'd258191151;
\$auto$proc_rom.cc:150:do_switch$987 [2033] = 32'd3932468;
\$auto$proc_rom.cc:150:do_switch$987 [2034] = 32'd3313735586;
\$auto$proc_rom.cc:150:do_switch$987 [2035] = 32'd126156807;
\$auto$proc_rom.cc:150:do_switch$987 [2036] = 32'd252049171;
\$auto$proc_rom.cc:150:do_switch$987 [2037] = 32'd123045731;
\$auto$proc_rom.cc:150:do_switch$987 [2038] = 32'd604358417;
\$auto$proc_rom.cc:150:do_switch$987 [2039] = 32'd4281604067;
\$auto$proc_rom.cc:150:do_switch$987 [2040] = 32'd3078179333;
\$auto$proc_rom.cc:150:do_switch$987 [2041] = 32'd5399;
\$auto$proc_rom.cc:150:do_switch$987 [2042] = 32'd2311390483;
\$auto$proc_rom.cc:150:do_switch$987 [2043] = 32'd2890920175;
\$auto$proc_rom.cc:150:do_switch$987 [2044] = 32'd1182877449;
\$auto$proc_rom.cc:150:do_switch$987 [2045] = 32'd1166099969;
\$auto$proc_rom.cc:150:do_switch$987 [2046] = 32'd4042229066;
\$auto$proc_rom.cc:150:do_switch$987 [2047] = 32'd127109119;
\$auto$proc_rom.cc:150:do_switch$987 [2048] = 32'd2217935108;
\$auto$proc_rom.cc:150:do_switch$987 [2049] = 32'd1141047335;
\$auto$proc_rom.cc:150:do_switch$987 [2050] = 32'd1894186884;
\$auto$proc_rom.cc:150:do_switch$987 [2051] = 32'd1950778658;
\$auto$proc_rom.cc:150:do_switch$987 [2052] = 32'd2030466214;
\$auto$proc_rom.cc:150:do_switch$987 [2053] = 32'd1782999526;
\$auto$proc_rom.cc:150:do_switch$987 [2054] = 32'd1795582630;
\$auto$proc_rom.cc:150:do_switch$987 [2055] = 32'd2084731874;
\$auto$proc_rom.cc:150:do_switch$987 [2056] = 32'd2097314978;
\$auto$proc_rom.cc:150:do_switch$987 [2057] = 32'd1628007906;
\$auto$proc_rom.cc:150:do_switch$987 [2058] = 32'd127107202;
\$auto$proc_rom.cc:150:do_switch$987 [2059] = 32'd85394704;
\$auto$proc_rom.cc:150:do_switch$987 [2060] = 32'd396492800;
\$auto$proc_rom.cc:150:do_switch$987 [2061] = 32'd85133189;
\$auto$proc_rom.cc:150:do_switch$987 [2062] = 32'd2354936357;
\$auto$proc_rom.cc:150:do_switch$987 [2063] = 32'd2807034095;
\$auto$proc_rom.cc:150:do_switch$987 [2064] = 32'd730183109;
\$auto$proc_rom.cc:150:do_switch$987 [2065] = 32'd536872851;
\$auto$proc_rom.cc:150:do_switch$987 [2066] = 32'd224617861;
\$auto$proc_rom.cc:150:do_switch$987 [2067] = 32'd3933076;
\$auto$proc_rom.cc:150:do_switch$987 [2068] = 32'd3762029851;
\$auto$proc_rom.cc:150:do_switch$987 [2069] = 32'd8881843;
\$auto$proc_rom.cc:150:do_switch$987 [2070] = 32'd263579;
\$auto$proc_rom.cc:150:do_switch$987 [2071] = 32'd2280299777;
\$auto$proc_rom.cc:150:do_switch$987 [2072] = 32'd1492483;
\$auto$proc_rom.cc:150:do_switch$987 [2073] = 32'd34051859;
\$auto$proc_rom.cc:150:do_switch$987 [2074] = 32'd2535887617;
\$auto$proc_rom.cc:150:do_switch$987 [2075] = 32'd13041699;
\$auto$proc_rom.cc:150:do_switch$987 [2076] = 32'd109389701;
\$auto$proc_rom.cc:150:do_switch$987 [2077] = 32'd4277475043;
\$auto$proc_rom.cc:150:do_switch$987 [2078] = 32'd534087579;
\$auto$proc_rom.cc:150:do_switch$987 [2079] = 32'd3642779;
\$auto$proc_rom.cc:150:do_switch$987 [2080] = 32'd2474710914;
\$auto$proc_rom.cc:150:do_switch$987 [2081] = 32'd34346643;
\$auto$proc_rom.cc:150:do_switch$987 [2082] = 32'd2392691329;
\$auto$proc_rom.cc:150:do_switch$987 [2083] = 32'd2527479553;
\$auto$proc_rom.cc:150:do_switch$987 [2084] = 32'd2236237313;
\$auto$proc_rom.cc:150:do_switch$987 [2085] = 32'd4266651887;
\$auto$proc_rom.cc:150:do_switch$987 [2086] = 32'd4179985450;
\$auto$proc_rom.cc:150:do_switch$987 [2087] = 32'd3426049;
\$auto$proc_rom.cc:150:do_switch$987 [2088] = 32'd1170294273;
\$auto$proc_rom.cc:150:do_switch$987 [2089] = 32'd4042229066;
\$auto$proc_rom.cc:150:do_switch$987 [2090] = 32'd2217409839;
\$auto$proc_rom.cc:150:do_switch$987 [2091] = 32'd203160889;
\$auto$proc_rom.cc:150:do_switch$987 [2092] = 32'd219881484;
\$auto$proc_rom.cc:150:do_switch$987 [2093] = 32'd1241849869;
\$auto$proc_rom.cc:150:do_switch$987 [2094] = 32'd3950714083;
\$auto$proc_rom.cc:150:do_switch$987 [2095] = 32'd62588003;
\$auto$proc_rom.cc:150:do_switch$987 [2096] = 32'd363480525;
\$auto$proc_rom.cc:150:do_switch$987 [2097] = 32'd1183122821;
\$auto$proc_rom.cc:150:do_switch$987 [2098] = 32'd2236219440;
\$auto$proc_rom.cc:150:do_switch$987 [2099] = 32'd4042253314;
\$auto$proc_rom.cc:150:do_switch$987 [2100] = 32'd1705160063;
\$auto$proc_rom.cc:150:do_switch$987 [2101] = 32'd85427242;
\$auto$proc_rom.cc:150:do_switch$987 [2102] = 32'd85131264;
\$auto$proc_rom.cc:150:do_switch$987 [2103] = 32'd4042226981;
\$auto$proc_rom.cc:150:do_switch$987 [2104] = 32'd3072695599;
\$auto$proc_rom.cc:150:do_switch$987 [2105] = 32'd1182877449;
\$auto$proc_rom.cc:150:do_switch$987 [2106] = 32'd1166099969;
\$auto$proc_rom.cc:150:do_switch$987 [2107] = 32'd4042229066;
\$auto$proc_rom.cc:150:do_switch$987 [2108] = 32'd3206674607;
\$auto$proc_rom.cc:150:do_switch$987 [2109] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2110] = 32'd1769496923;
\$auto$proc_rom.cc:150:do_switch$987 [2111] = 32'd1668050015;
\$auto$proc_rom.cc:150:do_switch$987 [2112] = 32'd1480663133;
\$auto$proc_rom.cc:150:do_switch$987 [2113] = 32'd1280057417;
\$auto$proc_rom.cc:150:do_switch$987 [2114] = 32'd1700143171;
\$auto$proc_rom.cc:150:do_switch$987 [2115] = 32'd1869181810;
\$auto$proc_rom.cc:150:do_switch$987 [2116] = 32'd538976366;
\$auto$proc_rom.cc:150:do_switch$987 [2117] = 32'd538976314;
\$auto$proc_rom.cc:150:do_switch$987 [2118] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2119] = 32'd1814394928;
\$auto$proc_rom.cc:150:do_switch$987 [2120] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2121] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2122] = 32'd1769496923;
\$auto$proc_rom.cc:150:do_switch$987 [2123] = 32'd1668050015;
\$auto$proc_rom.cc:150:do_switch$987 [2124] = 32'd1699946589;
\$auto$proc_rom.cc:150:do_switch$987 [2125] = 32'd1933647988;
\$auto$proc_rom.cc:150:do_switch$987 [2126] = 32'd1768124275;
\$auto$proc_rom.cc:150:do_switch$987 [2127] = 32'd1986622561;
\$auto$proc_rom.cc:150:do_switch$987 [2128] = 32'd544830569;
\$auto$proc_rom.cc:150:do_switch$987 [2129] = 32'd538976314;
\$auto$proc_rom.cc:150:do_switch$987 [2130] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2131] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2132] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2133] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2134] = 32'd1769496923;
\$auto$proc_rom.cc:150:do_switch$987 [2135] = 32'd1668050015;
\$auto$proc_rom.cc:150:do_switch$987 [2136] = 32'd1968054365;
\$auto$proc_rom.cc:150:do_switch$987 [2137] = 32'd1816273005;
\$auto$proc_rom.cc:150:do_switch$987 [2138] = 32'd1936417647;
\$auto$proc_rom.cc:150:do_switch$987 [2139] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2140] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2141] = 32'd538976314;
\$auto$proc_rom.cc:150:do_switch$987 [2142] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2143] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2144] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2145] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2146] = 32'd1769496923;
\$auto$proc_rom.cc:150:do_switch$987 [2147] = 32'd1668050015;
\$auto$proc_rom.cc:150:do_switch$987 [2148] = 32'd1968054365;
\$auto$proc_rom.cc:150:do_switch$987 [2149] = 32'd1766596717;
\$auto$proc_rom.cc:150:do_switch$987 [2150] = 32'd544433518;
\$auto$proc_rom.cc:150:do_switch$987 [2151] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2152] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2153] = 32'd538976314;
\$auto$proc_rom.cc:150:do_switch$987 [2154] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2155] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2156] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2157] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2158] = 32'd1769496923;
\$auto$proc_rom.cc:150:do_switch$987 [2159] = 32'd1668050015;
\$auto$proc_rom.cc:150:do_switch$987 [2160] = 32'd1229070429;
\$auto$proc_rom.cc:150:do_switch$987 [2161] = 32'd1327518803;
\$auto$proc_rom.cc:150:do_switch$987 [2162] = 32'd1868788853;
\$auto$proc_rom.cc:150:do_switch$987 [2163] = 32'd538994029;
\$auto$proc_rom.cc:150:do_switch$987 [2164] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2165] = 32'd538976314;
\$auto$proc_rom.cc:150:do_switch$987 [2166] = 32'd538976288;
\$auto$proc_rom.cc:150:do_switch$987 [2167] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2168] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2169] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2170] = 32'd1768976195;
\$auto$proc_rom.cc:150:do_switch$987 [2171] = 32'd1679844453;
\$auto$proc_rom.cc:150:do_switch$987 [2172] = 32'd1667855973;
\$auto$proc_rom.cc:150:do_switch$987 [2173] = 32'd1920213093;
\$auto$proc_rom.cc:150:do_switch$987 [2174] = 32'd1948280165;
\$auto$proc_rom.cc:150:do_switch$987 [2175] = 32'd2016419951;
\$auto$proc_rom.cc:150:do_switch$987 [2176] = 32'd225995813;
\$auto$proc_rom.cc:150:do_switch$987 [2177] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2178] = 32'd1768976195;
\$auto$proc_rom.cc:150:do_switch$987 [2179] = 32'd1713398885;
\$auto$proc_rom.cc:150:do_switch$987 [2180] = 32'd2003661417;
\$auto$proc_rom.cc:150:do_switch$987 [2181] = 32'd543519329;
\$auto$proc_rom.cc:150:do_switch$987 [2182] = 32'd807432052;
\$auto$proc_rom.cc:150:do_switch$987 [2183] = 32'd2020353400;
\$auto$proc_rom.cc:150:do_switch$987 [2184] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2185] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2186] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2187] = 32'd1701080941;
\$auto$proc_rom.cc:150:do_switch$987 [2188] = 32'd540684320;
\$auto$proc_rom.cc:150:do_switch$987 [2189] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2190] = 32'd543649385;
\$auto$proc_rom.cc:150:do_switch$987 [2191] = 32'd1836020326;
\$auto$proc_rom.cc:150:do_switch$987 [2192] = 32'd541348640;
\$auto$proc_rom.cc:150:do_switch$987 [2193] = 32'd1685217603;
\$auto$proc_rom.cc:150:do_switch$987 [2194] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2195] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2196] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2197] = 32'd1701080941;
\$auto$proc_rom.cc:150:do_switch$987 [2198] = 32'd540684576;
\$auto$proc_rom.cc:150:do_switch$987 [2199] = 32'd1852403524;
\$auto$proc_rom.cc:150:do_switch$987 [2200] = 32'd1869488231;
\$auto$proc_rom.cc:150:do_switch$987 [2201] = 32'd1852401780;
\$auto$proc_rom.cc:150:do_switch$987 [2202] = 32'd691675239;
\$auto$proc_rom.cc:150:do_switch$987 [2203] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2204] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2205] = 32'd1701080941;
\$auto$proc_rom.cc:150:do_switch$987 [2206] = 32'd540684832;
\$auto$proc_rom.cc:150:do_switch$987 [2207] = 32'd1852403524;
\$auto$proc_rom.cc:150:do_switch$987 [2208] = 32'd1869488231;
\$auto$proc_rom.cc:150:do_switch$987 [2209] = 32'd1852401780;
\$auto$proc_rom.cc:150:do_switch$987 [2210] = 32'd691675239;
\$auto$proc_rom.cc:150:do_switch$987 [2211] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2212] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2213] = 32'd1701080941;
\$auto$proc_rom.cc:150:do_switch$987 [2214] = 32'd540685088;
\$auto$proc_rom.cc:150:do_switch$987 [2215] = 32'd1852403524;
\$auto$proc_rom.cc:150:do_switch$987 [2216] = 32'd1869488231;
\$auto$proc_rom.cc:150:do_switch$987 [2217] = 32'd1852401780;
\$auto$proc_rom.cc:150:do_switch$987 [2218] = 32'd691675239;
\$auto$proc_rom.cc:150:do_switch$987 [2219] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2220] = 32'd1953460034;
\$auto$proc_rom.cc:150:do_switch$987 [2221] = 32'd1701080941;
\$auto$proc_rom.cc:150:do_switch$987 [2222] = 32'd979641632;
\$auto$proc_rom.cc:150:do_switch$987 [2223] = 32'd1768899616;
\$auto$proc_rom.cc:150:do_switch$987 [2224] = 32'd1847617390;
\$auto$proc_rom.cc:150:do_switch$987 [2225] = 32'd1768453231;
\$auto$proc_rom.cc:150:do_switch$987 [2226] = 32'd975202158;
\$auto$proc_rom.cc:150:do_switch$987 [2227] = 32'd658729;
\$auto$proc_rom.cc:150:do_switch$987 [2228] = 32'd728329830;
\$auto$proc_rom.cc:150:do_switch$987 [2229] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2230] = 32'd6909542;
\$auto$proc_rom.cc:150:do_switch$987 [2231] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2232] = 32'd7233902;
\$auto$proc_rom.cc:150:do_switch$987 [2233] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2234] = 32'd761884262;
\$auto$proc_rom.cc:150:do_switch$987 [2235] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2236] = 32'd4294961728;
\$auto$proc_rom.cc:150:do_switch$987 [2237] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2238] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2239] = 32'd4294961720;
\$auto$proc_rom.cc:150:do_switch$987 [2240] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2241] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2242] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2243] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2244] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2245] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2246] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2247] = 32'd4294961712;
\$auto$proc_rom.cc:150:do_switch$987 [2248] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2249] = 32'd4294961704;
\$auto$proc_rom.cc:150:do_switch$987 [2250] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2251] = 32'd4294961576;
\$auto$proc_rom.cc:150:do_switch$987 [2252] = 32'd4294961696;
\$auto$proc_rom.cc:150:do_switch$987 [2253] = 32'd4294961956;
\$auto$proc_rom.cc:150:do_switch$987 [2254] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2255] = 32'd4294961570;
\$auto$proc_rom.cc:150:do_switch$987 [2256] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2257] = 32'd4294961930;
\$auto$proc_rom.cc:150:do_switch$987 [2258] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2259] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2260] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2261] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2262] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2263] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2264] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2265] = 32'd4294961570;
\$auto$proc_rom.cc:150:do_switch$987 [2266] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2267] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2268] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2269] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2270] = 32'd4294961580;
\$auto$proc_rom.cc:150:do_switch$987 [2271] = 32'd4294961570;
\$auto$proc_rom.cc:150:do_switch$987 [2272] = 32'd4294962006;
\$auto$proc_rom.cc:150:do_switch$987 [2273] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2274] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2275] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2276] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2277] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2278] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2279] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2280] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2281] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2282] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2283] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2284] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2285] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2286] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2287] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2288] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2289] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2290] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2291] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2292] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2293] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2294] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2295] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2296] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2297] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2298] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2299] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2300] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2301] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2302] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2303] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2304] = 32'd4294962242;
\$auto$proc_rom.cc:150:do_switch$987 [2305] = 32'd4294961900;
\$auto$proc_rom.cc:150:do_switch$987 [2306] = 32'd4294962242;
\$auto$proc_rom.cc:150:do_switch$987 [2307] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2308] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2309] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2310] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2311] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2312] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2313] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2314] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2315] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2316] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2317] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2318] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2319] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2320] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2321] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2322] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2323] = 32'd4294962288;
\$auto$proc_rom.cc:150:do_switch$987 [2324] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2325] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2326] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2327] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2328] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2329] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2330] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2331] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2332] = 32'd4294961370;
\$auto$proc_rom.cc:150:do_switch$987 [2333] = 32'd4294962288;
\$auto$proc_rom.cc:150:do_switch$987 [2334] = 32'd4294961934;
\$auto$proc_rom.cc:150:do_switch$987 [2335] = 32'd4294962288;
\$auto$proc_rom.cc:150:do_switch$987 [2336] = 32'd4294962242;
\$auto$proc_rom.cc:150:do_switch$987 [2337] = 32'd4294961900;
\$auto$proc_rom.cc:150:do_switch$987 [2338] = 32'd4294962242;
\$auto$proc_rom.cc:150:do_switch$987 [2339] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2340] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2341] = 32'd1072693248;
\$auto$proc_rom.cc:150:do_switch$987 [2342] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2343] = 32'd1076101120;
\$auto$proc_rom.cc:150:do_switch$987 [2344] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2345] = 32'd1079574528;
\$auto$proc_rom.cc:150:do_switch$987 [2346] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2347] = 32'd1083129856;
\$auto$proc_rom.cc:150:do_switch$987 [2348] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2349] = 32'd1086556160;
\$auto$proc_rom.cc:150:do_switch$987 [2350] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2351] = 32'd1090021888;
\$auto$proc_rom.cc:150:do_switch$987 [2352] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2353] = 32'd1093567616;
\$auto$proc_rom.cc:150:do_switch$987 [2354] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2355] = 32'd1097011920;
\$auto$proc_rom.cc:150:do_switch$987 [2356] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2357] = 32'd1100470148;
\$auto$proc_rom.cc:150:do_switch$987 [2358] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2359] = 32'd1104006501;
\$auto$proc_rom.cc:150:do_switch$987 [2360] = 32'd1663059027;
\$auto$proc_rom.cc:150:do_switch$987 [2361] = 32'd543453793;
\$auto$proc_rom.cc:150:do_switch$987 [2362] = 32'd2037411683;
\$auto$proc_rom.cc:150:do_switch$987 [2363] = 32'd543584032;
\$auto$proc_rom.cc:150:do_switch$987 [2364] = 32'd1684104552;
\$auto$proc_rom.cc:150:do_switch$987 [2365] = 32'd1713402469;
\$auto$proc_rom.cc:150:do_switch$987 [2366] = 32'd1701603681;
\$auto$proc_rom.cc:150:do_switch$987 [2367] = 32'd168632676;
\$auto$proc_rom.cc:150:do_switch$987 [2368] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2369] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2370] = 32'd542396487;
\$auto$proc_rom.cc:150:do_switch$987 [2371] = 32'd1953653104;
\$auto$proc_rom.cc:150:do_switch$987 [2372] = 32'd1869182057;
\$auto$proc_rom.cc:150:do_switch$987 [2373] = 32'd1635000430;
\$auto$proc_rom.cc:150:do_switch$987 [2374] = 32'd543517794;
\$auto$proc_rom.cc:150:do_switch$987 [2375] = 32'd1684104552;
\$auto$proc_rom.cc:150:do_switch$987 [2376] = 32'd221934181;
\$auto$proc_rom.cc:150:do_switch$987 [2377] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2378] = 32'd1734963977;
\$auto$proc_rom.cc:150:do_switch$987 [2379] = 32'd1970561390;
\$auto$proc_rom.cc:150:do_switch$987 [2380] = 32'd154822002;
\$auto$proc_rom.cc:150:do_switch$987 [2381] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2382] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2383] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2384] = 32'd1986359817;
\$auto$proc_rom.cc:150:do_switch$987 [2385] = 32'd1869181801;
\$auto$proc_rom.cc:150:do_switch$987 [2386] = 32'd537475694;
\$auto$proc_rom.cc:150:do_switch$987 [2387] = 32'd2015721520;
\$auto$proc_rom.cc:150:do_switch$987 [2388] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2389] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2390] = 32'd1634035721;
\$auto$proc_rom.cc:150:do_switch$987 [2391] = 32'd544367972;
\$auto$proc_rom.cc:150:do_switch$987 [2392] = 32'd1702521203;
\$auto$proc_rom.cc:150:do_switch$987 [2393] = 32'd537463098;
\$auto$proc_rom.cc:150:do_switch$987 [2394] = 32'd2015721520;
\$auto$proc_rom.cc:150:do_switch$987 [2395] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2396] = 32'd1936028169;
\$auto$proc_rom.cc:150:do_switch$987 [2397] = 32'd1702261349;
\$auto$proc_rom.cc:150:do_switch$987 [2398] = 32'd537475684;
\$auto$proc_rom.cc:150:do_switch$987 [2399] = 32'd2015721520;
\$auto$proc_rom.cc:150:do_switch$987 [2400] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2401] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2402] = 32'd544828681;
\$auto$proc_rom.cc:150:do_switch$987 [2403] = 32'd979460716;
\$auto$proc_rom.cc:150:do_switch$987 [2404] = 32'd2016419849;
\$auto$proc_rom.cc:150:do_switch$987 [2405] = 32'd225995813;
\$auto$proc_rom.cc:150:do_switch$987 [2406] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2407] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2408] = 32'd1953259785;
\$auto$proc_rom.cc:150:do_switch$987 [2409] = 32'd1634628197;
\$auto$proc_rom.cc:150:do_switch$987 [2410] = 32'd1814062452;
\$auto$proc_rom.cc:150:do_switch$987 [2411] = 32'd154820962;
\$auto$proc_rom.cc:150:do_switch$987 [2412] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2413] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2414] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2415] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2416] = 32'd1918988297;
\$auto$proc_rom.cc:150:do_switch$987 [2417] = 32'd1769236852;
\$auto$proc_rom.cc:150:do_switch$987 [2418] = 32'd1696624239;
\$auto$proc_rom.cc:150:do_switch$987 [2419] = 32'd2037544046;
\$auto$proc_rom.cc:150:do_switch$987 [2420] = 32'd1633840160;
\$auto$proc_rom.cc:150:do_switch$987 [2421] = 32'd807405882;
\$auto$proc_rom.cc:150:do_switch$987 [2422] = 32'd2020353400;
\$auto$proc_rom.cc:150:do_switch$987 [2423] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2424] = 32'd1836412425;
\$auto$proc_rom.cc:150:do_switch$987 [2425] = 32'd544367970;
\$auto$proc_rom.cc:150:do_switch$987 [2426] = 32'd1953653104;
\$auto$proc_rom.cc:150:do_switch$987 [2427] = 32'd1869182057;
\$auto$proc_rom.cc:150:do_switch$987 [2428] = 32'd1852121198;
\$auto$proc_rom.cc:150:do_switch$987 [2429] = 32'd1701409396;
\$auto$proc_rom.cc:150:do_switch$987 [2430] = 32'd537475699;
\$auto$proc_rom.cc:150:do_switch$987 [2431] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2432] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2433] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2434] = 32'd2053731081;
\$auto$proc_rom.cc:150:do_switch$987 [2435] = 32'd1634738277;
\$auto$proc_rom.cc:150:do_switch$987 [2436] = 32'd1953068146;
\$auto$proc_rom.cc:150:do_switch$987 [2437] = 32'd544108393;
\$auto$proc_rom.cc:150:do_switch$987 [2438] = 32'd1920233061;
\$auto$proc_rom.cc:150:do_switch$987 [2439] = 32'd980641129;
\$auto$proc_rom.cc:150:do_switch$987 [2440] = 32'd537468960;
\$auto$proc_rom.cc:150:do_switch$987 [2441] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2442] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2443] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2444] = 32'd1663059027;
\$auto$proc_rom.cc:150:do_switch$987 [2445] = 32'd543453793;
\$auto$proc_rom.cc:150:do_switch$987 [2446] = 32'd2037411683;
\$auto$proc_rom.cc:150:do_switch$987 [2447] = 32'd543584032;
\$auto$proc_rom.cc:150:do_switch$987 [2448] = 32'd1953653104;
\$auto$proc_rom.cc:150:do_switch$987 [2449] = 32'd1869182057;
\$auto$proc_rom.cc:150:do_switch$987 [2450] = 32'd1852121198;
\$auto$proc_rom.cc:150:do_switch$987 [2451] = 32'd1701409396;
\$auto$proc_rom.cc:150:do_switch$987 [2452] = 32'd1634082931;
\$auto$proc_rom.cc:150:do_switch$987 [2453] = 32'd1684368489;
\$auto$proc_rom.cc:150:do_switch$987 [2454] = 32'd658721;
\$auto$proc_rom.cc:150:do_switch$987 [2455] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2456] = 32'd542396487;
\$auto$proc_rom.cc:150:do_switch$987 [2457] = 32'd1953653104;
\$auto$proc_rom.cc:150:do_switch$987 [2458] = 32'd1869182057;
\$auto$proc_rom.cc:150:do_switch$987 [2459] = 32'd1852121198;
\$auto$proc_rom.cc:150:do_switch$987 [2460] = 32'd544830068;
\$auto$proc_rom.cc:150:do_switch$987 [2461] = 32'd168649765;
\$auto$proc_rom.cc:150:do_switch$987 [2462] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2463] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2464] = 32'd1919510025;
\$auto$proc_rom.cc:150:do_switch$987 [2465] = 32'd1814066291;
\$auto$proc_rom.cc:150:do_switch$987 [2466] = 32'd154820962;
\$auto$proc_rom.cc:150:do_switch$987 [2467] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2468] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2469] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2470] = 32'd1935764489;
\$auto$proc_rom.cc:150:do_switch$987 [2471] = 32'd1651253364;
\$auto$proc_rom.cc:150:do_switch$987 [2472] = 32'd537475681;
\$auto$proc_rom.cc:150:do_switch$987 [2473] = 32'd1814394928;
\$auto$proc_rom.cc:150:do_switch$987 [2474] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2475] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2476] = 32'd1953784073;
\$auto$proc_rom.cc:150:do_switch$987 [2477] = 32'd1969383794;
\$auto$proc_rom.cc:150:do_switch$987 [2478] = 32'd980641140;
\$auto$proc_rom.cc:150:do_switch$987 [2479] = 32'd2016419849;
\$auto$proc_rom.cc:150:do_switch$987 [2480] = 32'd225995813;
\$auto$proc_rom.cc:150:do_switch$987 [2481] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2482] = 32'd1835101705;
\$auto$proc_rom.cc:150:do_switch$987 [2483] = 32'd604773;
\$auto$proc_rom.cc:150:do_switch$987 [2484] = 32'd25381;
\$auto$proc_rom.cc:150:do_switch$987 [2485] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2486] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2487] = 32'd1936028192;
\$auto$proc_rom.cc:150:do_switch$987 [2488] = 32'd1701601136;
\$auto$proc_rom.cc:150:do_switch$987 [2489] = 32'd2016419950;
\$auto$proc_rom.cc:150:do_switch$987 [2490] = 32'd1948284965;
\$auto$proc_rom.cc:150:do_switch$987 [2491] = 32'd1814065007;
\$auto$proc_rom.cc:150:do_switch$987 [2492] = 32'd1701278305;
\$auto$proc_rom.cc:150:do_switch$987 [2493] = 32'd1919903264;
\$auto$proc_rom.cc:150:do_switch$987 [2494] = 32'd1600418592;
\$auto$proc_rom.cc:150:do_switch$987 [2495] = 32'd543452515;
\$auto$proc_rom.cc:150:do_switch$987 [2496] = 32'd2019650856;
\$auto$proc_rom.cc:150:do_switch$987 [2497] = 32'd544434464;
\$auto$proc_rom.cc:150:do_switch$987 [2498] = 32'd168634680;
\$auto$proc_rom.cc:150:do_switch$987 [2499] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2500] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2501] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2502] = 32'd1701978160;
\$auto$proc_rom.cc:150:do_switch$987 [2503] = 32'd1852797043;
\$auto$proc_rom.cc:150:do_switch$987 [2504] = 32'd540697971;
\$auto$proc_rom.cc:150:do_switch$987 [2505] = 32'd2015721520;
\$auto$proc_rom.cc:150:do_switch$987 [2506] = 32'd2573;
\$auto$proc_rom.cc:150:do_switch$987 [2507] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2508] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2509] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2510] = 32'd1701978168;
\$auto$proc_rom.cc:150:do_switch$987 [2511] = 32'd1852797043;
\$auto$proc_rom.cc:150:do_switch$987 [2512] = 32'd540697971;
\$auto$proc_rom.cc:150:do_switch$987 [2513] = 32'd1814394928;
\$auto$proc_rom.cc:150:do_switch$987 [2514] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2515] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2516] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2517] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2518] = 32'd1914713397;
\$auto$proc_rom.cc:150:do_switch$987 [2519] = 32'd1869640549;
\$auto$proc_rom.cc:150:do_switch$987 [2520] = 32'd979727214;
\$auto$proc_rom.cc:150:do_switch$987 [2521] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2522] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2523] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2524] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2525] = 32'd1296253216;
\$auto$proc_rom.cc:150:do_switch$987 [2526] = 32'd540095556;
\$auto$proc_rom.cc:150:do_switch$987 [2527] = 32'd1886610802;
\$auto$proc_rom.cc:150:do_switch$987 [2528] = 32'd1702063727;
\$auto$proc_rom.cc:150:do_switch$987 [2529] = 32'd2016419898;
\$auto$proc_rom.cc:150:do_switch$987 [2530] = 32'd225995813;
\$auto$proc_rom.cc:150:do_switch$987 [2531] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2532] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2533] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2534] = 32'd1914714165;
\$auto$proc_rom.cc:150:do_switch$987 [2535] = 32'd1869640549;
\$auto$proc_rom.cc:150:do_switch$987 [2536] = 32'd979727214;
\$auto$proc_rom.cc:150:do_switch$987 [2537] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2538] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2539] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2540] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2541] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2542] = 32'd1914713649;
\$auto$proc_rom.cc:150:do_switch$987 [2543] = 32'd1869640549;
\$auto$proc_rom.cc:150:do_switch$987 [2544] = 32'd979727214;
\$auto$proc_rom.cc:150:do_switch$987 [2545] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2546] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2547] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2548] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2549] = 32'd1852396320;
\$auto$proc_rom.cc:150:do_switch$987 [2550] = 32'd543517799;
\$auto$proc_rom.cc:150:do_switch$987 [2551] = 32'd1668246626;
\$auto$proc_rom.cc:150:do_switch$987 [2552] = 32'd1920213099;
\$auto$proc_rom.cc:150:do_switch$987 [2553] = 32'd1718840929;
\$auto$proc_rom.cc:150:do_switch$987 [2554] = 32'd1713402469;
\$auto$proc_rom.cc:150:do_switch$987 [2555] = 32'd544042866;
\$auto$proc_rom.cc:150:do_switch$987 [2556] = 32'd541147724;
\$auto$proc_rom.cc:150:do_switch$987 [2557] = 32'd1814394928;
\$auto$proc_rom.cc:150:do_switch$987 [2558] = 32'd1869881464;
\$auto$proc_rom.cc:150:do_switch$987 [2559] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2560] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2561] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2562] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2563] = 32'd1819626784;
\$auto$proc_rom.cc:150:do_switch$987 [2564] = 32'd1646291316;
\$auto$proc_rom.cc:150:do_switch$987 [2565] = 32'd1801678700;
\$auto$proc_rom.cc:150:do_switch$987 [2566] = 32'd1634890784;
\$auto$proc_rom.cc:150:do_switch$987 [2567] = 32'd1701213038;
\$auto$proc_rom.cc:150:do_switch$987 [2568] = 32'd1718558834;
\$auto$proc_rom.cc:150:do_switch$987 [2569] = 32'd543434016;
\$auto$proc_rom.cc:150:do_switch$987 [2570] = 32'd1668246626;
\$auto$proc_rom.cc:150:do_switch$987 [2571] = 32'd1713402731;
\$auto$proc_rom.cc:150:do_switch$987 [2572] = 32'd544042866;
\$auto$proc_rom.cc:150:do_switch$987 [2573] = 32'd541147724;
\$auto$proc_rom.cc:150:do_switch$987 [2574] = 32'd1814394928;
\$auto$proc_rom.cc:150:do_switch$987 [2575] = 32'd1869881464;
\$auto$proc_rom.cc:150:do_switch$987 [2576] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2577] = 32'd168654956;
\$auto$proc_rom.cc:150:do_switch$987 [2578] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2579] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2580] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2581] = 32'd1953449760;
\$auto$proc_rom.cc:150:do_switch$987 [2582] = 32'd1869373984;
\$auto$proc_rom.cc:150:do_switch$987 [2583] = 32'd1914727267;
\$auto$proc_rom.cc:150:do_switch$987 [2584] = 32'd543449445;
\$auto$proc_rom.cc:150:do_switch$987 [2585] = 32'd1835888483;
\$auto$proc_rom.cc:150:do_switch$987 [2586] = 32'd543452769;
\$auto$proc_rom.cc:150:do_switch$987 [2587] = 32'd1886610802;
\$auto$proc_rom.cc:150:do_switch$987 [2588] = 32'd1702063727;
\$auto$proc_rom.cc:150:do_switch$987 [2589] = 32'd2016419898;
\$auto$proc_rom.cc:150:do_switch$987 [2590] = 32'd168654885;
\$auto$proc_rom.cc:150:do_switch$987 [2591] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2592] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2593] = 32'd1920091424;
\$auto$proc_rom.cc:150:do_switch$987 [2594] = 32'd1948283503;
\$auto$proc_rom.cc:150:do_switch$987 [2595] = 32'd1852140399;
\$auto$proc_rom.cc:150:do_switch$987 [2596] = 32'd1667592736;
\$auto$proc_rom.cc:150:do_switch$987 [2597] = 32'd1702259045;
\$auto$proc_rom.cc:150:do_switch$987 [2598] = 32'd807418468;
\$auto$proc_rom.cc:150:do_switch$987 [2599] = 32'd225977720;
\$auto$proc_rom.cc:150:do_switch$987 [2600] = 32'd10;
\$auto$proc_rom.cc:150:do_switch$987 [2601] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2602] = 32'd1566864219;
\$auto$proc_rom.cc:150:do_switch$987 [2603] = 32'd1145914144;
\$auto$proc_rom.cc:150:do_switch$987 [2604] = 32'd1914712625;
\$auto$proc_rom.cc:150:do_switch$987 [2605] = 32'd1869640549;
\$auto$proc_rom.cc:150:do_switch$987 [2606] = 32'd979727214;
\$auto$proc_rom.cc:150:do_switch$987 [2607] = 32'd628633632;
\$auto$proc_rom.cc:150:do_switch$987 [2608] = 32'd658808;
\$auto$proc_rom.cc:150:do_switch$987 [2609] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2610] = 32'd4294967295;
\$auto$proc_rom.cc:150:do_switch$987 [2611] = 32'd2146435071;
\$auto$proc_rom.cc:150:do_switch$987 [2612] = 32'd4294967295;
\$auto$proc_rom.cc:150:do_switch$987 [2613] = 32'd4293918719;
\$auto$proc_rom.cc:150:do_switch$987 [2614] = 32'd1352628731;
\$auto$proc_rom.cc:150:do_switch$987 [2615] = 32'd1070810131;
\$auto$proc_rom.cc:150:do_switch$987 [2616] = 32'd2338375859;
\$auto$proc_rom.cc:150:do_switch$987 [2617] = 32'd1069976104;
\$auto$proc_rom.cc:150:do_switch$987 [2618] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2619] = 32'd1073217536;
\$auto$proc_rom.cc:150:do_switch$987 [2620] = 32'd1668236129;
\$auto$proc_rom.cc:150:do_switch$987 [2621] = 32'd1070761895;
\$auto$proc_rom.cc:150:do_switch$987 [2622] = 32'd158966641;
\$auto$proc_rom.cc:150:do_switch$987 [2623] = 32'd1074434895;
\$auto$proc_rom.cc:150:do_switch$987 [2624] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2625] = 32'd1071644672;
\$auto$proc_rom.cc:150:do_switch$987 [2626] = 32'd4277811695;
\$auto$proc_rom.cc:150:do_switch$987 [2627] = 32'd1072049730;
\$auto$proc_rom.cc:150:do_switch$987 [2628] = 32'd3149223190;
\$auto$proc_rom.cc:150:do_switch$987 [2629] = 32'd1073900465;
\$auto$proc_rom.cc:150:do_switch$987 [2630] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2631] = 32'd1076625408;
\$auto$proc_rom.cc:150:do_switch$987 [2632] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2633] = 32'd1076101120;
\$auto$proc_rom.cc:150:do_switch$987 [2634] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2635] = 32'd1075314688;
\$auto$proc_rom.cc:150:do_switch$987 [2636] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2637] = 32'd1073741824;
\$auto$proc_rom.cc:150:do_switch$987 [2638] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2639] = 32'd1072693248;
\$auto$proc_rom.cc:150:do_switch$987 [2640] = 32'd3944497965;
\$auto$proc_rom.cc:150:do_switch$987 [2641] = 32'd1058682594;
\$auto$proc_rom.cc:150:do_switch$987 [2642] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2643] = 32'd1093567616;
\$auto$proc_rom.cc:150:do_switch$987 [2644] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2645] = 32'd1104006501;
\$auto$proc_rom.cc:150:do_switch$987 [2646] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2647] = 32'd3251490149;
\$auto$proc_rom.cc:150:do_switch$987 [2648] = 32'd109191;
\$auto$proc_rom.cc:150:do_switch$987 [2649] = 32'd18432;
\$auto$proc_rom.cc:150:do_switch$987 [2650] = 32'd131327;
\$auto$proc_rom.cc:150:do_switch$987 [2651] = 32'd20480;
\$auto$proc_rom.cc:150:do_switch$987 [2652] = 32'd84017409;
\$auto$proc_rom.cc:150:do_switch$987 [2653] = 32'd83886080;
\$auto$proc_rom.cc:150:do_switch$987 [2654] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2655] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2656] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2657] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2658] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2659] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2660] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2661] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2662] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2663] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2664] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2665] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2666] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2667] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2668] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2669] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2670] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2671] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2672] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2673] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2674] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2675] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2676] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2677] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2678] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2679] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2680] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2681] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2682] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2683] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2684] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2685] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2686] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2687] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2688] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2689] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2690] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2691] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2692] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2693] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2694] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2695] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2696] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2697] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2698] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2699] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2700] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2701] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2702] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2703] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2704] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2705] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2706] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2707] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2708] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2709] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2710] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2711] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2712] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2713] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2714] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2715] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2716] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2717] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2718] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2719] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2720] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2721] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2722] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2723] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2724] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2725] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2726] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2727] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2728] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2729] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2730] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2731] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2732] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2733] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2734] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2735] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2736] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2737] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2738] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2739] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2740] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2741] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2742] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2743] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2744] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2745] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2746] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2747] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2748] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2749] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2750] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2751] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2752] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2753] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2754] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2755] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2756] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2757] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2758] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2759] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2760] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2761] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2762] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2763] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2764] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2765] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2766] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2767] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2768] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2769] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2770] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2771] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2772] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2773] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2774] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2775] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2776] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2777] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2778] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2779] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2780] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2781] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2782] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2783] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2784] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2785] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2786] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2787] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2788] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2789] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2790] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2791] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2792] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2793] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2794] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2795] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2796] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2797] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2798] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2799] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2800] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2801] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2802] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2803] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2804] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2805] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2806] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2807] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2808] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2809] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2810] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2811] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2812] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2813] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2814] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2815] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2816] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2817] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2818] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2819] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2820] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2821] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2822] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2823] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2824] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2825] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2826] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2827] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2828] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2829] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2830] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2831] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2832] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2833] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2834] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2835] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2836] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2837] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2838] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2839] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2840] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2841] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2842] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2843] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2844] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2845] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2846] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2847] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2848] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2849] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2850] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2851] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2852] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2853] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2854] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2855] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2856] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2857] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2858] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2859] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2860] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2861] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2862] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2863] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2864] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2865] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2866] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2867] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2868] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2869] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2870] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2871] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2872] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2873] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2874] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2875] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2876] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2877] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2878] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2879] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2880] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2881] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2882] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2883] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2884] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2885] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2886] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2887] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2888] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2889] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2890] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2891] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2892] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2893] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2894] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2895] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2896] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2897] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2898] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2899] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2900] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2901] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2902] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2903] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2904] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2905] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2906] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2907] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2908] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2909] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2910] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2911] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2912] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2913] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2914] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2915] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2916] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2917] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2918] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2919] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2920] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2921] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2922] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2923] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2924] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2925] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2926] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2927] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2928] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2929] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2930] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2931] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2932] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2933] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2934] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2935] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2936] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2937] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2938] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2939] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2940] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2941] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2942] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2943] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2944] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2945] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2946] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2947] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2948] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2949] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2950] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2951] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2952] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2953] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2954] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2955] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2956] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2957] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2958] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2959] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2960] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2961] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2962] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2963] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2964] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2965] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2966] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2967] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2968] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2969] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2970] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2971] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2972] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2973] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2974] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2975] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2976] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2977] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2978] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2979] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2980] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2981] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2982] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2983] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2984] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2985] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2986] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2987] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2988] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2989] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2990] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2991] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2992] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2993] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2994] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2995] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2996] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2997] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2998] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [2999] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3000] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3001] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3002] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3003] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3004] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3005] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3006] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3007] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3008] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3009] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3010] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3011] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3012] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3013] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3014] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3015] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3016] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3017] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3018] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3019] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3020] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3021] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3022] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3023] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3024] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3025] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3026] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3027] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3028] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3029] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3030] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3031] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3032] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3033] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3034] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3035] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3036] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3037] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3038] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3039] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3040] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3041] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3042] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3043] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3044] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3045] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3046] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3047] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3048] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3049] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3050] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3051] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3052] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3053] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3054] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3055] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3056] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3057] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3058] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3059] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3060] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3061] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3062] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3063] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3064] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3065] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3066] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3067] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3068] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3069] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3070] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3071] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3072] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3073] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3074] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3075] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3076] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3077] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3078] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3079] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3080] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3081] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3082] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3083] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3084] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3085] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3086] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3087] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3088] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3089] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3090] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3091] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3092] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3093] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3094] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3095] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3096] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3097] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3098] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3099] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3100] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3101] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3102] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3103] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3104] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3105] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3106] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3107] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3108] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3109] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3110] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3111] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3112] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3113] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3114] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3115] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3116] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3117] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3118] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3119] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3120] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3121] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3122] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3123] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3124] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3125] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3126] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3127] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3128] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3129] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3130] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3131] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3132] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3133] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3134] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3135] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3136] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3137] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3138] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3139] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3140] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3141] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3142] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3143] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3144] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3145] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3146] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3147] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3148] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3149] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3150] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3151] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3152] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3153] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3154] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3155] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3156] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3157] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3158] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3159] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3160] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3161] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3162] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3163] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3164] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3165] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3166] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3167] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3168] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3169] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3170] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3171] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3172] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3173] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3174] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3175] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3176] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3177] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3178] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3179] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3180] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3181] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3182] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3183] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3184] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3185] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3186] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3187] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3188] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3189] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3190] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3191] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3192] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3193] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3194] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3195] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3196] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3197] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3198] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3199] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3200] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3201] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3202] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3203] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3204] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3205] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3206] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3207] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3208] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3209] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3210] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3211] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3212] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3213] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3214] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3215] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3216] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3217] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3218] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3219] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3220] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3221] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3222] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3223] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3224] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3225] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3226] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3227] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3228] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3229] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3230] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3231] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3232] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3233] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3234] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3235] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3236] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3237] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3238] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3239] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3240] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3241] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3242] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3243] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3244] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3245] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3246] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3247] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3248] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3249] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3250] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3251] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3252] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3253] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3254] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3255] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3256] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3257] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3258] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3259] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3260] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3261] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3262] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3263] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3264] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3265] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3266] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3267] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3268] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3269] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3270] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3271] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3272] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3273] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3274] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3275] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3276] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3277] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3278] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3279] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3280] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3281] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3282] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3283] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3284] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3285] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3286] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3287] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3288] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3289] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3290] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3291] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3292] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3293] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3294] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3295] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3296] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3297] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3298] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3299] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3300] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3301] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3302] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3303] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3304] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3305] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3306] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3307] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3308] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3309] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3310] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3311] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3312] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3313] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3314] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3315] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3316] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3317] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3318] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3319] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3320] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3321] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3322] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3323] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3324] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3325] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3326] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3327] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3328] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3329] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3330] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3331] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3332] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3333] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3334] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3335] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3336] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3337] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3338] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3339] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3340] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3341] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3342] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3343] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3344] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3345] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3346] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3347] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3348] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3349] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3350] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3351] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3352] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3353] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3354] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3355] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3356] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3357] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3358] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3359] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3360] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3361] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3362] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3363] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3364] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3365] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3366] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3367] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3368] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3369] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3370] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3371] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3372] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3373] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3374] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3375] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3376] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3377] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3378] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3379] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3380] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3381] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3382] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3383] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3384] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3385] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3386] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3387] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3388] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3389] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3390] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3391] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3392] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3393] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3394] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3395] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3396] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3397] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3398] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3399] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3400] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3401] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3402] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3403] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3404] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3405] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3406] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3407] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3408] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3409] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3410] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3411] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3412] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3413] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3414] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3415] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3416] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3417] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3418] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3419] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3420] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3421] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3422] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3423] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3424] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3425] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3426] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3427] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3428] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3429] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3430] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3431] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3432] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3433] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3434] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3435] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3436] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3437] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3438] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3439] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3440] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3441] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3442] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3443] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3444] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3445] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3446] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3447] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3448] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3449] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3450] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3451] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3452] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3453] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3454] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3455] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3456] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3457] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3458] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3459] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3460] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3461] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3462] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3463] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3464] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3465] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3466] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3467] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3468] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3469] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3470] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3471] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3472] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3473] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3474] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3475] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3476] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3477] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3478] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3479] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3480] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3481] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3482] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3483] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3484] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3485] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3486] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3487] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3488] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3489] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3490] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3491] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3492] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3493] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3494] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3495] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3496] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3497] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3498] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3499] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3500] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3501] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3502] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3503] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3504] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3505] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3506] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3507] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3508] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3509] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3510] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3511] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3512] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3513] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3514] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3515] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3516] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3517] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3518] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3519] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3520] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3521] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3522] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3523] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3524] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3525] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3526] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3527] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3528] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3529] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3530] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3531] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3532] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3533] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3534] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3535] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3536] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3537] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3538] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3539] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3540] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3541] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3542] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3543] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3544] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3545] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3546] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3547] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3548] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3549] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3550] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3551] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3552] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3553] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3554] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3555] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3556] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3557] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3558] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3559] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3560] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3561] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3562] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3563] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3564] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3565] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3566] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3567] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3568] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3569] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3570] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3571] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3572] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3573] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3574] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3575] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3576] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3577] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3578] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3579] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3580] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3581] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3582] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3583] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3584] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3585] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3586] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3587] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3588] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3589] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3590] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3591] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3592] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3593] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3594] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3595] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3596] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3597] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3598] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3599] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3600] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3601] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3602] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3603] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3604] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3605] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3606] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3607] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3608] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3609] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3610] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3611] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3612] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3613] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3614] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3615] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3616] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3617] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3618] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3619] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3620] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3621] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3622] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3623] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3624] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3625] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3626] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3627] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3628] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3629] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3630] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3631] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3632] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3633] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3634] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3635] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3636] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3637] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3638] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3639] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3640] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3641] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3642] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3643] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3644] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3645] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3646] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3647] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3648] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3649] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3650] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3651] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3652] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3653] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3654] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3655] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3656] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3657] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3658] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3659] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3660] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3661] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3662] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3663] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3664] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3665] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3666] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3667] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3668] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3669] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3670] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3671] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3672] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3673] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3674] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3675] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3676] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3677] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3678] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3679] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3680] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3681] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3682] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3683] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3684] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3685] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3686] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3687] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3688] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3689] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3690] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3691] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3692] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3693] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3694] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3695] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3696] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3697] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3698] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3699] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3700] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3701] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3702] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3703] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3704] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3705] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3706] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3707] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3708] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3709] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3710] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3711] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3712] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3713] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3714] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3715] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3716] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3717] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3718] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3719] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3720] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3721] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3722] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3723] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3724] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3725] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3726] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3727] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3728] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3729] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3730] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3731] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3732] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3733] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3734] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3735] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3736] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3737] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3738] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3739] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3740] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3741] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3742] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3743] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3744] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3745] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3746] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3747] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3748] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3749] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3750] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3751] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3752] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3753] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3754] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3755] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3756] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3757] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3758] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3759] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3760] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3761] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3762] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3763] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3764] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3765] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3766] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3767] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3768] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3769] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3770] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3771] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3772] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3773] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3774] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3775] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3776] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3777] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3778] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3779] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3780] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3781] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3782] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3783] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3784] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3785] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3786] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3787] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3788] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3789] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3790] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3791] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3792] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3793] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3794] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3795] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3796] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3797] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3798] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3799] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3800] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3801] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3802] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3803] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3804] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3805] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3806] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3807] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3808] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3809] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3810] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3811] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3812] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3813] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3814] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3815] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3816] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3817] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3818] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3819] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3820] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3821] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3822] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3823] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3824] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3825] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3826] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3827] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3828] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3829] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3830] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3831] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3832] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3833] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3834] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3835] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3836] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3837] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3838] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3839] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3840] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3841] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3842] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3843] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3844] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3845] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3846] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3847] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3848] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3849] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3850] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3851] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3852] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3853] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3854] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3855] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3856] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3857] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3858] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3859] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3860] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3861] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3862] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3863] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3864] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3865] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3866] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3867] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3868] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3869] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3870] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3871] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3872] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3873] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3874] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3875] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3876] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3877] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3878] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3879] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3880] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3881] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3882] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3883] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3884] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3885] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3886] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3887] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3888] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3889] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3890] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3891] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3892] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3893] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3894] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3895] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3896] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3897] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3898] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3899] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3900] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3901] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3902] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3903] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3904] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3905] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3906] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3907] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3908] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3909] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3910] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3911] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3912] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3913] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3914] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3915] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3916] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3917] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3918] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3919] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3920] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3921] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3922] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3923] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3924] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3925] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3926] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3927] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3928] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3929] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3930] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3931] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3932] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3933] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3934] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3935] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3936] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3937] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3938] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3939] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3940] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3941] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3942] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3943] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3944] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3945] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3946] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3947] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3948] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3949] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3950] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3951] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3952] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3953] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3954] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3955] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3956] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3957] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3958] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3959] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3960] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3961] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3962] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3963] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3964] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3965] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3966] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3967] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3968] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3969] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3970] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3971] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3972] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3973] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3974] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3975] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3976] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3977] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3978] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3979] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3980] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3981] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3982] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3983] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3984] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3985] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3986] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3987] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3988] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3989] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3990] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3991] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3992] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3993] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3994] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3995] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3996] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3997] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3998] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [3999] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4000] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4001] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4002] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4003] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4004] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4005] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4006] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4007] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4008] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4009] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4010] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4011] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4012] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4013] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4014] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4015] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4016] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4017] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4018] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4019] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4020] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4021] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4022] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4023] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4024] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4025] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4026] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4027] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4028] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4029] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4030] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4031] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4032] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4033] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4034] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4035] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4036] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4037] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4038] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4039] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4040] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4041] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4042] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4043] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4044] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4045] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4046] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4047] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4048] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4049] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4050] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4051] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4052] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4053] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4054] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4055] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4056] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4057] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4058] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4059] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4060] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4061] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4062] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4063] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4064] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4065] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4066] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4067] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4068] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4069] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4070] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4071] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4072] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4073] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4074] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4075] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4076] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4077] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4078] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4079] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4080] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4081] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4082] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4083] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4084] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4085] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4086] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4087] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4088] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4089] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4090] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4091] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4092] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4093] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4094] = 32'd0;
\$auto$proc_rom.cc:150:do_switch$987 [4095] = 32'd0;
end
assign data
Raw
yosys_commands
View raw

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