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[ ] [ ] Code for optimized function 'package:hello_world/main.dart_SimdMatrix4_invert' { | |
[ ] [ ] ;; B0 | |
[ ] [ ] ;; B1 | |
[ ] [ ] ;; Enter frame | |
[ ] [ ] 0x112d968f0 a9bf79fd stp fp, lr, [r15, #-16 ]! | |
[ ] [ ] 0x112d968f4 aa0f03fd mov fp, r15 | |
[ ] [ ] 0x112d968f8 d10101ef subi r15, r15, 0x40 | |
[ ] [ ] ;; ParallelMove r0 <- S+2 | |
[ ] [ ] 0x112d968fc f9400ba0 ldrx r0, [fp, #16] | |
[ ] [ ] ;; v3 <- LoadField(v2 . _column0@18166706 {final}) T{_Float32x4} | |
[ ] [ ] ;; UnboxedFloat32x4LoadFieldInstr | |
[ ] [ ] 0x112d96900 3cc07000 fldrq v0, [r0, #7] | |
[ ] [ ] ;; v5 <- LoadField(v2 . _column1@18166706 {final}) T{_Float32x4} | |
[ ] [ ] ;; UnboxedFloat32x4LoadFieldInstr | |
[ ] [ ] 0x112d96904 3cc17001 fldrq v1, [r0, #23] | |
[ ] [ ] ;; v7 <- LoadField(v2 . _column2@18166706 {final}) T{_Float32x4} | |
[ ] [ ] ;; UnboxedFloat32x4LoadFieldInstr | |
[ ] [ ] 0x112d96908 3cc27002 fldrq v2, [r0, #39] | |
[ ] [ ] ;; v9 <- LoadField(v2 . _column3@18166706 {final}) T{_Float32x4} | |
[ ] [ ] ;; UnboxedFloat32x4LoadFieldInstr | |
[ ] [ ] 0x112d9690c 3cc37003 fldrq v3, [r0, #55] | |
[ ] [ ] ;; v200 <- SimdOp:20(Float32x4ShuffleMix, mask = 68, v3, v5) T{_Float32x4} | |
[ ] [ ] 0x112d96910 6e040404 vinss v4[0], v0[0] | |
[ ] [ ] 0x112d96914 6e0c2404 vinss v4[1], v0[1] | |
[ ] [ ] 0x112d96918 6e140424 vinss v4[2], v1[0] | |
[ ] [ ] 0x112d9691c 6e1c2424 vinss v4[3], v1[1] | |
[ ] [ ] ;; v202 <- SimdOp:22(Float32x4ShuffleMix, mask = 68, v7, v9) T{_Float32x4} | |
[ ] [ ] 0x112d96920 6e040445 vinss v5[0], v2[0] | |
[ ] [ ] 0x112d96924 6e0c2445 vinss v5[1], v2[1] | |
[ ] [ ] 0x112d96928 6e140465 vinss v5[2], v3[0] | |
[ ] [ ] 0x112d9692c 6e1c2465 vinss v5[3], v3[1] | |
[ ] [ ] ;; v204 <- SimdOp:24(Float32x4ShuffleMix, mask = 136, v200, v202) T{_Float32x4} | |
[ ] [ ] 0x112d96930 6e040486 vinss v6[0], v4[0] | |
[ ] [ ] 0x112d96934 6e0c4486 vinss v6[1], v4[2] | |
[ ] [ ] 0x112d96938 6e1404a6 vinss v6[2], v5[0] | |
[ ] [ ] 0x112d9693c 6e1c44a6 vinss v6[3], v5[2] | |
[ ] [ ] ;; v206 <- SimdOp:26(Float32x4ShuffleMix, mask = 221, v202, v200) T{_Float32x4} | |
[ ] [ ] 0x112d96940 6e0424a7 vinss v7[0], v5[1] | |
[ ] [ ] 0x112d96944 6e0c64a7 vinss v7[1], v5[3] | |
[ ] [ ] 0x112d96948 6e142487 vinss v7[2], v4[1] | |
[ ] [ ] 0x112d9694c 6e1c6487 vinss v7[3], v4[3] | |
[ ] [ ] ;; v208 <- SimdOp:28(Float32x4ShuffleMix, mask = 238, v3, v5) T{_Float32x4} | |
[ ] [ ] 0x112d96950 6e044404 vinss v4[0], v0[2] | |
[ ] [ ] 0x112d96954 6e0c6404 vinss v4[1], v0[3] | |
[ ] [ ] 0x112d96958 6e144424 vinss v4[2], v1[2] | |
[ ] [ ] 0x112d9695c 6e1c6424 vinss v4[3], v1[3] | |
[ ] [ ] ;; v210 <- SimdOp:30(Float32x4ShuffleMix, mask = 238, v7, v9) T{_Float32x4} | |
[ ] [ ] 0x112d96960 6e044440 vinss v0[0], v2[2] | |
[ ] [ ] 0x112d96964 6e0c6440 vinss v0[1], v2[3] | |
[ ] [ ] 0x112d96968 6e144460 vinss v0[2], v3[2] | |
[ ] [ ] 0x112d9696c 6e1c6460 vinss v0[3], v3[3] | |
[ ] [ ] ;; v212 <- SimdOp:32(Float32x4ShuffleMix, mask = 136, v208, v210) T{_Float32x4} | |
[ ] [ ] 0x112d96970 6e040481 vinss v1[0], v4[0] | |
[ ] [ ] 0x112d96974 6e0c4481 vinss v1[1], v4[2] | |
[ ] [ ] 0x112d96978 6e140401 vinss v1[2], v0[0] | |
[ ] [ ] 0x112d9697c 6e1c4401 vinss v1[3], v0[2] | |
[ ] [ ] ;; v214 <- SimdOp:34(Float32x4ShuffleMix, mask = 221, v210, v208) T{_Float32x4} | |
[ ] [ ] 0x112d96980 6e042402 vinss v2[0], v0[1] | |
[ ] [ ] 0x112d96984 6e0c6402 vinss v2[1], v0[3] | |
[ ] [ ] 0x112d96988 6e142482 vinss v2[2], v4[1] | |
[ ] [ ] 0x112d9698c 6e1c6482 vinss v2[3], v4[3] | |
[ ] [ ] ;; v220 <- SimdOp:36(Float32x4Mul, v212, v214) T{_Float32x4} | |
[ ] [ ] 0x112d96990 6e22dc20 vmuls v0, v1, v2 | |
[ ] [ ] ;; v222 <- SimdOp:38(Float32x4Shuffle, mask = 177, v220) T{_Float32x4} | |
[ ] [ ] 0x112d96994 6e042403 vinss v3[0], v0[1] | |
[ ] [ ] 0x112d96998 6e0c0403 vinss v3[1], v0[0] | |
[ ] [ ] 0x112d9699c 6e146403 vinss v3[2], v0[3] | |
[ ] [ ] 0x112d969a0 6e1c4403 vinss v3[3], v0[2] | |
[ ] [ ] ;; v228 <- SimdOp:40(Float32x4Mul, v206, v222) T{_Float32x4} | |
[ ] [ ] 0x112d969a4 6e23dce0 vmuls v0, v7, v3 | |
[ ] [ ] ;; v234 <- SimdOp:42(Float32x4Mul, v204, v222) T{_Float32x4} | |
[ ] [ ] 0x112d969a8 6e23dcc4 vmuls v4, v6, v3 | |
[ ] [ ] ;; v236 <- SimdOp:44(Float32x4Shuffle, mask = 78, v222) T{_Float32x4} | |
[ ] [ ] 0x112d969ac 6e044465 vinss v5[0], v3[2] | |
[ ] [ ] 0x112d969b0 6e0c6465 vinss v5[1], v3[3] | |
[ ] [ ] 0x112d969b4 6e140465 vinss v5[2], v3[0] | |
[ ] [ ] 0x112d969b8 6e1c2465 vinss v5[3], v3[1] | |
[ ] [ ] ;; v242 <- SimdOp:46(Float32x4Mul, v206, v236) T{_Float32x4} | |
[ ] [ ] 0x112d969bc 6e25dce3 vmuls v3, v7, v5 | |
[ ] [ ] ;; v248 <- SimdOp:48(Float32x4Sub, v242, v228) T{_Float32x4} | |
[ ] [ ] 0x112d969c0 4ea0d468 vsubs v8, v3, v0 | |
[ ] [ ] ;; v254 <- SimdOp:50(Float32x4Mul, v204, v236) T{_Float32x4} | |
[ ] [ ] 0x112d969c4 6e25dcc0 vmuls v0, v6, v5 | |
[ ] [ ] ;; v260 <- SimdOp:52(Float32x4Sub, v254, v234) T{_Float32x4} | |
[ ] [ ] 0x112d969c8 4ea4d403 vsubs v3, v0, v4 | |
[ ] [ ] ;; v262 <- SimdOp:54(Float32x4Shuffle, mask = 78, v260) T{_Float32x4} | |
[ ] [ ] 0x112d969cc 6e044460 vinss v0[0], v3[2] | |
[ ] [ ] 0x112d969d0 6e0c6460 vinss v0[1], v3[3] | |
[ ] [ ] 0x112d969d4 6e140460 vinss v0[2], v3[0] | |
[ ] [ ] 0x112d969d8 6e1c2460 vinss v0[3], v3[1] | |
[ ] [ ] ;; v268 <- SimdOp:56(Float32x4Mul, v206, v212) T{_Float32x4} | |
[ ] [ ] 0x112d969dc 6e21dce3 vmuls v3, v7, v1 | |
[ ] [ ] ;; v270 <- SimdOp:58(Float32x4Shuffle, mask = 177, v268) T{_Float32x4} | |
[ ] [ ] 0x112d969e0 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x112d969e4 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x112d969e8 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x112d969ec 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v276 <- SimdOp:60(Float32x4Mul, v214, v270) T{_Float32x4} | |
[ ] [ ] 0x112d969f0 6e24dc43 vmuls v3, v2, v4 | |
[ ] [ ] ;; v282 <- SimdOp:62(Float32x4Add, v276, v248) T{_Float32x4} | |
[ ] [ ] 0x112d969f4 4e28d465 vadds v5, v3, v8 | |
[ ] [ ] ;; v288 <- SimdOp:64(Float32x4Mul, v204, v270) T{_Float32x4} | |
[ ] [ ] 0x112d969f8 6e24dcc3 vmuls v3, v6, v4 | |
[ ] [ ] ;; v290 <- SimdOp:66(Float32x4Shuffle, mask = 78, v270) T{_Float32x4} | |
[ ] [ ] 0x112d969fc 6e044488 vinss v8[0], v4[2] | |
[ ] [ ] 0x112d96a00 6e0c6488 vinss v8[1], v4[3] | |
[ ] [ ] 0x112d96a04 6e140488 vinss v8[2], v4[0] | |
[ ] [ ] 0x112d96a08 6e1c2488 vinss v8[3], v4[1] | |
[ ] [ ] ;; v296 <- SimdOp:68(Float32x4Mul, v214, v290) T{_Float32x4} | |
[ ] [ ] 0x112d96a0c 6e28dc44 vmuls v4, v2, v8 | |
[ ] [ ] ;; v302 <- SimdOp:70(Float32x4Sub, v282, v296) T{_Float32x4} | |
[ ] [ ] 0x112d96a10 4ea4d4a9 vsubs v9, v5, v4 | |
[ ] [ ] ;; v308 <- SimdOp:72(Float32x4Mul, v204, v290) T{_Float32x4} | |
[ ] [ ] 0x112d96a14 6e28dcc4 vmuls v4, v6, v8 | |
[ ] [ ] ;; v314 <- SimdOp:74(Float32x4Sub, v308, v288) T{_Float32x4} | |
[ ] [ ] 0x112d96a18 4ea3d485 vsubs v5, v4, v3 | |
[ ] [ ] ;; v316 <- SimdOp:76(Float32x4Shuffle, mask = 78, v314) T{_Float32x4} | |
[ ] [ ] 0x112d96a1c 6e0444a3 vinss v3[0], v5[2] | |
[ ] [ ] 0x112d96a20 6e0c64a3 vinss v3[1], v5[3] | |
[ ] [ ] 0x112d96a24 6e1404a3 vinss v3[2], v5[0] | |
[ ] [ ] 0x112d96a28 6e1c24a3 vinss v3[3], v5[1] | |
[ ] [ ] ;; v318 <- SimdOp:78(Float32x4Shuffle, mask = 78, v206) T{_Float32x4} | |
[ ] [ ] 0x112d96a2c 6e0444e4 vinss v4[0], v7[2] | |
[ ] [ ] 0x112d96a30 6e0c64e4 vinss v4[1], v7[3] | |
[ ] [ ] 0x112d96a34 6e1404e4 vinss v4[2], v7[0] | |
[ ] [ ] 0x112d96a38 6e1c24e4 vinss v4[3], v7[1] | |
[ ] [ ] ;; v324 <- SimdOp:80(Float32x4Mul, v318, v214) T{_Float32x4} | |
[ ] [ ] 0x112d96a3c 6e22dc85 vmuls v5, v4, v2 | |
[ ] [ ] ;; v326 <- SimdOp:82(Float32x4Shuffle, mask = 177, v324) T{_Float32x4} | |
[ ] [ ] 0x112d96a40 6e0424a4 vinss v4[0], v5[1] | |
[ ] [ ] 0x112d96a44 6e0c04a4 vinss v4[1], v5[0] | |
[ ] [ ] 0x112d96a48 6e1464a4 vinss v4[2], v5[3] | |
[ ] [ ] 0x112d96a4c 6e1c44a4 vinss v4[3], v5[2] | |
[ ] [ ] ;; v328 <- SimdOp:84(Float32x4Shuffle, mask = 78, v212) T{_Float32x4} | |
[ ] [ ] 0x112d96a50 6e044425 vinss v5[0], v1[2] | |
[ ] [ ] 0x112d96a54 6e0c6425 vinss v5[1], v1[3] | |
[ ] [ ] 0x112d96a58 6e140425 vinss v5[2], v1[0] | |
[ ] [ ] 0x112d96a5c 6e1c2425 vinss v5[3], v1[1] | |
[ ] [ ] ;; v334 <- SimdOp:86(Float32x4Mul, v328, v326) T{_Float32x4} | |
[ ] [ ] 0x112d96a60 6e24dca1 vmuls v1, v5, v4 | |
[ ] [ ] ;; v340 <- SimdOp:88(Float32x4Add, v334, v302) T{_Float32x4} | |
[ ] [ ] 0x112d96a64 4e29d428 vadds v8, v1, v9 | |
[ ] [ ] ;; v346 <- SimdOp:90(Float32x4Mul, v204, v326) T{_Float32x4} | |
[ ] [ ] 0x112d96a68 6e24dcc1 vmuls v1, v6, v4 | |
[ ] [ ] ;; v348 <- SimdOp:92(Float32x4Shuffle, mask = 78, v326) T{_Float32x4} | |
[ ] [ ] 0x112d96a6c 6e044489 vinss v9[0], v4[2] | |
[ ] [ ] 0x112d96a70 6e0c6489 vinss v9[1], v4[3] | |
[ ] [ ] 0x112d96a74 6e140489 vinss v9[2], v4[0] | |
[ ] [ ] 0x112d96a78 6e1c2489 vinss v9[3], v4[1] | |
[ ] [ ] ;; v354 <- SimdOp:94(Float32x4Mul, v328, v348) T{_Float32x4} | |
[ ] [ ] 0x112d96a7c 6e29dca4 vmuls v4, v5, v9 | |
[ ] [ ] ;; v360 <- SimdOp:96(Float32x4Sub, v340, v354) T{_Float32x4} | |
[ ] [ ] 0x112d96a80 4ea4d50a vsubs v10, v8, v4 | |
[ ] [ ] ;; v366 <- SimdOp:98(Float32x4Mul, v204, v348) T{_Float32x4} | |
[ ] [ ] 0x112d96a84 6e29dcc4 vmuls v4, v6, v9 | |
[ ] [ ] ;; v372 <- SimdOp:100(Float32x4Sub, v366, v346) T{_Float32x4} | |
[ ] [ ] 0x112d96a88 4ea1d488 vsubs v8, v4, v1 | |
[ ] [ ] ;; v374 <- SimdOp:102(Float32x4Shuffle, mask = 78, v372) T{_Float32x4} | |
[ ] [ ] 0x112d96a8c 6e044501 vinss v1[0], v8[2] | |
[ ] [ ] 0x112d96a90 6e0c6501 vinss v1[1], v8[3] | |
[ ] [ ] 0x112d96a94 6e140501 vinss v1[2], v8[0] | |
[ ] [ ] 0x112d96a98 6e1c2501 vinss v1[3], v8[1] | |
[ ] [ ] ;; v380 <- SimdOp:104(Float32x4Mul, v204, v206) T{_Float32x4} | |
[ ] [ ] 0x112d96a9c 6e27dcc4 vmuls v4, v6, v7 | |
[ ] [ ] ;; v382 <- SimdOp:106(Float32x4Shuffle, mask = 177, v380) T{_Float32x4} | |
[ ] [ ] 0x112d96aa0 6e042488 vinss v8[0], v4[1] | |
[ ] [ ] 0x112d96aa4 6e0c0488 vinss v8[1], v4[0] | |
[ ] [ ] 0x112d96aa8 6e146488 vinss v8[2], v4[3] | |
[ ] [ ] 0x112d96aac 6e1c4488 vinss v8[3], v4[2] | |
[ ] [ ] ;; v388 <- SimdOp:108(Float32x4Mul, v214, v382) T{_Float32x4} | |
[ ] [ ] 0x112d96ab0 6e28dc44 vmuls v4, v2, v8 | |
[ ] [ ] ;; v394 <- SimdOp:110(Float32x4Add, v388, v374) T{_Float32x4} | |
[ ] [ ] 0x112d96ab4 4e21d489 vadds v9, v4, v1 | |
[ ] [ ] ;; v400 <- SimdOp:112(Float32x4Mul, v328, v382) T{_Float32x4} | |
[ ] [ ] 0x112d96ab8 6e28dca1 vmuls v1, v5, v8 | |
[ ] [ ] ;; v406 <- SimdOp:114(Float32x4Sub, v400, v316) T{_Float32x4} | |
[ ] [ ] 0x112d96abc 4ea3d424 vsubs v4, v1, v3 | |
[ ] [ ] ;; v408 <- SimdOp:116(Float32x4Shuffle, mask = 78, v382) T{_Float32x4} | |
[ ] [ ] 0x112d96ac0 6e044501 vinss v1[0], v8[2] | |
[ ] [ ] 0x112d96ac4 6e0c6501 vinss v1[1], v8[3] | |
[ ] [ ] 0x112d96ac8 6e140501 vinss v1[2], v8[0] | |
[ ] [ ] 0x112d96acc 6e1c2501 vinss v1[3], v8[1] | |
[ ] [ ] ;; v414 <- SimdOp:118(Float32x4Mul, v214, v408) T{_Float32x4} | |
[ ] [ ] 0x112d96ad0 6e21dc43 vmuls v3, v2, v1 | |
[ ] [ ] ;; v420 <- SimdOp:120(Float32x4Sub, v414, v394) T{_Float32x4} | |
[ ] [ ] 0x112d96ad4 4ea9d468 vsubs v8, v3, v9 | |
[ ] [ ] ;; v426 <- SimdOp:122(Float32x4Mul, v328, v408) T{_Float32x4} | |
[ ] [ ] 0x112d96ad8 6e21dca3 vmuls v3, v5, v1 | |
[ ] [ ] ;; v432 <- SimdOp:124(Float32x4Sub, v406, v426) T{_Float32x4} | |
[ ] [ ] 0x112d96adc 4ea3d481 vsubs v1, v4, v3 | |
[ ] [ ] ;; v438 <- SimdOp:126(Float32x4Mul, v204, v214) T{_Float32x4} | |
[ ] [ ] 0x112d96ae0 6e22dcc3 vmuls v3, v6, v2 | |
[ ] [ ] ;; v440 <- SimdOp:128(Float32x4Shuffle, mask = 177, v438) T{_Float32x4} | |
[ ] [ ] 0x112d96ae4 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x112d96ae8 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x112d96aec 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x112d96af0 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v446 <- SimdOp:130(Float32x4Mul, v328, v440) T{_Float32x4} | |
[ ] [ ] 0x112d96af4 6e24dca3 vmuls v3, v5, v4 | |
[ ] [ ] ;; v452 <- SimdOp:132(Float32x4Sub, v262, v446) T{_Float32x4} | |
[ ] [ ] 0x112d96af8 4ea3d409 vsubs v9, v0, v3 | |
[ ] [ ] ;; v458 <- SimdOp:134(Float32x4Mul, v206, v440) T{_Float32x4} | |
[ ] [ ] 0x112d96afc 6e24dce0 vmuls v0, v7, v4 | |
[ ] [ ] ;; v464 <- SimdOp:136(Float32x4Add, v458, v420) T{_Float32x4} | |
[ ] [ ] 0x112d96b00 4e28d403 vadds v3, v0, v8 | |
[ ] [ ] ;; v466 <- SimdOp:138(Float32x4Shuffle, mask = 78, v440) T{_Float32x4} | |
[ ] [ ] 0x112d96b04 6e044480 vinss v0[0], v4[2] | |
[ ] [ ] 0x112d96b08 6e0c6480 vinss v0[1], v4[3] | |
[ ] [ ] 0x112d96b0c 6e140480 vinss v0[2], v4[0] | |
[ ] [ ] 0x112d96b10 6e1c2480 vinss v0[3], v4[1] | |
[ ] [ ] ;; v472 <- SimdOp:140(Float32x4Mul, v328, v466) T{_Float32x4} | |
[ ] [ ] 0x112d96b14 6e20dca4 vmuls v4, v5, v0 | |
[ ] [ ] ;; v478 <- SimdOp:142(Float32x4Add, v472, v452) T{_Float32x4} | |
[ ] [ ] 0x112d96b18 4e29d488 vadds v8, v4, v9 | |
[ ] [ ] ;; v484 <- SimdOp:144(Float32x4Mul, v206, v466) T{_Float32x4} | |
[ ] [ ] 0x112d96b1c 6e20dce4 vmuls v4, v7, v0 | |
[ ] [ ] ;; v490 <- SimdOp:146(Float32x4Sub, v464, v484) T{_Float32x4} | |
[ ] [ ] 0x112d96b20 4ea4d460 vsubs v0, v3, v4 | |
[ ] [ ] ;; v496 <- SimdOp:148(Float32x4Mul, v204, v328) T{_Float32x4} | |
[ ] [ ] 0x112d96b24 6e25dcc3 vmuls v3, v6, v5 | |
[ ] [ ] ;; v498 <- SimdOp:150(Float32x4Shuffle, mask = 177, v496) T{_Float32x4} | |
[ ] [ ] 0x112d96b28 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x112d96b2c 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x112d96b30 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x112d96b34 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v504 <- SimdOp:152(Float32x4Mul, v214, v498) T{_Float32x4} | |
[ ] [ ] 0x112d96b38 6e24dc43 vmuls v3, v2, v4 | |
[ ] [ ] ;; v510 <- SimdOp:154(Float32x4Add, v504, v478) T{_Float32x4} | |
[ ] [ ] 0x112d96b3c 4e28d465 vadds v5, v3, v8 | |
[ ] [ ] ;; v516 <- SimdOp:156(Float32x4Mul, v206, v498) T{_Float32x4} | |
[ ] [ ] 0x112d96b40 6e24dce3 vmuls v3, v7, v4 | |
[ ] [ ] ;; v522 <- SimdOp:158(Float32x4Sub, v432, v516) T{_Float32x4} | |
[ ] [ ] 0x112d96b44 4ea3d428 vsubs v8, v1, v3 | |
[ ] [ ] ;; v524 <- SimdOp:160(Float32x4Shuffle, mask = 78, v498) T{_Float32x4} | |
[ ] [ ] 0x112d96b48 6e044481 vinss v1[0], v4[2] | |
[ ] [ ] 0x112d96b4c 6e0c6481 vinss v1[1], v4[3] | |
[ ] [ ] 0x112d96b50 6e140481 vinss v1[2], v4[0] | |
[ ] [ ] 0x112d96b54 6e1c2481 vinss v1[3], v4[1] | |
[ ] [ ] ;; v530 <- SimdOp:162(Float32x4Mul, v214, v524) T{_Float32x4} | |
[ ] [ ] 0x112d96b58 6e21dc43 vmuls v3, v2, v1 | |
[ ] [ ] ;; v536 <- SimdOp:164(Float32x4Sub, v510, v530) T{_Float32x4} | |
[ ] [ ] 0x112d96b5c 4ea3d4a2 vsubs v2, v5, v3 | |
[ ] [ ] ;; v542 <- SimdOp:166(Float32x4Mul, v206, v524) T{_Float32x4} | |
[ +3 ms] [ ] 0x112d96b60 6e21dce3 vmuls v3, v7, v1 | |
[ ] [ ] ;; v548 <- SimdOp:168(Float32x4Add, v542, v522) T{_Float32x4} | |
[ ] [ ] 0x112d96b64 4e28d461 vadds v1, v3, v8 | |
[ ] [ ] ;; v554 <- SimdOp:170(Float32x4Mul, v204, v360) T{_Float32x4} | |
[ ] [ ] 0x112d96b68 6e2adcc3 vmuls v3, v6, v10 | |
[ ] [ ] ;; v556 <- SimdOp:172(Float32x4Shuffle, mask = 78, v554) T{_Float32x4} | |
[ ] [ ] 0x112d96b6c 6e044464 vinss v4[0], v3[2] | |
[ ] [ ] 0x112d96b70 6e0c6464 vinss v4[1], v3[3] | |
[ ] [ ] 0x112d96b74 6e140464 vinss v4[2], v3[0] | |
[ ] [ ] 0x112d96b78 6e1c2464 vinss v4[3], v3[1] | |
[ ] [ ] ;; v562 <- SimdOp:174(Float32x4Add, v556, v554) T{_Float32x4} | |
[ ] [ ] 0x112d96b7c 4e23d485 vadds v5, v4, v3 | |
[ ] [ ] ;; v564 <- SimdOp:176(Float32x4Shuffle, mask = 177, v562) T{_Float32x4} | |
[ ] [ ] 0x112d96b80 6e0424a3 vinss v3[0], v5[1] | |
[ ] [ ] 0x112d96b84 6e0c04a3 vinss v3[1], v5[0] | |
[ ] [ ] 0x112d96b88 6e1464a3 vinss v3[2], v5[3] | |
[ ] [ ] 0x112d96b8c 6e1c44a3 vinss v3[3], v5[2] | |
[ ] [ ] ;; v570 <- SimdOp:178(Float32x4Add, v564, v562) T{_Float32x4} | |
[ ] [ ] 0x112d96b90 4e25d464 vadds v4, v3, v5 | |
[ ] [ ] ;; v572 <- SimdOp:180(Float32x4Reciprocal, v570) T{_Float32x4} | |
[ ] [ ] 0x112d96b94 4ea1d883 vrecpes v3, v4 | |
[ ] [ ] 0x112d96b98 4e23fc9f vrecpss v31, v4, v3 | |
[ ] [ ] 0x112d96b9c 6e3fdc63 vmuls v3, v3, v31 | |
[ ] [ ] 0x112d96ba0 4e23fc9f vrecpss v31, v4, v3 | |
[ ] [ ] 0x112d96ba4 6e3fdc63 vmuls v3, v3, v31 | |
[ ] [ ] ;; v578 <- SimdOp:182(Float32x4Add, v572, v572) T{_Float32x4} | |
[ ] [ ] 0x112d96ba8 4e23d465 vadds v5, v3, v3 | |
[ ] [ ] ;; v584 <- SimdOp:184(Float32x4Mul, v572, v572) T{_Float32x4} | |
[ ] [ ] 0x112d96bac 6e23dc66 vmuls v6, v3, v3 | |
[ ] [ ] ;; v590 <- SimdOp:186(Float32x4Mul, v570, v584) T{_Float32x4} | |
[ ] [ ] 0x112d96bb0 6e26dc83 vmuls v3, v4, v6 | |
[ ] [ ] ;; v596 <- SimdOp:188(Float32x4Sub, v578, v590) T{_Float32x4} | |
[ ] [ ] 0x112d96bb4 4ea3d4a4 vsubs v4, v5, v3 | |
[ ] [ ] ;; v598 <- SimdOp:190(Float32x4Shuffle, mask = 0, v596) T{_Float32x4} | |
[ ] [ ] 0x112d96bb8 4e040483 vdups v3, v4[0] | |
[ ] [ ] ;; v604 <- SimdOp:192(Float32x4Mul, v598, v360) T{_Float32x4} | |
[ ] [ ] 0x112d96bbc 6e2adc64 vmuls v4, v3, v10 | |
[ ] [ ] ;; ParallelMove QS-8 <- v4 | |
[ ] [ ] 0x112d96bc0 3c9c03a4 fstrq v4, [fp, #-64] | |
[ ] [ ] ;; v610 <- SimdOp:194(Float32x4Mul, v598, v536) T{_Float32x4} | |
[ ] [ ] 0x112d96bc4 6e22dc65 vmuls v5, v3, v2 | |
[ ] [ ] ;; ParallelMove QS-6 <- v5 | |
[ ] [ ] 0x112d96bc8 3c9d03a5 fstrq v5, [fp, #-48] | |
[ ] [ ] ;; v616 <- SimdOp:196(Float32x4Mul, v598, v490) T{_Float32x4} | |
[ ] [ ] 0x112d96bcc 6e20dc62 vmuls v2, v3, v0 | |
[ ] [ ] ;; ParallelMove QS-4 <- v2 | |
[ ] [ ] 0x112d96bd0 3c9e03a2 fstrq v2, [fp, #-32] | |
[ ] [ ] ;; v622 <- SimdOp:198(Float32x4Mul, v598, v548) T{_Float32x4} | |
[ ] [ ] 0x112d96bd4 6e21dc60 vmuls v0, v3, v1 | |
[ ] [ ] ;; ParallelMove QS-2 <- v0 | |
[ ] [ ] 0x112d96bd8 3c9f03a0 fstrq v0, [fp, #-16] | |
[ ] [ ] ;; ParallelMove QS-8 <- v4, QS-6 <- v5, QS-4 <- v2, QS-2 <- v0 | |
[ ] [ ] 0x112d96bdc 3c9c03a4 fstrq v4, [fp, #-64] | |
[ ] [ ] 0x112d96be0 3c9d03a5 fstrq v5, [fp, #-48] | |
[ ] [ ] 0x112d96be4 3c9e03a2 fstrq v2, [fp, #-32] | |
[ ] [ ] 0x112d96be8 3c9f03a0 fstrq v0, [fp, #-16] | |
[ ] [ ] ;; v198 <- AllocateObject(SimdMatrix4 <not-aliased>) T{SimdMatrix4} | |
[ ] [ ] 0x112d96bec 94000000 bl 0x112d96bec | |
[ ] [ ] ;; ParallelMove r0 <- r0, v0 <- QS-8 | |
[ ] [ ] 0x112d96bf0 3cdc03a0 fldrq v0, [fp, #-64] | |
[ ] [ ] ;; StoreInstanceField(v198 . _column0@18166706 = v604, NoStoreBarrier) | |
[ ] [ ] ;; UnboxedFloat32x4StoreInstanceFieldInstr | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96bf4 3c807000 fstrq v0, [r0, #7] | |
[ ] [ ] ;; ParallelMove v0 <- QS-6 | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96bf8 3cdd03a0 fldrq v0, [fp, #-48] | |
[ ] [ ] ;; StoreInstanceField(v198 . _column1@18166706 = v610, NoStoreBarrier) | |
[ ] [ ] ;; UnboxedFloat32x4StoreInstanceFieldInstr | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96bfc 3c817000 fstrq v0, [r0, #23] | |
[ ] [ ] ;; ParallelMove v0 <- QS-4 | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96c00 3cde03a0 fldrq v0, [fp, #-32] | |
[ ] [ ] ;; StoreInstanceField(v198 . _column2@18166706 = v616, NoStoreBarrier) | |
[ ] [ ] ;; UnboxedFloat32x4StoreInstanceFieldInstr | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96c04 3c827000 fstrq v0, [r0, #39] | |
[ ] [ ] ;; ParallelMove v0 <- QS-2 | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96c08 3cdf03a0 fldrq v0, [fp, #-16] | |
[ ] [ ] ;; StoreInstanceField(v198 . _column3@18166706 = v622, NoStoreBarrier) | |
[ ] [ ] ;; UnboxedFloat32x4StoreInstanceFieldInstr | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x112d96c0c 3c837000 fstrq v0, [r0, #55] | |
[ ] [ ] ;; ParallelMove r0 <- r0 | |
[ ] [ ] ;; Return:204(v198) | |
[ ] [ ] 0x112d96c10 aa1d03ef mov r15, fp | |
[ ] [ ] 0x112d96c14 a8c179fd ldp fp, lr, [r15], #16 ! | |
[ ] [ ] 0x112d96c18 d65f03c0 ret lr | |
[ ] [ ] } | |
[ ] [ ] (No object pool for bare instructions.) |
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[ ] [ ] Code for optimized function 'package:hello_world/main.dart_SimdMatrix4_invert' { | |
[ ] [ ] ;; B0 | |
[ ] [ ] ;; B1 | |
[ ] [ ] ;; Enter frame | |
[ ] [ ] 0x106117500 a9bf79fd stp fp, lr, [r15, #-16 ]! | |
[ ] [ ] 0x106117504 aa0f03fd mov fp, r15 | |
[ ] [ ] 0x106117508 d10121ef subi r15, r15, 0x48 | |
[ ] [ ] ;; CheckStackOverflow:8(stack=0, loop=0) | |
[ ] [ ] 0x10611750c f9402750 ldrx ip0, [thr, #72] | |
[ ] [ ] 0x106117510 eb1001ff cmp r15, ip0 | |
[ ] [ ] 0x106117514 54002ac9 bls 0x106117a6c | |
[ ] [ ] ;; ParallelMove r0 <- S+2 | |
[ ] [ ] 0x106117518 f9400ba0 ldrx r0, [fp, #16] | |
[ ] [ ] ;; v3 <- LoadField(v2 . _data@18166706 {final}) T{_Float32x4List?} | |
[ ] [ ] 0x10611751c f8407002 ldrx r2, [r0, #7] | |
[ ] [ ] ;; CheckNull:14(v3, NoSuchMethodError) T{_Float32x4List} | |
[ ] [ ] 0x106117520 eb16005f cmp r2, nr | |
[ ] [ ] 0x106117524 54002a80 beq 0x106117a74 | |
[ ] [ ] ;; v219 <- LoadField(v3 T{_Float32x4List} . TypedDataBase.length {final}) [0, 4611686018427387903] T{_Smi} | |
[ ] [ ] 0x106117528 f840f043 ldrx r3, [r2, #15] | |
[ ] [ ] ;; ParallelMove r0 <- r3, r1 <- C | |
[ ] [ ] 0x10611752c aa0303e0 mov r0, r3 | |
[ ] [ ] 0x106117530 d2800001 movz r1, 0x0 | |
[ ] [ ] ;; GenericCheckBound:16(v219, v5) [-4611686018427387904, 4611686018427387903] T{_Smi} | |
[ ] [ ] 0x106117534 eb00003f cmp r1, r0 | |
[ ] [ ] 0x106117538 54002a02 bcs 0x106117a78 | |
[ ] [ ] ;; v223 <- LoadIndexed(v3 T{_Float32x4List}, v5) T{_Float32x4} | |
[ ] [ ] 0x10611753c 3cc17040 fldrq v0, [r2, #23] | |
[ ] [ ] ;; ParallelMove r0 <- r3, r1 <- C | |
[ ] [ ] 0x106117540 aa0303e0 mov r0, r3 | |
[ ] [ ] 0x106117544 d2800041 movz r1, 0x2 | |
[ ] [ ] ;; GenericCheckBound:22(v219, v10) [-4611686018427387904, 4611686018427387903] T{_Smi} | |
[ ] [ ] 0x106117548 eb00003f cmp r1, r0 | |
[ ] [ ] 0x10611754c 54002982 bcs 0x106117a7c | |
[ ] [ ] ;; v229 <- LoadIndexed(v3 T{_Float32x4List}, v10) T{_Float32x4} | |
[ ] [ ] 0x106117550 3cc27041 fldrq v1, [r2, #39] | |
[ ] [ ] ;; ParallelMove r0 <- r3, r1 <- C | |
[ ] [ ] 0x106117554 aa0303e0 mov r0, r3 | |
[ ] [ ] 0x106117558 d2800081 movz r1, 0x4 | |
[ ] [ ] ;; GenericCheckBound:28(v219, v15) [-4611686018427387904, 4611686018427387903] T{_Smi} | |
[ ] [ ] 0x10611755c eb00003f cmp r1, r0 | |
[ ] [ ] 0x106117560 54002902 bcs 0x106117a80 | |
[ ] [ ] ;; v235 <- LoadIndexed(v3 T{_Float32x4List}, v15) T{_Float32x4} | |
[ ] [ ] 0x106117564 3cc37042 fldrq v2, [r2, #55] | |
[ ] [ ] ;; ParallelMove r0 <- r3, r1 <- C | |
[ ] [ ] 0x106117568 aa0303e0 mov r0, r3 | |
[ ] [ ] 0x10611756c d28000c1 movz r1, 0x6 | |
[ ] [ ] ;; GenericCheckBound:34(v219, v20) [-4611686018427387904, 4611686018427387903] T{_Smi} | |
[ ] [ ] 0x106117570 eb00003f cmp r1, r0 | |
[ ] [ ] 0x106117574 54002882 bcs 0x106117a84 | |
[ ] [ ] ;; v241 <- LoadIndexed(v3 T{_Float32x4List}, v20) T{_Float32x4} | |
[ ] [ ] 0x106117578 3cc47043 fldrq v3, [r2, #71] | |
[ ] [ ] ;; v243 <- SimdOp:36(Float32x4ShuffleMix, mask = 68, v223, v229) T{_Float32x4} | |
[ ] [ ] 0x10611757c 6e040404 vinss v4[0], v0[0] | |
[ ] [ ] 0x106117580 6e0c2404 vinss v4[1], v0[1] | |
[ ] [ ] 0x106117584 6e140424 vinss v4[2], v1[0] | |
[ ] [ ] 0x106117588 6e1c2424 vinss v4[3], v1[1] | |
[ ] [ ] ;; v245 <- SimdOp:38(Float32x4ShuffleMix, mask = 68, v235, v241) T{_Float32x4} | |
[ ] [ ] 0x10611758c 6e040445 vinss v5[0], v2[0] | |
[ ] [ ] 0x106117590 6e0c2445 vinss v5[1], v2[1] | |
[ ] [ ] 0x106117594 6e140465 vinss v5[2], v3[0] | |
[ ] [ ] 0x106117598 6e1c2465 vinss v5[3], v3[1] | |
[ ] [ ] ;; v247 <- SimdOp:40(Float32x4ShuffleMix, mask = 136, v243, v245) T{_Float32x4} | |
[ ] [ ] 0x10611759c 6e040486 vinss v6[0], v4[0] | |
[ ] [ ] 0x1061175a0 6e0c4486 vinss v6[1], v4[2] | |
[ ] [ ] 0x1061175a4 6e1404a6 vinss v6[2], v5[0] | |
[ ] [ ] 0x1061175a8 6e1c44a6 vinss v6[3], v5[2] | |
[ ] [ ] ;; v249 <- SimdOp:42(Float32x4ShuffleMix, mask = 221, v245, v243) T{_Float32x4} | |
[ ] [ ] 0x1061175ac 6e0424a7 vinss v7[0], v5[1] | |
[ ] [ ] 0x1061175b0 6e0c64a7 vinss v7[1], v5[3] | |
[ ] [ ] 0x1061175b4 6e142487 vinss v7[2], v4[1] | |
[ ] [ ] 0x1061175b8 6e1c6487 vinss v7[3], v4[3] | |
[ ] [ ] ;; v251 <- SimdOp:44(Float32x4ShuffleMix, mask = 238, v223, v229) T{_Float32x4} | |
[ ] [ ] 0x1061175bc 6e044404 vinss v4[0], v0[2] | |
[ ] [ ] 0x1061175c0 6e0c6404 vinss v4[1], v0[3] | |
[ ] [ ] 0x1061175c4 6e144424 vinss v4[2], v1[2] | |
[ ] [ ] 0x1061175c8 6e1c6424 vinss v4[3], v1[3] | |
[ ] [ ] ;; v253 <- SimdOp:46(Float32x4ShuffleMix, mask = 238, v235, v241) T{_Float32x4} | |
[ ] [ ] 0x1061175cc 6e044440 vinss v0[0], v2[2] | |
[ ] [ ] 0x1061175d0 6e0c6440 vinss v0[1], v2[3] | |
[ ] [ ] 0x1061175d4 6e144460 vinss v0[2], v3[2] | |
[ ] [ ] 0x1061175d8 6e1c6460 vinss v0[3], v3[3] | |
[ ] [ ] ;; v255 <- SimdOp:48(Float32x4ShuffleMix, mask = 136, v251, v253) T{_Float32x4} | |
[ ] [ ] 0x1061175dc 6e040481 vinss v1[0], v4[0] | |
[ ] [ ] 0x1061175e0 6e0c4481 vinss v1[1], v4[2] | |
[ ] [ ] 0x1061175e4 6e140401 vinss v1[2], v0[0] | |
[ ] [ ] 0x1061175e8 6e1c4401 vinss v1[3], v0[2] | |
[ ] [ ] ;; v257 <- SimdOp:50(Float32x4ShuffleMix, mask = 221, v253, v251) T{_Float32x4} | |
[ ] [ ] 0x1061175ec 6e042402 vinss v2[0], v0[1] | |
[ ] [ ] 0x1061175f0 6e0c6402 vinss v2[1], v0[3] | |
[ ] [ ] 0x1061175f4 6e142482 vinss v2[2], v4[1] | |
[ ] [ ] 0x1061175f8 6e1c6482 vinss v2[3], v4[3] | |
[ ] [ ] ;; v263 <- SimdOp:52(Float32x4Mul, v255, v257) T{_Float32x4} | |
[ ] [ ] 0x1061175fc 6e22dc20 vmuls v0, v1, v2 | |
[ ] [ ] ;; v265 <- SimdOp:54(Float32x4Shuffle, mask = 177, v263) T{_Float32x4} | |
[ ] [ ] 0x106117600 6e042403 vinss v3[0], v0[1] | |
[ ] [ ] 0x106117604 6e0c0403 vinss v3[1], v0[0] | |
[ ] [ ] 0x106117608 6e146403 vinss v3[2], v0[3] | |
[ ] [ ] 0x10611760c 6e1c4403 vinss v3[3], v0[2] | |
[ ] [ ] ;; v271 <- SimdOp:56(Float32x4Mul, v249, v265) T{_Float32x4} | |
[ ] [ ] 0x106117610 6e23dce0 vmuls v0, v7, v3 | |
[ ] [ ] ;; v277 <- SimdOp:58(Float32x4Mul, v247, v265) T{_Float32x4} | |
[ ] [ ] 0x106117614 6e23dcc4 vmuls v4, v6, v3 | |
[ ] [ ] ;; v279 <- SimdOp:60(Float32x4Shuffle, mask = 78, v265) T{_Float32x4} | |
[ ] [ ] 0x106117618 6e044465 vinss v5[0], v3[2] | |
[ ] [ ] 0x10611761c 6e0c6465 vinss v5[1], v3[3] | |
[ ] [ ] 0x106117620 6e140465 vinss v5[2], v3[0] | |
[ ] [ ] 0x106117624 6e1c2465 vinss v5[3], v3[1] | |
[ ] [ ] ;; v285 <- SimdOp:62(Float32x4Mul, v249, v279) T{_Float32x4} | |
[ ] [ ] 0x106117628 6e25dce3 vmuls v3, v7, v5 | |
[ ] [ ] ;; v291 <- SimdOp:64(Float32x4Sub, v285, v271) T{_Float32x4} | |
[ ] [ ] 0x10611762c 4ea0d468 vsubs v8, v3, v0 | |
[ ] [ ] ;; v297 <- SimdOp:66(Float32x4Mul, v247, v279) T{_Float32x4} | |
[ ] [ ] 0x106117630 6e25dcc0 vmuls v0, v6, v5 | |
[ ] [ ] ;; v303 <- SimdOp:68(Float32x4Sub, v297, v277) T{_Float32x4} | |
[ ] [ ] 0x106117634 4ea4d403 vsubs v3, v0, v4 | |
[ ] [ ] ;; v305 <- SimdOp:70(Float32x4Shuffle, mask = 78, v303) T{_Float32x4} | |
[ ] [ ] 0x106117638 6e044460 vinss v0[0], v3[2] | |
[ ] [ ] 0x10611763c 6e0c6460 vinss v0[1], v3[3] | |
[ ] [ ] 0x106117640 6e140460 vinss v0[2], v3[0] | |
[ ] [ ] 0x106117644 6e1c2460 vinss v0[3], v3[1] | |
[ ] [ ] ;; v311 <- SimdOp:72(Float32x4Mul, v249, v255) T{_Float32x4} | |
[ ] [ ] 0x106117648 6e21dce3 vmuls v3, v7, v1 | |
[ ] [ ] ;; v313 <- SimdOp:74(Float32x4Shuffle, mask = 177, v311) T{_Float32x4} | |
[ ] [ ] 0x10611764c 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x106117650 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x106117654 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x106117658 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v319 <- SimdOp:76(Float32x4Mul, v257, v313) T{_Float32x4} | |
[ ] [ ] 0x10611765c 6e24dc43 vmuls v3, v2, v4 | |
[ ] [ ] ;; v325 <- SimdOp:78(Float32x4Add, v319, v291) T{_Float32x4} | |
[ ] [ ] 0x106117660 4e28d465 vadds v5, v3, v8 | |
[ ] [ ] ;; v331 <- SimdOp:80(Float32x4Mul, v247, v313) T{_Float32x4} | |
[ ] [ ] 0x106117664 6e24dcc3 vmuls v3, v6, v4 | |
[ ] [ ] ;; v333 <- SimdOp:82(Float32x4Shuffle, mask = 78, v313) T{_Float32x4} | |
[ ] [ ] 0x106117668 6e044488 vinss v8[0], v4[2] | |
[ ] [ ] 0x10611766c 6e0c6488 vinss v8[1], v4[3] | |
[ ] [ ] 0x106117670 6e140488 vinss v8[2], v4[0] | |
[ ] [ ] 0x106117674 6e1c2488 vinss v8[3], v4[1] | |
[ ] [ ] ;; v339 <- SimdOp:84(Float32x4Mul, v257, v333) T{_Float32x4} | |
[ ] [ ] 0x106117678 6e28dc44 vmuls v4, v2, v8 | |
[ ] [ ] ;; v345 <- SimdOp:86(Float32x4Sub, v325, v339) T{_Float32x4} | |
[ ] [ ] 0x10611767c 4ea4d4a9 vsubs v9, v5, v4 | |
[ ] [ ] ;; v351 <- SimdOp:88(Float32x4Mul, v247, v333) T{_Float32x4} | |
[ ] [ ] 0x106117680 6e28dcc4 vmuls v4, v6, v8 | |
[ ] [ ] ;; v357 <- SimdOp:90(Float32x4Sub, v351, v331) T{_Float32x4} | |
[ ] [ ] 0x106117684 4ea3d485 vsubs v5, v4, v3 | |
[ ] [ ] ;; v359 <- SimdOp:92(Float32x4Shuffle, mask = 78, v357) T{_Float32x4} | |
[ ] [ ] 0x106117688 6e0444a3 vinss v3[0], v5[2] | |
[ ] [ ] 0x10611768c 6e0c64a3 vinss v3[1], v5[3] | |
[ ] [ ] 0x106117690 6e1404a3 vinss v3[2], v5[0] | |
[ ] [ ] 0x106117694 6e1c24a3 vinss v3[3], v5[1] | |
[ ] [ ] ;; v361 <- SimdOp:94(Float32x4Shuffle, mask = 78, v249) T{_Float32x4} | |
[ ] [ ] 0x106117698 6e0444e4 vinss v4[0], v7[2] | |
[ ] [ ] 0x10611769c 6e0c64e4 vinss v4[1], v7[3] | |
[ ] [ ] 0x1061176a0 6e1404e4 vinss v4[2], v7[0] | |
[ ] [ ] 0x1061176a4 6e1c24e4 vinss v4[3], v7[1] | |
[ ] [ ] ;; v367 <- SimdOp:96(Float32x4Mul, v361, v257) T{_Float32x4} | |
[ ] [ ] 0x1061176a8 6e22dc85 vmuls v5, v4, v2 | |
[ ] [ ] ;; v369 <- SimdOp:98(Float32x4Shuffle, mask = 177, v367) T{_Float32x4} | |
[ ] [ ] 0x1061176ac 6e0424a4 vinss v4[0], v5[1] | |
[ ] [ ] 0x1061176b0 6e0c04a4 vinss v4[1], v5[0] | |
[ ] [ ] 0x1061176b4 6e1464a4 vinss v4[2], v5[3] | |
[ ] [ ] 0x1061176b8 6e1c44a4 vinss v4[3], v5[2] | |
[ ] [ ] ;; v371 <- SimdOp:100(Float32x4Shuffle, mask = 78, v255) T{_Float32x4} | |
[ ] [ ] 0x1061176bc 6e044425 vinss v5[0], v1[2] | |
[ ] [ ] 0x1061176c0 6e0c6425 vinss v5[1], v1[3] | |
[ ] [ ] 0x1061176c4 6e140425 vinss v5[2], v1[0] | |
[ ] [ ] 0x1061176c8 6e1c2425 vinss v5[3], v1[1] | |
[ ] [ ] ;; v377 <- SimdOp:102(Float32x4Mul, v371, v369) T{_Float32x4} | |
[ ] [ ] 0x1061176cc 6e24dca1 vmuls v1, v5, v4 | |
[ ] [ ] ;; v383 <- SimdOp:104(Float32x4Add, v377, v345) T{_Float32x4} | |
[ ] [ ] 0x1061176d0 4e29d428 vadds v8, v1, v9 | |
[ ] [ ] ;; v389 <- SimdOp:106(Float32x4Mul, v247, v369) T{_Float32x4} | |
[ ] [ ] 0x1061176d4 6e24dcc1 vmuls v1, v6, v4 | |
[ ] [ ] ;; v391 <- SimdOp:108(Float32x4Shuffle, mask = 78, v369) T{_Float32x4} | |
[ ] [ ] 0x1061176d8 6e044489 vinss v9[0], v4[2] | |
[ ] [ ] 0x1061176dc 6e0c6489 vinss v9[1], v4[3] | |
[ ] [ ] 0x1061176e0 6e140489 vinss v9[2], v4[0] | |
[ ] [ ] 0x1061176e4 6e1c2489 vinss v9[3], v4[1] | |
[ ] [ ] ;; v397 <- SimdOp:110(Float32x4Mul, v371, v391) T{_Float32x4} | |
[ ] [ ] 0x1061176e8 6e29dca4 vmuls v4, v5, v9 | |
[ ] [ ] ;; v403 <- SimdOp:112(Float32x4Sub, v383, v397) T{_Float32x4} | |
[ ] [ ] 0x1061176ec 4ea4d50a vsubs v10, v8, v4 | |
[ ] [ ] ;; v409 <- SimdOp:114(Float32x4Mul, v247, v391) T{_Float32x4} | |
[ ] [ ] 0x1061176f0 6e29dcc4 vmuls v4, v6, v9 | |
[ ] [ ] ;; v415 <- SimdOp:116(Float32x4Sub, v409, v389) T{_Float32x4} | |
[ ] [ ] 0x1061176f4 4ea1d488 vsubs v8, v4, v1 | |
[ ] [ ] ;; v417 <- SimdOp:118(Float32x4Shuffle, mask = 78, v415) T{_Float32x4} | |
[ ] [ ] 0x1061176f8 6e044501 vinss v1[0], v8[2] | |
[ ] [ ] 0x1061176fc 6e0c6501 vinss v1[1], v8[3] | |
[ ] [ ] 0x106117700 6e140501 vinss v1[2], v8[0] | |
[ ] [ ] 0x106117704 6e1c2501 vinss v1[3], v8[1] | |
[ ] [ ] ;; v423 <- SimdOp:120(Float32x4Mul, v247, v249) T{_Float32x4} | |
[ ] [ ] 0x106117708 6e27dcc4 vmuls v4, v6, v7 | |
[ ] [ ] ;; v425 <- SimdOp:122(Float32x4Shuffle, mask = 177, v423) T{_Float32x4} | |
[ ] [ ] 0x10611770c 6e042488 vinss v8[0], v4[1] | |
[ ] [ ] 0x106117710 6e0c0488 vinss v8[1], v4[0] | |
[ ] [ ] 0x106117714 6e146488 vinss v8[2], v4[3] | |
[ ] [ ] 0x106117718 6e1c4488 vinss v8[3], v4[2] | |
[ ] [ ] ;; v431 <- SimdOp:124(Float32x4Mul, v257, v425) T{_Float32x4} | |
[ ] [ ] 0x10611771c 6e28dc44 vmuls v4, v2, v8 | |
[ ] [ ] ;; v437 <- SimdOp:126(Float32x4Add, v431, v417) T{_Float32x4} | |
[ ] [ ] 0x106117720 4e21d489 vadds v9, v4, v1 | |
[ ] [ ] ;; v443 <- SimdOp:128(Float32x4Mul, v371, v425) T{_Float32x4} | |
[ ] [ ] 0x106117724 6e28dca1 vmuls v1, v5, v8 | |
[ ] [ ] ;; v449 <- SimdOp:130(Float32x4Sub, v443, v359) T{_Float32x4} | |
[ ] [ ] 0x106117728 4ea3d424 vsubs v4, v1, v3 | |
[ ] [ ] ;; v451 <- SimdOp:132(Float32x4Shuffle, mask = 78, v425) T{_Float32x4} | |
[ ] [ ] 0x10611772c 6e044501 vinss v1[0], v8[2] | |
[ ] [ ] 0x106117730 6e0c6501 vinss v1[1], v8[3] | |
[ ] [ ] 0x106117734 6e140501 vinss v1[2], v8[0] | |
[ ] [ ] 0x106117738 6e1c2501 vinss v1[3], v8[1] | |
[ ] [ ] ;; v457 <- SimdOp:134(Float32x4Mul, v257, v451) T{_Float32x4} | |
[ ] [ ] 0x10611773c 6e21dc43 vmuls v3, v2, v1 | |
[ ] [ ] ;; v463 <- SimdOp:136(Float32x4Sub, v457, v437) T{_Float32x4} | |
[ ] [ ] 0x106117740 4ea9d468 vsubs v8, v3, v9 | |
[ ] [ ] ;; v469 <- SimdOp:138(Float32x4Mul, v371, v451) T{_Float32x4} | |
[ ] [ ] 0x106117744 6e21dca3 vmuls v3, v5, v1 | |
[ ] [ ] ;; v475 <- SimdOp:140(Float32x4Sub, v449, v469) T{_Float32x4} | |
[ ] [ ] 0x106117748 4ea3d481 vsubs v1, v4, v3 | |
[ ] [ ] ;; v481 <- SimdOp:142(Float32x4Mul, v247, v257) T{_Float32x4} | |
[ ] [ ] 0x10611774c 6e22dcc3 vmuls v3, v6, v2 | |
[ ] [ ] ;; v483 <- SimdOp:144(Float32x4Shuffle, mask = 177, v481) T{_Float32x4} | |
[ ] [ ] 0x106117750 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x106117754 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x106117758 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x10611775c 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v489 <- SimdOp:146(Float32x4Mul, v371, v483) T{_Float32x4} | |
[ ] [ ] 0x106117760 6e24dca3 vmuls v3, v5, v4 | |
[ ] [ ] ;; v495 <- SimdOp:148(Float32x4Sub, v305, v489) T{_Float32x4} | |
[ ] [ ] 0x106117764 4ea3d409 vsubs v9, v0, v3 | |
[ ] [ ] ;; v501 <- SimdOp:150(Float32x4Mul, v249, v483) T{_Float32x4} | |
[ ] [ ] 0x106117768 6e24dce0 vmuls v0, v7, v4 | |
[ ] [ ] ;; v507 <- SimdOp:152(Float32x4Add, v501, v463) T{_Float32x4} | |
[ ] [ ] 0x10611776c 4e28d403 vadds v3, v0, v8 | |
[ ] [ ] ;; v509 <- SimdOp:154(Float32x4Shuffle, mask = 78, v483) T{_Float32x4} | |
[ ] [ ] 0x106117770 6e044480 vinss v0[0], v4[2] | |
[ ] [ ] 0x106117774 6e0c6480 vinss v0[1], v4[3] | |
[ ] [ ] 0x106117778 6e140480 vinss v0[2], v4[0] | |
[ ] [ ] 0x10611777c 6e1c2480 vinss v0[3], v4[1] | |
[ ] [ ] ;; v515 <- SimdOp:156(Float32x4Mul, v371, v509) T{_Float32x4} | |
[ ] [ ] 0x106117780 6e20dca4 vmuls v4, v5, v0 | |
[ ] [ ] ;; v521 <- SimdOp:158(Float32x4Add, v515, v495) T{_Float32x4} | |
[ ] [ ] 0x106117784 4e29d488 vadds v8, v4, v9 | |
[ ] [ ] ;; v527 <- SimdOp:160(Float32x4Mul, v249, v509) T{_Float32x4} | |
[ ] [ ] 0x106117788 6e20dce4 vmuls v4, v7, v0 | |
[ ] [ ] ;; v533 <- SimdOp:162(Float32x4Sub, v507, v527) T{_Float32x4} | |
[ ] [ ] 0x10611778c 4ea4d460 vsubs v0, v3, v4 | |
[ ] [ ] ;; v539 <- SimdOp:164(Float32x4Mul, v247, v371) T{_Float32x4} | |
[ ] [ ] 0x106117790 6e25dcc3 vmuls v3, v6, v5 | |
[ ] [ ] ;; v541 <- SimdOp:166(Float32x4Shuffle, mask = 177, v539) T{_Float32x4} | |
[ ] [ ] 0x106117794 6e042464 vinss v4[0], v3[1] | |
[ ] [ ] 0x106117798 6e0c0464 vinss v4[1], v3[0] | |
[ ] [ ] 0x10611779c 6e146464 vinss v4[2], v3[3] | |
[ ] [ ] 0x1061177a0 6e1c4464 vinss v4[3], v3[2] | |
[ ] [ ] ;; v547 <- SimdOp:168(Float32x4Mul, v257, v541) T{_Float32x4} | |
[ ] [ ] 0x1061177a4 6e24dc43 vmuls v3, v2, v4 | |
[ ] [ ] ;; v553 <- SimdOp:170(Float32x4Add, v547, v521) T{_Float32x4} | |
[ ] [ ] 0x1061177a8 4e28d465 vadds v5, v3, v8 | |
[ ] [ ] ;; v559 <- SimdOp:172(Float32x4Mul, v249, v541) T{_Float32x4} | |
[ ] [ ] 0x1061177ac 6e24dce3 vmuls v3, v7, v4 | |
[ ] [ ] ;; v565 <- SimdOp:174(Float32x4Sub, v475, v559) T{_Float32x4} | |
[ ] [ ] 0x1061177b0 4ea3d428 vsubs v8, v1, v3 | |
[ ] [ ] ;; v567 <- SimdOp:176(Float32x4Shuffle, mask = 78, v541) T{_Float32x4} | |
[ ] [ ] 0x1061177b4 6e044481 vinss v1[0], v4[2] | |
[ ] [ ] 0x1061177b8 6e0c6481 vinss v1[1], v4[3] | |
[ ] [ ] 0x1061177bc 6e140481 vinss v1[2], v4[0] | |
[ ] [ ] 0x1061177c0 6e1c2481 vinss v1[3], v4[1] | |
[ ] [ ] ;; v573 <- SimdOp:178(Float32x4Mul, v257, v567) T{_Float32x4} | |
[ ] [ ] 0x1061177c4 6e21dc43 vmuls v3, v2, v1 | |
[ ] [ ] ;; v579 <- SimdOp:180(Float32x4Sub, v553, v573) T{_Float32x4} | |
[ ] [ ] 0x1061177c8 4ea3d4a2 vsubs v2, v5, v3 | |
[ ] [ ] ;; v585 <- SimdOp:182(Float32x4Mul, v249, v567) T{_Float32x4} | |
[ ] [ ] 0x1061177cc 6e21dce3 vmuls v3, v7, v1 | |
[ ] [ ] ;; v591 <- SimdOp:184(Float32x4Add, v585, v565) T{_Float32x4} | |
[ ] [ ] 0x1061177d0 4e28d461 vadds v1, v3, v8 | |
[ ] [ ] ;; v597 <- SimdOp:186(Float32x4Mul, v247, v403) T{_Float32x4} | |
[ ] [ ] 0x1061177d4 6e2adcc3 vmuls v3, v6, v10 | |
[ ] [ ] ;; v599 <- SimdOp:188(Float32x4Shuffle, mask = 78, v597) T{_Float32x4} | |
[ ] [ ] 0x1061177d8 6e044464 vinss v4[0], v3[2] | |
[ ] [ ] 0x1061177dc 6e0c6464 vinss v4[1], v3[3] | |
[ ] [ ] 0x1061177e0 6e140464 vinss v4[2], v3[0] | |
[ ] [ ] 0x1061177e4 6e1c2464 vinss v4[3], v3[1] | |
[ ] [ ] ;; v605 <- SimdOp:190(Float32x4Add, v599, v597) T{_Float32x4} | |
[ ] [ ] 0x1061177e8 4e23d485 vadds v5, v4, v3 | |
[ ] [ ] ;; v607 <- SimdOp:192(Float32x4Shuffle, mask = 177, v605) T{_Float32x4} | |
[ ] [ ] 0x1061177ec 6e0424a3 vinss v3[0], v5[1] | |
[ ] [ ] 0x1061177f0 6e0c04a3 vinss v3[1], v5[0] | |
[ ] [ ] 0x1061177f4 6e1464a3 vinss v3[2], v5[3] | |
[ ] [ ] 0x1061177f8 6e1c44a3 vinss v3[3], v5[2] | |
[ ] [ ] ;; v613 <- SimdOp:194(Float32x4Add, v607, v605) T{_Float32x4} | |
[ ] [ ] 0x1061177fc 4e25d464 vadds v4, v3, v5 | |
[ ] [ ] ;; v615 <- SimdOp:196(Float32x4Reciprocal, v613) T{_Float32x4} | |
[ ] [ ] 0x106117800 4ea1d883 vrecpes v3, v4 | |
[ ] [ ] 0x106117804 4e23fc9f vrecpss v31, v4, v3 | |
[ ] [ ] 0x106117808 6e3fdc63 vmuls v3, v3, v31 | |
[ ] [ ] 0x10611780c 4e23fc9f vrecpss v31, v4, v3 | |
[ ] [ ] 0x106117810 6e3fdc63 vmuls v3, v3, v31 | |
[ ] [ ] ;; v621 <- SimdOp:198(Float32x4Add, v615, v615) T{_Float32x4} | |
[ ] [ ] 0x106117814 4e23d465 vadds v5, v3, v3 | |
[ ] [ ] ;; v627 <- SimdOp:200(Float32x4Mul, v615, v615) T{_Float32x4} | |
[ ] [ ] 0x106117818 6e23dc66 vmuls v6, v3, v3 | |
[ ] [ ] ;; v633 <- SimdOp:202(Float32x4Mul, v613, v627) T{_Float32x4} | |
[ ] [ ] 0x10611781c 6e26dc83 vmuls v3, v4, v6 | |
[ ] [ ] ;; v639 <- SimdOp:204(Float32x4Sub, v621, v633) T{_Float32x4} | |
[ ] [ ] 0x106117820 4ea3d4a4 vsubs v4, v5, v3 | |
[ ] [ ] ;; v641 <- SimdOp:206(Float32x4Shuffle, mask = 0, v639) T{_Float32x4} | |
[ ] [ ] 0x106117824 4e040483 vdups v3, v4[0] | |
[ ] [ ] ;; v647 <- SimdOp:208(Float32x4Mul, v641, v403) T{_Float32x4} | |
[ ] [ ] 0x106117828 6e2adc64 vmuls v4, v3, v10 | |
[ ] [ ] ;; ParallelMove QS-9 <- v4 | |
[ ] [ ] 0x10611782c 3c9b83a4 fstrq v4, [fp, #-72] | |
[ ] [ ] ;; v653 <- SimdOp:210(Float32x4Mul, v641, v579) T{_Float32x4} | |
[ ] [ ] 0x106117830 6e22dc65 vmuls v5, v3, v2 | |
[ ] [ ] ;; ParallelMove QS-7 <- v5 | |
[ ] [ ] 0x106117834 3c9c83a5 fstrq v5, [fp, #-56] | |
[ ] [ ] ;; v659 <- SimdOp:212(Float32x4Mul, v641, v533) T{_Float32x4} | |
[ ] [ ] 0x106117838 6e20dc62 vmuls v2, v3, v0 | |
[ ] [ ] ;; ParallelMove QS-5 <- v2 | |
[ ] [ ] 0x10611783c 3c9d83a2 fstrq v2, [fp, #-40] | |
[ ] [ ] ;; v665 <- SimdOp:214(Float32x4Mul, v641, v591) T{_Float32x4} | |
[ ] [ ] 0x106117840 6e21dc60 vmuls v0, v3, v1 | |
[ ] [ ] ;; ParallelMove QS-3 <- v0 | |
[ ] [ ] 0x106117844 3c9e83a0 fstrq v0, [fp, #-24] | |
[ ] [ ] ;; ParallelMove QS-9 <- v4, QS-7 <- v5, QS-5 <- v2, QS-3 <- v0 | |
[ ] [ ] 0x106117848 3c9b83a4 fstrq v4, [fp, #-72] | |
[ ] [ ] 0x10611784c 3c9c83a5 fstrq v5, [fp, #-56] | |
[ ] [ ] 0x106117850 3c9d83a2 fstrq v2, [fp, #-40] | |
[ ] [ ] 0x106117854 3c9e83a0 fstrq v0, [fp, #-24] | |
[ ] [ ] ;; v209 <- AllocateObject(SimdMatrix4 <not-aliased>) T{SimdMatrix4} | |
[ ] [ ] 0x106117858 94000000 bl 0x106117858 | |
[ ] [ ] ;; ParallelMove r1 <- C, r2 <- C, r0 <- r0 | |
[ ] [ ] 0x10611785c f9714761 ldrx r1, [pp, #25224] | |
[ ] [ ] 0x106117860 d2800102 movz r2, 0x8 | |
[ ] [ ] ;; ParallelMove S-1 <- r0 | |
[ ] [ ] 0x106117864 f81f83a0 strx r0, [fp, #-8] | |
[ ] [ ] ;; v213 <- CreateArray:216(v211, v212) T{_List} | |
[ ] [ ] 0x106117868 94000000 bl 0x106117868 | |
[ ] [ ] ;; ParallelMove r2 <- r0, v0 <- QS-9 | |
[ ] [ ] 0x10611786c aa0003e2 mov r2, r0 | |
[ ] [ ] 0x106117870 3cdb83a0 fldrq v0, [fp, #-72] | |
[ ] [ ] ;; v1159 <- Box(v647) T{_Float32x4} | |
[ ] [ ] 0x106117874 f9402f41 ldrx r1, [thr, #88] | |
[ ] [ ] 0x106117878 f9402421 ldrx r1, [r1, #72] | |
[ ] [ ] 0x10611787c f9400021 ldrx r1, [r1] | |
[ ] [ ] 0x106117880 9100e021 addi r1, r1, 0x38 | |
[ ] [ ] 0x106117884 39400021 ldrb r1, [r1] | |
[ ] [ ] 0x106117888 b5001001 cbnz r1, 0x106117a88 | |
[ ] [ ] 0x10611788c a946c340 ldp r0, ip0, [thr, #104 ] | |
[ ] [ ] 0x106117890 91008001 addi r1, r0, 0x20 | |
[ ] [ ] 0x106117894 eb01021f cmp ip0, r1 | |
[ ] [ ] 0x106117898 54000f89 bls 0x106117a88 | |
[ ] [ ] 0x10611789c f9003741 strx r1, [thr, #104] | |
[ ] [ ] 0x1061178a0 d2804090 movz ip0, 0x204 | |
[ ] [ ] 0x1061178a4 f2a00710 movk ip0, 0x38 lsl 16 | |
[ ] [ ] 0x1061178a8 f9000010 strx ip0, [r0] | |
[ ] [ ] 0x1061178ac 91000400 addi r0, r0, 0x1 | |
[ ] [ ] 0x1061178b0 3c807000 fstrq v0, [r0, #7] | |
[ ] [ ] ;; ParallelMove r1 <- r2, r0 <- r0 | |
[ ] [ ] 0x1061178b4 aa0203e1 mov r1, r2 | |
[ ] [ ] ;; StoreIndexed(v213, v5, v1159) | |
[ ] [ ] 0x1061178b8 91005c39 addi r25, r1, 0x17 | |
[ ] [ ] 0x1061178bc f9000320 strx r0, [r25] | |
[ ] [ ] 0x1061178c0 360000e0 tbzw r0, #0, 0x1061178dc | |
[ ] [ ] 0x1061178c4 385ff030 ldrb ip0, [r1, #-1] | |
[ ] [ ] 0x1061178c8 385ff011 ldrb ip1, [r0, #-1] | |
[ ] [ ] 0x1061178cc 8a500a30 and ip0, ip1, ip0 lsr #2 | |
[ ] [ ] 0x1061178d0 ea1c021f ands zr, ip0, ctx | |
[ ] [ ] 0x1061178d4 54000040 beq 0x1061178dc | |
[ ] [ ] 0x1061178d8 94000000 bl 0x1061178d8 | |
[ ] [ ] ;; ParallelMove v0 <- QS-7 | |
[ ] [ ] 0x1061178dc 3cdc83a0 fldrq v0, [fp, #-56] | |
[ ] [ ] ;; v1165 <- Box(v653) T{_Float32x4} | |
[ ] [ ] 0x1061178e0 f9402f41 ldrx r1, [thr, #88] | |
[ ] [ ] 0x1061178e4 f9402421 ldrx r1, [r1, #72] | |
[ ] [ ] 0x1061178e8 f9400021 ldrx r1, [r1] | |
[ ] [ ] 0x1061178ec 9100e021 addi r1, r1, 0x38 | |
[ ] [ ] 0x1061178f0 39400021 ldrb r1, [r1] | |
[ ] [ ] 0x1061178f4 b5000d61 cbnz r1, 0x106117aa0 | |
[ ] [ ] 0x1061178f8 a946c340 ldp r0, ip0, [thr, #104 ] | |
[ ] [ ] 0x1061178fc 91008001 addi r1, r0, 0x20 | |
[ ] [ ] 0x106117900 eb01021f cmp ip0, r1 | |
[ ] [ ] 0x106117904 54000ce9 bls 0x106117aa0 | |
[ ] [ ] 0x106117908 f9003741 strx r1, [thr, #104] | |
[ ] [ ] 0x10611790c d2804090 movz ip0, 0x204 | |
[ ] [ ] 0x106117910 f2a00710 movk ip0, 0x38 lsl 16 | |
[ ] [ ] 0x106117914 f9000010 strx ip0, [r0] | |
[ ] [ ] 0x106117918 91000400 addi r0, r0, 0x1 | |
[ ] [ ] 0x10611791c 3c807000 fstrq v0, [r0, #7] | |
[ ] [ ] ;; ParallelMove r1 <- r2, r0 <- r0 | |
[ ] [ ] 0x106117920 aa0203e1 mov r1, r2 | |
[ ] [ ] ;; StoreIndexed(v213, v10, v1165) | |
[ ] [ ] 0x106117924 91007c39 addi r25, r1, 0x1f | |
[ ] [ ] 0x106117928 f9000320 strx r0, [r25] | |
[ ] [ ] 0x10611792c 360000e0 tbzw r0, #0, 0x106117948 | |
[ ] [ ] 0x106117930 385ff030 ldrb ip0, [r1, #-1] | |
[ ] [ ] 0x106117934 385ff011 ldrb ip1, [r0, #-1] | |
[ ] [ ] 0x106117938 8a500a30 and ip0, ip1, ip0 lsr #2 | |
[ ] [ ] 0x10611793c ea1c021f ands zr, ip0, ctx | |
[ ] [ ] 0x106117940 54000040 beq 0x106117948 | |
[ +12 ms] [ ] 0x106117944 94000000 bl 0x106117944 | |
[ ] [ ] ;; ParallelMove v0 <- QS-5 | |
[ ] [ ] 0x106117948 3cdd83a0 fldrq v0, [fp, #-40] | |
[ ] [ ] ;; v1171 <- Box(v659) T{_Float32x4} | |
[ ] [ ] 0x10611794c f9402f41 ldrx r1, [thr, #88] | |
[ ] [ ] 0x106117950 f9402421 ldrx r1, [r1, #72] | |
[ ] [ ] 0x106117954 f9400021 ldrx r1, [r1] | |
[ ] [ ] 0x106117958 9100e021 addi r1, r1, 0x38 | |
[ ] [ ] 0x10611795c 39400021 ldrb r1, [r1] | |
[ ] [ ] 0x106117960 b5000ac1 cbnz r1, 0x106117ab8 | |
[ ] [ ] 0x106117964 a946c340 ldp r0, ip0, [thr, #104 ] | |
[ ] [ ] 0x106117968 91008001 addi r1, r0, 0x20 | |
[ ] [ ] 0x10611796c eb01021f cmp ip0, r1 | |
[ ] [ ] 0x106117970 54000a49 bls 0x106117ab8 | |
[ ] [ ] 0x106117974 f9003741 strx r1, [thr, #104] | |
[ ] [ ] 0x106117978 d2804090 movz ip0, 0x204 | |
[ ] [ ] 0x10611797c f2a00710 movk ip0, 0x38 lsl 16 | |
[ ] [ ] 0x106117980 f9000010 strx ip0, [r0] | |
[ ] [ ] 0x106117984 91000400 addi r0, r0, 0x1 | |
[ ] [ ] 0x106117988 3c807000 fstrq v0, [r0, #7] | |
[ ] [ ] ;; ParallelMove r1 <- r2, r0 <- r0 | |
[ ] [ ] 0x10611798c aa0203e1 mov r1, r2 | |
[ ] [ ] ;; StoreIndexed(v213, v15, v1171) | |
[ ] [ ] 0x106117990 91009c39 addi r25, r1, 0x27 | |
[ ] [ ] 0x106117994 f9000320 strx r0, [r25] | |
[ ] [ ] 0x106117998 360000e0 tbzw r0, #0, 0x1061179b4 | |
[ ] [ ] 0x10611799c 385ff030 ldrb ip0, [r1, #-1] | |
[ ] [ ] 0x1061179a0 385ff011 ldrb ip1, [r0, #-1] | |
[ ] [ ] 0x1061179a4 8a500a30 and ip0, ip1, ip0 lsr #2 | |
[ ] [ ] 0x1061179a8 ea1c021f ands zr, ip0, ctx | |
[ ] [ ] 0x1061179ac 54000040 beq 0x1061179b4 | |
[ ] [ ] 0x1061179b0 94000000 bl 0x1061179b0 | |
[ ] [ ] ;; ParallelMove v0 <- QS-3 | |
[ ] [ ] 0x1061179b4 3cde83a0 fldrq v0, [fp, #-24] | |
[ ] [ ] ;; v1177 <- Box(v665) T{_Float32x4} | |
[ ] [ ] 0x1061179b8 f9402f41 ldrx r1, [thr, #88] | |
[ ] [ ] 0x1061179bc f9402421 ldrx r1, [r1, #72] | |
[ ] [ ] 0x1061179c0 f9400021 ldrx r1, [r1] | |
[ ] [ ] 0x1061179c4 9100e021 addi r1, r1, 0x38 | |
[ ] [ ] 0x1061179c8 39400021 ldrb r1, [r1] | |
[ ] [ ] 0x1061179cc b5000821 cbnz r1, 0x106117ad0 | |
[ ] [ ] 0x1061179d0 a946c340 ldp r0, ip0, [thr, #104 ] | |
[ ] [ ] 0x1061179d4 91008001 addi r1, r0, 0x20 | |
[ ] [ ] 0x1061179d8 eb01021f cmp ip0, r1 | |
[ ] [ ] 0x1061179dc 540007a9 bls 0x106117ad0 | |
[ ] [ ] 0x1061179e0 f9003741 strx r1, [thr, #104] | |
[ ] [ ] 0x1061179e4 d2804090 movz ip0, 0x204 | |
[ ] [ ] 0x1061179e8 f2a00710 movk ip0, 0x38 lsl 16 | |
[ ] [ ] 0x1061179ec f9000010 strx ip0, [r0] | |
[ ] [ ] 0x1061179f0 91000400 addi r0, r0, 0x1 | |
[ ] [ ] 0x1061179f4 3c807000 fstrq v0, [r0, #7] | |
[ ] [ ] ;; ParallelMove r1 <- r2, r0 <- r0 | |
[ ] [ ] 0x1061179f8 aa0203e1 mov r1, r2 | |
[ ] [ ] ;; StoreIndexed(v213, v20, v1177) | |
[ ] [ ] 0x1061179fc 9100bc39 addi r25, r1, 0x2f | |
[ ] [ ] 0x106117a00 f9000320 strx r0, [r25] | |
[ ] [ ] 0x106117a04 360000e0 tbzw r0, #0, 0x106117a20 | |
[ ] [ ] 0x106117a08 385ff030 ldrb ip0, [r1, #-1] | |
[ ] [ ] 0x106117a0c 385ff011 ldrb ip1, [r0, #-1] | |
[ ] [ ] 0x106117a10 8a500a30 and ip0, ip1, ip0 lsr #2 | |
[ ] [ ] 0x106117a14 ea1c021f ands zr, ip0, ctx | |
[ ] [ ] 0x106117a18 54000040 beq 0x106117a20 | |
[ ] [ ] 0x106117a1c 94000000 bl 0x106117a1c | |
[ ] [ ] ;; PushArgument(v211) | |
[ ] [ ] 0x106117a20 f9714770 ldrx ip0, [pp, #25224] | |
[ ] [ ] 0x106117a24 a9bf41e2 stp r2, ip0, [r15, #-16 ]! | |
[ ] [ ] ;; PushArgument(v213) | |
[ ] [ ] ;; v215 <- StaticCall:218( List._fromLiteral@0150898<0> v211, v213) T{*?} | |
[ ] [ ] 0x106117a28 94000000 bl 0x106117a28 | |
[ ] [ ] 0x106117a2c 910041ef addi r15, r15, 0x10 | |
[ ] [ ] ;; ParallelMove r0 <- r0 | |
[ ] [ ] ;; PushArgument(v0) | |
[ ] [ ] 0x106117a30 a9bf59e0 stp r0, nr, [r15, #-16 ]! | |
[ ] [ ] ;; PushArgument(v215) | |
[ ] [ ] ;; v217 <- StaticCall:220( Float32x4List.fromList<0> v0, v215, result_type = T{_Float32x4List}) T{_Float32x4List} | |
[ ] [ ] 0x106117a34 94000000 bl 0x106117a34 | |
[ ] [ ] 0x106117a38 910041ef addi r15, r15, 0x10 | |
[ ] [ ] ;; ParallelMove r0 <- r0, r1 <- S-1 | |
[ ] [ ] 0x106117a3c f85f83a1 ldrx r1, [fp, #-8] | |
[ ] [ ] ;; StoreInstanceField(v209 . _data@18166706 = v217) | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x106117a40 f8007020 strx r0, [r1, #7] | |
[ ] [ ] 0x106117a44 385ff030 ldrb ip0, [r1, #-1] | |
[ ] [ ] 0x106117a48 385ff011 ldrb ip1, [r0, #-1] | |
[ ] [ ] 0x106117a4c 8a500a30 and ip0, ip1, ip0 lsr #2 | |
[ ] [ ] 0x106117a50 ea1c021f ands zr, ip0, ctx | |
[ ] [ ] 0x106117a54 54000040 beq 0x106117a5c | |
[ ] [ ] 0x106117a58 94000008 bl 0x106117a78 | |
[ ] [ ] ;; ParallelMove r0 <- r1 | |
[ ] [ ] ;; Inlined [SimdMatrix4.SimdMatrix4._@18166706] | |
[ ] [ ] 0x106117a5c aa0103e0 mov r0, r1 | |
[ ] [ ] ;; Return:226(v209) | |
[ ] [ ] 0x106117a60 aa1d03ef mov r15, fp | |
[ ] [ ] 0x106117a64 a8c179fd ldp fp, lr, [r15], #16 ! | |
[ ] [ ] 0x106117a68 d65f03c0 ret lr | |
[ ] [ ] ;; CheckStackOverflowSlowPath | |
[ ] [ ] 0x106117a6c 94000000 bl 0x106117a6c | |
[ ] [ ] 0x106117a70 54ffd54e b 0x106117518 | |
[ ] [ ] ;; slow path check null (nsm) operation | |
[ ] [ ] 0x106117a74 94000000 bl 0x106117a74 | |
[ ] [ ] ;; slow path check bound operation | |
[ ] [ ] 0x106117a78 94000000 bl 0x106117a78 | |
[ ] [ ] ;; slow path check bound operation | |
[ ] [ ] 0x106117a7c 94000000 bl 0x106117a7c | |
[ ] [ ] ;; slow path check bound operation | |
[ ] [ ] 0x106117a80 94000000 bl 0x106117a80 | |
[ ] [ ] ;; slow path check bound operation | |
[ ] [ ] 0x106117a84 94000000 bl 0x106117a84 | |
[ ] [ ] ;; Box slow path allocation of _Float32x4 | |
[ ] [ ] 0x106117a88 3c9f0de0 fstrq v0, [r15, #-16] ! | |
[ ] [ ] 0x106117a8c f81f8de2 strx r2, [r15, #-8] ! | |
[ ] [ ] 0x106117a90 94000000 bl 0x106117a90 | |
[ ] [ ] 0x106117a94 f84085e2 ldrx r2, [r15], #8 ! | |
[ ] [ ] 0x106117a98 3cc105e0 fldrq v0, [r15], #16 ! | |
[ ] [ ] 0x106117a9c 54fff0ae b 0x1061178b0 | |
[ ] [ ] ;; Box slow path allocation of _Float32x4 | |
[ ] [ ] 0x106117aa0 3c9f0de0 fstrq v0, [r15, #-16] ! | |
[ ] [ ] 0x106117aa4 f81f8de2 strx r2, [r15, #-8] ! | |
[ ] [ ] 0x106117aa8 94000000 bl 0x106117aa8 | |
[ ] [ ] 0x106117aac f84085e2 ldrx r2, [r15], #8 ! | |
[ ] [ ] 0x106117ab0 3cc105e0 fldrq v0, [r15], #16 ! | |
[ ] [ ] 0x106117ab4 54fff34e b 0x10611791c | |
[ ] [ ] ;; Box slow path allocation of _Float32x4 | |
[ ] [ ] 0x106117ab8 3c9f0de0 fstrq v0, [r15, #-16] ! | |
[ ] [ ] 0x106117abc f81f8de2 strx r2, [r15, #-8] ! | |
[ ] [ ] 0x106117ac0 94000000 bl 0x106117ac0 | |
[ ] [ ] 0x106117ac4 f84085e2 ldrx r2, [r15], #8 ! | |
[ ] [ ] 0x106117ac8 3cc105e0 fldrq v0, [r15], #16 ! | |
[ ] [ ] 0x106117acc 54fff5ee b 0x106117988 | |
[ ] [ ] ;; Box slow path allocation of _Float32x4 | |
[ ] [ ] 0x106117ad0 3c9f0de0 fstrq v0, [r15, #-16] ! | |
[ ] [ ] 0x106117ad4 f81f8de2 strx r2, [r15, #-8] ! | |
[ ] [ ] 0x106117ad8 94000000 bl 0x106117ad8 | |
[ ] [ ] 0x106117adc f84085e2 ldrx r2, [r15], #8 ! | |
[ ] [ ] 0x106117ae0 3cc105e0 fldrq v0, [r15], #16 ! | |
[ ] [ ] 0x106117ae4 54fff88e b 0x1061179f4 | |
[ ] [ ] } | |
[ ] [ ] (No object pool for bare instructions.) | |
[ ] [ ] Source positions for function 'package:hello_world/main.dart_SimdMatrix4_invert' { |
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/// An implementation of matrix inversion using SIMD. | |
/// | |
/// This is based on https://github.com/tc39/ecmascript_simd/blob/master/src/benchmarks/inverse4x4.js | |
SimdMatrix4 invert() { | |
final Float32x4 src0 = _data[0]; | |
final Float32x4 src1 = _data[1]; | |
final Float32x4 src2 = _data[2]; | |
final Float32x4 src3 = _data[3]; | |
// Incorrect transposition? | |
Float32x4 tmp1 = src0.shuffleMix(src1, Float32x4.xyxy); // 0, 1, 4, 5 | |
Float32x4 row1 = src2.shuffleMix(src3, Float32x4.xyxy); // 0, 1, 4, 5 | |
Float32x4 row0 = tmp1.shuffleMix(row1, Float32x4.xzxz); // 0, 2, 4, 6 | |
row1 = row1.shuffleMix(tmp1, Float32x4.ywyw); // 1, 3, 5, 7 | |
// | |
// | |
tmp1 = src0.shuffleMix(src1, Float32x4.zwzw); // 2, 3, 6, 7 | |
Float32x4 row3 = src2.shuffleMix(src3, Float32x4.zwzw); // 2, 3, 6, 7 | |
Float32x4 row2 = tmp1.shuffleMix(row3, Float32x4.xzxz); // 0, 2, 4, 6 | |
row3 = row3.shuffleMix(tmp1, Float32x4.ywyw); // 1, 3, 5, 7 | |
// | |
// Float32x4 tmp1 = src0.shuffleMix(src1, Float32x4.xyxy); | |
// Float32x4 tmp2 = src2.shuffleMix(src3, Float32x4.xyxy); | |
// Float32x4 row0 = tmp1.shuffleMix(tmp2, Float32x4.xzxz); | |
// Float32x4 row1 = tmp1.shuffleMix(tmp2, Float32x4.ywyw); | |
// tmp1 = src0.shuffleMix(src1, Float32x4.zwzw); | |
// tmp2 = src2.shuffleMix(src3, Float32x4.zwzw); | |
// Float32x4 row2 = tmp1.shuffleMix(tmp2, Float32x4.xzxz); | |
// Float32x4 row3 = tmp1.shuffleMix(tmp2, Float32x4.ywyw); | |
// | |
tmp1 = row2 * row3; | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); // 1, 0, 3, 2 | |
Float32x4 minor0 = row1 * tmp1; | |
Float32x4 minor1 = row0 * tmp1; | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
minor0 = (row1 * tmp1) - minor0; | |
minor1 = (row0 * tmp1) - minor1; | |
minor1 = minor1.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
// | |
// | |
tmp1 = row1 * row2; | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); // 1, 0, 3, 2 | |
minor0 = (row3 * tmp1) + minor0; | |
Float32x4 minor3 = row0 * tmp1; | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
minor0 = minor0 - (row3 * tmp1); | |
minor3 = (row0 * tmp1) - minor3; | |
minor3 = minor3.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
// | |
// | |
tmp1 = row1.shuffle(Float32x4.zwxy) * row3; // 2, 3, 0, 1 | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); // 1, 0, 3, 2 | |
row2 = row2.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
minor0 = (row2 * tmp1) + minor0; | |
Float32x4 minor2 = row0 * tmp1; | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
minor0 = minor0 - (row2 * tmp1); | |
minor2 = (row0 * tmp1) - minor2; | |
minor2 = minor2.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
// | |
// | |
tmp1 = row0 * row1; | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); // 1, 0, 3, 2 | |
minor2 = (row3 * tmp1) + minor2; | |
minor3 = (row2 * tmp1) - minor3; | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); // 2, 3, 0, 1 | |
minor2 = (row3 * tmp1) - minor2; | |
minor3 = minor3 - (row2 * tmp1); | |
// | |
// | |
tmp1 = row0 * row3; | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); | |
minor1 = minor1 - (row2 * tmp1); | |
minor2 = (row1 * tmp1) + minor2; | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); | |
minor1 = (row2 * tmp1) + minor1; | |
minor2 = minor2 - (row1 * tmp1); | |
// | |
// ---- | |
tmp1 = row0 * row2; | |
tmp1 = tmp1.shuffle(Float32x4.yxwz); | |
minor1 = (row3 * tmp1) + minor1; | |
minor3 = minor3 - (row1 * tmp1); | |
tmp1 = tmp1.shuffle(Float32x4.zwxy); | |
minor1 = minor1 - (row3 * tmp1); | |
minor3 = (row1 * tmp1) + minor3; | |
// Compute determinant | |
Float32x4 det = row0 * minor0; | |
det = det.shuffle(Float32x4.zwxy) + det; | |
det = det.shuffle(Float32x4.yxwz) + det; | |
tmp1 = det.reciprocal(); | |
det = (tmp1 + tmp1) - (det * (tmp1 * tmp1)); | |
det = det.shuffle(Float32x4.xxxx); | |
// minor0 = minor0.shuffle(Float32x4.zyxw); | |
// minor1 = minor1.shuffle(Float32x4.zyxw); | |
// minor2 = minor2.shuffle(Float32x4.zyxw); | |
// minor3 = minor3.shuffle(Float32x4.zyxw); | |
// Compute final values by multiplying with 1/det | |
minor0 = det * minor0; | |
minor1 = det * minor1; | |
minor2 = det * minor2; | |
minor3 = det * minor3; | |
return SimdMatrix4._(Float32x4List.fromList(<Float32x4>[ | |
minor0, | |
minor1, | |
minor2, | |
minor3 | |
])); | |
} |
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