MyHDL Structured Types in action.

aos.vhd

-- File: aos.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Aug 31 15:57:52 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity aos is
	port(
		Clk   : in  std_logic;
		Reset : in  std_logic;
		A0    : in  unsigned(1 downto 0);
		A1    : in  unsigned(1 downto 0);
		CI    : in  unsigned(1 downto 0);
		D     : in  unsigned(7 downto 0);
		Wr    : in  std_logic;
		WrCI  : in  std_logic;
		Q     : out unsigned(23 downto 0)
	);
end entity aos;
-- a small example to test the StructType experimental implementation 

architecture MyHDL of aos is
	type a3_rgbpix is array (0 to 3 - 1) of rgbpix;
	type a3_a3_rgbpix is array (0 to 3 - 1) of a3_rgbpix;
	type rgbpix is record
		r : unsigned(7 downto 0);
		b : unsigned(7 downto 0);
		g : unsigned(7 downto 0);
	end record;

	signal lg    : unsigned(7 downto 0);
	signal lb    : unsigned(7 downto 0);
	signal plane : a3_a3_rgbpix;
	signal pixel : rgbpix;

begin
	aos_aoifill : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			Q  <= to_unsigned(0, 24);
			lg <= to_unsigned(0, 8);
			lb <= to_unsigned(0, 8);
		elsif rising_edge(Clk) then
			if ((0 = CI) and bool(WrCI)) then
				lb <= D;
			end if;
			if ((1 = CI) and bool(WrCI)) then
				lg <= D;
			end if;
			if ((2 = CI) and bool(WrCI)) then
				pixel.b                 <= lb;
				pixel.g                 <= lg;
				pixel.r(4 - 1 downto 0) := D(8 - 1 downto 4);
				pixel.r(8 - 1 downto 4) := D(4 - 1 downto 0);
			end if;
			for k in 0 to 3 - 1 loop
				for j in 0 to 3 - 1 loop
					if ((k = signed(resize(A1, 3))) and (j = signed(resize(A0, 3))) and bool(Wr)) then
						plane(k)(j) <= pixel;
					end if;
				end loop;
			end loop;
			Q(8 - 1 downto 0)   <= plane(to_integer(A1))(to_integer(A0)).b;
			Q(16 - 1 downto 8)  <= plane(to_integer(A1))(to_integer(A0)).g;
			Q(24 - 1 downto 16) <= plane(to_integer(A1))(to_integer(A0)).r;
		end if;
	end process aos_aoifill;

end architecture MyHDL;

array_of_struct.py

'''
Created on 28 August 2015


@author: Josy
'''

from __future__ import print_function

import random

import myhdl

import hdlutils

 
class rgbpix( myhdl.StructType ):
    ''' an struct/record with conversion routines '''

    def __init__( self, WIDTH_PIXEL = 10, values = None ):
        self._WIDTH_PIXEL = WIDTH_PIXEL
        if values is None:
            self.b = myhdl.Signal( myhdl.intbv( 0 )[self._WIDTH_PIXEL:] )
            self.g = myhdl.Signal( myhdl.intbv( 0 )[self._WIDTH_PIXEL:] )
            self.r = myhdl.Signal( myhdl.intbv( 0 )[self._WIDTH_PIXEL:] )
        else:
            self.b = myhdl.Signal( myhdl.intbv( values[0] )[self._WIDTH_PIXEL:] )
            self.g = myhdl.Signal( myhdl.intbv( values[1] )[self._WIDTH_PIXEL:] )
            self.r = myhdl.Signal( myhdl.intbv( values[2] )[self._WIDTH_PIXEL:] )

    def torecord( self, v ):
        ''' we 'reformat' a vector into an interface/record '''
        trWIDTH_PIXEL = self._WIDTH_PIXEL
        @myhdl.always_comb
        def torecord():
            lv = v
            self.b.next = lv[( 0 + 1 ) * trWIDTH_PIXEL : 0 * trWIDTH_PIXEL]
            self.g.next = lv[( 1 + 1 ) * trWIDTH_PIXEL : 1 * trWIDTH_PIXEL]
            self.r.next = lv[( 2 + 1 ) * trWIDTH_PIXEL : 2 * trWIDTH_PIXEL]

        return torecord

    def tointbv( self, y ):
        ''' build a flattened vector from the record's elements in ascending order'''
        tiWIDTH_PIXEL = self._WIDTH_PIXEL
        @myhdl.always_comb
        def tointbv():
            y.next[( 0 + 1 ) * tiWIDTH_PIXEL : 0 * tiWIDTH_PIXEL ] = self.b
            y.next[( 1 + 1 ) * tiWIDTH_PIXEL : 1 * tiWIDTH_PIXEL ] = self.g
            y.next[( 2 + 1 ) * tiWIDTH_PIXEL : 2 * tiWIDTH_PIXEL ] = self.r

        return tointbv

    def tonatural( self ):
        return ( ( ( self.r << self._WIDTH_PIXEL ) + self.g ) << self._WIDTH_PIXEL ) + self.b

    def flatten(self):
        return myhdl.ConcatSignal( self.r, self.g, self.b)


def aos( Clk, Reset, A0, A1, CI, D , Wr , WrCI, Q ):
    ''' a small example to test the StructType experimental implementation '''

    lb,lg = [myhdl.Signal( myhdl.intbv(0)[8:]) for _ in range(2)]
    pixel = rgbpix(8)
    plane = myhdl.Array( ( 3, 3 ), rgbpix( 8 ) )
#     qpixel = rgbpix(8)

    @myhdl.always_seq( Clk.posedge, reset = Reset )
    def aoifill():
        if  0 == CI and WrCI:
            lb.next = D
        if  1 == CI and WrCI:
            lg.next = D
        if  2 == CI and WrCI:
            pixel.b.next = lb
            pixel.g.next = lg
            pixel.r.next[4:] = D[:4] # this works
            pixel.r.next[:4] = D[4:]
        
        for k in range( 3 ):
            for j in range( 3 ):
                if k == A1 and j == A0 and Wr:
                    plane[k][j].next = pixel # this works
#                     plane[k][j].b.next = pixel.b
#                     plane[k][j].g.next = pixel.g
#                     plane[k][j].r.next[4:] = pixel.r[:4] # this doesn't work
#                     plane[k][j].r.next[:4] = pixel.r[4:] # this doesn't work
                    
        # always reading
#         Q.next = (plane[A1][A0].r << 16) +  (plane[A1][A0].g << 8) + plane[A1][A0].b
#         qpixel.next = plane[A1][A0]
        Q.next[ 8:  ] = plane[A1][A0].b
        Q.next[16: 8] = plane[A1][A0].g 
        Q.next[24:16] = plane[A1][A0].r 

    return aoifill



def tb_aos():
    TB_WIDTH_D = 8
    Clk = myhdl.Signal( bool( 0 ) )
    Reset = myhdl.ResetSignal( 0, active = 1, async = True )
    A0, A1 , CI = [myhdl.Signal( myhdl.intbv( 0 , min = 0, max = 3 ) ) for _ in range( 3 )]
    D = myhdl.Signal( myhdl.intbv( 0 )[TB_WIDTH_D:] )
    Wr = myhdl.Signal( bool( 0 ) )
    WrCI = myhdl.Signal( bool( 0 ) )
    Q = myhdl.Signal( myhdl.intbv( 0 )[TB_WIDTH_D * 3:] )

    dut = aos( Clk, Reset, A0, A1, CI, D, Wr, WrCI, Q )

    td = [[[ ( k * 3 + j ) * 3 + i + 1 for i in range( 3 )] for j in range( 3 )] for k in range( 3 ) ]

     # tally
    ClkCount = myhdl.Signal( myhdl.intbv( 0 )[32:] )
    tCK = 20

    @myhdl.instance
    def clkgen():
        yield hdlutils.genClk( Clk, tCK, ClkCount )

    @myhdl.instance
    def resetgen():
        yield hdlutils.genReset( Clk, tCK, Reset )

    @myhdl.instance
    def stimulusin():
        yield hdlutils.delayclks( Clk, tCK, 5 )
        for  k in range( 3 ):
            A1.next = k
            for j in range( 3 ):
                A0.next = j
                for i in range( 3 ):
                    CI.next = i
                    D.next = td[k][j][i]
                    yield hdlutils.pulsesig( Clk, tCK, WrCI, 1, 1 )
                    yield hdlutils.delayclks( Clk, tCK, 1 )
                
                yield hdlutils.pulsesig( Clk, tCK, Wr, 1, 1 )
                yield hdlutils.delayclks( Clk, tCK, 1 )

        for  k in range( 3 ):
            A1.next = k
            for j in range( 3 ):
                A0.next = j
                yield hdlutils.delayclks( Clk, tCK, 3 )
        
        yield hdlutils.delayclks( Clk, tCK, 5 )
        raise myhdl.StopSimulation


    return dut, clkgen, resetgen, stimulusin


def convert():
    WIDTH_D = 8
    Clk = myhdl.Signal( bool( 0 ) )
    Reset = myhdl.ResetSignal( 0, active = 1, async = True )
    A0, A1 , CI = [myhdl.Signal( myhdl.intbv( 0 , min = 0, max = 3 ) ) for _ in range( 3 )]
    D = myhdl.Signal( myhdl.intbv( 0 )[WIDTH_D:] )
    B = myhdl.Signal( bool( 0 ) )
    Wr = myhdl.Signal( bool( 0 ) )
    WrCI = myhdl.Signal( bool( 0 ) )
    Q = myhdl.Signal( myhdl.intbv( 0 )[WIDTH_D * 3:] )

    myhdl.toVHDL( aos, Clk, Reset, A0, A1, CI, D, Wr, WrCI, Q )


if __name__ == '__main__':
    hdlutils.simulate( 10000, tb_aos )
    convert()

tb_aos.vcd

$date
    Mon Aug 31 15:57:52 2015
$end
$version
    MyHDL 1.0dev
$end
$timescale
    1ns
$end

$scope module tb_aos $end
$var reg 1 ! Reset $end
$var reg 24 " Q $end
$var reg 2 # CI $end
$var reg 8 $ D $end
$var reg 1 % Clk $end
$var reg 2 & A1 $end
$var reg 2 ' A0 $end
$var reg 1 ( Wr $end
$var reg 32 ) ClkCount $end
$var reg 1 * WrCI $end
$scope module dut $end
$var reg 1 ! Reset $end
$var reg 8 + lg $end
$var reg 2 # CI $end
$var reg 2 & A1 $end
$var reg 8 , lb $end
$var reg 8 $ D $end
$var reg 1 % Clk $end
$var reg 24 " Q $end
$var reg 2 ' A0 $end
$var reg 1 ( Wr $end
$var reg 1 * WrCI $end
$scope module plane $end
$scope module plane(0)(0) $end
$var reg 8 - plane(0)(0).b $end
$var reg 8 . plane(0)(0).r $end
$var reg 8 / plane(0)(0).g $end
$upscope $end
$scope module plane(0)(1) $end
$var reg 8 0 plane(0)(1).b $end
$var reg 8 1 plane(0)(1).r $end
$var reg 8 2 plane(0)(1).g $end
$upscope $end
$scope module plane(0)(2) $end
$var reg 8 3 plane(0)(2).b $end
$var reg 8 4 plane(0)(2).r $end
$var reg 8 5 plane(0)(2).g $end
$upscope $end
$scope module plane(1)(0) $end
$var reg 8 6 plane(1)(0).b $end
$var reg 8 7 plane(1)(0).r $end
$var reg 8 8 plane(1)(0).g $end
$upscope $end
$scope module plane(1)(1) $end
$var reg 8 9 plane(1)(1).b $end
$var reg 8 : plane(1)(1).r $end
$var reg 8 ; plane(1)(1).g $end
$upscope $end
$scope module plane(1)(2) $end
$var reg 8 < plane(1)(2).b $end
$var reg 8 = plane(1)(2).r $end
$var reg 8 > plane(1)(2).g $end
$upscope $end
$scope module plane(2)(0) $end
$var reg 8 ? plane(2)(0).b $end
$var reg 8 @ plane(2)(0).r $end
$var reg 8 A plane(2)(0).g $end
$upscope $end
$scope module plane(2)(1) $end
$var reg 8 B plane(2)(1).b $end
$var reg 8 C plane(2)(1).r $end
$var reg 8 D plane(2)(1).g $end
$upscope $end
$scope module plane(2)(2) $end
$var reg 8 E plane(2)(2).b $end
$var reg 8 F plane(2)(2).r $end
$var reg 8 G plane(2)(2).g $end
$upscope $end
$upscope $end
$scope module pixel $end
$var reg 8 H pixel.r $end
$var reg 8 I pixel.b $end
$var reg 8 J pixel.g $end
$upscope $end
$upscope $end
$upscope $end

$enddefinitions $end
$dumpvars
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$end
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1%
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b01 &
b00 '
#1710
0%
b00000000000000000000000001010110 )
#1720
1%
b110000000000101100001010 "
#1730
0%
b00000000000000000000000001010111 )
#1740
1%
#1750
0%
b00000000000000000000000001011000 )
#1760
1%
#1765
b01 '
#1770
0%
b00000000000000000000000001011001 )
#1780
1%
b111100000000111000001101 "
#1790
0%
b00000000000000000000000001011010 )
#1800
1%
#1810
0%
b00000000000000000000000001011011 )
#1820
1%
#1825
b10 '
#1830
0%
b00000000000000000000000001011100 )
#1840
1%
b001000010001000100010000 "
#1850
0%
b00000000000000000000000001011101 )
#1860
1%
#1870
0%
b00000000000000000000000001011110 )
#1880
1%
#1885
b10 &
b00 '
#1890
0%
b00000000000000000000000001011111 )
#1900
1%
b010100010001010000010011 "
#1910
0%
b00000000000000000000000001100000 )
#1920
1%
#1930
0%
b00000000000000000000000001100001 )
#1940
1%
#1945
b01 '
#1950
0%
b00000000000000000000000001100010 )
#1960
1%
b100000010001011100010110 "
#1970
0%
b00000000000000000000000001100011 )
#1980
1%
#1990
0%
b00000000000000000000000001100100 )
#2000
1%
#2005
b10 '
#2010
0%
b00000000000000000000000001100101 )
#2020
1%
b101100010001101000011001 "
#2030
0%
b00000000000000000000000001100110 )
#2040
1%
#2050
0%
b00000000000000000000000001100111 )
#2060
1%
#2065
#2070
0%
b00000000000000000000000001101000 )
#2080
1%
#2090
0%
b00000000000000000000000001101001 )
#2100
1%
#2110
0%
b00000000000000000000000001101010 )
#2120
1%
#2130
0%
b00000000000000000000000001101011 )
#2140
1%
#2150
0%
b00000000000000000000000001101100 )
#2160
1%
#2165