Created
September 8, 2015 19:10
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A MyHDL test_ template for Eclipse
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''' | |
Created on ${date} | |
@author: ${user} | |
''' | |
from __future__ import print_function | |
# optional import to mark 'xfail' tests | |
import py.test | |
import myhdl | |
def ${name}(clk, reset, ): | |
''' ''' | |
@myhdl.always_comb | |
def rtlcomb(): | |
pass | |
@myhdl.always_seq( clk.posedge, reset = reset) | |
def rtlreg(): | |
pass | |
return rtlcomb, rtlreg | |
def test_${name}(): | |
clk = myhdl.Signal( bool( 0 )) | |
reset = myhdl.ResetSignal( 0, active = 1, async = True) | |
assert myhdl.conversion.analyze( ${name}, clk, reset, ) == 0 | |
def tb_${name}(): | |
clk = myhdl.Signal( bool( 0 )) | |
reset = myhdl.ResetSignal( 0, active = 1, async = True) | |
tbdut = ${name}(clk, reset, ) | |
tCK = 10 | |
RESETLENGTH = 3 | |
clkcount = 0 | |
@myhdl.instance | |
def genclkreset(): | |
reset.next = 1 | |
clk.next = 1 | |
yield myhdl.delay( int( tCK / 2 )) | |
clk.next = 0 | |
for _ in range(RESETLENGTH): | |
if not (clkcount is None): | |
clkcount += 1 | |
yield myhdl.delay( int( tCK / 2 )) | |
clk.next = 1 | |
yield myhdl.delay( tCK - int( tCK / 2 )) | |
clk.next = 0 | |
reset.next = 0 | |
yield myhdl.delay( int( tCK / 2 )) | |
while True: | |
clk.next = 1 | |
if not (clkcount is None): | |
clkcount += 1 | |
yield myhdl.delay( int( tCK / 2 )) | |
clk.next = 0 | |
yield myhdl.delay( tCK - int( tCK / 2 )) | |
@myhdl.instance | |
def stimulus(): | |
for _ in range(5): | |
yield clk.posedge() | |
myhdl.delay( tCK / 2) | |
return tbdut, genclkreset, stimulus | |
def test_tb_${name}(): | |
assert myhdl.conversion.verify( tb_${name}) == 0 | |
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