reworked and reformatted example from MyHDL issue#43

myhdl_issue43_jb

from __future__ import print_function

import random

from myhdl import *


def m_top_const(COEF, N, clock, reset, a, b, x, y):

    v = [Signal(x.val) for _ in range(N-1)]
    glist = [None for _ in range(N)]

    # create multiple instances
    glist[0] = m_constants( COEF[0], clock, reset, a, b, x)
    for ii in range(N-1):
        # append the constant module to the list of generators
        glist[1+ii] = m_constants(COEF[1+ii], clock, reset, a, b, v[ii])

    # combine all the outputs into one output
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        psum = 0          # sorta declaring the variable
#         # the next line forces 'x' into an 'inout' port which is considered 'bad practice'?
#         psum = psum + x   # initial value of the variable
        for ii in range(N-1):
            psum = psum + v[ii]
        y.next = psum

    return glist, rtl


def m_constants(COEF, clock, reset, a, b, x):
    # use fixed indexes from the coef
    @always_seq(clock.posedge, reset=reset)
    def rtl():
        x.next = a * COEF[0] + b * COEF[1]

    return rtl


def test_constant():

    random.seed("We want repeatable randomness")
    N = 10

    # a list (not a tuple!) of constant ints
    COEF = [[random.randint(-19, 23), random.randint(0, 127)] for _ in range(N)]

    clock = Signal(bool(1))
    reset = ResetSignal(0, active = 1, async = True)
    x = Signal(intbv(0, min = -19 * 23 + -3 * 127, max = 17 * 23 + 37 * 127))
    y = Signal(intbv(0, min = (-19 * 23 + -3 * 127) * N, max = (17 * 23 + 37 * 127) * N))
    a = Signal(intbv(random.randint(-19, 17), min = -19, max = 17))
    b = Signal(intbv(random.randint(-3, 37), min = -3, max = 37))

    # a test function
    def _test():
        # instantiate the design under test
        tbdut = m_top_const(COEF, N, clock, reset, a, b, x, y)

        @always(delay(3))
        def tbclk():
            clock.next = not clock

        @instance
        def tbstim():
            reset.next = reset.active
            yield delay(21)
            reset.next = not reset.active

            yield clock.posedge
            yield clock.posedge
            yield clock.posedge

            psum = 0
            for coef in COEF[1:]:
                psum = psum + (a * coef[0] + b * coef[1])

            assert psum == y

            raise StopSimulation

        return tbdut, tbclk, tbstim


    Simulation(_test()).run()
    print("** Simulation Successfull **")
    toVHDL(m_top_const, COEF, N, clock, reset, a, b, x, y)
    toVerilog(m_top_const, COEF, N, clock, reset, a, b, x, y)


if __name__ == '__main__':
    test_constant()