Verilog top-level for counter with IO pads

top.v

module top (
    output  wire p_count3,
    output  wire p_count2,
    output  wire p_count1,
    output wire p_count0,
    input  wire p_clk,
    input  wire p_rst
);

    wire clk, rst;
    wire [3:0] count;

    Counter count_i (
        .clk(clk),
        .rst(rst),
        .count(count)
    );

  (* keep *) sg13g2_IOPadIn u_pad_io_clk (.pad(p_clk), .p2c(clk)) ;
  (* keep *) sg13g2_IOPadIn u_pad_io_rst (.pad(p_rst), .p2c(rst)) ;

  (* keep *) sg13g2_IOPadOut4mA u_pad_io_count0 (.pad(p_count0), .c2p(count[0])) ;
  (* keep *) sg13g2_IOPadOut4mA u_pad_io_count1 (.pad(p_count1), .c2p(count[1])) ;
  (* keep *) sg13g2_IOPadOut4mA u_pad_io_count2 (.pad(p_count2), .c2p(count[2])) ;
  (* keep *) sg13g2_IOPadOut4mA u_pad_io_count3 (.pad(p_count3), .c2p(count[3])) ;

  (* keep *) sg13g2_IOPadIOVdd u_pad_vddpad_0 () ;
  (* keep *) sg13g2_IOPadIOVdd u_pad_vddpad_1 () ;

  (* keep *) sg13g2_IOPadVdd u_pad_vddcore_0 () ;
  (* keep *) sg13g2_IOPadVdd u_pad_vddcore_1 () ;

  (* keep *) sg13g2_IOPadIOVss u_pad_gndpad_0 () ;
  (* keep *) sg13g2_IOPadIOVss u_pad_gndpad_1 () ;

  (* keep *) sg13g2_IOPadVss u_pad_gndcore_0 () ;
  (* keep *) sg13g2_IOPadVss u_pad_gndcore_1 () ;

endmodule